Chip, coating method thereof and electronic equipment
By combining wet etching and dry etching to remove the oxide film and residual adhesive on the chip surface, and combined with low-temperature annealing, the problem of film-chip bonding defects after coating was solved, thus improving the chip reliability.
Patent Information
- Application Number
- CN202510973736.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-15
- Publication Date
- 2025-10-28
AI Technical Summary
After coating the chip surface, there may be localized oxidation and the adhesive film may not be completely removed, resulting in bonding defects between the coated film and the chip, which affects the chip performance.
The barrier layer was removed by wet etching, followed by dry etching to remove the oxide film and residual adhesive layer. Chip damage was repaired by low-temperature annealing, and then a coating process was performed.
It effectively removes residual oxide film and adhesive film between the chip and the coating, avoids bonding defects, and improves the reliability of chip performance.
Smart Images
Figure CN120857680A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a chip, its coating method, and an electronic device. Background Technology
[0002] With the rapid development of infrared technology, various application fields such as remote sensing, space astronomy, and industry and agriculture are placing increasingly wider demands on the operating spectral range of infrared detectors. Individual detectors are required not only to cover single bands such as short, medium, and long wavelengths, but also to achieve multi-spectral band coverage, including the visible and near-infrared regions, short and medium waves, and medium and long waves. Therefore, the research and fabrication of high-transmittance, high-reliability, broadband antireflective coatings is an important future direction for infrared detector research, such as mercury cadmium telluride (HCd) chips.
[0003] To improve the corrosion resistance, wear resistance, and conductivity of mercury cadmium telluride (HCDT) chips, a thin film is coated onto the chip surface, a process known as chip coating. However, even after coating, localized oxidation and incomplete removal of the coating film can occur, leading to bonding defects between the coated film and the chip, thus affecting chip performance.
[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide a chip and its coating method, as well as an electronic device, to solve the problem that after coating the chip surface, there is still local oxidation and the adhesive film cannot be completely removed, resulting in bonding defects between the coated film and the chip, which affects the chip performance.
[0006] To solve the above-mentioned technical problems, the present invention provides a chip coating method, comprising:
[0007] A chip is provided, the surface of which has a barrier layer;
[0008] The barrier layer is removed by wet etching;
[0009] Dry etching is used to etch the chip surface after the barrier layer has been removed;
[0010] The chip after dry etching is subjected to low-temperature annealing.
[0011] The chip is coated.
[0012] Preferably, the reagent used in the wet etching process is hydrochloric acid.
[0013] Preferably, reactive ion etching is used to etch the chip surface after the barrier layer has been removed.
[0014] Preferably, the gas used in the reactive ion etching process includes CH4, H2, and Ar, with a gas volume ratio of CH4:H2:Ar = 3:1:1-4:1:2.
[0015] Preferably, the reactive ion etching rate is 50-100 nm / min, the etching pressure is 0.5 Torr-1.5 mTorr, the RF power is 40 W-80 W, the self-bias voltage range is 60 V-90 V, and the etching time is 2 min-5 min.
[0016] Preferably, the temperature range for low-temperature annealing is 20℃-40℃.
[0017] Preferably, the chip is a mercury cadmium telluride chip.
[0018] Preferably, the coating material includes zinc sulfide.
[0019] Based on the same inventive concept, the present invention also provides a chip, comprising:
[0020] The chip is coated using the method described above.
[0021] Based on the same inventive concept, the present invention also provides an electronic device, comprising:
[0022] The chip described above.
[0023] Compared with the prior art, the chip coating method of the present invention has the following advantages:
[0024] This invention removes the barrier layer using wet etching, then removes the oxide film and residual adhesive layer on the chip surface using dry etching, and finally repairs the chip damage using a low-temperature annealing process. This process removes residual oxide film and adhesive film between the chip and the coating, avoiding bonding defects between the coating and the chip after coating, and improving the reliability of chip performance.
[0025] The chip and electronic device provided by this invention belong to the same inventive concept as the chip coating method provided by this invention. Therefore, the chip and electronic device provided by this invention have at least all the advantages of the chip coating method provided by this invention, and the chip and electronic device have high reliability. Attached Figure Description
[0026] Figure 1 This is a flowchart of a chip coating method according to an embodiment of the present invention;
[0027] Figure 2 This is a schematic diagram of an oxide film formed on the chip surface according to an embodiment of the present invention;
[0028] Figure 3 This is an electron scanning image of the chip surface after coating in one embodiment of the present invention;
[0029] Figure 4 This is an image showing an opening formed on the coating surface in one embodiment of the present invention;
[0030] Figure 5 This is a graph showing the test results of the corrosion resistance of the coating in one embodiment of the present invention;
[0031] In the figure,
[0032] 100-Mercury cadmium telluride chip; 200-Oxide film and residual adhesive composite layer. Detailed Implementation
[0033] To make the objectives, advantages, and features of the present invention clearer, the chip, its coating method, and electronic device proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. It should be understood that the accompanying drawings do not necessarily show the specific structure of the present invention to scale, and the illustrative features used to illustrate certain principles of the present invention in the accompanying drawings are also drawn in a slightly simplified manner. Specific design features of the present invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and environment in which they are used. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0035] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0036] Because a barrier layer is formed during chip manufacturing, it needs to be removed after chip fabrication. After removing the barrier layer, a coating is then applied to the chip surface to increase corrosion resistance and protect the chip. However, in some examples, before coating, hydrochloric acid is first used to remove the barrier layer. Next, the chip is rinsed with pure water, and then the surface is dried with nitrogen before direct coating. However, after removing the barrier layer, localized oxide layers and adhesive films remain on the chip surface. Simply rinsing with hydrochloric acid and pure water is insufficient to effectively remove these, leading to bonding defects between the passivation film (i.e., the thin film after coating) and the chip, affecting chip performance.
[0037] The core idea of this invention is to provide a chip coating method that can remove residual oxide film and adhesive film between the chip and the coating, avoid bonding defects between the passivation film and the chip after coating, and improve the reliability of chip performance.
[0038] To achieve the above-mentioned goals, this invention provides a chip coating method, which includes... Figures 1 to 5 A specific embodiment of the disclosed chip coating method is described. The chip coating method includes the following steps S1 to S5.
[0039] Step S1: Provide a chip, the surface of which has a barrier layer.
[0040] Specifically, refer to Figure 1 As shown, the chip can be a memory chip, processor chip, image chip, power chip, or logic chip, or other types of chips; this application embodiment is not limited to these. For chips requiring surface coating, the method disclosed in this embodiment can be used for processing. In this embodiment, the preferred chip is a mercury cadmium telluride chip 100.
[0041] Step S2: Remove the barrier layer by wet etching.
[0042] Specifically, refer to Figure 1As shown, during the fabrication of the mercury cadmium telluride (HCdT) chip 100, a barrier layer is formed for the etching process. After the HCdT chip 100 is fabricated, the barrier layer needs to be removed before coating. Wet etching is generally used to remove the barrier layer. Materials for the barrier layer include TiN and TiW. The reagent used in wet etching is hydrochloric acid. The concentration of hydrochloric acid is commonly used for removing the barrier layer, such as 5% to 20%.
[0043] Step S3: Use dry etching to etch the chip surface after removing the barrier layer.
[0044] Specifically, refer to Figure 1 and Figure 2 As shown. After the barrier layer is removed, the surface of the chip is partially oxidized, forming an oxide film. Some adhesive residue remains. Therefore, after removing the barrier layer, an oxide film and adhesive residue combination layer 200 remains on the surface of the mercury cadmium telluride chip 100. To remove the oxide film and adhesive residue combination layer 200, reactive ion etching (RIE) is used to etch the chip surface after barrier layer removal, achieving anisotropy through plasma etching. The gases used in the reactive ion etching process include CH4, H2, and Ar. The gas volume ratio CH4:H2:Ar = 3:1:1-4:1:2. The CH4 gas flow rate is 20-300 sccm. The H2 flow rate is 5-30 sccm. The Ar flow rate is 50-800 sccm. The reactive ion etching rate is less than 1 μm / min, and the reactive ion etching rate is 50-100 nm / min. The etching pressure is 0.5 Torr-1.5 mTorr, the RF power is 40W-80W, and the self-bias voltage range is 60V-90V.
[0045] Dry etching is employed to remove the barrier layer from the mercury cadmium telluride (MDT) chip 100 to be coated with a passivation film. The chip is then placed in an etching machine, and the etching rate is adjusted for surface etching. As etching progresses, the oxide layer and adhesive film on the surface of the MDT chip 100 react fully with the etching gas and dissolve, thereby removing the oxide layer and contaminants, and adjusting the surface morphology. Dry etching achieves atomically smooth surfaces through three key mechanisms: selective physical bombardment (low-energy ion directional removal of protruding atoms), self-limiting chemical reaction (dynamic passivation layer protection), and extreme control of plasma uniformity. Ultimately, a thermodynamically stable monoatom layer is formed on the surface, providing a defect-free interface for the passivation layer, improving adhesion, and thus enhancing the adhesion of the coating and device performance.
[0046] Step S4: The chip after dry etching is subjected to low-temperature annealing.
[0047] Specifically, refer to Figure 1 and Figure 2As shown. After dry etching, the plasma generated by the etching gas causes damage to the surface of the mercury cadmium telluride chip 100 during the bombardment process. Therefore, after dry etching, after the etching is completed, the mercury cadmium telluride chip 100 is processed by a low-temperature annealing process in the etching machine to repair the damage of the mercury cadmium telluride chip 100. Because of the material of the mercury cadmium telluride chip 100, the mercury cadmium telluride material is a thermosensitive material, and the temperature range of the low-temperature annealing treatment is 20°C - 40°C to avoid the denaturation loss of the mercury cadmium telluride material caused by high temperature and prevent the damage of the mercury cadmium telluride chip 100 from being irreparable.
[0048] Step S5: Coat the chip.
[0049] Specifically, refer to Figures 1 to 5 As shown. After repairing the mercury cadmium telluride chip 100, it is immediately sent to a coating machine for coating. That is, the mercury cadmium telluride chip 100 is coated by a passivation process. The time for the mercury cadmium telluride chip 100 to stay in the environment is reduced. The coating material includes zinc sulfide. After the coating treatment, it also includes forming openings on the surface of the mercury cadmium telluride chip 100 through the passivation process.
[0050] Refer to Figures 3 to 5 As shown, Figure (3a) is an electron scanning image of the chip surface after coating the chip surface without using the method disclosed in this embodiment. Figure (3b) is an electron scanning image of the chip surface after coating the chip surface using the method disclosed in this embodiment. From the comparison between Figure (3a) and Figure (3b), it can be seen that the passivation film in Figure (3b) grows densely and tightly with a good growth state. Figure (4a) is a picture of the opening formed on the coating surface without using the method disclosed in this embodiment. Figure (4b) is a picture of the opening formed on the coating surface using the method disclosed in this embodiment. Forming an opening on the coating surface is to enable the growth of electrode metal blocks on the surface of the mercury cadmium telluride chip 100, which is an essential step in the preparation process of the infrared cooling detector. If the opening is not properly formed, it will hinder the process. It can be seen from Figure (4a) that there is a situation where the opening is not fully etched. It can be seen from Figure (4b) that the opening state is good and the aperture is below 5 μm. Figure (5a) is a test result graph of the corrosion resistance of the coating after coating without using the method disclosed in this embodiment. Figure (5b) is a test result graph of the corrosion resistance of the coating after coating using the method disclosed in this embodiment. It can be seen from Figure (5a) that the coating surface is corroded. The coating is not corrosion-resistant. It can be seen from Figure (5b) that the coating is corrosion-resistant.
[0051] In this embodiment, after removing the barrier layer, the oxide film and residual adhesive layer 200 on the surface of the mercury cadmium telluride (MDT) chip 100 are removed by dry etching. This removes the residual oxide film and adhesive film between the chip and the passivation film, avoiding bonding defects between the passivation film and the MDT chip 100 after coating, and improving the reliability of the MDT chip 100 performance. Dry etching optimizes the passivation film growth, resulting in a better zinc sulfide film. Dry etching can accurately control the surface morphology, achieving a roughness (Ra) < 1 nm, improving the uniformity and adhesion of the passivation layer. Subsequently, the MDT chip 100 is treated with a low-temperature annealing process. After dry etching, low-temperature annealing is performed in the etching machine to effectively repair ion damage. After annealing, it is immediately placed in a coating machine for vacuum coating to prevent oxidation.
[0052] To achieve the above idea, this embodiment also discloses a chip, including:
[0053] The chip is coated using the method described above.
[0054] The chip can be a memory chip, processor chip, image chip, power chip, or logic chip, or other types of chips. The embodiments of this application are not limited to this.
[0055] To achieve the above-mentioned ideas, this embodiment also discloses an electronic device, including:
[0056] The chip described above.
[0057] Electronic devices can be any electronic device, such as a personal digital assistant, a handheld computer system, a tablet computer, or a digital camera.
[0058] The chip and electronic device provided in this embodiment belong to the same inventive concept as the chip coating method provided in this embodiment. Therefore, the chip and electronic device provided in this embodiment have at least all the advantages of the chip coating method provided in this embodiment, and the chip and electronic device have high reliability.
[0059] In summary, the above embodiments have provided detailed descriptions of different configurations of chips and their coating methods, as well as electronic devices. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention in any way. The present invention includes, but is not limited to, the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure are within the scope of protection of the claims.
Claims
1. A chip coating method, characterized in that, include: A chip is provided, the surface of which has a barrier layer; The barrier layer is removed by wet etching; Dry etching is used to etch the chip surface after the barrier layer has been removed; The chip after dry etching is subjected to low-temperature annealing. The chip is coated.
2. The chip coating method according to claim 1, characterized in that, The reagent used in the wet etching process is hydrochloric acid.
3. The chip coating method according to claim 1, characterized in that, Reactive ion etching is used to etch the chip surface after the barrier layer has been removed.
4. The chip coating method according to claim 3, characterized in that, The gases used in the reactive ion etching process include CH4, H2, and Ar, with a gas volume ratio of CH4:H2:Ar = 3:1:1-4:1:
2.
5. The chip coating method according to claim 4, characterized in that, The reactive ion etching rate is 50-100 nm / min, the etching pressure is 0.5 Torr-1.5 mTorr, the RF power is 40 W-80 W, the self-bias voltage range is 60 V-90 V, and the etching time is 2 min-5 min.
6. The chip coating method according to claim 1, characterized in that, The temperature range for low-temperature annealing is 20℃-40℃.
7. The chip coating method according to claim 1, characterized in that, The chip is a mercury cadmium telluride chip.
8. The chip coating method according to claim 1, characterized in that, The coating material includes zinc sulfide.
9. A chip, characterized in that, include: The chip is coated using the method described in any one of claims 1-8.
10. An electronic device, characterized in that, include: The chip as described in claim 9.