Panel structure, pixel structure and pixel structure repairing method

Abstract

The invention discloses a panel structure, a pixel structure and a pixel structure repairing method. The pixel structure comprises a substrate, a plurality of vertical diode crystal grains, flip-chip diode crystal grains and an upper wiring layer. The substrate is provided with a lower wiring layer, the lower wiring layer comprises a plurality of first wires and second wires, the first wires belong to a first polarity, and the second wires belong to a second polarity. The plurality of vertical diode crystal grains are arranged on the substrate and are respectively coupled with the first wires. The flip-chip diode die is disposed on the substrate and coupled to a first wire and a second wire. The upper wiring layer is arranged on the plurality of vertical type diode crystal grains and the flip type diode crystal grains, the upper wiring layer comprises a plurality of third wires which are respectively coupled with the vertical type diode crystal grains, and the third wires belong to the second polarity.

Description

Technical Field

[0001] This invention relates to a substrate structure for micro light-emitting diodes, and more particularly to a substrate structure that incorporates multiple types of micro light-emitting diodes. Background Technology

[0002] Micro-LEDs are widely used in the lighting and display industries. Based on their layered structure, they can be mainly divided into flip-chip micro-LEDs and vertical micro-LEDs. In flip-chip micro-LEDs, the positive electrode (P-type) and negative electrode (N-type) are located on the same side of the die and are positioned on the same horizontal plane; while in vertical micro-LEDs, the positive and negative electrodes are located on the top and bottom sides of the die, respectively, and are arranged vertically. Because the positive and negative electrodes of flip-chip micro-LEDs are located on the same side, they are prone to current congestion. In contrast, vertical micro-LEDs have a more uniform electrode distribution, effectively improving current distribution and thus increasing luminous efficiency. Furthermore, vertical micro-LEDs have excellent heat dissipation performance, making them ideal for high-precision or small-size displays.

[0003] As display technology advances towards higher resolutions and higher pixels per inch (PPI), the pixel size of LED displays will become increasingly smaller, and the chip size must also shrink accordingly. Vertical LEDs, with their excellent heat dissipation and high luminous efficiency, hold a crucial position in the display industry.

[0004] However, existing technologies still face many challenges in mass transfer and grain repair of vertical micro-LEDs, which is the main reason why vertical micro-LEDs have not yet dominated the market.

[0005] On the other hand, with the advancement of technology, micro-LED display devices are expected to gradually replace traditional LCD displays and become the mainstream in the market. Existing micro-LEDs include two types: solid-color micro-LEDs and color-conversion micro-LEDs. Solid-color micro-LEDs can directly emit light of the corresponding color, while color-conversion micro-LEDs can use inkjet materials to change the color of the emitted light.

[0006] Compared to color-conversion micro-light-emitting diodes (LEDs), solid-color LEDs offer advantages such as simpler structure, wider color gamut, and higher reliability. However, the manufacturing process of solid-color LEDs requires multiple complex mass transfers, and their repair process is also quite complex. In contrast, while the manufacturing process of color-conversion LEDs only requires a single mass transfer, and their repair process is relatively simple, color-conversion LEDs also have disadvantages such as complex structure, narrower color gamut, and lower reliability.

[0007] On the other hand, the fabrication technology for micro LEDs varies in terms of production equipment and manufacturing techniques, resulting in specification differences between different types of micro LEDs (such as tri-color LEDs that emit red, green, and blue light). For example, the height difference between various micro LEDs can range from 2μm to 10μm.

[0008] Generally, the height differences of micro-LEDs mainly stem from variations in the fabrication processes of the following structural layers: epitaxial layer, electrode layer, bonding layer, and encapsulation layer. Height differences between micro-LEDs can adversely affect subsequent eutectic bonding processes, such as leading to poor bonding and reduced fabrication yield. Furthermore, these height differences can negatively impact alignment accuracy during fabrication and the optical performance of the final product.

[0009] Therefore, effectively addressing the significant differences between micro LEDs to improve manufacturing process stability and yield is a major challenge for the development of the LED industry.

[0010] On the other hand, due to the thickness differences between the red, green, and blue LED chips, traditional LED manufacturing processes use a filling technique to fill the gaps between each LED with a filler material to fix the multiple components within the LED. This filler material is then planarized to overcome the problems caused by the thickness differences. Furthermore, different filler materials can be used for different components within the LED to sequentially fix each component.

[0011] However, existing filling technologies still suffer from poor flatness of the filling material, which can cause open circuits between components and prevent the micro-LED from emitting light properly. Furthermore, when different filling materials are used to fix the components in a micro-LED, the interfaces between these materials can also lead to a decrease in the yield rate and reliability of the micro-LED during manufacturing.

[0012] On the other hand, the manufacturing process of micro-LED display devices requires multiple mass transfers to move millions of micro-LED units. However, existing mass transfer technologies cannot achieve precise positioning, and there is currently no suitable method to arrange scattered micro-LED units neatly and evenly on the same plane. Therefore, existing mass transfer technologies cannot accurately and efficiently move a massive number of micro-LED units, creating a bottleneck in the manufacturing process of micro-LED display devices.

[0013] On the other hand, existing mass transfer technology uses a thin film made of polydimethylsiloxane (PDMS) (hereinafter referred to as PDMS film) to transfer micro-light-emitting diode units. However, there is currently no suitable method to ensure that multiple micro-light-emitting diode units remain aligned and not skewed after being detached from the PDMS film, which creates a bottleneck in the manufacturing process of micro-light-emitting diode display devices. Summary of the Invention

[0014] In view of this, the inventors propose a pixel structure comprising: a substrate, a plurality of vertical diode chips, a flip-chip diode chip, and an upper wiring layer. The substrate has a lower wiring layer comprising a plurality of first wirings and a second wiring, the first wirings belonging to a first polarity and the second wiring belonging to a second polarity. The plurality of vertical diode chips are disposed on the substrate and coupled to the first wirings respectively. The flip-chip diode chip is disposed on the substrate and coupled to one of the first wirings and the second wiring. The upper wiring layer is disposed on the plurality of vertical diode chips and the flip-chip diode chip, and the upper wiring layer comprises a plurality of third wirings, respectively coupled to the vertical diode chips, the third wirings belonging to the second polarity.

[0015] In some embodiments, the pixel structure further includes a plurality of blocks and a light-transmitting fill layer. The plurality of blocks define a plurality of receiving sites. The plurality of vertical diode chips and the flip-chip diode chip are respectively located within the plurality of receiving sites. The light-transmitting fill layer covers the flip-chip diode chip, and the top surface of the light-transmitting fill layer is substantially coplanar with the top surfaces of the blocks.

[0016] In some embodiments, the plurality of vertical diode chips includes at least one inactive vertical diode chip and at least one active vertical diode chip, wherein the color category of the light beam corresponding to the flip-chip diode chip is different from the color category of the light beam corresponding to the at least one active vertical diode chip.

[0017] In some embodiments, the pixel structure further includes multiple first light conversion material layers, each covering the top of each vertical diode die.

[0018] In some embodiments, the pixel structure further includes a second light conversion material layer covering the flip-chip diode die.

[0019] The inventors also propose a panel structure comprising: a substrate, a first pixel structure, a second pixel structure, and an upper wiring layer. The substrate has a lower wiring layer comprising multiple first wirings and multiple second wirings, the first wirings belonging to a first polarity and the second wirings belonging to a second polarity. The first pixel structure has multiple first receiving sites, comprising multiple first vertical diode chips and a flip-chip diode chip. The multiple first vertical diode chips are disposed on the substrate and respectively located within the first receiving sites, and are respectively coupled to the first wirings. The flip-chip diode chip is disposed on the substrate and located within one of its first receiving sites, and is coupled to one of its first wirings and one of its second wirings. The second pixel structure has multiple second receiving sites, comprising multiple second vertical diode chips and a fill layer. The multiple second vertical diode chips are disposed on the substrate and respectively located within the second receiving sites, and are respectively coupled to the first wirings. A filler layer is disposed on the substrate and located within one of the second receiving sites. An upper trace layer is disposed on the first pixel structure and the second pixel structure. The upper trace layer includes multiple third traces that are respectively coupled to the first vertical diode chips and the second vertical diode chips. The third traces belong to the second polarity.

[0020] The inventors also proposed a method for repairing pixel structures, comprising: providing a substrate; forming a lower wiring layer on the substrate, the lower wiring layer including a first wiring and a second wiring, the first wiring belonging to a first polarity and the second wiring belonging to a second polarity; disposing a vertical diode die on the substrate and connecting it to the first wiring; and determining whether the vertical diode die is effective to decide whether to dispose of a flip-chip diode die on the substrate.

[0021] In some embodiments, the pixel structure repair method further includes, when it is determined that the vertical diode die is invalid, setting the flip-chip diode die on the substrate.

[0022] In some embodiments, the pixel structure repair method further includes: when it is determined that the vertical diode chip is invalid, setting the flip-chip diode chip on the substrate, wherein the flip-chip diode chip is a short-wavelength light-emitting diode chip; and coating a light conversion material layer on top of the flip-chip diode chip.

[0023] In some embodiments, the pixel structure repair method further includes: forming a plurality of blocks on the substrate, the plurality of blocks defining a plurality of accommodating sites; setting a plurality of vertical diode chips on the substrate and respectively located within the accommodating sites; and when it is determined that the vertical diode chips are all effective, setting a filling layer within the remaining accommodating sites, the remaining accommodating sites not containing the vertical diode chips.

[0024] In some embodiments, the pixel structure repair method further includes forming an upper trace layer on the plurality of vertical diode chips and the flip-chip diode chip, the upper trace layer including a third trace coupled to the vertical diode chip, the third trace belonging to the second polarity.

[0025] The inventors also propose a hybrid micro-light-emitting diode structure, comprising: a substrate; a red micro-light-emitting diode die disposed on the substrate; a green micro-light-emitting diode die disposed on the substrate; a blue micro-light-emitting diode die disposed on the substrate; a spare micro-light-emitting diode die disposed on the substrate; an isolation layer disposed on the substrate, the isolation layer surrounding the spare micro-light-emitting diode die and forming an inkjet space with the spare micro-light-emitting diode die, wherein the inkjet space is used to fill an inkjet material; a filling layer disposed on the substrate such that the red micro-light-emitting diode die, the green micro-light-emitting diode die, the blue micro-light-emitting diode die, the spare micro-light-emitting diode die, and the isolation layer are fixed on the substrate; and a light-transmitting layer disposed on the filling layer; wherein any one of the red micro-light-emitting diode die, the green micro-light-emitting diode die, the blue micro-light-emitting diode die, and the spare micro-light-emitting diode die is adjacent to at least one of the other three.

[0026] In some embodiments, the spare micro-LED die is an ultraviolet micro-LED die, and the light-transmitting layer comprises an anti-ultraviolet material.

[0027] In some embodiments, the spare microLED die is another blue microLED die.

[0028] In some embodiments, the spare microLED die is adjacent to the blue microLED die.

[0029] In some embodiments, the spare microLED die is more adjacent to the red microLED die or the green microLED die.

[0030] In some embodiments, the isolation layer comprises an opaque material that surrounds the spare microLED die and the inkjet space.

[0031] In some embodiments, the isolation layer includes an opaque material and an isolation material, wherein the opaque material surrounds the inkjet space and the isolation material surrounds the spare micro-LED die.

[0032] In some embodiments, when one of the red, green, and blue LED chips is damaged, the inkjet space is filled with an inkjet material of a color corresponding to that chip.

[0033] The inventors also propose a method for repairing a hybrid micro-LED structure, comprising: placing a red micro-LED chip, a green micro-LED chip, a blue micro-LED chip, and a spare micro-LED chip on a substrate; placing an insulating layer on the substrate to surround the spare micro-LED chip, such that the insulating layer and the spare micro-LED chip form an inkjet space; lighting up the red, green, and blue micro-LED chips respectively to check if any one of them is damaged; and when any one of the red, green, and blue micro-LED chips is damaged, performing the following steps: filling the inkjet space with an inkjet material corresponding to the color of the damaged red, green, and blue micro-LED chip.

[0034] In some embodiments, the spare microLED die is selected from an ultraviolet microLED die or another blue microLED die.

[0035] In some embodiments, the method for repairing a hybrid micro-LED structure further includes: when the red micro-LED chip, the green micro-LED chip, and the blue micro-LED chip are not damaged, performing the following steps: filling a substrate with a filler material to form a filler layer, wherein the filler layer is disposed on the substrate to fix the red micro-LED chip, the green micro-LED chip, the blue micro-LED chip, the spare micro-LED chip, and the isolation layer on the substrate; and disposing a light-transmitting layer on the filler layer.

[0036] The inventors also propose a panel structure comprising: a first diode die and a second diode die. The first diode die includes a first electrode having a first electrode thickness. The second diode die includes a second electrode having a second electrode thickness, the first electrode thickness being greater than the second electrode thickness, and the first diode die and the second diode die having substantially the same die height.

[0037] In some embodiments, the panel structure further includes a plurality of pixel structures, each including the first diode chip and the second diode chip, wherein the first electrode of the first electrode of the first diode chip of each pixel structure has substantially the same thickness, and the second electrode of the second electrode of the second diode chip of each pixel structure has substantially the same thickness.

[0038] In some embodiments, the first diode die and the second diode die are each a vertical diode die, and the first electrode and the second electrode are each a bottom electrode of the vertical diode die.

[0039] In some embodiments, the bottom electrode is a trapezoidal structure, and the thickness of the first electrode and the thickness of the second electrode are equal to the height of the trapezoidal structure.

[0040] In some embodiments, the panel structure further includes a third diode die, a third electrode having a third electrode thickness greater than the thickness of the second electrode, and the thickness of the first electrode being greater than the thickness of the third electrode. The first diode die, the second diode die, and the third diode die have substantially the same die height.

[0041] The inventors also proposed a method for manufacturing a diode die, comprising: providing a substrate; forming an epitaxial layer on the substrate; forming a connection layer on the epitaxial layer; disposing a bottom electrode layer on the connection layer; grinding the bottom electrode layer; and forming a top electrode layer below the epitaxial layer to form a first diode die.

[0042] In some embodiments, the method of manufacturing a diode die further includes: providing another substrate; forming another epitaxial layer on the other substrate; forming another interconnect layer on the other epitaxial layer; disposing another bottom electrode layer on the other interconnect layer; measuring a first height from the bottom of the substrate to the top of the bottom electrode layer; measuring a second height from the bottom of the other substrate to the top of the other bottom electrode layer; comparing the first height and the second height; and when it is determined that the first height is greater than the second height, grinding the bottom electrode layer until the first height decreases to the second height.

[0043] In some embodiments, the method for manufacturing a diode die further includes the step of not grinding the bottom electrode layer until the first height drops to the second height when it is determined that the second height is less than a lower limit height.

[0044] In some embodiments, the method of manufacturing a diode die further includes: forming another top electrode layer under the other epitaxial layer to form a second diode die; and transferring the first diode die and the second diode die to the same panel structure.

[0045] In some embodiments, there are multiple first diode chips and multiple second diode chips, and the panel structure includes multiple pixel structures, each pixel structure including one of the first diode chips and one of the second diode chips.

[0046] The inventors also propose a vertical micro-light-emitting diode (LED) unit, comprising: a first backplate and a second backplate. The first backplate includes a first substrate, a first circuit layer, a first contact pad, and a transparent electrode layer. The first circuit layer is disposed on the first substrate. The first contact pad is disposed on the first circuit layer. The transparent electrode layer is disposed on the first circuit layer and the first contact pad. The second backplate includes a second substrate, a second circuit layer, a eutectic metal layer, an alloy layer, a micro-light-emitting diode (LED) die, a second contact pad, and an isolation layer. The second circuit layer is disposed on the second substrate. The eutectic metal layer is disposed on the second circuit layer. The alloy layer is disposed on the eutectic metal layer. The LED die is disposed on the alloy layer. The second contact pad is disposed on the LED die. The isolation layer is disposed on the second substrate to surround the LED die. The first backplate is disposed on the second backplate to form a cavity, the projected areas of the first contact pad and the second contact pad along the normal direction of the first backplate at least partially overlap, and the transparent electrode layer connects the second contact pad and the isolation layer. When the first backplate is placed on the second backplate, the isolation layer deforms so that the thickness of the deformed isolation layer is equal to the sum of the thickness of the first contact pad, the thickness of the second circuit layer, the thickness of the eutectic metal layer, the thickness of the alloy layer, the thickness of the micro LED chip, and the thickness of the second contact pad.

[0047] In some embodiments, the chamber is in a vacuum state.

[0048] In some embodiments, the chamber is filled with an inert gas.

[0049] In some embodiments, the insulating layer comprises an opaque material.

[0050] In some embodiments, the isolation layer includes an opaque material and a translucent material, wherein the opaque material surrounds the micro-LED die and the second contact pad, and the translucent material surrounds the second circuit layer, the eutectic metal layer and the alloy layer.

[0051] In some embodiments, the alloy layer is trapezoidal in shape, with the upper base of the trapezoid connected to the eutectic metal layer and the lower base of the trapezoid connected to the micro-LED die.

[0052] The inventors also propose a vertical micro-light-emitting diode (LED) structure, comprising: a first LED unit, a second LED unit, and a third LED unit. The first LED unit comprises the vertical LED unit described in any of the preceding embodiments, wherein the LED chip of the first LED unit is a red LED chip. The second LED unit comprises the vertical LED unit described in any of the preceding embodiments, wherein the LED chip of the second LED unit is a green LED chip. The third LED unit comprises the vertical LED unit described in any of the preceding embodiments, wherein the LED chip of the third LED unit is a blue LED chip. Each of the first, second, and third LED units is adjacent to at least one of the other two.

[0053] In some embodiments, the thickness of the first contact pad of the second micro-LED unit and the thickness of the first contact pad of the third micro-LED unit are greater than the thickness of the first contact pad of the first micro-LED unit.

[0054] The inventors also propose a method for manufacturing a vertical micro-light-emitting diode (LED) unit, comprising: forming a first backplate; forming a second backplate; and disposing the first backplate on the second backplate to form a cavity. The step of forming the first backplate includes: disposing a first circuit layer on a first substrate; disposing a first contact pad on the first circuit layer; and disposing a transparent electrode layer on the first circuit layer and the first contact pad. The step of forming the second backplate includes: disposing a second circuit layer on a second substrate; disposing a micro-light-emitting diode (LED) die on the second circuit layer; disposing a second contact pad on the LED die; and disposing an isolation layer on the second substrate to surround the LED die. The projected areas of the first contact pad and the second contact pad along the normal direction of the first backplate at least partially overlap, and the transparent electrode layer connects the second contact pad and the isolation layer.

[0055] The inventors also propose a method for manufacturing a vertical micro-light-emitting diode (LED) structure, comprising: forming a first backplate; forming a second backplate; and disposing the first backplate on the second backplate to form a plurality of chambers. The step of forming the first backplate includes: disposing a plurality of first circuit layers on a first substrate; disposing a plurality of first contact pads on corresponding first circuit layers; and disposing a plurality of transparent electrode layers on corresponding first circuit layers and first contact pads. The step of forming the second backplate includes: disposing a plurality of second circuit layers on a second substrate; disposing a red LED chip, a green LED chip, and a blue LED chip on corresponding second circuit layers; disposing a plurality of second contact pads corresponding to the plurality of first contact pads on the red LED chip, green LED chip, and blue LED chip, respectively; and disposing an isolation layer on the second substrate to surround the red LED chip, green LED chip, and blue LED chip. The projected areas of each first contact pad and the corresponding second contact pad along the normal direction of the first back plate overlap at least partially, and each transparent electrode layer connects to the corresponding second contact pad and the isolation layer.

[0056] The inventors also propose a pre-alignment device suitable for multiple micro-LED units, comprising: a vibratory machine, an alignment disk, multiple electromagnets, and a controller. The vibratory machine includes multiple sidewalls and a base plate, with the sidewalls arranged around the perimeter of the base plate. The alignment disk is disposed on the base plate and includes multiple grooves arranged in an array. Each groove accommodates a micro-LED unit, and the bottom of each groove includes a through-hole. Each electromagnet is disposed in a through-hole and generates a magnetic field along the extension direction of the through-hole. The controller is electrically connected to the vibratory machine and the multiple electromagnets and controls the generation of the magnetic field by each electromagnet. The thickness of the alignment disk is less than the height of each sidewall.

[0057] In some embodiments, each groove is trapezoidal in shape, and the width of the bottom of each groove is smaller than the width of the top surface of each groove.

[0058] In some embodiments, each of the grooves is rectangular in shape.

[0059] The inventors also propose a pre-alignment method suitable for multiple micro-LED units, comprising: placing multiple micro-LED units on an alignment disk, wherein the alignment disk includes multiple grooves and each groove has a through hole at its bottom; generating an attractive force along the extension direction of the through hole; and generating a vibrational force to cause the alignment disk to vibrate, wherein each micro-LED unit vibrates and moves into its respective groove; wherein, in response to the attractive force being greater than the vibrational force, each micro-LED unit is fixed in its respective groove; and in response to the attractive force being less than the vibrational force, each micro-LED unit detaches from its respective groove.

[0060] In some embodiments, the attraction force is a magnetic attraction.

[0061] In some embodiments, each micro-LED unit includes a micro-LED die, a carrier layer, and a magnetic layer, wherein the carrier layer is disposed on the magnetic layer, and the micro-LED die is disposed on the carrier layer; wherein the height of each micro-LED unit is greater than the depth of each groove.

[0062] In some embodiments, the shape of the carrier layer and the shape of the magnetic conductive layer are both trapezoidal, and the width of the bottom of the magnetic conductive layer is smaller than the width of the bottom of each groove.

[0063] In some embodiments, the material of the carrier layer is conductive and non-magnetic.

[0064] In some embodiments, the pre-alignment method further includes: stopping the generation of the vibrational force in response to each of the micro-LED units being fixed in the respective grooves; and stopping the generation of the attractive force.

[0065] In some embodiments, the attractive force is a vacuum suction.

[0066] The inventors also propose an aligning device suitable for multiple micro-LED units, comprising a support disk and an aligning disk. The support disk includes multiple trenches. Each trench extends along a first direction and the multiple trenches are spaced apart along a second direction, and the first direction is orthogonal to the second direction. The aligning disk is disposed on the support disk. The aligning disk includes multiple columns, and the multiple columns are spaced apart along the second direction and each column is aligned with a trench. Each column is provided with multiple recesses, the bottom of each recess includes a through hole, and the multiple recesses in each column are spaced apart along the first direction.

[0067] In some embodiments, the alignment device further includes: a vacuum machine coupled to the plurality of trenches; and a controller electrically connected to the vacuum machine for controlling the vacuum machine.

[0068] In some embodiments, the array of trays includes a conductive film, and the conductive film is disposed on the wall surface of each of the grooves.

[0069] In some embodiments, the alignment device further includes: a tilting mechanism disposed on the lower surface of the support plate and electrically connected to the controller; wherein the controller is further used to control the tilting mechanism.

[0070] In some embodiments, the alignment device further includes: a vibrator disposed on the lower surface of the support plate and electrically connected to the controller; wherein the controller is further used to control the vibrator.

[0071] The inventors also propose a method for aligning multiple micro-light-emitting diode (LED) units, comprising: moving a pre-aligned plurality of LED units disposed on a carrier plate to a vertical position above an aligning disk, wherein the aligning disk includes a plurality of grooves, each groove including a through hole at its bottom, and each LED unit being aligned with each groove; and generating an attractive force along the extension direction of the through hole to attract each LED unit from the carrier plate to the bottom of each groove.

[0072] In some embodiments, the attractive force is a vacuum suction.

[0073] In some embodiments, the aligning method further includes: stopping the generation of the attractive force; placing a transparent cover plate above the aligning tray, wherein a conductive film is formed on the lower surface of the transparent cover plate, and a conductive film is also formed on the wall surface of each of the grooves of the aligning tray; and energizing the plurality of micro-light-emitting diode units through the conductive film of the transparent cover plate and the conductive film of the aligning tray.

[0074] In some embodiments, the aligning method further includes: removing the transparent cover plate; and removing the damaged plurality of micro-light-emitting diode units.

[0075] In some embodiments, the alignment method further includes: stopping the generation of the attractive force; and tilting the alignment disk so that each of the micro-LED units aligns with a wall of the respective recess.

[0076] In some embodiments, the alignment method further includes: stopping the generation of the attractive force; and generating a vibrational force to cause the alignment disk to vibrate; wherein, in response to the vibration of the alignment disk, each of the micro-LED units aligns with a wall of the respective groove. Attached Figure Description

[0077] Figure 1 These are cross-sectional views of the pixel structure in some embodiments;

[0078] Figure 2A This is a schematic diagram of the layered structure of a vertical diode die in some embodiments;

[0079] Figure 2B This is a schematic diagram of the layered structure of a flip-chip diode die in some embodiments;

[0080] Figure 3A These are schematic diagrams illustrating the configuration of vertical diode chips in some embodiments;

[0081] Figure 3B These are schematic diagrams illustrating the configuration of flip-chip diode chips in some embodiments;

[0082] Figures 4A to 4D These are top views of the pixel structure in different embodiments;

[0083] Figure 5 These are top views of the panel structure in some embodiments;

[0084] Figure 6 This is a flowchart of the pixel structure repair method in the first embodiment;

[0085] Figures 7A to 7H This is a schematic diagram of the manufacturing process of the pixel structure repair method in the first embodiment;

[0086] Figure 8 This is a flowchart of the pixel structure repair method of the second embodiment;

[0087] Figures 9A to 9C This is a schematic diagram of the manufacturing process of the pixel structure repair method in the second embodiment;

[0088] Figure 10 This is a flowchart of the pixel structure repair method in the third embodiment;

[0089] Figure 11 This is a schematic diagram of the manufacturing process of the pixel structure repair method in the third embodiment;

[0090] Figure 12 This is a top plan view of the hybrid micro-light-emitting diode structure of the fourth embodiment;

[0091] Figure 13 yes Figure 12 A cross-sectional view of the hybrid micro-light-emitting diode structure along section line 2-2;

[0092] Figure 14 This is a top plan view of the hybrid micro-light-emitting diode structure of the fifth embodiment;

[0093] Figure 15 yes Figure 12 A flowchart illustrating the operation of an embodiment of a hybrid micro-light-emitting diode structure;

[0094] Figure 16 yes Figure 15 A flowchart illustrating the operation of an embodiment of the subsequent step S42;

[0095] Figure 17 yes Figure 12 A cross-sectional view of the hybrid micro-light-emitting diode structure along section line 2-2;

[0096] Figure 18 This is a schematic diagram of several diode dies with different grain heights in some embodiments;

[0097] Figure 19 This is a flowchart of a method for manufacturing diode chips according to some embodiments;

[0098] Figures 20A to 20K This is a schematic diagram of a method for manufacturing a diode die according to some embodiments;

[0099] Figure 21 These are schematic diagrams of diode chips in some embodiments;

[0100] Figure 22 This is a schematic diagram comparing the heights of multiple semi-finished substrates according to some embodiments;

[0101] Figure 23 This is a flowchart of a method for manufacturing diode chips according to other embodiments;

[0102] Figures 24A to 24B This is a schematic diagram of a method for manufacturing a diode die according to other embodiments;

[0103] Figure 25 These are schematic diagrams of the panel structure in some embodiments;

[0104] Figure 26 This is a side plan view of the vertical micro-light-emitting diode unit of the sixth embodiment;

[0105] Figure 27 yes Figure 26 Side plan view of one embodiment of the first backplate;

[0106] Figure 28 yes Figure 26 Side plan view of one embodiment of the second backplate;

[0107] Figure 29 yes Figure 26 A partial exploded view of a vertical micro-light-emitting diode unit;

[0108] Figure 30 yes Figure 26 A top plan view of one embodiment of the first backplate;

[0109] Figure 31 yes Figure 26 A top plan view of one embodiment of the second backplate;

[0110] Figure 32 yes Figure 26 A flowchart illustrating the operation of an embodiment of a vertical micro-light-emitting diode unit;

[0111] Figure 33 This is a side plan view of the vertical micro-light-emitting diode unit of the seventh embodiment;

[0112] Figure 34 These are side plan views of vertical micro-light-emitting diode structures according to some embodiments;

[0113] Figure 35 yes Figure 34 Side plan view of one embodiment of the first backplate;

[0114] Figure 36 yes Figure 34 Side plan view of one embodiment of the second backplate;

[0115] Figure 37 yes Figure 34 A partial exploded view of a vertical micro-light-emitting diode unit;

[0116] Figure 38 yes Figure 34 A top plan view of one embodiment of the first backplate;

[0117] Figure 39 yes Figure 34 A top plan view of one embodiment of the second backplate;

[0118] Figure 40 yes Figure 34 A flowchart illustrating the operation of an embodiment of a vertical micro-light-emitting diode structure;

[0119] Figure 41 This is a side view schematic diagram of the pre-alignment device according to the eighth embodiment;

[0120] Figure 42 yes Figure 41 A top view of the pre-alignment unit;

[0121] Figure 43 These are flowcharts illustrating the operation of the pre-alignment device in some embodiments;

[0122] Figure 44 yes Figure 41 Schematic diagram of the operation of the pre-training unit;

[0123] Figure 45 yes Figure 44 A partial enlarged view of the pre-alignment device according to the eighth embodiment;

[0124] Figure 46 yes Figure 44 A partial enlarged view of the pre-alignment device according to the ninth embodiment;

[0125] Figure 47 This is a side view schematic diagram of the pre-alignment device according to the ninth embodiment;

[0126] Figure 48 This is a side view schematic diagram of the aligning device according to the tenth embodiment;

[0127] Figure 49 yes Figure 48 A top view schematic diagram of one embodiment of the central support plate;

[0128] Figure 50 yes Figure 48 A top view schematic diagram of an embodiment of a central array disk;

[0129] Figure 51 yes Figure 48 A flowchart illustrating the operation of an embodiment of the alignment device;

[0130] Figure 52 yes Figure 48 A schematic diagram of the first demonstration state of the alignment device;

[0131] Figure 53 yes Figure 48 A schematic diagram of the first demonstration state of the alignment device;

[0132] Figure 54 yes Figure 51 The operation flowchart of the next step S11;

[0133] Figure 55 This is a side view of the aligning device according to the eleventh embodiment;

[0134] Figure 56 yes Figure 55 A schematic diagram of the first demonstration state of the alignment device;

[0135] Figure 57 yes Figure 55 A schematic diagram of the second demonstration state of the alignment device;

[0136] Figure 58 yes Figure 51 The operation flowchart of the next step S11;

[0137] Figure 59 This is a block diagram of the aligning device according to the twelfth embodiment;

[0138] Figure 60 yes Figure 48 Side view of the alignment device;

[0139] Figure 61 yes Figure 51 The operation flowchart of the next step S11;

[0140] Figure 62 This is a block diagram of the aligning device according to the thirteenth embodiment;

[0141] Figure 63 yes Figure 62 A side view of the alignment device.

[0142] Symbol explanation:

[0143] 1: Array device

[0144] 10: Support level

[0145] 100: Trench

[0146] 11: Array of disks

[0147] 110: Groove

[0148] 111: Through hole

[0149] 12: Micro LED Unit

[0150] 13: Carrier board

[0151] 13': Carrier plate

[0152] 131: Substrate layer

[0153] 132: Thin film layer

[0154] 133: Bump

[0155] 134: Conductive film

[0156] 14: Vacuum machine

[0157] 15: Controller

[0158] 16: Conductive film

[0159] 17: Tilting Mechanism

[0160] 18: Vibration machine

[0161] F11: Attraction

[0162] F12: Vibration force

[0163] R11: Column

[0164] R12: Column

[0165] R13: column

[0166] R14: Column

[0167] R15: Column

[0168] R16: Column

[0169] RX: column

[0170] S10: Steps

[0171] S11: Steps

[0172] S12: Steps

[0173] S13: Steps

[0174] S14: Steps

[0175] S15: Steps

[0176] S16: Steps

[0177] S17: Steps

[0178] S18: Steps

[0179] TC1: Transparent cover

[0180] 2: Pre-alignment device

[0181] 20: Vibration machine

[0182] 201: Sidewall

[0183] 202: Base Plate

[0184] 21: Array of disks

[0185] 210: Groove

[0186] 211: Through hole

[0187] 22: Electromagnet

[0188] 23: Controller

[0189] 24: Micro LED Unit

[0190] 241: Micro LED chip

[0191] 242: Bearing layer

[0192] 243: Magnetic layer

[0193] F21: Attraction

[0194] F22: Vibration force

[0195] R21: Dashed box

[0196] R22: Dashed box

[0197] S20: Step

[0198] S21: Steps

[0199] S22: Steps

[0200] S23: Steps

[0201] S24: Steps

[0202] 3: Vertical micro-light-emitting diode structure

[0203] 30: Vertical micro LED unit

[0204] 30B: Micro LED Unit

[0205] 30G: Micro LED Unit

[0206] 30R: Micro LED Unit

[0207] 31: First backplate

[0208] 310: First substrate

[0209] 311: First Circuit Layer

[0210] 311B: First circuit layer

[0211] 311G: First Circuit Layer

[0212] 311R: First circuit layer

[0213] 312: First contact pad

[0214] 312B: First contact pad

[0215] 312G: First contact pad

[0216] 312R: First contact pad

[0217] 313: Transparent electrode layer

[0218] 313B: Transparent Electrode Layer

[0219] 313G: Transparent Electrode Layer

[0220] 313R: Transparent Electrode Layer

[0221] 32: Second backplate

[0222] 320: Second substrate

[0223] 321: Second Circuit Layer

[0224] 321B: Second Circuit Layer

[0225] 321G: Second Circuit Layer

[0226] 321R: Second Circuit Layer

[0227] 322: Eutectic metal layer

[0228] 323: Alloy layer

[0229] 324: Micro LED chip

[0230] 324B: Micro LED chip

[0231] 324G: Micro LED chip

[0232] 324R: Micro LED chip

[0233] 325: Second contact pad

[0234] 325B: Second contact pad

[0235] 325G: Second contact pad

[0236] 325R: Second contact pad

[0237] 326: Isolation layer

[0238] 326A: Opaque material

[0239] 326B: Translucent material

[0240] 327: Chamber

[0241] A1: Axis

[0242] A2: Axis

[0243] A3: Axis

[0244] L1: Thickness

[0245] L2: Thickness

[0246] S30~S35: Steps

[0247] S300~S302: Steps

[0248] S310~S313: Steps

[0249] S330~S332: Steps

[0250] S340~S343: Steps

[0251] 40: Hybrid Micro-LED Structure

[0252] 400:Substrate

[0253] 410: Micro LED chip

[0254] 410R: Red micro-LED chip

[0255] 410G: Green micro LED chip

[0256] 410B: Blue micro LED chip

[0257] 410S: Spare micro LED chip

[0258] 420: Isolation layer

[0259] 420A: Opaque material

[0260] 420B: Insulation Material

[0261] 430: Fill layer

[0262] 440: Translucent layer

[0263] 450: Inkjet Space

[0264] IM: Inkjet Materials

[0265] S40~S45: Steps

[0266] 50: Pixel Structure

[0267] 500:Substrate

[0268] 510: Lower cabling layer

[0269] 511: First route

[0270] 512: Second route

[0271] 513: Lower electrode

[0272] 520, V1, V2, V3: Vertical diode chips

[0273] V2', V3': Ineffective vertical diode die

[0274] 521: First electrode

[0275] 522: First doped layer

[0276] 523: The First Quantum Well

[0277] 524: Second doped layer

[0278] 525: Second electrode

[0279] 526: First light conversion material layer

[0280] 530, F: Flip-chip diode die

[0281] 531: Third electrode

[0282] 532: Third doped layer

[0283] 533: The Second Quantum Well

[0284] 534: Fourth doped layer

[0285] 535: Fourth electrode

[0286] 536: Substrate layer

[0287] 537: Second light conversion material layer

[0288] 538: First fill layer

[0289] 539: Second filler layer

[0290] 540: Upper wiring layer

[0291] 541: Third route

[0292] 542: Upper electrode

[0293] 550: First stop

[0294] 551: Accommodation site

[0295] 560: Second stop

[0296] 570: Protective layer

[0297] 580: Third filler layer

[0298] 51: Panel Structure

[0299] S511~S519: Steps

[0300] S521~S5212: Steps

[0301] S531~S5312: Steps

[0302] 600: Panel Structure

[0303] 60: Diode die

[0304] 601: First diode die

[0305] 602: Second diode die

[0306] 603: Third Diode Chip

[0307] 601': First diode substrate

[0308] 602': Second diode substrate

[0309] 603': Third diode substrate

[0310] 61, 611, 612, 613: First substrate

[0311] 62, 621, 622, 623: Top electrode

[0312] 63, 631, 632, 633: Epitaxial layers

[0313] 64, 641, 642, 643: Bottom electrodes

[0314] 65, 651, 652, 653: Second substrate

[0315] 66: First Connector Layer

[0316] 67: Second Connecting Layer

[0317] 68, 681, 682, 683: Conductor layer

[0318] 69: Third substrate

[0319] G6: Grinding machine

[0320] BL1: First baseline

[0321] BL2: Second baseline

[0322] BL3: Third baseline

[0323] BL4: Fourth Baseline

[0324] D61, D62, D63: Thickness

[0325] H61, H62, H63: Height

[0326] S601~S612: Steps

[0327] S6051~S6054: Steps Detailed Implementation

[0328] To make the objectives, means, and effects of the technical means disclosed in different embodiments of the present invention more readily understood, the following description, in conjunction with the accompanying drawings, provides a detailed explanation of specific embodiments of the proposed technical means. The descriptions of technical means in the following embodiments of the present invention are merely illustrative and do not represent all embodiments of the present invention, nor do they limit the present invention to specific embodiments. All other embodiments obtained by those skilled in the art based on different embodiments of the present invention without excessive experimentation should fall within the scope of protection of the present invention. Unless otherwise defined, all technical and technical terms used in the present invention have the same meaning as commonly understood by those skilled in the art. The terminology used in the present invention is for the purpose of describing specific implementations only and is not intended to limit the present invention.

[0329] It should be noted that when a component is referred to as being "located" on another component, it can be directly on the other component and in direct physical or electrical contact with each other; or it can include components existing between the two and indirect physical or electrical contact with each other. When a component is referred to as being "connected," "coupled," "located," or "electrically connected" to another component, it can be two or more components in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other.

[0330] In all descriptions related to specific numerical values ​​in this invention, although not directly described, they all contain the meaning of "approximately" or "substantially," that is, these specific numerical values ​​will cover the possible range of numerical error, used to represent the range of error implied by possible unintended effects and deviations in the manufacturing process or material selection. The error range can include a range of changes that do not significantly alter the material, structure, configuration, properties, or effect, for example, a range of deviations from 0% to 10%, wherein such error range is clear to those skilled in the art. For example, describing "two objects are substantially parallel," but if a slight height difference is observed between the two objects, but this difference is negligible relative to the size of the objects themselves (e.g., less than 10%) and does not affect the effect, then the observed relative configuration between the two objects will still be interpreted as falling within the range of "substantially parallel" as described in this invention.

[0331] The terms "vertical," "horizontal," "left," "right," "up," "down," "inner," "outer," "front," "back," and similar expressions used in this invention are merely to indicate relative positional relationships based on the accompanying drawings and do not limit the elements using these terms to implementation only in the indicated manner. When the absolute position of the described object changes, the description of the relative position may also change accordingly.

[0332] The term "column" as used in this invention is not limited to multiple units arranged sequentially "from left to right" and "from right to left" in the accompanying drawings. Multiple units arranged sequentially "from top to bottom" and "from bottom to top" in the accompanying drawings can also be referred to as a "column." The "trapezoidal" configuration mentioned in this invention refers to a configuration where the width of the upper base is smaller than the width of the lower base, but this is not intended to limit the configuration of the "trapezoidal" configuration. In other words, a "trapezoidal" configuration where the width of the upper base is greater than the width of the lower base is still within the scope of the claims of this invention.

[0333] The terms "a" or "an" as used in this invention are used to describe the elements and components of the invention. These terms are for ease of description and to give the basic concept of the invention. This description should be understood to include one or at least one, and unless explicitly stated otherwise, the singular includes the plural. The term "comprising" is an open-ended term and should therefore be interpreted as "including but not limited to". The term "and / or" as used in this invention includes any and all combinations of one or more of the associated listed items.

[0334] The terms “a,” “another,” “first,” “second,” and “third” used in this invention are used to distinguish the elements referred to, and unless otherwise specified, are not used to order or limit the differences between the elements referred to, nor are they used to limit the scope of this invention.

[0335] Figure 1This is a cross-sectional view of the pixel structure according to some embodiments; please refer to... Figure 1 In this embodiment, the pixel structure 50 includes a substrate 500, a plurality of vertical diode chips 520, flip-chip diode chips 530, and an upper wiring layer 540. The plurality of vertical diode chips 520 and flip-chip diode chips 530 are disposed above the substrate 500, and the upper wiring layer 540 is disposed above the plurality of vertical diode chips 520 and flip-chip diode chips 530. "Above" can be, but is not limited to, directly above; for example, Figure 1 The upper wiring layer 540 has a third wiring 541. The third wiring 541 can be connected to the upper electrode 542 directly above the vertical diode die 520 only through a thin strip-shaped finger electrode structure. Simultaneously, the third wiring 541 does not pass directly above the flip-chip diode die 530. A lower wiring layer 510 can be disposed above the substrate 500. The lower wiring layer 510 includes a first wiring 511 and a second wiring 512. Part of the first wiring 511 is connected to the lower electrode 513 of the vertical diode die 520, one first wiring 511 is connected to the lower electrode 513 of the flip-chip diode die 530, and the second wiring 512 is connected to the other lower electrode 513 of the flip-chip diode die 530. It should be understood that... Figure 1 The illustrated layout of the bottom trace layer 510 is merely an example for illustrative purposes and does not limit the bottom trace layer 510 to be located inside the substrate 500. The bottom trace layer 510 can also be disposed on the surface of the substrate 500. In other words, the substrate 500 can be a single-sided, double-sided, or multi-layer circuit board.

[0336] The main difference between the first trace 511 and the second trace 512 lies in their polarity. Therefore, the first trace 511 belongs to the first polarity, and the second trace 512 belongs to the second polarity; furthermore, the third trace 541 also belongs to the second polarity. The polarities of the first and second polarities are opposite; that is, when the first polarity is P, the second polarity is N; and when the first polarity is N, the second polarity is P. Figure 2A This is a schematic diagram of the layered structure of a vertical diode die according to some embodiments; Figure 2B This is a schematic diagram of the layered structure of a flip-chip diode die according to some embodiments. Please refer to it as well. Figure 1 , Figure 2A and Figure 2B .

[0337] like Figure 2AAs shown, the layered structure of the vertical diode chip 520 can be roughly divided into a first electrode 521, a first doped layer 522, a first quantum well 523, a second doped layer 524, and a second electrode 525. The first electrode 521 and the second electrode 525 have opposite polarities, and the electrodes can be conductive materials, such as metals. The first doped layer 522 and the second doped layer 524 have opposite polarities, and the doped layers can be P-type or N-type doped layers. The doping elements are selected according to the number of valence electrons of the layer material to form P-type or N-type doped layers. For example, the layer material of the doped layer is gallium nitride (GaN), the dopant of the P-type doped layer can be magnesium (Mg) of group 2, and the dopant of the N-type doped layer can be silicon (Si) of group 5. The quantum well is used to confine the movement of charge carriers to form a quantum binding effect, thereby improving the luminous efficiency of the diode chip. The first electrode 521 is used to connect the first trace 511 and belongs to the first polarity, while the second electrode 525 is used to connect the third trace 541 and belongs to the second polarity. The first electrode 521 and the second electrode 525 are arranged in a vertical direction, and the current (electron flow) of the first trace 511 flows to the third trace 541 through the vertical diode chip 520.

[0338] like Figure 2B As shown, the layered structure of the flip-chip diode die 530 can be roughly divided into a third electrode 531, a third doped layer 532, a second quantum well 533, a fourth doped layer 534, a fourth electrode 535, and a substrate layer 536. The polarities of the third electrode 531 and the fourth electrode 535 are opposite, and the polarities of the third doped layer 532 and the fourth doped layer 534 are also opposite. The substrate layer 536 is used in the die fabrication process to support the layered structure, such as a sapphire substrate 500. In some embodiments, the flip-chip diode die 530 may not have a substrate layer 536. The third electrode 531 is used to connect to the first trace 511 and belongs to the first polarity, while the fourth electrode 535 is used to connect to the second trace 512 and belongs to the second polarity. The third electrode 531 and the fourth electrode 535 are arranged horizontally, and the current (electron flow) of the first trace 511 flows through the flip-chip diode die 530 to the second trace 512.

[0339] Reference Figure 1 In some embodiments, the vertical diode dies 520 have color categories, and the color categories of multiple vertical diode dies 520 included in the same pixel structure 50 are different. For example, such as Figure 1As shown, this embodiment includes three vertical diode chips 520, which are red, green, and blue, respectively. The color category can be defined according to the main wavelength of the emitted light from the diode chip, or according to the manufacturer's nominal specifications. The flip-chip diode chip 530 also has a color category; in this embodiment, the flip-chip diode chip 530 can be red, green, or blue. It should be understood that the color categories of the vertical diode chips 520 and the flip-chip diode chips 530 are not limited to red, green, and blue. Furthermore, in some other embodiments, the vertical diode chips 520 and / or the flip-chip diode chips 530 themselves do not have a color category, but the light beam corresponding to the vertical diode chip 520 or the flip-chip diode chip 530 has a color category, which will be described in detail later.

[0340] In some embodiments, the pixel structure 50 includes a substrate 500, a plurality of vertical diode dies 520, a flip-chip diode die 530, an upper wiring layer 540, a plurality of first blocks 550, and a second fill layer 539. For example... Figure 1 As shown, the pixel structure 50 includes a first block 550, which defines four receiving sites. A vertical diode die 520 and a flip-chip diode die 530 are respectively located within these receiving sites. Furthermore, a third trace 541 is primarily disposed directly above the first block 550. The first block 550 serves to prevent light emitted by the diode die from interfering with adjacent diode dies. Therefore, in this embodiment, the first block 550 surrounds the diode die with an opaque material. In some embodiments, the opaque material can be a black matrix (BM) material or a light-reflective material, such as, but not limited to, alumina, dielectric multilayer films, and reflective resin materials. A second filler layer 539 covers the flip-chip diode die 530, and the top surface of the second filler layer 539 is substantially coplanar with the top surface of the first block 550. The second filler layer 539 can be a light-transmitting material to allow light emitted by the flip-chip diode die 530 to pass through it. The light-transmitting material may be, but is not limited to, silicone, epoxy resin, polyimide, benzocyclobutene, perfluorocyclobutane, SU8 photoresist, acrylic resin, polyethylene phthalate, and polyetherimide.

[0341] Figure 3A This is a schematic diagram of the configuration of vertical diode chips according to some embodiments; Figure 3B This is a schematic diagram illustrating the configuration of flip-chip diodes according to some embodiments. Please refer to it as well. Figure 3A and Figure 3BWhen a vertical diode die 520 is disposed on the substrate 500, the first electrode 521 of the vertical diode die 520 is connected to the lower electrode 513 on the surface of the substrate 500, while the second electrode 525 of the vertical diode die 520 is not yet connected to the trace, thus forming an open circuit. Conversely, when a flip-chip diode die 530 is disposed on the substrate 500, the third electrode 531 and the fourth electrode 535 of the flip-chip diode die 530 are respectively connected to the lower electrode 513 on the surface of the substrate 500, thus forming a conductive state. Therefore, the flip-chip diode die 530 can be tested immediately after being transferred to the substrate 500 to confirm whether there are defects in the diode die itself; or whether there are defects in the connection state between the diode die and the substrate 500. However, the vertical diode die 520 can only be tested after the upper trace layer 540 is formed at the end of the packaging process. This makes it difficult to replace the vertical diode die 520 in the pixel structure 50 after most of the packaging process has been completed.

[0342] Figures 4A to 4D These are top views of the pixel structure based on different embodiments; please refer to them as well. Figures 4A to 4D In this embodiment, the pixel structure 50 includes vertical diode chips V1, V2, and V3, and a flip-chip diode chip F. The arrangement of the flip-chip diode chip F with the other vertical diode chips V1, V2, and V3 can be arbitrarily combined. In some embodiments, all pixel structures 50 contained in the same panel structure 51 have the same arrangement relationship, for example... Figure 4A The pixel structures 50 are periodically configured. In other embodiments, the same panel structure 51 may contain pixel structures 50 with various arrangements, such as... Figure 4A and Figure 4B The pixel structures 50 are arranged in an alternating periodic configuration. Each pixel structure 50 contains four accommodating sites, such as... Figure 4A As shown, the accommodating site in the upper left corner corresponds to the flip-chip diode die F. In some embodiments, the first trace 511 of the substrate 500 forms the lower electrode 513 at each accommodating site, while the second trace 512 forms the lower electrode 513 only at the accommodating sites corresponding to the flip-chip diode die F.

[0343] Within the vertical diode dies V1, V2, and V3, there may be both valid and invalid vertical diode dies 520. In some embodiments, a valid vertical diode die 520 refers to a diode die itself or its connection with the substrate 500 that is free from defects, while an invalid vertical diode die 520 refers to a diode die itself or its connection with the substrate 500 that is defective. These defects are defined according to the yield standards of the manufacturing process. For example, a beam intensity threshold at a specific wavelength is used as the defect criterion. In other embodiments, a valid vertical diode die 520 refers to a diode die and its attachments that produce a light-emitting effect free from defects, while an invalid vertical diode die 520 refers to a diode die and its attachments that produce a light-emitting effect that is defective, as will be described in detail later.

[0344] Figure 5 This is a top view of the panel structure according to some embodiments; please refer to... Figure 5 In this embodiment, Figure 4D The pixel structures 50 are periodically arranged to form the panel structure 51. This embodiment only shows four groups of pixel structures 50 included in the panel structure 51. Figure 5 The pixel structure 50 in the upper left corner contains an invalid vertical diode die V2'. Figure 5 The pixel structure 50 in the lower right corner contains invalid vertical diode dies V3', and these pixel structures 50 are defined as the first pixel structure 50. Figure 5 The vertical diode chips 520 included in the pixel structures 50 at the upper right and lower left are all valid vertical diode chips 520, and these pixel structures 50 are defined as the second pixel structure 50. In this embodiment, the flip-chip diode chip F can be used to replace the invalid vertical diode chips V2', V3'. Specifically, in this embodiment, the pixel structure 50 includes vertical diode chips 520 of various color categories. When any color category of vertical diode chip 520 is invalid, the pixel structure 50 will be unable to generate a light beam of that color category, resulting in a defect; and, as mentioned above, the replacement process of the vertical diode chip 520 is relatively complex. In this embodiment, the flip-chip diode chip F is disposed within the pixel structure 50 having invalid vertical diode chips V2', V3' to generate a light beam of that color category. Thus, a specific type of flip-chip diode chip F can be selected and directly configured at a preset receiving site to replace the invalid vertical diode chips V2', V3'. In addition, the installed flip-chip diode die F can be inspected immediately to ensure that there are no defects.

[0345] In some embodiments, the color category of the flip-chip diode die F is the same as that of the ineffective vertical diode dies V2', V3'. Therefore, the light beam generated by the flip-chip diode die F can cover the spectral range originally intended to be covered by the ineffective vertical diode dies V2', V3'. In some embodiments, a specific pixel structure 50 includes ineffective vertical diode dies V2', V3', and the color category of the flip-chip diode die F is different from the color category of the effective vertical diodes included in the specific pixel structure 50. Therefore, the light beam generated by the flip-chip diode die F can cover the spectral range that the light beam generated by the specific pixel structure 50 cannot cover. In some embodiments, the second pixel structure 50 includes receiving sites corresponding to the flip-chip diode die F, filled with a third filler layer 580. The third filler layer 580 can be used to seal the substrate 500 at the lower electrode 513 of the receiving site, and can be made of the light-transmitting or opaque material described in this invention. In some embodiments, the third filler layer 580 can also be made of the same material as the first stop 550 or the second filler layer 539. In this embodiment, the panel structure 51 includes both a first pixel structure 50 and a second pixel structure 50. In other words, each pixel structure 50 on the panel structure 51 does not necessarily include a flip-chip diode F, and each pixel structure 50 on the panel structure 51 does not necessarily include a third filler layer 580. Furthermore, the panel structure 51 may include invalid vertical diodes V2' and V3', or these may be removed.

[0346] Figure 6 This is a flowchart of the pixel structure repair method according to the first embodiment; Figures 7A to 7H This is a schematic diagram of the manufacturing process of the pixel structure repair method according to the first embodiment. Please refer to... Figure 6 Refer to the steps in sequence Figures 7A to 7H In some embodiments, the pixel structure 50 repair method (hereinafter referred to as the "repair method") can be used to repair pixels containing invalid vertical diode dies V2', V3' to produce pixel structure 50. The repair method is described below with reference to different embodiments. It should be understood that although the flowcharts of the present invention are presented in a specific order, the order is only illustrative and other implementations with different orders are expected.

[0347] Please refer to Figure 7AThe repair method provides a substrate 500 (step S511) and configures a lower electrode 513 and traces on the substrate 500 (step S512). In this embodiment, a first trace 511 and a second trace 512 are provided on the substrate 500 and are respectively connected to the lower electrode 513. The lower electrode 513 is disposed at a specific position on the substrate 500, which is equivalent to a receiving site. Among them, a pair of lower electrodes 513 are provided within the specific receiving site, which are suitable for connecting the flip-chip diode chip 530. The traces respectively connected to the pair of lower electrodes 513 are the first trace 511 and the second trace 512. The substrate 500 may be made of, but is not limited to, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), silicon carbide (SiC), glass, silicone, epoxy resin, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), and polyetherimide. The lower electrode 513 and the wiring may be made of conductive materials, such as metal, and the forming methods may include, but are not limited to, coating, electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), zone selective deposition (ASD), and atomic layer deposition (ALD).

[0348] Please refer to Figure 7B The repair method involves setting a vertical diode die 520 on the substrate 500 (step S513). The vertical diode die 520 is disposed on the substrate 500, and its first electrode 521 can be electrically connected to the lower electrode 513 of the lower trace layer 510 by soldering. (Refer to...) Figure 7C The repair method forms a first stop 550 on the substrate 500 (step S514). The first stop 550 can be formed on the surface of the substrate 500, or it can be attached to the surface of the substrate 500 after forming. The first stop 550 forms receiving sites 551 around the positions of each lower electrode 513. Figure 7C Two of the accommodating sites 551 contain vertical diode chips 520, and one accommodating site 551 is a vacancy. The substrate 500 surface at the bottom of the vacancy has a lower electrode 513 connected to different traces.

[0349] Please refer to Figure 7DThe repair method forms a first filling layer 538 between the first blocks 550 (step S515). The first filling layer 538 is used to cover and protect the vertical diode die 520, exposing only a portion of the second electrode 525; in addition, the first filling layer 538 can also be used to cover and protect the lower electrode 513 within the vacancy, exposing only a portion of the lower electrode 513. The first filling layer 538 can be made of a light-transmitting material or an opaque material as described in this invention, and the materials used for different accommodating sites 551 can be different. For example, the vertical diode die 520 is covered with a first filling layer 538 formed of a light-transmitting material, while the vacancy can be covered with a first filling layer 538 formed of an opaque material.

[0350] Please refer to Figure 7E The repair method involves configuring the upper electrode 542 and the traces on the first filling layer 538 (step S516). In this embodiment, the upper electrode 542 is disposed on the vertical diode die 520 and electrically connected to the second electrode 525 of the vertical diode die 520. The upper trace layer 540 is disposed on the upper electrode 542 and the first stop 550 to form a third trace 541. The third trace 541 mainly passes directly above the first stop 550 and extends to the surface of the upper electrode 542 through a thin strip structure. The upper electrode 542 is a light-transmitting conductive material, such as, but not limited to, indium tin oxide (ITO), zinc oxide (ZnO), fluorine-doped tin oxide (FTO), graphene, and poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate (PEDOT:PSS). The upper trace is made of conductive material and can be formed on the upper electrode 542 and the first stop block 550 using the trace fabrication process described in this invention.

[0351] In step S517, the repair method determines whether each pixel contains invalid vertical diode chips V2' and V3'. For example, the repair method provides a power supply and electrically connects the first trace 511 to the first polarity of the power supply and the third trace 541 to the second polarity of the power supply, allowing current to flow through each vertical diode. Subsequently, the repair method uses a camera to photograph each pixel structure 50 to determine whether the pixel structure 50 does not generate a beam of a specific color category, or whether the beam intensity at a specific accommodating point 551 does not reach an intensity threshold, in order to determine whether each vertical diode chip 520 within the pixel structure 50 is valid. When the repair method determines that each pixel does not contain invalid vertical diode chips V2' and V3' (step S517, the determination result is "No"), a filling layer is formed between the first blocks 550 (step S518), for example, forming a third filling layer 580 in the vacancy. In some embodiments, a third filler layer 580 fills the receiving site 551 until the top surface of the third filler layer 580 is substantially coplanar with the top surface of the first stop 550.

[0352] When the repair method determines that any pixel contains invalid vertical diode chips V2' and V3' (step S517, the determination result is "yes"), then a flip-chip diode chip 530 is set (step S519). In some embodiments, between steps S517 and S519, the repair method further determines whether the number of invalid vertical diode chips V2' and V3' is greater than a quantity threshold (not shown). The quantity threshold may refer to the defect acceptance standard of the panel structure 51 (containing multiple pixel structures 50). When the repair method determines that the number of invalid vertical diode chips V2' and V3' is less than the quantity threshold, step S518 is executed; when the repair method determines that the number of invalid vertical diode chips V2' and V3' is greater than or equal to the quantity threshold, step S519 is executed.

[0353] Please refer to the above as well. Figure 7F and Figure 7G In this embodiment, the repair method determines the state of a specific pixel structure 50 to determine the presence and / or color category of a defect. The repair method selects a specific flip-chip diode die 530 and transfers it to the receiving site 551 of the pixel structure 50 using an aspirating method. The color category of the specific flip-chip diode die 530 corresponds to the color category of the defect. Subsequently, please refer to... Figure 7H The repair method forms a filling layer between the first blocks 550 (step S518), for example, forming a second filling layer 539 on the flip-chip diode die 530. In this embodiment, the second filling layer 539 fills the receiving site 551 until the top surface of the second filling layer 539 is substantially coplanar with the top surface of the first block 550.

[0354] Figure 8 This is a flowchart of the pixel structure repair method according to the second embodiment; Figures 9A to 9C This is a schematic diagram of the manufacturing process of the pixel structure repair method according to the second embodiment. Please refer to it. Figure 8 Refer to the steps in sequence Figures 9A to 9CThe main difference between the second embodiment and the first embodiment lies in steps S527 to S5212. In this embodiment, the vertical diode chip 520 itself does not have a color category. For example, the vertical diode chip 520 is a short-wavelength light-emitting diode chip, such as, but not limited to, a blue light-emitting diode or an ultraviolet light-emitting diode. In this embodiment, the short-wavelength light-emitting diode chip is used to excite the light conversion material to generate an emission beam corresponding to a specific color category. The short-wavelength light-emitting diode chip can refer to the light-emitting diode chip used to generate the excitation beam. The wavelength of the excitation beam is lower than the wavelength of the emission beam from the light conversion material, or lower than the absorption edge wavelength of the light conversion material. The light conversion material can be a fluorescent material or a quantum dot. Fluorescent materials can be sulfides, oxides, oxysulfides, nitrides, oxynitrides, halides, or organic polymers, such as, but not limited to, yttrium aluminum garnet (YAG), zinc silicate (Zn₂SiO₄), zinc sulfide (ZnS), and poly(p-phenylenevinylene). Quantum dot materials can be, but are not limited to, cadmium selenide (CdSe), indium phosphide (InP), zinc telluride selenide (ZnTeSe), lead sulfide (PbS), and perovskite.

[0355] In step S527, the repair method determines whether each pixel contains invalid vertical diode chips V2' and V3'. In this embodiment, the repair method can determine whether the beam generated by the vertical diode chip 520 exceeds an intensity threshold, or whether the generated beam exceeds a preset wavelength range. When the repair method determines that each pixel does not contain invalid vertical diode chips V2' and V3' (step S527, the determination result is "No"), a filling layer is formed between the first blocks 550 (step S528); when the repair method determines that any pixel contains invalid vertical diode chips V2' and V3' (step S527, the determination result is "Yes"), a flip-chip diode chip 530 is set (step S529). In this embodiment, the repair method determines that there are accommodating sites 551 for invalid vertical diode chips V2' and V3' within the pixel structure 50, which are used to confirm the color category of the corresponding emitted beam. For example, Figure 4D Vertical diode chip V1 corresponds to a red emission beam, vertical diode chip V2 corresponds to a green emission beam, and vertical diode chip V3 corresponds to a blue emission beam. Then, for... Figure 5The pixel structure 50 in the lower right corner, if it is confirmed that the lower left corner of the pixel structure 50 contains an invalid vertical diode chip V3', it can be determined that the pixel structure 50 has a defect that prevents it from generating blue light after completion. It should be understood that "corresponding" here means that the receiving site 551 corresponding to a specific vertical diode chip V1, V2, V3 is the same as the receiving site 551 corresponding to a specific color emission beam; however, it is not limited to specific vertical diode chips V1, V2, V3 generating emission beams of a specific color. For example, vertical diode chip V1 generates a red beam; or, vertical diode chip V1 generates ultraviolet light, which is then converted to a red beam through color conversion. Based on this, the repair method selects a specific flip-chip diode chip 530 and transfers it to the receiving site 551 of the pixel structure 50. The color category of the specific flip-chip diode chip 530 corresponds to the color category of the defect. Subsequently, the repair method forms a filling layer between the first blocks 550 (step S528), for example, forming a second filling layer 539 on the flip-chip diode die 530.

[0356] Please refer to Figure 9A The repair method forms a second stop 560 above the first stop 550 (step S5210). In this embodiment, the second stop 560 is located directly above the first stop 550 and surrounds only the receiving site 551 containing the vertical diode die 520. In other embodiments, the second stop 560 may also be located on the inner edge of the first stop 550 surrounding the receiving site 551. Furthermore, the second stop 560 may also surround the receiving site 551 containing the flip-chip diode die 530. The second stop 560 may be made of the opaque material described in this invention. In some embodiments, the second stop 560 is made of the same material as the first stop 550.

[0357] Please refer to Figure 9B The repair method forms a first light conversion material layer 526 between the second blocks 560 (step S5211). The first light conversion material layer 526 has a color category, each corresponding to a specific accommodating site 551 on the pixel structure 50. In this embodiment, the color category of each first light conversion material 526 is different from the color category of the flip-chip diode die 530. For example, Figure 9B The two first light conversion material layers 526 are used to generate red and green emitted light beams, respectively, while the flip-chip diode die 530 is used to generate a blue emitted light beam. Please refer to... Figure 9C The repair method forms a protective layer 570 on the first stop 550 (step S5212). In this embodiment, the protective layer 570 is used to cover and protect the vertical diode chip 520, the flip-chip diode chip 530, and the light conversion material layer. The protective layer 570 can be made of the light-transmitting material described in this invention. In some embodiments, the protective layer 570 uses the same material as the second filler layer 539.

[0358] Figure 10 This is a flowchart of the pixel structure repair method according to the third embodiment; Figure 11 This is a schematic diagram illustrating the manufacturing process of the pixel structure repair method according to the third embodiment. Please refer to it as well. Figure 10 and Figure 11 The main difference between the third embodiment and the second embodiment lies in steps S538 to S5311. In this embodiment, the flip-chip diode chip 530 itself does not have a color category. For example, the flip-chip diode chip 530 is a short-wavelength light-emitting diode chip.

[0359] In step S537, when the repair method determines that any pixel contains invalid vertical diode chips V2' and V3' (step S537, the determination result is "yes"), a flip-chip diode chip 530 is set (step S539). In this embodiment, the repair method determines that there are accommodating sites 551 for invalid vertical diode chips V2' and V3' within the pixel structure 50 to confirm the color category of the corresponding emitted beam; however, the flip-chip diode chip 530 does not need to correspond to the color category of the defect. Subsequently, the repair method forms a second light conversion material layer 537 between the first blocks 550 (step S538). The second light conversion material layer 537 has a color category and corresponds to the color category of the defect. For example, Figure 11 The system comprises three first light-conversion material layers 526, used to generate red, green, and blue emitted light beams, respectively. If the vertical diode chip 520 corresponding to the red beam is invalid, the repair method forms a second light-conversion material layer 537 corresponding to the red beam on top of the flip-chip diode chip 530. In other embodiments, if the repair method determines that the vertical diode chip 520 at a specific location of the pixel structure 50 is invalid, then no first light-conversion material layer 526 is formed on that specific location.

[0360] In other embodiments, the repair method determines that there are invalid vertical diode die V2', V3' accommodating sites 551 within the pixel structure 50. Then, in step S538, the repair method forms a second light conversion material layer 537 between the first blocks 550 to cover the flip-chip diode die 530. Next, a second block 560 is formed on the first block 550 (step S5310). In step S5311, the repair method forms a first light conversion material layer 526 between the second blocks 560 to cover the vertical diode die 520. Each first light conversion material layer 526 and the second light conversion material layer 537 has a different color category. Then, a protective layer 570 is formed on the first block 550 (step S5312). In this embodiment, the repair method does not need to confirm the color category of the defect before selecting a second light conversion material layer 537 with the corresponding color category. Therefore, the accommodating sites 551 of the pixel structure 50 are not necessarily related to the color category.

[0361] Rereference Figure 1 In some embodiments, the pixel structure 50 includes a substrate 500, a plurality of vertical diode dies 520, flip-chip diode dies 530, and an upper wiring layer 540. The flip-chip diode dies 530 can be installed in the pixel structure 50 after the repair fabrication process or before the repair fabrication process. In some embodiments, the pixel structure 50 may face challenges in application, as the fabrication process of pure-color micro-light-emitting diodes requires multiple complex mass transfers and complex repair fabrication processes, while color-conversion micro-light-emitting diodes suffer from complex structures, narrow color gamuts, and low reliability. In some embodiments, the hybrid micro-light-emitting diode structures and their repair methods described in the following embodiments can be used to implement or apply to the pixel structure 50. By combining pure-color micro-light-emitting diodes and color-conversion micro-light-emitting diodes within the micro-light-emitting diode, a pixel structure 50 with a simple structure, wide color gamut, high reliability, and simple repair process can be achieved. However, the present invention is not limited thereto. In different design considerations or application scenarios, other structures, processes or manufacturing techniques may be used to realize the pixel structure 50 disclosed in the present invention.

[0362] Please refer to Figures 12 to 14A hybrid micro-light-emitting diode (LED) structure 40 includes a substrate 400, a plurality of LED chips 410 (including a red LED chip 410R, a green LED chip 410G, a blue LED chip 410B, and a spare LED chip 410S), an insulating layer 420, a filling layer 430, and a light-transmitting layer 440. The red LED chip 410R, the green LED chip 410G, the blue LED chip 410B, the spare LED chip 410S, and the insulating layer 420 are disposed on the substrate 400. In some embodiments, the spare LED chip 410S may be another blue LED chip or an ultraviolet (UV) LED chip, and is not limited thereto.

[0363] An insulating layer 420 surrounds the standby micro-LED chip 410S and forms an inkjet space 450 with the standby micro-LED chip 410S, wherein the inkjet space 450 is filled with an inkjet material IM. In other words, in some embodiments, the combination of the standby micro-LED chip 410S, the insulating layer 420, the inkjet space 450, and the inkjet material IM can be considered as a color-converting micro-LED. Specifically, by filling the inkjet space 450 with the inkjet material IM and illuminating the standby micro-LED chip 410S, the color-converting micro-LED can emit light corresponding to the color of the inkjet material IM. In other words, in some embodiments, the light emitted by the standby micro-LED chip 410S (e.g., blue light or ultraviolet light) can be converted to different colors by the inkjet material IM, allowing the color-converting micro-LED to emit light of different colors.

[0364] The red LED chip 410R, the green LED chip 410G, the blue LED chip 410B, and the spare LED chip 410S are adjacent to at least one of the other three. Figure 13 For example, in this embodiment, red micro-light-emitting diode chips 410R, green micro-light-emitting diode chips 410G, blue micro-light-emitting diode chips 410B and spare micro-light-emitting diode chips 410S are arranged sequentially along a first direction (e.g., but not limited to the X-axis direction) to be disposed on the substrate 400, thereby forming a rectangular array with 4 rows and 1 column.

[0365] And with Figure 14For example, in this embodiment, red micro-light-emitting diode chips 410R, green micro-light-emitting diode chips 410G, blue micro-light-emitting diode chips 410B and spare micro-light-emitting diode chips 410S are arranged sequentially along a first direction (e.g., but not limited to the X-axis direction) and a second direction (e.g., but not limited to the Y-axis direction) to be disposed on the substrate 400, thereby forming a rectangular array with two rows and two columns.

[0366] It should be noted that the arrangement order of the red micro-LED chip 410R, the green micro-LED chip 410G, the blue micro-LED chip 410B, and the spare micro-LED chip 410S is not limited to the above embodiments (including...). Figure 12 and Figure 14 For example, the spare microLED chip 410S can be disposed between any two of the red microLED chip 410R, the green microLED chip 410G, and the blue microLED chip 410B (not shown). Alternatively, the red microLED chip 410R can be disposed between any two of the green microLED chip 410G, the blue microLED chip 410B, and the spare microLED chip 410S (not shown).

[0367] In some embodiments, the hybrid micro-LED structure 40 can be applied in a micro-LED display device. The hybrid micro-LED structure 40 constitutes a pixel in the micro-LED display device, and the red micro-LED chip 410R, green micro-LED chip 410G, blue micro-LED chip 410B, and spare micro-LED chip 410S are each a sub-pixel. "Adjacent to at least one of the other three" means that each sub-pixel in a single pixel is adjacent to at least one of the other three sub-pixels. If two adjacent sub-pixels belong to different pixels, they are not considered "adjacent" as described herein.

[0368] Please refer to Figure 12 , Figure 13 , Figure 15 and Figure 16 The following will be in the format of... Figure 12 and Figure 13The manufacturing process of the hybrid micro-LED structure 40 and the repair method when the micro-LED chip 410 is damaged are illustrated using an example. First, a red micro-LED chip 410R, a green micro-LED chip 410G, a blue micro-LED chip 410B, and a spare micro-LED chip 410S are disposed on a substrate 400 (step S40). In some embodiments, the micro-LED chip 410 can be disposed on the substrate 400 by mass transfer technology.

[0369] In some embodiments, the substrate 400 may be made of an opaque insulating material, such as, but not limited to, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), and silicon carbide (SiC). In other embodiments, the substrate 400 may be made of a transparent insulating material, such as, but not limited to, glass, silicone, epoxy, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), and polyetherimide.

[0370] In some embodiments, when multiple micro-LED chips 410 are disposed on the substrate 400, each micro-LED chip 410 is electrically connected to at least one driving circuit (not shown) in the hybrid micro-LED structure 40 through paired electrodes (including N-terminal and P-terminal electrodes). In some embodiments, the hybrid micro-LED structure 40 can drive each micro-LED chip 410 to emit light through a single driving circuit. In other embodiments, the hybrid micro-LED structure 40 can also drive each micro-LED chip 410 to emit light separately through multiple driving circuits. In other words, in some embodiments, each micro-LED chip 410 can be driven independently to emit light independently.

[0371] In some embodiments, when the spare micro-LED chip 410S is another blue micro-LED chip, the spare micro-LED chip 410S is adjacent to the blue micro-LED chip 410B (e.g., Figure 12 (As shown). Therefore, when multiple micro-LED chips 410 are disposed on the substrate 400 using mass transfer technology, the blue micro-LED chip 410B and the spare micro-LED chip 410S can be simultaneously transferred and disposed in adjacent positions, thereby improving the efficiency of mass transfer. In some embodiments, the spare micro-LED chip 410S is further adjacent to the red micro-LED chip 410R or the green micro-LED chip 410G. Figure 14For example, in this embodiment, the spare micro-LED chip 410S is adjacent to the green micro-LED chip 410G and the blue micro-LED chip 410B.

[0372] After step S40, an isolation layer 420 is disposed on the substrate 400 to surround the standby micro-LED die 410S, such that the isolation layer 420 and the standby micro-LED die 410S form an inkjet space 450 (step S41). In some embodiments, the isolation layer 420 can be disposed on the substrate 400 by deposition techniques, such as, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), area selective deposition (ASD), and atomic layer deposition (ALD).

[0373] Please refer to Figure 13 and Figure 17 .like Figure 13 As shown, in some embodiments, the insulating layer 420 includes an opaque material 420A (such as...). Figure 13 As shown), and the opaque material 420A surrounds the spare micro LED chip 410S and the inkjet space 450. In other embodiments, the insulating layer 420 includes an opaque material 420A and an insulating material 420B (as shown). Figure 17 As shown, an opaque material 420A surrounds the inkjet space 450, and an insulating material 420B surrounds the standby micro-LED chip 410S. In other words, in this embodiment, the insulating material 420B is formed on the substrate 400 to surround the standby micro-LED chip 410S, and then the opaque material 420A is formed on the insulating material 420B to surround the inkjet space 450.

[0374] In some embodiments, the isolation layer 420 is used to prevent light emitted by the standby micro-LED chip 410S from interfering with the light emitted by the adjacent micro-LED chip 410. Therefore, the isolation layer 420 surrounds the inkjet space 450 with an opaque material 420A. In some embodiments, the opaque material 420A may be a black matrix (BM) material or a light-reflective material, such as, but not limited to, alumina, dielectric multilayer films, and reflective resin materials. In some embodiments, the isolation material 420B may be a light-transmitting material (e.g., but not limited to, silicone, epoxy resin, polyimide, benzocyclobutene, perfluorocyclobutane, SU8 photoresist, acrylic resin, polyethylene phthalate, and polyetherimide) or an opaque material (e.g., but not limited to, black matrix materials, alumina, dielectric multilayer films, and reflective resin materials).

[0375] After step S41, the red micro-LED chip 410R, the green micro-LED chip 410G, and the blue micro-LED chip 410B are lit up respectively to check whether any of them is damaged and unable to emit light (step S42). In some embodiments, the failure of the micro-LED chip 410 to emit light includes, but is not limited to, cases where it is defective and unable to emit light, or cases where it is physically damaged during mass transfer.

[0376] When one of the red LED chip 410R, green LED chip 410G, or blue LED chip 410B is damaged, the hybrid LED structure 40 cannot emit light of the correct color. In this case, the hybrid LED structure 40 needs to be repaired. Therefore, in some embodiments after step S42, the inkjet space 450 can be filled with inkjet material IM of the color corresponding to the damaged LED chip 410 (step S43) to compensate for the missing color of light in the hybrid LED structure 40. For example, when the red LED chip 410R is damaged and cannot emit light, the hybrid LED structure 40 cannot emit red light. In this case, the inkjet space 450 can be filled with red inkjet material IM to change the color of the light emitted by the spare LED chip 410S, thereby allowing the hybrid LED structure 40 to emit red light through the spare LED chip 410S and the red inkjet material IM.

[0377] In some embodiments, the inkjet material IM is a quantum dot (QD). A quantum dot is a nanomaterial used to change the wavelength of light emitted by the micro-light-emitting diode chip 410 (hereinafter referred to as μLED light) to change the color of the μLED light. For example, larger quantum dots (e.g., 5 to 6 nanometers in diameter, but not limited thereto) can change the color of the μLED light to red or orange, and smaller quantum dots (e.g., 2 to 3 nanometers in diameter, but not limited thereto) can change the color of the μLED light to blue or green. In some embodiments, the quantum dots are selected from materials such as cadmium selenide (CdSe), indium phosphide (InP), zinc telluride selenide (ZnTeSe), and perovskite, but not limited thereto.

[0378] In some embodiments, when one of the red LED chip 410R, the green LED chip 410G, and the blue LED chip 410B is damaged, the damaged LED chip 410 can be kept off to reduce the power consumption of the hybrid LED structure 40 during use. For example, when the red LED chip 410R is damaged, it is kept off so that only the green LED chip 410G, the blue LED chip 410B, and the spare LED chip 410S in the hybrid LED structure 40 can emit light.

[0379] After the micro-LED chips 410 in the hybrid micro-LED structure 40 are repaired, the hybrid micro-LED structure 40 can continue its manufacturing process. Therefore, in some embodiments after step S43, a filler material is filled onto the substrate 400 to form a filler layer 430 (step S44). Here, the filler layer 430 is disposed on the substrate 400, and the filler layer 430 is used to fix each micro-LED chip 410 and the isolation layer 420 onto the substrate 400. In some embodiments, the filler material can be a transparent material with adhesive properties, such as, but not limited to, adhesive, underfill, anisotropic conductive adhesive (ACP), anisotropic conductive film (ACF), non-conductive adhesive (NCP), and non-conductive film (NCF).

[0380] Finally, after step S44, a light-transmitting layer 440 is disposed on the filler layer 430 (step S45) to strengthen and protect the hybrid micro-LED structure 40. In some embodiments, the material of the light-transmitting layer 440 may be a rigid material with light transmittance, such as, but not limited to, glass and acrylic. In other embodiments, when the standby micro-LED chip 410S is an ultraviolet micro-LED chip, the material of the light-transmitting layer 440 may be a rigid material with light transmittance and UV resistance, such as, but not limited to, polycarbonate (PC) and polymethyl methacrylate (PMMA).

[0381] When the red LED chip 410R, green LED chip 410G, and blue LED chip 410B are all undamaged, the inkjet space 450 does not need to be filled with any inkjet material IM. Therefore, in some embodiments after step S42, the filling material can be directly filled onto the substrate 400 to form a filling layer 430 (step S44), and the light-transmitting layer 440 can be disposed on the filling layer 430 (step S45). In some embodiments, when the red LED chip 410R, green LED chip 410G, and blue LED chip 410B are all undamaged, the spare LED chip 410S can be kept off to reduce the power consumption of the hybrid LED structure 40 during use. That is, at this time, only the red LED chip 410R, green LED chip 410G, and blue LED chip 410B in the hybrid LED structure 40 can emit light.

[0382] According to any embodiment, the hybrid micro-LED structure combines the characteristics of pure color micro-LEDs and color-conversion micro-LEDs, giving it the advantages of both small area and high color accuracy. Furthermore, because the repair process of the hybrid micro-LED structure is simple, when a panel or display device made with the hybrid micro-LED structure has a defect, the manufacturer can easily locate and repair the defect, thereby improving the yield and reliability of the panel and display device.

[0383] Rereference Figure 1 In some embodiments, the pixel structure 50 includes a substrate 500, a plurality of vertical diode dies 520, flip-chip diode dies 530, and an upper wiring layer 540. In some embodiments, the vertical diode dies 520 or flip-chip diode dies 530 may face variations in production equipment or manufacturing technology during application, resulting in specification differences between different types of diode dies. Height differences between diode dies may adversely affect subsequent eutectic bonding processes, such as causing poor bonding and reducing manufacturing yield. These height differences can also negatively impact alignment accuracy in the manufacturing process and the optical performance of the final product. In some embodiments, the diode dies and their manufacturing methods described in the following embodiments can be used to implement or apply to the vertical diode dies 520 or flip-chip diode dies 530, and the pixel structure 50 can also be used to implement or apply to the panel structures described in the following embodiments. However, the present invention is not limited thereto. Under different design considerations or application scenarios, other structures, processes or manufacturing processes may be adopted to realize the vertical diode die 520 or the flip-chip diode die 530 disclosed in the present invention.

[0384] Figure 18This is a schematic diagram of multiple diode dies with different grain heights according to some embodiments. In this embodiment, there are three diode dies 60: a first diode die 601, a second diode die 602, and a third diode die 603. In this embodiment, the diode dies 60 are vertical diode dies. Each vertical diode die includes a top electrode 62 (i.e., top electrodes 621, 622, 623), an epitaxial layer 63 (i.e., epitaxial layers 631, 632, 633), a bottom electrode 64 (i.e., bottom electrodes 641, 642, 643), and a second substrate 65 (i.e., second substrates 651, 652, 653). The bottom electrode 64 is disposed on the second substrate 65, the epitaxial layer 63 is disposed on the bottom electrode 64, and the top electrode 62 is disposed on the epitaxial layer 63. In other embodiments, the vertical diode die may not include the second substrate 65, and the epitaxial layer 63 may be a multilayer structure, for example, including P-type or N-type doped layers. Figure 18 The first diode chip 601, the second diode chip 602, and the third diode chip 603 shown are placed on the same horizontal plane. The first reference line BL1 represents the height of the horizontal plane, and the second reference line BL2 represents the height of the upper surface of one of the diode chips 601. For example... Figure 18 The height of the upper surface of the top electrode 622 of the second diode die 602. In this embodiment, the height of the first diode die 601 is higher than the second reference line BL2, and the height of the third diode die 603 is lower than the second reference line BL2. The main reason is the variation in the manufacturing process between the individual diode dies 60, which results in the first diode die 601 having a thicker bottom electrode 641 and the third diode die 603 having a thinner epitaxial layer 633.

[0385] Figure 19 This is a flowchart of a method for manufacturing a diode die according to some embodiments; Figures 20A to 20K This is a schematic diagram of a diode die manufacturing method according to some embodiments. Please refer to it based on... Figure 19 Refer to in sequence Figures 20A to 20K .like Figure 20AAs shown, the manufacturing method includes providing a first substrate 61 (step S601) and forming an epitaxial layer 63 on the first substrate 61 (step S602). The material of the first substrate 61 may be selected from the group consisting of silicon (Si), silicon dioxide (SiO2), aluminum oxide (Al2O3), gallium arsenide (GaAs), silicon carbide (SiC), glass, silicone, epoxy resin, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), polyetherimide, and combinations thereof. The material of the epitaxial layer 63 can be selected from the group consisting of gallium nitride (GaN), gallium arsenide (GaAs), indium gallium phosphide (InGaP), zinc selenide (ZnSe), silicon carbide (SiC), aluminum gallium nitride (AlGaN), zinc sulfide (ZnS), silicon (Si), and combinations thereof. The epitaxial layer 63 has the same or approximately the same lattice constant as the first substrate 61. The fabrication process for forming the epitaxial layer 63 can be a deposition method, such as, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), zone selective deposition (ASD), and atomic layer deposition (ALD).

[0386] like Figure 20B As shown, the manufacturing method includes forming a first interconnect layer 66 on the epitaxial layer 63 (step S603). The first interconnect layer 66 serves as an intermediate dielectric layer between the epitaxial layer 63 and the bottom electrode 64 to enhance the bonding strength between the two. The fabrication process for forming the first interconnect layer 66 can employ deposition or coating methods. Figure 20C and Figure 20D As shown, the manufacturing method includes depositing an electrode layer on the first connecting layer 66 (step S604), so that the bottom electrode 64 is indirectly bonded to the epitaxial layer 63. In this embodiment, the bottom electrode 64 is pre-formed and then deposited on the first connecting layer 66. Therefore, the bottom electrode 64 can have a thicker layered structure to facilitate further processing of the bottom electrode 64 in subsequent manufacturing processes. The manufacturing process for depositing the electrode layer can involve pressing and annealing. The bottom electrode 64 can be a conductive material, such as, but not limited to, gold, silver, copper, aluminum, or alloys containing these metals.

[0387] like Figure 20EAs shown, the manufacturing method includes grinding the electrode layer (step S605). In this embodiment, variations in the manufacturing process of the bottom electrode 64 may result in the thickness of the bottom electrode 64 not meeting requirements. The grinding process in step S605 ensures that the thickness of the bottom electrode 64 conforms to the absolute thickness acceptance specifications and / or relative thickness acceptance specifications. The absolute thickness acceptance specifications refer to absolute values, such as limiting the thickness of the bottom electrode 64 to an acceptable range between 10 μm and 100 μm. In some embodiments, the bottom electrode 64 of the diode die 60 is shaped into a special shape (e.g., trapezoidal) for use in a pre-alignment manufacturing process. This special shape (e.g., trapezoidal) must conform to a specified absolute value range. Accordingly, the manufacturing method includes grinding the electrode layer to make its thickness conform to the thickness specification acceptance range of the special shape. The relative thickness acceptance specifications refer to relative values, such as limiting the thickness of the bottom electrode 64 of a particular diode die 60 so that the height of the particular diode die 60 is substantially the same as the height of other diode dies 60, as will be described in detail later.

[0388] like Figure 20F As shown, the manufacturing method includes forming a second interconnect layer 67 on the electrode layer (step S606). The second interconnect layer 67 serves as an intermediate dielectric layer between the second substrate 65 and the bottom electrode 64 to enhance the bonding strength between them. The fabrication process for forming the second interconnect layer 67 can employ deposition or coating methods. Figure 20G As shown, the manufacturing method includes depositing a second substrate 65 on a second interconnect layer 67 (step S607), so that the second substrate 65 is indirectly bonded to the bottom electrode 64. The fabrication process for depositing the second substrate 65 can be lamination followed by annealing. The material of the second substrate 65 can be selected from the group consisting of silicon (Si), silicon dioxide (SiO2), aluminum oxide (Al2O3), gallium arsenide (GaAs), silicon carbide (SiC), glass, silicone, epoxy resin, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), polyetherimide, and combinations thereof. The material of the second substrate 65 can be different from that of the first substrate 61. For example, the first substrate 61 may be a substrate that is easy to form an epitaxial layer 63, while the second substrate 65 may be a reflective substrate to improve the luminous efficiency of the diode chip 60. Alternatively, the material of the second substrate 65 can be the same as that of the first substrate 61. For example, both the first substrate 61 and the second substrate 65 are made of sapphire substrate.

[0389] like Figure 20HAs shown, the manufacturing method includes removing the first substrate 61 (step S608). Accordingly, the semi-finished diode substrate is transferred from the first substrate 61 to the second substrate 65. In this embodiment, when the diode substrate is inverted, the second substrate 65 is located at the bottom of the diode substrate, and the epitaxial layer 63 is located at the top, to facilitate subsequent fabrication processes on the epitaxial layer 63. Figure 20I As shown, the manufacturing method includes performing another electrode fabrication process (step S609). Specifically, in this embodiment, another electrode layer is formed on the surface of the epitaxial layer 63 and is cut into multiple independent grains, each of which has a top electrode 62. The material of the top electrode 62 can be a conductive material, and can be the same as or different from the material of the bottom electrode 64. The top electrode 62 can be formed by deposition or lamination.

[0390] like Figure 20J As shown, the manufacturing method includes cutting the electrode layer (step S610). In this embodiment, the bottom electrode layer is cut to form bottom electrodes 64 of individual grains. In some embodiments, the manufacturing method may use a specific angle to cut the electrode layer, so that the side surfaces of the bottom electrodes 64 of each individual grain have an angle, thereby forming a trapezoidal bottom electrode 64. The manufacturing method of this embodiment only cuts the bottom electrode layer. In other embodiments, the manufacturing method cuts the bottom electrode layer and the second substrate 65 to form the bottom electrodes 64 of each individual grain and the bottom substrate (e.g., ...). Figure 18 The first diode die 601 shown is illustrated.

[0391] like Figure 20K As shown, the manufacturing method includes removing the second substrate 65 (step S611) and forming diode dies 60 (step S612). In this embodiment, the manufacturing method produces at least seven diode dies 60, which can be applied to the panel structure 600. Figure 21 This is a schematic diagram of a diode die according to some embodiments. Please refer to it. Figure 21In this embodiment, the diode die 60 includes a top electrode 62, an epitaxial layer 63, a bottom electrode 64, and conductor layers 68 (i.e., conductor layers 681, 682, 683). The bottom electrode 64 is disposed on the conductor layer 68, the epitaxial layer 63 is disposed on the bottom electrode 64, and the top electrode 62 is disposed on the epitaxial layer 63. The conductor layer 68 can be a second connection layer 67 or another conductive layer formed on the surface of the bottom electrode 64 (or the second connection layer 67) to protect the bottom electrode 64 and connect to the external substrate. In this embodiment, the bottom electrode 64 has a trapezoidal structure, with its sidewalls being the hypotenuse of the trapezoid and its thickness being the height of the trapezoid. The trapezoidal structure of the bottom electrode 64 facilitates pre-alignment of the diode dies 60 before transfer. For example, the trapezoidal structure of the bottom electrode 64 corresponds to the trapezoidal recesses on the alignment disk, allowing a large number of aligned diode dies 60 to be transferred to the external substrate at once. In this embodiment, the diode die 60 may have a lower height limit to facilitate the corresponding array of disk recesses.

[0392] The manufacturing methods described in the foregoing embodiments (e.g., some or all of steps S601 to S612) can be repeated to produce a first diode die 601, a second diode die 602, and a third diode die 603. However, variations in the manufacturing process may result in differences in the dimensional specifications of the individual diode dies 60. For example, one or more of the epitaxial layer 63 formed in step S602, the first interconnect layer 66 formed in step S603, and the electrode layer provided in step S604 may have thickness differences.

[0393] Figure 22 This is a schematic diagram comparing the heights of multiple semi-finished substrates according to some embodiments. Please refer to... Figure 22 In this embodiment, the first diode substrate 601', the second diode substrate 602', and the third diode substrate 603' respectively correspond to the semi-finished substrate in step S604 (see reference). Figure 20D , Figure 22 (First connection layer 66 not shown). When the first diode substrate 601', the second diode substrate 602', and the third diode substrate 603' are placed on the same horizontal plane, the third reference line BL3 represents the height of the horizontal plane, and the fourth reference line BL4 represents the height of the upper surface of the diode substrate with the lowest height, for example... Figure 22The height of the upper surface of the bottom electrode 643 of the third diode substrate 603'. In this embodiment, the first diode substrate 601' has a height H61, and its bottom electrode 641 has a thickness D61; the second diode substrate 602' has a height H62, and its bottom electrode 642 has a thickness D62; the third diode substrate 603' has a height H63, and its bottom electrode 643 has a thickness D63. Wherein, thickness D61 is greater than thickness D62, and thickness D62 is greater than thickness D63; height H61 is greater than height H62, and height H62 is greater than height H63. The main reason is that the bottom electrode 641 of the first diode substrate 601' has a larger thickness D61 due to variations in the manufacturing process, while the epitaxial layer 633 of the third diode substrate 603' has a smaller thickness due to variations in the manufacturing process.

[0394] Figure 23 This is a flowchart of a method for manufacturing a diode die according to other embodiments; Figures 24A to 24B This is a schematic diagram of a diode die manufacturing method according to other embodiments. Please refer to it based on... Figure 23 Refer to in sequence Figures 24A to 24B In this embodiment, step S605 of the manufacturing method further includes steps S6051 to S6054. In step S6051, the manufacturing method measures the height of multiple semi-finished substrates to obtain the heights H61, H62, and H63 of each diode substrate. For example, the first substrates 61 (i.e., first substrates 611, 612, 613) of each diode substrate are placed on the same third reference line BL3, and a laser thickness gauge measures the upper surface of the bottom electrode 64 of each diode substrate to obtain the height of the diode substrate.

[0395] Subsequently, the manufacturing method includes comparing the heights of each semi-finished substrate (step S6052) to obtain the lowest height value (step S6053). For example... Figure 24A As shown, the manufacturing method determines that the third diode substrate 603' has the lowest height; therefore, the fourth reference line BL4 is disposed on the top surface of the bottom electrode 643 of the third diode substrate 603'. In some embodiments, the lowest height value refers to the height value of the semi-finished diode substrate with the lowest height among a plurality of semi-finished diode substrates expected to be placed in the same panel structure 600. The manufacturing method includes grinding the electrode layers of each semi-finished substrate to achieve the lowest height value (step S6054). In this embodiment, the top surfaces of both the first diode substrate 601' and the second diode substrate 602' exceed the fourth reference line BL4; therefore, the manufacturing method grinds both to grind height H61 to the value of height H63, and height H62 is also ground to the value of height H63. Figure 24BAs shown, after step S6054, the values ​​of height H61, height H62 and height H63 are essentially the same. Each bottom electrode 64 is ground so that the thickness D61 is greater than the thickness D63, and the thickness D63 is greater than the thickness D62.

[0396] In some embodiments, "substantially identical" can mean sampling multiple diode dies 60 formed on each diode substrate to obtain multiple sets of samples, where the height of the diode dies 60 in each set of samples does not differ significantly (e.g., at a 5% significance level). In other embodiments, "substantially identical" can mean that the allowable variation in height between the individual diode substrates (diode dies 60) is within the accuracy range of the polishing machine G6. In still other embodiments, "substantially identical" can mean that the allowable variation in height between the individual diode substrates (diode dies 60) is less than the allowable variation in thickness between the bottom electrodes 64 of the individual diode substrates (diode dies 60). For example, in this embodiment, if thickness D61 is 100 μm and thickness D62 is 80 μm, then the variation ratio between thickness D61 and thickness D62 is (100-80) / 80, i.e., 25%. Therefore, when the height variation ratio between the individual diode substrates (diode dies 60) is less than 25%, they can be considered substantially identical. It should be understood that the variation ratios illustrated in this embodiment are merely illustrative examples, and the actual height variation ratios should be defined based on the actual thickness variation ratios.

[0397] Based on the above, in step S6052, the manufacturing method includes comparing the height of one substrate (first height) with the height of another substrate (second height). In some embodiments, the manufacturing method includes, when it is determined that the second height is less than a certain lower limit height, not performing the step of grinding the bottom electrode layer until the first height decreases to the second height. For example, such as Figure 24A As shown, when the value of height H63 is less than the lower limit height but the value of height H62 is greater than the lower limit height, the polishing machine G6 will not polish the first diode substrate 601' to the value of height H63, nor will it polish the second diode substrate 602' to the value of height H63. However, the polishing machine G6 may polish the first diode substrate 601' to the value of height H62. The lower limit height can be defined according to the manufacturing process requirements. For example, the lower limit height may be the sum of the dimensional specifications of the first substrate 61 and the epitaxial layer 63 in the semi-finished substrate, such as the sum of the upper limit values ​​of the acceptable thickness range, to avoid the bottom electrode 64 being completely polished away. As another example, the lower limit height may be a value within the acceptable thickness range required for pre-aligning the diode die 60, such as the minimum acceptable thickness value, to allow the pre-aligning manufacturing process to be performed on the diode die 60 produced from the diode substrate.

[0398] Figure 25This is a schematic diagram of the panel structure according to some embodiments. Please refer to it. Figure 25 The first diode substrate 601' has undergone... Figure 23 The process involves steps to fabricate a first diode die 601, and a second diode substrate 602' is then processed. Figure 23 The process involves steps to fabricate a second diode die 602, and a third diode substrate 603' is then processed. Figure 23 The process involves transferring a first diode die 601, a second diode die 602, and a third diode die 603 to a third substrate 69 to form a panel structure 600. Therefore, in this embodiment, the panel structure 600 includes a first diode die 601, a second diode die 602, and a third diode die 603, and the plurality of diode dies 60 on the panel structure 600 have substantially the same height. Figure 25 As shown, the first reference line BL1 is disposed on the upper surface of the panel structure 600, and the second reference line BL2 is disposed on the upper surface of the top electrode 62 of the diode chip 60. The first diode chip 601, the second diode chip 602, and the third diode chip 603 have substantially the same height; however, the thickness D61 of the bottom electrode 64 of each diode chip 60 is greater than the thickness D63, and the thickness D63 is greater than the thickness D62.

[0399] In some embodiments, the panel structure 600 includes multiple pixel structures. For example, Figure 25 The first diode chip 601, the second diode chip 602, and the third diode chip 603 shown are located in the same pixel structure and correspond to red light, green light, and blue light, respectively. The manufacturing method includes transferring a plurality of first diode chips 601 generated from processing a first diode substrate 601' to various pixel structures on a panel structure 600, transferring a plurality of second diode chips 602 generated from processing a second diode substrate 602' to various pixel structures on a panel structure 600, and transferring a plurality of third diode chips 603 generated from processing a third diode substrate 603' to various pixel structures on a panel structure 600. Accordingly, the thickness of the bottom electrode 64 of the same type of diode chip 60 within each pixel structure is substantially the same. For example, the bottom electrode 641 of the first diode chip 601 within each pixel structure has a thickness D61, the bottom electrode 642 of the second diode chip 602 has a thickness D62, and the bottom electrode 643 of the third diode chip 603 has a thickness D63, and the height of each diode chip 60 is substantially the same.

[0400] Rereference Figure 1In some embodiments, the pixel structure 50 includes a substrate 500, a plurality of vertical diode dies 520, flip-chip diode dies 530, and an upper wiring layer 540. In some embodiments, the vertical diode dies 520 or flip-chip diode dies 530 may face thickness differences between diode dies due to variations in production equipment or manufacturing technology during application. Although this thickness difference problem can be overcome by filling the gaps between diode dies with filler material to fix the diode dies, existing filling techniques still suffer from poor flatness of the filler material, causing open circuits between components and preventing the micro-LEDs from emitting light normally. In some embodiments, the vertical micro-LED structures, vertical micro-LED units, and manufacturing methods of the following embodiments can be used to implement or apply the pixel structure 50. However, the present invention is not limited thereto, and other structures, processes, or manufacturing techniques may be used to implement the pixel structure 50 disclosed in the present invention under different design considerations or application scenarios.

[0401] Please refer to Figures 26 to 31 , Figure 26 Presentation Figure 1 A vertical diode die 520 is disposed within the receiving site 551. To facilitate illustrating the connection relationship between the vertical diode die 520 and its surrounding components, the upper wiring layer 540 is magnified and represented as a first circuit layer 311, and the lower wiring layer 510 is magnified and represented as a second circuit layer 321. In this embodiment, a vertical micro-light-emitting diode unit 30 includes a first backplate 31 and a second backplate 32. Figure 27 As shown, the first backplate 31 includes a first substrate 310, a first circuit layer 311, a first contact pad 312, and a transparent electrode layer 313. The first circuit layer 311 is disposed on the first substrate 310. The first contact pad 312 is disposed on the first circuit layer 311. The transparent electrode layer 313 is disposed on the first circuit layer 311 and the first contact pad 312.

[0402] like Figure 28As shown, the second backplane 32 includes a second substrate 320, a second circuit layer 321, a eutectic metal layer 322, an alloy layer 323, a micro-LED chip 324, a second contact pad 325, and an isolation layer 326. The second circuit layer 321 is disposed on the second substrate 320. The eutectic metal layer 322 is disposed on the second circuit layer 321. The alloy layer 323 is disposed on the eutectic metal layer 322. The micro-LED chip 324 is disposed on the alloy layer 323. The second contact pad 325 is disposed on the micro-LED chip 324. The isolation layer 326 is disposed on the second substrate 320 to surround the micro-LED chip 324. In other words, in some embodiments, the thickness L2 of the isolation layer 326 is greater than the sum of the thickness of the second circuit layer 321, the thickness of the eutectic metal layer 322, the thickness of the alloy layer 323, and the thickness of the micro-LED chip 324, so that the isolation layer 326 can surround the micro-LED chip 324.

[0403] like Figure 26 and Figure 29 As shown, the transparent electrode layer 313 of the first backplate 31 faces the second contact pad 325 and the insulating layer 326 of the second backplate 32 and is disposed on the second backplate 32, and a chamber 327 is formed between the first backplate 31 and the second backplate 32. In some embodiments, the chamber 327 is in a vacuum state to avoid the generation of water vapor in the vertical micro-LED unit 30, thereby preventing water vapor from causing short circuits and damage between the components in the vertical micro-LED unit 30. In addition, in other embodiments, the chamber 327 may also be filled with an inert gas to achieve the same protective effect.

[0404] In some embodiments, the projected areas of the first contact pad 312 and the second contact pad 325 along the normal direction of the first back plate 31 at least partially overlap, and the transparent electrode layer 313 connects the second contact pad 325 and the insulating layer 326. Figures 29 to 31 For example, in this embodiment, the first contact pad 312 and the second contact pad 325 are coaxial with axis A1 (e.g., Figure 29 As shown), the projected areas of the first contact pad 312 and the second contact pad 325 along axis A1 overlap (as shown). Figure 30 and Figure 31 (As shown).

[0405] In some embodiments, when the first backplate 31 is disposed on the second backplate 32, the insulating layer 326 is deformed such that the thickness L1 of the deformed insulating layer 326 is equal to the sum of the thickness of the first contact pad 312, the thickness of the second circuit layer 321, the thickness of the eutectic metal layer 322, the thickness of the alloy layer 323, the thickness of the micro-LED die 324, and the thickness of the second contact pad 325. In other words, in some embodiments, the thickness L2 of the insulating layer 326 before deformation (e.g., Figure 28(As shown) is greater than the thickness L1 of the deformed isolation layer 326 (as shown) Figure 26 (As shown).

[0406] like Figure 30 and Figure 31 As shown, in some embodiments, the area of ​​the first contact pad 312 is smaller than the area of ​​the first circuit layer 311, the area of ​​the first circuit layer 311 is smaller than the area of ​​the micro-LED chip 324, and the area of ​​the second contact pad 325 is smaller than the area of ​​the micro-LED chip 324. Since the first circuit layer 311, the first contact pad 312, and the second contact pad 325 are all opaque, their areas must all be smaller than the area of ​​the micro-LED chip 324 to avoid obscuring its light emission. Furthermore, in some embodiments, the projected areas of the first circuit layer 311 and the isolation layer 326 along the normal direction of the first backplate 31 at least partially overlap. In other words, since a portion of the first circuit layer 311 is disposed on the isolation layer 326, the first circuit layer 311 will not completely obscure the light emission of the micro-LED chip 324.

[0407] Please refer to Figures 26 to 32 The following will be based on Figures 26 to 31 The manufacturing process and steps of the vertical micro-light-emitting diode unit 30 are illustrated using an example. Figure 32 As shown, when manufacturing the vertical micro-LED unit 30 begins, the first backplate 31 and the second backplate 32 are formed separately (steps S30 and S31). It should be noted that the order of step S30 (forming the first backplate 31) and step S31 (forming the second backplate 32) can be interchanged. In other words, the vertical micro-LED unit 30 can have the first backplate 31 formed first, followed by the second backplate 32 (e.g., ...). Figure 32 (As shown), the second backplate 32 can also be formed first, followed by the first backplate 31.

[0408] like Figure 27As shown, in step S30 of forming the first backplane 31, the first circuit layer 311 is first disposed on the first substrate 310 (step S300). In some embodiments, the material of the first substrate 310 is a light-transmitting insulating material, such as, but not limited to, glass, silicone, epoxy resin, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), and polyetherimide. In some embodiments, the first circuit layer 311 can be disposed on the first substrate 310 by deposition techniques, wherein the deposition techniques include, but are not limited to, sputtering, electron beam evaporation, chemical vapor deposition (CVD), physical vapor deposition (PVD), area selective deposition (ASD), and atomic layer deposition (ALD).

[0409] After step S300, the first contact pad 312 is disposed on the first circuit layer 311 (step S301), and then the transparent electrode layer 313 is disposed on the first circuit layer 311 and the first contact pad 312 (step S302). Here, the first circuit layer 311, the first contact pad 312, and the transparent electrode layer 313 are electrically connected to each other. In some embodiments, the first contact pad 312 can be disposed on the first circuit layer 311 using screen printing technology, wherein the material of the first contact pad 312 is a conductive material, such as, but not limited to, gold, copper, and aluminum. In some embodiments, the transparent electrode layer 313 can be a transparent conductive film, such as, but not limited to, indium tin oxide (ITO), tin oxide (SnO2), antimony tin oxide (ATO), conductive polymer (PEDOT), carbon nanotubes (CNTs), silver nanowires, and graphene.

[0410] like Figure 28 As shown, in step S31 of forming the second backplane 32, the second circuit layer 321 is first disposed on the second substrate 320 (step S310). In some embodiments, the material of the second substrate 320 may be an opaque insulating material, such as, but not limited to, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), and silicon carbide (SiC). In other embodiments, the material of the second substrate 320 may be the aforementioned transparent insulating material.

[0411] After step S310, the micro-LED chip 324 is disposed on the second circuit layer 321 (step S311), and then the second contact pad 325 is disposed on the micro-LED chip 324 (step S312). Here, the second circuit layer 321, the micro-LED chip 324, and the second contact pad 325 are electrically connected to each other. In some embodiments, the second contact pad 325 can be disposed on the second circuit layer 321 by screen printing technology, wherein the material of the second contact pad 325 is a conductive material, such as, but not limited to, gold, copper, and aluminum.

[0412] After step S312, an isolation layer 326 is disposed on the second substrate 320 to surround the micro-LED die 324 (step S313), wherein the isolation layer 326 can be disposed on the second substrate 320 by the aforementioned deposition technique. Finally, the transparent electrode layer 313 of the first backplate 31 is disposed on the second backplate 32, facing the second contact pad 325 and the isolation layer 326, to complete the fabrication of the vertical micro-LED unit 30. At this time, a cavity 327 is formed between the first backplate 31 and the second backplate 32, and the projected areas of the first contact pad 312 and the second contact pad 325 along the normal direction of the first backplate 31 at least partially overlap. The transparent electrode layer 313 connects to the second contact pad 325, such that the first circuit layer 311 is electrically connected to the second circuit layer 321. Here, the first circuit layer 311 and the second circuit layer 321 can be used as the two electrodes (including the P-terminal and the N-terminal) of the vertical micro-LED unit 30.

[0413] Please refer to Figure 26 and Figure 33 .like Figure 26 As shown, in some embodiments, the insulating layer 326 includes an opaque material 326A (such as...). Figure 26 (As shown). In other embodiments, the insulating layer 326 includes an opaque material 326A and a light-transmitting material 326B (e.g., ...). Figure 33(As shown). In some embodiments, the isolation layer 326 is used to prevent the light emitted by the micro-LED chip 324 from interfering with the light emitted by the adjacent micro-LED chip 324. Therefore, the opaque material 326A only needs to surround the micro-LED chip 324. In some embodiments, the opaque material 326A can be a black matrix (BM) material or a light-reflective material, such as, but not limited to, alumina, dielectric multilayer film, and reflective resin material. In some embodiments, the light-transmitting material 326B is, for example, but not limited to, silicone, epoxy resin, polyimide, benzocyclobutene, perfluorocyclobutane, SU8 photoresist, acrylic resin, polyethylene phthalate, and polyetherimide. It should be noted that, since the isolation layer 326 is malleable, the opaque material 326A in the isolation layer 326 is only used to make the isolation layer 326 opaque without affecting the malleability of the isolation layer 326.

[0414] In some embodiments, the micro-LED chip 324 is disposed on the second circuit layer 321 using mass transfer technology. It should be noted that when the micro-LED chip 324 is disposed on the second circuit layer 321 using mass transfer, a eutectic metal layer 322 and an alloy layer 323 (e.g., ...) need to be first disposed on the second circuit layer 321. Figure 26 , Figure 28 and Figure 29 As shown, the micro-LED chips 324 serve as a carrier during mass transfer, allowing them to be disposed on and electrically connected to the second circuit layer 321. The eutectic metal layer 322 is used to pre-align the micro-LED chips 324 to their placement positions, and the alloy layer 323 is used to bond the micro-LED chips 324. In some embodiments, the alloy layer 323 is trapezoidal, with the upper base of the trapezoid connected to the eutectic metal layer 322 and the lower base connected to the micro-LED chips 324. In other words, the longer of the two parallel base sides of the trapezoid is connected to the micro-LED chips 324.

[0415] Please refer to Figure 34 and Figure 35 In some embodiments, multiple vertical micro-light-emitting diode units 30 can constitute a vertical micro-light-emitting diode structure 3. Figure 34For example, in this embodiment, the vertical micro-light-emitting diode structure 3 includes three vertical micro-light-emitting diode units 30 (hereinafter referred to as the first micro-light-emitting diode unit 30R, the second micro-light-emitting diode unit 30G, and the third micro-light-emitting diode unit 30B, respectively). The micro-light-emitting diode chip 324R of the first micro-light-emitting diode unit 30R is a red micro-light-emitting diode chip, the micro-light-emitting diode chip 324G of the second micro-light-emitting diode unit 30G is a green micro-light-emitting diode chip, and the micro-light-emitting diode chip 324B of the third micro-light-emitting diode unit 30B is a blue micro-light-emitting diode chip.

[0416] In some embodiments, the first contact pads 312R, 312G, and 312B at least partially overlap the projected areas of the second contact pads 325R, 325G, and 325B along the normal direction of the first backplate 31, and each transparent electrode layer 313R, 313G, and 313B is connected to the corresponding second contact pads 325R, 325G, and 325B and the insulating layer 326. Figures 37 to 39 For example, in this embodiment, the first contact pad 312R and the second contact pad 325R are coaxial with axis A1 (e.g., Figure 37 As shown), the projected areas of the first contact pad 312R and the second contact pad 325R along axis A1 overlap (as shown). Figure 38 and Figure 39 (As shown); the first contact pad 312G and the second contact pad 325G are coaxial with axis A2 (as shown). Figure 37 As shown), the projected areas of the first contact pad 312G and the second contact pad 325G along axis A2 overlap (as shown). Figure 38 and Figure 39 (As shown); the first contact pad 312B and the second contact pad 325B are coaxial with axis A3 (as shown). Figure 37 As shown), the projected areas of the first contact pad 312B and the second contact pad 325B along axis A3 overlap (as shown). Figure 38 and Figure 39 (As shown).

[0417] In some embodiments, the vertical micro-LED structure 3 can be applied in a micro-LED display device. The vertical micro-LED structure 3 constitutes a pixel in the micro-LED display device, and the first micro-LED unit 30R, the second micro-LED unit 30G, and the third micro-LED unit 30B are each a sub-pixel. In some embodiments, any one of the first micro-LED unit 30R, the second micro-LED unit 30G, and the third micro-LED unit 30B is adjacent to at least one of the other two. In other words, each sub-pixel in a single pixel of the micro-LED display device is adjacent to at least one of the other two sub-pixels. If two adjacent sub-pixels belong to different pixels, they are not considered "adjacent" as described herein.

[0418] Please refer to Figures 26 to 31 and Figures 34 to 40 The following will be based on Figures 26 to 31 , Figures 34 to 39 The manufacturing process and steps of the vertical micro-light-emitting diode structure 3 are illustrated using an example. Figure 40 As shown, when manufacturing the vertical micro-LED structure 3 begins, the first backplate 31 and the second backplate 32 are formed separately (steps S33 and S34). It should be noted that the order of step S33 (forming the first backplate 31) and step S34 (forming the second backplate 32) can be interchanged. In other words, the vertical micro-LED structure 3 can be formed with the first backplate 31 first, followed by the second backplate 32 (e.g., ...). Figure 40 (As shown), the second backplate 32 can also be formed first, followed by the first backplate 31.

[0419] like Figure 35 As shown, in step S33 of forming the first backplane 31, a plurality of first circuit layers 311 are first disposed on the first substrate 310 (step S330). In other words, the first circuit layers 311R, 311G, and 311B of each of the vertical micro-light-emitting diode units 30R, 30G, and 30B are disposed on the same first substrate 310. It should be noted that the first circuit layers 311R, 311G, and 311B are disposed adjacent to each other on the first substrate 310, and the first circuit layers 311R, 311G, and 311B are not electrically connected to each other.

[0420] After step S330, multiple first contact pads 312R, 312G, and 312B are disposed on corresponding multiple first circuit layers 311R, 311G, and 311B (step S331). Subsequently, multiple transparent electrode layers 313R, 313G, and 313B are disposed on corresponding multiple first circuit layers 311 and multiple first contact pads 312R, 312G, and 312B (step S332). A gap is left between each of the multiple first contact pads 312R, 312G, and 312B, and a gap is also left between each of the multiple transparent electrode layers 313R, 313G, and 313B (e.g., ...). Figure 35 (As shown). Here, the first circuit layer 311R, the first contact pad 312R and the transparent electrode layer 313R are electrically connected to each other, the first circuit layer 311G, the first contact pad 312G and the transparent electrode layer 313G are electrically connected to each other, and the first circuit layer 311B, the first contact pad 312B and the transparent electrode layer 313B are electrically connected to each other.

[0421] like Figure 36 As shown, in step S34 of forming the second backplane 32, multiple second circuit layers 321R, 321G, and 321B are first disposed on the second substrate 320 (step S340). Similar to the first backplane 31, the second circuit layers 321R, 321G, and 321B of the vertical micro-light-emitting diode units 30R, 30G, and 30B are disposed on the same second substrate 320, and there is a gap between each of the multiple second circuit layers 321R, 321G, and 321B.

[0422] Following step S340, red micro-LED chips 324R, green micro-LED chips 324G, and blue micro-LED chips 324B are disposed on corresponding second circuit layers 321R, 321G, and 321B (step S341). Subsequently, multiple second contact pads 325R, 325G, and 325B are disposed on the red micro-LED chips 324R, green micro-LED chips 324G, and blue micro-LED chips 324B respectively (step S342), wherein each second contact pad 325R, 325G, and 325B corresponds to each first contact pad 312R, 312G, and 312B. Here, the micro-LED chip 324 is electrically connected to the second circuit layer 321 and the second contact pad 325.

[0423] After step S342, an isolation layer 326 is disposed on the second substrate 320 to surround the red micro-LED chip 324R, the green micro-LED chip 324G, and the blue micro-LED chip 324B (step S343). Finally, the plurality of transparent electrode layers 313R, 313G, and 313B of the first backplate 31 are disposed on the second backplate 32 facing the plurality of second contact pads 325R, 325G, 325B and the isolation layer 326 (step S35) to complete the fabrication of the vertical micro-LED structure 3. At this time, a plurality of chambers 327 are formed between the first backplate 31 and the second backplate 32, and the projected areas of each first contact pad 312R, 312G, 312B and each second contact pad 325R, 325G, 325B along the normal direction of the first backplate 31 at least partially overlap. In this configuration, each transparent electrode layer 313R, 313G, and 313B is connected to a corresponding second contact pad 325R, 325G, and 325B, such that each first circuit layer 311R, 311G, and 311B is electrically connected to a corresponding second circuit layer 321R, 321G, and 321B. Thus, the paired first circuit layer 311 and second circuit layer 321 can each be used as a two-electrode (including P-terminal and N-terminal) of the vertical micro-LED units 30R, 30G, and 30B.

[0424] It should be noted that the thickness of the red LED chip 324R is greater than the thickness of the green LED chip 324G and the blue LED chip 324B, and the thickness of the green LED chip 324G is approximately equal to the thickness of the blue LED chip 324B. Therefore, in some embodiments, the thickness of the first contact pad 312G and the first contact pad 312B is greater than the thickness of the first contact pad 312R, so that the first backplate 31 can be stably disposed on the second backplate 32.

[0425] Similar to the manufacturing process of the vertical micro-LED unit 30, in some embodiments, micro-LED chips 324R, 324G, and 324B are respectively disposed on the second circuit layer 321 using mass transfer technology. Furthermore, when the micro-LED chips 324R, 324G, and 324B are respectively disposed on the corresponding second circuit layers 321R, 321G, and 321B using mass transfer, a eutectic metal layer 322 and an alloy layer 323 (e.g., ...) need to be first disposed on the second circuit layers 321R, 321G, and 321B. Figure 34 , Figure 36 and Figure 37 As shown, the micro-LED chips 324R, 324G, and 324B serve as carriers for mass transfer during the transfer of each micro-LED chip 324R, 324G, and 324B. Only then can the micro-LED chips 324R, 324G, and 324B be disposed on the corresponding second circuit layers 321R, 321G, and 321B and electrically connected to them.

[0426] According to any embodiment, employing a dual-backplane structure (i.e., a first backplane and a second backplane) to assemble and manufacture micro-light-emitting diodes avoids various problems caused by current filling techniques. Furthermore, by adjusting the contact pad thickness accordingly based on the die thickness of the micro-light-emitting diodes of different emission colors, and ensuring that the contact pads on the top surface of each micro-light-emitting diode unit are located on the same plane as much as possible, the micro-light-emitting diodes can avoid open-circuit problems, thereby improving the yield during micro-light-emitting diode manufacturing and the reliability of the micro-light-emitting diodes themselves.

[0427] Rereference Figure 1 In some embodiments, the pixel structure 50 includes a substrate 500, a plurality of vertical diode chips 520, flip-chip diode chips 530, and an upper wiring layer 540. In some embodiments, the pixel structure 50 may face the problem that mass transfer technology cannot accurately and effectively move a large number of vertical diode chips 520 or flip-chip diode chips 530, causing a bottleneck in the panel structure manufacturing process. See also... Figure 21 In some embodiments, the vertical diode die 520 can adopt a structure similar to that of diode die 60. Diode die 60 includes a top electrode 62, an epitaxial layer 63, a bottom electrode 64, and a conductor layer 68. The bottom electrode 64 can have a trapezoidal structure to facilitate pre-alignment of the diode dies 60 before transfer, enabling the efficient transfer of a large number of diode dies 60. In some embodiments, the pre-alignment apparatus and pre-alignment method described in the following embodiments can be applied to the transfer of the vertical diode die 520 or the flip-chip diode die 530. However, the present invention is not limited thereto. Under different design considerations or application scenarios, other structures, processes, or manufacturing processes can be used to process the vertical diode die 520 or the flip-chip diode die 530 disclosed in this invention.

[0428] Please refer to Figure 41 and Figure 42 A pre-alignment device 2 includes a vibrator 20, an alignment tray 21, multiple electromagnets 22, and a controller 23. The vibrator 20 includes multiple side walls 201 and a base plate 202, with the multiple side walls 201 disposed around the base plate 202 (e.g., ...). Figure 42 (As shown). The array of trays 21 is disposed on the base plate 202 and includes a plurality of grooves 210 arranged in an array, and the bottom of each groove 210 includes a through hole 211. Figure 42 For example, in this embodiment, the array 21 includes 36 grooves 210 arranged in an array of 6 rows and 6 columns.

[0429] Each electromagnet 22 is disposed in each through hole 211, and each electromagnet 22 is used to generate a magnetic field along the extending direction of the through hole 211. Figure 41 For example, in this embodiment, the extension direction of the through hole 211 is the Y direction. Therefore, each electromagnet 22 generates a magnetic field along the Y direction. The controller 23 is electrically connected to the plurality of electromagnets 22, and the controller 23 is used to control each electromagnet 22 to generate a magnetic field. In other words, in some embodiments, each electromagnet 22 can be controlled independently. Therefore, when the controller 23 controls all the electromagnets 22 to be energized to generate a magnetic field, the magnitude of the magnetic field generated by each electromagnet 22 is the same, so that each through hole 211 in the entire array 21 has a magnetic field of the same magnitude.

[0430] In some embodiments, the electromagnet 22 is a coil of wire comprising at least one turn. Furthermore, in this embodiment, the electromagnet 22 also includes a columnar body (e.g., but not limited to, a cylinder, triangular prism, square prism, or polygonal prism) having a magnetically conductive material, and at least one coil of wire in the electromagnet 22 is wrapped around this columnar body to magnetize it, thereby enhancing the strength of the magnetic field generated by the electromagnet 22. The magnetically conductive material of this columnar body is, for example, but not limited to, iron (Fe), cobalt (Co), nickel (Ni), chromium (Cr), molybdenum (Mo), and alloys comprising at least two of the above materials.

[0431] In some embodiments, the controller 23 may be a circuit module integrated into the vibratory machine 20 and having control functions. Figure 41 For example, in this embodiment, the controller 23 is a circuit layer and is disposed in the base plate 202 of the vibratory machine 20. In other embodiments, the controller 23 may also be a hardware component (not shown) that is independent of the pre-alignment device 2 and has control functions, such as, but not limited to, a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a microcontroller unit (MCU).

[0432] Please refer to Figures 41 to 46 ,in Figure 45 and Figure 46 They are respectively Figure 44 Enlarged schematic diagrams of a single groove 210 within the dashed box R21 and R22. The following will use... Figure 41 The pre-alignment method for multiple micro-LED units 24 is illustrated using the pre-alignment device 2 shown as an example, but this is not intended to limit the devices, hardware components, or software components that perform the pre-alignment method. When the pre-alignment device 2 begins to pre-align multiple micro-LED units 24, the user can place the multiple micro-LED units 24 on the alignment disk 21 of the pre-alignment device 2 (step S20). Figure 44 For example, in this embodiment, multiple scattered micro-light-emitting diode units 24 are arbitrarily placed on the array disk 21.

[0433] After step S20, the pre-alignment device 2 generates an attractive force F21 along the extending direction of each through hole 211 (step S21), and the pre-alignment device 2 generates a vibration force F22 through the vibrator 20, causing the alignment tray 21 to vibrate (step S22). In some embodiments, when the alignment tray 21 begins to vibrate, each micro-LED unit 24 moves into each groove 210 of the alignment tray 21 with the vibration. Figure 45 or Figure 46 As shown, in this embodiment, the pre-aligning device 2 generates an attractive force F21 along the extension direction of each through hole 211, and the direction of force application of the attractive force F21 is parallel to the Y direction. Furthermore, the direction of force application of the vibration force F22 generated by the vibrator 20 is also parallel to the Y direction, and the direction of force application of the vibration force F22 is opposite to the direction of force application of the attractive force F21. Therefore, in some embodiments, the attractive force F21 generated by the pre-aligning device 2 and the vibration force F22 generated by the vibrator 20 can cancel each other out. Specifically, when the attractive force F21 is greater than the vibration force F22, the vibration force F22 is eliminated, leaving only the attractive force F21; when the attractive force F21 is less than the vibration force F22, the attractive force F21 is eliminated, leaving only the vibration force F22.

[0434] In some embodiments, when the attractive force F21 is greater than the vibrational force F22 (e.g.) Figure 45 As shown), the micro-LED units 24 that have moved into the grooves 210 are fixed in each groove 210 by the attractive force F21. In other embodiments, when the attractive force F21 is less than the vibration force F22 (e.g., Figure 46 As shown, the micro-LED units 24 that have moved into the grooves 210 are detached from each groove 210 by the vibration force F22. Thus, through the interaction between the attraction force F21 and the vibration force F22, each micro-LED unit 24 can gradually move into each groove 210 to arrange itself into another array, where the other array corresponds to the array formed by the arrangement of multiple grooves 210. Figure 42 For example, in this embodiment, due to Figure 42 The array 21 shown contains 36 grooves 210. Figure 42The pre-alignment device 2 shown can arrange 36 micro-light-emitting diode units in the same plane and neatly by pre-alignment method.

[0435] In some embodiments, the thickness of the alignment tray 21 is less than the height of each sidewall 201. Thus, when the alignment tray 21 begins to vibrate, even if the attractive force F21 on the micro-LED unit 24 is less than the vibration force F22, the micro-LED unit 24 can be blocked by the sidewalls 201 around the vibrating machine 20 and will not be dislodged from the pre-alignment device 2 by the vibration force F22.

[0436] In some embodiments, the attractive force F21 generated by the pre-alignment device 2 in step S22 is a magnetic force or a vacuum force. Figure 45 and Figure 46 For example, in this embodiment, the attractive force F21 generated by the pre-alignment device 2 is a magnetic attraction. Here, the pre-alignment device 2 includes hardware components for generating a magnetic field, such as, but not limited to, an electromagnet 22. Furthermore, in this embodiment, each micro-LED unit 24 needs to be magnetically permeable so that the magnetic field generated by the electromagnet 22 can generate a magnetic attraction force (i.e., attractive force F21) on each micro-LED unit 24. Therefore, in some embodiments, each micro-LED unit 24 includes a micro-LED die 241, a carrier layer 242, and a magnetically permeable layer 243 (e.g., ...). Figure 45 and Figure 46 (As shown).

[0437] In some embodiments, a carrier layer 242 is disposed on a magnetically conductive layer 243, and a micro-LED die 241 is disposed on the carrier layer 242. Both the carrier layer 242 and the magnetically conductive layer 243 are trapezoidal in shape, and the width of the bottom of the magnetically conductive layer 243 is smaller than the width of the bottom of each groove 210. Figure 45 For example, in this embodiment, the micro-LED chip 241 is disposed on the upper bottom of the carrier layer 242, and the carrier layer 242 is disposed on the upper bottom of the magnetic conductive layer 243. The width of the lower bottom of the carrier layer 242 is equal to the width of the upper bottom of the magnetic conductive layer 243, and the width of the lower bottom of the magnetic conductive layer 243 is less than the width of the bottom of each groove 210.

[0438] In some embodiments, the material of the carrier layer 242 is conductive and non-magnetic, such as, but not limited to, aluminum (Al), copper (Cu), and their alloys. In some embodiments, the material of the magnetic layer 243 is magnetic, such as, but not limited to, iron, cobalt, nickel, chromium, molybdenum, and alloys containing at least two of the above materials.

[0439] In some embodiments, the material of the alignment tray 21 is a non-magnetic insulating material, such as, but not limited to, glass, silicone, epoxy, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), polyetherimide, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), and silicon carbide (SiC). Here, the pre-alignment device 2 ensures that the magnetic force generated by each electromagnet 22 does not affect the alignment tray 21.

[0440] In some embodiments, when each micro-LED unit 24 moves into each recess 210, the orientation of each micro-LED unit 24 determines the magnitude of the attractive force F21. Figure 45 For example, in this embodiment, the micro-light-emitting diode unit 24 is disposed in the groove 210 with the micro-light-emitting diode die 241 facing upwards. At this time, the magnetically conductive layer 243 directly contacts the bottom of the groove 210; and with Figure 46 For example, in this embodiment, the micro-LED unit 24 is disposed in the groove 210 with the magnetic layer 243 facing upward. At this time, the non-magnetic micro-LED chip 241 directly contacts the bottom of the groove 210.

[0441] In some embodiments, since Figure 45 The distance between the magnetically conductive layer 243 and the electromagnet 22 in the micro-LED unit 24 shown is less than [missing information]. Figure 46 The distance between the magnetically conductive layer 243 and the electromagnet 22 in the micro LED unit 24 shown is... Figure 45 The attractive force F21 (i.e., magnetic attraction) experienced by the micro-LED unit 24 shown is greater than Figure 46 The micro-LED unit 24 shown is subjected to an attractive force F21 (i.e., magnetic attraction). In some embodiments, the user can adjust the value of the vibration force F22 generated by the vibrator 20 in the pre-alignment device 2 to be between... Figure 45 The value of the attraction F21 shown is related to Figure 46 The values ​​of the attractive force F21 shown indicate that the micro-LED unit 24 experiences different forces when it moves into the groove 210 in different orientations.

[0442] by Figure 45For example, in this embodiment, when the micro-LED unit 24 is disposed in the groove 210 with the micro-LED die 241 facing upward, the attractive force F21 received by the micro-LED unit 24 is greater than the vibration force F22, so that the micro-LED unit 24 is fixed in each groove 210 by the attractive force F21. Furthermore, Figure 46 For example, in this embodiment, when the micro-LED unit 24 is disposed in the groove 210 with the magnetic layer 243 facing upward, the attractive force F21 on the micro-LED unit 24 is less than the vibration force F22, causing the micro-LED unit 24 to detach from the groove 210 under the action of the vibration force F22. Thus, when the pre-alignment device 2 completes the pre-alignment of multiple micro-LED units 24, it means that all micro-LED units 24 are fixed in the groove 210 with the micro-LED die 241 facing upward, so that all micro-LED units 24 are facing upward.

[0443] In some embodiments, after step S22, when all micro-LED units 24 are fixed in their respective grooves 210, it indicates that the pre-alignment device 2 has pre-aligned all the micro-LED units 24. At this time, the pre-alignment device 2 first stops generating the vibration force F22 (step S23) so that the micro-LED units 24 are fixed in the grooves 210 only by the attraction force F21, thereby preventing the micro-LED units 24 from detaching from the grooves 210. Subsequently, the pre-alignment device 2 stops generating the attraction force F21 (step S24) so ​​that the micro-LED units 24 are no longer attracted by the attraction force F21 and can move. At this time, the user can continue to perform mass transfer of the micro-LED units 24.

[0444] In some embodiments, the height of each micro-LED unit 24 is greater than the depth of each groove 210. In other words, when the micro-LED unit 24 is disposed in the groove 210, the micro-LED unit 24 protrudes from the top surface of the groove 210 (e.g., Figure 45 or Figure 46 (As shown). Therefore, during the pre-alignment process performed by the pre-alignment device 2, when each micro-LED unit 24 is not fixed in its respective groove 210, each micro-LED unit 24 can easily detach from its respective groove 210 without being blocked by the walls of the groove 210. Furthermore, when the pre-alignment device 2 has completed the pre-alignment process and the user begins to perform a large-scale transfer of the micro-LED units 24, the micro-LED units 24 can be easily moved without being stuck in the groove 210.

[0445] Please refer to Figure 41 and Figure 47 .like Figure 41As shown, in some embodiments, each groove 210 can be trapezoidal in shape, and the width of the bottom of each groove 210 is smaller than the width of the top surface of each groove 210. In other words, the bottom of each groove 210 corresponds to the upper base of the trapezoid, and the top surface of each groove 210 corresponds to the lower base of the trapezoid. Therefore, when the micro-LED unit 24 moves into the groove 210 and the attractive force F21 is greater than the vibration force F22, the micro-LED unit 24 can be stably fixed in the groove 210. Furthermore, the trapezoidal shape ensures that the micro-LED unit 24 not yet fixed in the groove 210 can easily detach from the groove 210 during vibration.

[0446] like Figure 47 As shown, in some embodiments, each groove 210 may also be rectangular. In this case, when the micro-LED unit 24 moves into the groove 210 and the attractive force F21 is greater than the vibration force F22, the micro-LED unit 24 can be stably fixed in the groove 210. Furthermore, the rectangular shape ensures that the micro-LED unit 24, already fixed in the groove 210, will not easily detach from the groove 210 during vibration.

[0447] According to any embodiment, the pre-alignment device and method can arrange scattered micro-LED units on the same surface and neatly, enabling mass transfer technology to accurately and efficiently move a large number of micro-LED units. Furthermore, regardless of whether the micro-LED units are magnetically conductive, the pre-alignment method can generate a corresponding attractive force (e.g., but not limited to magnetic attraction or vacuum attraction) to fix the micro-LED units in the grooves of the alignment disk.

[0448] Rereference Figure 1 In some embodiments, the pixel structure 50 includes a substrate 500, a plurality of vertical diode dies 520, a flip-chip diode die 530, and an upper wiring layer 540. In some embodiments, the pixel structure 50 may face the problem of lacking a suitable method to ensure that the plurality of vertical diode dies 520 or flip-chip diode dies 530 remain aligned and unskewed after detaching from the PDMS film, causing a bottleneck in the manufacturing process of the pixel structure 50. In some embodiments, the alignment apparatus and alignment method described below can be applied to the transfer of the vertical diode dies 520 or flip-chip diode dies 530. However, the present invention is not limited thereto; under different design considerations or application scenarios, other structures, processes, or manufacturing techniques may be employed to process the vertical diode dies 520 or flip-chip diode dies 530 disclosed in this invention.

[0449] Please refer to Figures 48 to 50An aligning device 1 includes a support disk 10 and an aligning disk 11. The support disk 10 includes a plurality of grooves 100, each groove 100 extending along a first direction and the plurality of grooves 100 spaced apart along a second direction, wherein the first direction is orthogonal to the second direction. In other words, the first direction is perpendicular to the second direction. Figure 49 For example, in this embodiment, the support disk 10 includes six grooves 100, with a first direction corresponding to the Z direction and a second direction corresponding to the X direction. Each of the six grooves 100 extends along the Z direction, and the six grooves 100 are spaced apart along the X direction.

[0450] A row of trays 11 is disposed on a support tray 10. The row of trays 11 includes multiple rows RX, which are spaced apart along a second direction and individually aligned with multiple grooves 100. Each row of RX has multiple recesses 110, and the bottom of each recess 110 includes a through hole 111. The recesses 110 in each row of RX are spaced apart along a first direction. Figure 50 For example, in this embodiment, the array disk 11 includes 6 columns R11 to R16, and each column R11 / R12 / R13 / R14 / R15 / R16 includes 6 grooves 110. The columns R11 to R16 are spaced apart along the X direction (i.e., the second direction) and individually aligned with the grooves 100, and the 6 grooves 110 in each column R11 / R12 / R13 / R14 / R15 / R16 are spaced apart along the Z direction (i.e., the first direction). Therefore, the array disk 11 includes 36 grooves 110, and the 36 grooves 110 are arranged in an array on the array disk 11.

[0451] Please refer to Figures 48 to 53 The following will be in the format of... Figure 48 The arrangement device 1 shown is used as an example to illustrate the arrangement method of multiple micro-light-emitting diode units 12, but this is not intended to limit the device, hardware component, or software component performing the arrangement method. When the user begins to arrange multiple micro-light-emitting diode units 12, the user operates a moving mechanism (not shown) to move the pre-arranged multiple micro-light-emitting diode units 12 disposed on a carrier plate 13 to a position vertically above the arrangement disk 11 (step S10). It should be noted that "pre-arranged multiple micro-light-emitting diode units 12" means that the multiple micro-light-emitting diode units 12 on the carrier plate 13 have been pre-arranged into another array, and the other array corresponds to the array formed by the spaced arrangement of multiple recesses 110. Here, when the multiple micro-light-emitting diode units 12 are moved to a position vertically above the arrangement disk 11, each micro-light-emitting diode unit 12 is located vertically above each recess 110 on the arrangement disk 11 (e.g., ...). Figure 52 (As shown).

[0452] In some embodiments, the moving mechanism may be a device having the function of two-dimensionally moving an object, such as, but not limited to, a robotic arm. In some embodiments, the carrier plate 13 includes a substrate layer 131, a thin film layer 132, and a plurality of bumps 133. The thin film layer 132 is disposed on the lower surface of the substrate layer 131, and the plurality of bumps 133 are disposed on the lower surface of the thin film layer 132 (e.g., ...). Figure 52 (As shown). Here, the user can attach multiple micro-LED units 12 to the multiple bumps 133 on the carrier plate 13, and then move the multiple micro-LED units 12.

[0453] In some embodiments, the substrate layer 131 may be made of a transparent insulating material, such as, but not limited to, glass, silicone, epoxy, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene terephthalate (PET), and polyetherimide. In other embodiments, the substrate layer 131 may be made of an opaque insulating material, such as, but not limited to, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), and silicon carbide (SiC). Furthermore, in some embodiments, the materials of the thin film layer 132 and the plurality of bumps 133 may be flexible materials with adhesion properties, such as, but not limited to, polydimethylsiloxane (PDMS) or polysiloxane.

[0454] After step S10, the alignment device 1 generates an attractive force F11 along the extension direction of the through-hole 111 to move each micro-LED unit 12 from the carrier plate 13 to the bottom of each groove 110 (step S11). In some embodiments, the alignment device 1 further includes a vacuum machine 14 and a controller 15. The vacuum machine 14 is coupled to a plurality of grooves 100 on the support plate 10, and the controller 15 is electrically connected to the vacuum machine 14. In some embodiments, the alignment device 1 can control the vacuum machine 14 to evacuate the plurality of grooves 100 via the controller 15, thereby generating a vacuum suction force (i.e., attractive force F11) along the extension direction of each through-hole 111 to apply force to each micro-LED unit 12 (e.g., ...). Figure 52 (As shown). Here, each micro-LED unit 12 is detached from its respective bump 133 on the carrier plate 13 by the attractive force F11, and then moves to the bottom of its respective groove 110 (as shown). Figure 53 (As shown).

[0455] In some embodiments, the controller 15 may be a hardware component with control functions that is independent of the vacuum machine 14, such as, but not limited to, a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a microcontroller unit (MCU). In other embodiments, the controller 15 may also be a circuit module with control functions integrated into the vacuum machine 14.

[0456] Please refer to Figures 48 to 57 .like Figure 54 As shown, in some embodiments, the aligning device 1 can further perform a lighting test on the multiple micro-LED units 12 to check whether the multiple micro-LED units 12 are functioning normally. Here, in this embodiment, the aligning disk 11 of the aligning device 1 includes a conductive film 16, and the conductive film 16 is disposed on the wall surface of each groove 110 (e.g., Figure 55 (As shown).

[0457] In some embodiments, after step S11, the aligning device 1 first stops generating the attractive force F11 (step S12). Subsequently, the user can operate the aforementioned moving mechanism to place a transparent cover plate TC1 above the aligning tray 11 (step S13). A conductive film 134 is also formed on the lower surface of the transparent cover plate TC1. Therefore, in this embodiment, when the transparent cover plate TC1 is placed above the aligning tray 11 such that the conductive film 134 of the transparent cover plate TC1 is directly connected to multiple micro-light-emitting diode units 12 (e.g., ... Figure 56 As shown, the conductive film 134 of the transparent cover plate TC1 and the conductive film 16 of the array disk 11 can serve as the two terminals (i.e., the N-pole and the P-pole) of the micro light-emitting diode unit 12.

[0458] In some embodiments, the user can electrically connect one of the conductive film 134 of the transparent cover plate TC1 and the conductive film 16 of the array tray 11 to an external power source, and ground the other of the conductive film 134 of the transparent cover plate TC1 and the conductive film 16 of the array tray 11. Then, after step S13, the user can control the external power source to power the multiple micro-LED units 12 through the conductive film 134 of the transparent cover plate TC1 and the conductive film 16 of the array tray 11 (step S14), thereby performing a lighting test on the multiple micro-LED units 12.

[0459] In some embodiments, after the lighting test of the plurality of micro-LED units 12 is completed (i.e., after step S14), the user operates the moving mechanism to remove the transparent cover TC1 (step S15). Subsequently, the user operates the moving mechanism to remove the damaged micro-LED unit 12 (step S16). Figure 57 For example, in this embodiment, another carrier plate 13' is coupled to the moving mechanism (not shown), and the other carrier plate 13' includes the aforementioned substrate layer 131, thin film layer 132, and a single bump 133. Thus, when performing the step of removing the damaged micro-LED unit 12 (i.e., step S16), the moving mechanism can only remove one damaged micro-LED unit 12 at a time.

[0460] Please refer to Figures 48 to 52 and Figures 58 to 60 .like Figure 59 As shown, in some embodiments, the alignment device 1 further includes a tilting mechanism 17. The tilting mechanism 17 is disposed on the lower surface of the support disk 10 and electrically connected to the controller 15, and the controller 15 is also used to control the tilting mechanism 17. Here, after each micro-LED unit 12 has been disposed in each groove 110 (i.e., after step S11), the alignment device 1 can control the vacuum machine 14 to stop generating the attractive force F11 (i.e., vacuum suction) via the controller 15 (step S12). Subsequently, the alignment device 1 can control the tilting mechanism 17 to tilt via the controller 15, causing the alignment disk 11 to tilt accordingly so that each micro-LED unit 12 aligns with a wall of each groove 110 (step S17). Figure 60 For example, in this embodiment, the tilting mechanism 17 tilts in a clockwise direction. Here, the right half of the array disk 11 tilts downward, so that each micro-LED unit 12 is aligned with the right side wall of each groove 110.

[0461] It should be noted that the tilting mechanism 17 is not limited to tilting in a clockwise direction. In other embodiments, the tilting mechanism 17 may also tilt in a counterclockwise direction, so that the left half of the array disk 11 tilts downward, thereby aligning each micro LED unit 12 with the left side wall of each groove 110 (not shown).

[0462] Please refer to Figures 48 to 52 and Figures 61 to 63 .like Figure 62 As shown, in some embodiments, the alignment device 1 further includes a vibrator 18. The vibrator 18 is disposed on the lower surface of the support disk 10 and electrically connected to the controller 15, which also controls the vibrator 18. Here, after each micro-LED unit 12 has been disposed in each recess 110 (i.e., after step S11), the alignment device 1 can control the vacuum machine 14 to stop generating the attractive force F11 (i.e., vacuum suction) via the controller 15 (step S12). Subsequently, the alignment device 1 can control the vibrator 18 to generate a vibration force F12 to cause the alignment disk 11 to vibrate (step S18). In response to the vibration of the alignment disk 11, each micro-LED unit 12 aligns with a wall of each recess 110. Figure 63 For example, in this embodiment, the vibrator 18 generates a vibration force F12 in the X direction to cause the entire array of disks 11 to vibrate in the X direction. Here, a frictional force (not shown) in the opposite direction to the X direction is generated between each micro-LED unit 12 and the bottom of each groove 110, causing each micro-LED unit 12 to be displaced to the left by the frictional force, thereby aligning each micro-LED unit 12 with the left side wall of each groove 110.

[0463] It should be noted that the vibrator 18 is not limited to generating a vibration force F12 in the X direction. In some other embodiments, the vibrator 18 may also generate a vibration force F12 in the opposite direction to the X direction, so that each micro LED unit 12 and the bottom of each groove 110 generate a frictional force in the X direction, thereby causing each micro LED unit 12 to be displaced to the right and aligned with the right side wall of each groove 110 (not shown) under the action of the frictional force.

[0464] In some embodiments, the support disk 10 is a non-conductive rigid material, such as, but not limited to, glass, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), and silicon carbide (SiC). Furthermore, in some embodiments, the array disk 11 is an insulating material, such as, but not limited to, silicone, epoxy, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), and polyetherimide. Here, thanks to the properties of the material of the support disk 10, the sidewalls surrounding each groove 100 in the support disk 10 can support the array disk 11, thereby ensuring that the array disk 11 is not deformed by attractive force F11 (e.g., but not limited to vacuum suction) or vibration force F12.

[0465] According to any embodiment, the aligning device and method can remove the pre-aligned multiple micro-light-emitting diode (LED) units from their films and place each LED unit in a groove of the aligning disk. Furthermore, the aligning device and method can align each LED unit to a wall of a groove using a tilting mechanism or a vibrating machine to achieve a neat arrangement of the multiple LED units, thereby improving the accuracy and efficiency of subsequent mass transfer of the multiple LED units.

[0466] Although the present invention has been clearly disclosed according to the different embodiments described above, the embodiments are not intended to limit the present invention. Any modifications, substitutions or omissions made by those skilled in the art relative to the above embodiments without departing from the spirit and scope of the present invention shall still fall within the technical scope protected by the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A pixel structure, characterized in that, This pixel structure contains: The substrate has a lower wiring layer, which includes a plurality of first wirings and a second wiring, wherein the first wirings are of a first polarity and the second wiring is of a second polarity. Multiple vertical diode chips are disposed on the substrate and are respectively coupled to the first traces; A flip-chip diode die is disposed on the substrate and coupled to one of the first traces and the second trace; as well as An upper trace layer is disposed on the plurality of vertical diode chips and the flip-chip diode chip. The upper trace layer includes a plurality of third traces, which are respectively coupled to the vertical diode chips. The third traces belong to the second polarity.

2. The pixel structure as described in claim 1, characterized in that, The pixel structure also includes a light-transmitting filling layer and multiple blocks, which define multiple receiving sites. The multiple vertical diode chips and the multiple flip-chip diode chips are respectively located within the multiple receiving sites. The light-transmitting filling layer covers the flip-chip diode chips, and the top surface of the light-transmitting filling layer is substantially coplanar with the top surface of the blocks.

3. The pixel structure as described in claim 1, characterized in that, The plurality of vertical diode chips include at least one inactive vertical diode and at least one active vertical diode, and the color category of the light beam corresponding to the flip-chip diode chip is different from the color category of the light beam corresponding to the at least one active vertical diode.

4. The pixel structure as described in claim 1, characterized in that, The pixel structure also includes multiple first light conversion material layers, each covering the top of the vertical diode die.

5. The pixel structure as described in claim 1, characterized in that, The pixel structure also includes a second light conversion material layer covering the flip-chip diode die.

6. The pixel structure as described in claim 1, characterized in that, The pixel structure also includes vertical diode die units, comprising: The first back panel includes: Another substrate; The upper wiring layer is disposed on the other substrate; The first contact pad is disposed on the upper trace layer; and A transparent electrode layer is disposed on the upper wiring layer and the first contact pad; as well as The second back panel includes: The substrate; The lower wiring layer is disposed on the substrate; A eutectic metal layer is disposed on the lower trace layer; An alloy layer is disposed on the eutectic metal layer; Firstly, the vertical diode die is disposed on the alloy layer; A second contact pad is disposed on one of the vertical diode chips; and An isolation layer is disposed on the substrate to surround one of the vertical diode chips; The first backplate is disposed on the second backplate to form a cavity, the projected areas of the first contact pad and the second contact pad along the normal direction of the first backplate at least partially overlap, and the transparent electrode layer connects the second contact pad and the isolation layer. When the first backplate is disposed on the second backplate, the isolation layer is deformed such that the thickness of the deformed isolation layer is equal to the sum of the thickness of the first contact pad, the thickness of the lower trace layer, the thickness of the eutectic metal layer, the thickness of the alloy layer, the thickness of one of the vertical diode chips, and the thickness of the second contact pad.

7. The pixel structure as described in claim 6, characterized in that, The isolation layer of the vertical diode die unit includes an opaque material and a transparent material, wherein the opaque material surrounds one of the vertical diode dies and the second contact pad, and the transparent material surrounds the lower trace layer, the eutectic metal layer and the alloy layer.

8. The pixel structure as described in claim 1, characterized in that, These multiple vertical diode chips contain: A first diode die, comprising a first electrode having a first electrode thickness; and The second diode die includes a second electrode with a second electrode thickness. The thickness of the first electrode is greater than the thickness of the second electrode. The first diode die and the second diode die have substantially the same die height.

9. The pixel structure as described in claim 8, characterized in that, The first electrode is the bottom electrode of the first diode die, and the second electrode is the bottom electrode of the second diode die.

10. A panel structure, characterized in that, The panel structure includes a plurality of pixel structures as described in claim 8, each including the first diode chip and the second diode chip, wherein the first electrode of the first electrode of the first diode chip of each pixel structure has substantially the same thickness, and the second electrode of the second electrode of the second diode chip of each pixel structure has substantially the same thickness.

11. A panel structure, characterized in that, The panel structure includes: The substrate has a lower wiring layer, which includes a plurality of first wirings and a plurality of second wirings, wherein the first wirings are of a first polarity and the second wirings are of a second polarity. A first pixel structure having multiple first accommodating sites, the first pixel structure comprising: A plurality of first vertical diode chips are disposed on the substrate and respectively located within the first accommodating sites, and respectively coupled to the first traces; and A flip-chip diode die is disposed on the substrate and located within one of its first receiving sites, and coupled to one of its first traces and one of its second traces; The second pixel structure has multiple second accommodating sites, the second pixel structure comprising: Multiple second vertical diode chips are disposed on the substrate and located within the second accommodating sites, and are respectively coupled to the first traces; as well as A filler layer is disposed on the substrate and located within one of the second receiving sites; as well as An upper trace layer is disposed on the first pixel structure and the second pixel structure. The upper trace layer includes multiple third traces that are respectively coupled to the first vertical diode chips and the second vertical diode chips. These third traces belong to the second polarity.

12. A pixel structure repair method, characterized in that, This pixel structure repair method includes: Provide substrate; A lower trace layer is formed on the substrate. The lower trace layer includes a first trace and a second trace. The first trace belongs to a first polarity, and the second trace belongs to a second polarity. A vertical diode die is disposed on the substrate and connected to the first trace; and Determine whether the vertical diode chip is effective to decide whether to install a flip-chip diode chip on the substrate.

13. The pixel structure repair method as described in claim 12, characterized in that, The pixel structure repair method also includes setting the flip-chip diode on the substrate when it is determined that the vertical diode chip is invalid.

14. The pixel structure repair method as described in claim 12, characterized in that, This pixel structure restoration method also includes: When the vertical diode chip is determined to be invalid, a flip-chip diode chip is disposed on the substrate; the flip-chip diode chip is a short-wavelength light-emitting diode chip; and A light conversion material layer is coated on top of the flip-chip diode die.

15. The pixel structure repair method as described in claim 12, characterized in that, This pixel structure restoration method also includes: Multiple blocks are formed on the substrate, and the multiple blocks define multiple receiving sites; Multiple vertical diode chips are disposed on the substrate and are respectively located within the accommodating sites; as well as When it is determined that all the vertical diode chips are effective, a filling layer is set within the remaining accommodating sites, where the remaining accommodating sites do not contain the vertical diode chips.

16. The pixel structure repair method as described in claim 12, characterized in that, The pixel structure repair method further includes forming an upper trace layer on the plurality of vertical diode chips and the flip-chip diode chip, the upper trace layer including a third trace coupled to the vertical diode chip, the third trace belonging to the second polarity.

17. A pixel structure, characterized in that, This pixel structure contains: substrate; A red micro-light-emitting diode chip is disposed on the substrate; Green micro-light-emitting diode chips are disposed on the substrate; Blue micro-light-emitting diode chips are disposed on the substrate; A spare micro-light-emitting diode chip is disposed on the substrate; An isolation layer is disposed on the substrate. The isolation layer surrounds the spare micro LED chip and forms an inkjet space with the spare micro LED chip, wherein the inkjet space is used to fill inkjet material. A filler layer is disposed on the substrate to fix the red LED chip, the green LED chip, the blue LED chip, the spare LED chip, and the insulating layer to the substrate; and A light-transmitting layer is disposed on the filler layer; In this configuration, any one of the red micro-LED chip, the green micro-LED chip, the blue micro-LED chip, and the spare micro-LED chip is adjacent to at least one of the other three.

18. The pixel structure as described in claim 17, characterized in that, The spare micro-LED chip is an ultraviolet micro-LED chip, and the light-transmitting layer contains an anti-ultraviolet material.

19. The pixel structure as described in claim 17, characterized in that, The spare microLED chip is another blue microLED chip.

20. The pixel structure as described in claim 19, characterized in that, The spare microLED die is adjacent to the blue microLED die.

21. The pixel structure as described in claim 20, characterized in that, The spare microLED die is more adjacent to the red microLED die or the green microLED die.

22. The pixel structure as described in claim 17, characterized in that, The isolation layer contains an opaque material that surrounds the spare micro-LED die and the inkjet space.

23. The pixel structure as described in claim 17, characterized in that, The isolation layer comprises an opaque material and a translucent material, wherein the opaque material surrounds the inkjet space and the translucent material surrounds the spare micro-LED chip.

24. The pixel structure as described in claim 17, characterized in that, When one of the red, green, and blue LED chips is damaged, the inkjet space is filled with inkjet material of the color corresponding to that chip.

25. The pixel structure as described in claim 17, characterized in that, The spare micro LED chip is a flip-chip diode chip.

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