Resistive random access memory (RERAM) configured to overcome read disturb effects

Abstract

Resistive random access memories (ReRAMs) suffer from read disturb phenomena due to the same voltage polarity used by read and program operations despite at different voltages. After multiple reads, according to the characteristics of each cell, the number of reads can be large or small, and abnormal cells are obviously switched after much less number of reads than other cells. Thus, a process including a set or reset operation of the ReRAM cell is followed by a clear operation. The clear operation includes applying a clear voltage greater than the read voltage and less than the program voltage. Subsequently, a read operation is performed to identify those ReRAM cells that have switched from their intended state. In one embodiment, a reprogramming operation is performed to fix a resistance filament of a ReRAM cell identified as suffering from a read disturb.

Description

Technical Field

[0001] This disclosure generally relates to resistive random-access memory (ReRAM) cells, and more particularly to read interference or ReRAM cells. Background Technology

[0002] Typical resistive random access memory (ReRAM) devices suffer from a phenomenon known as read interference. While small read voltages may not interfere with the current state of a ReRAM cell, the cell distribution makes these events non-negligible. Interference occurs when a cell that should be in a low-resistance state (LRS), typically a logic "1", is affected by one or more read cycles and switches to a high-resistance state (HRS), typically a logic "0". Similarly, the reverse may also be true: a cell that should be in HRS may be affected by one or more read cycles and switch to LRS. This is possible because reads and writes to ReRAM cells are performed under the same voltage polarity, albeit at different voltage amplitudes. Therefore, after a sufficient number of read cycles, the memory may unintentionally switch. This can limit applications that rely heavily on read operations, such as artificial intelligence (AI) circuits, inference modes, etc.

[0003] Figure 1 The description V is shown. read (That is, the voltage used to read the ReRAM cell) and V prog Graph 100 shows the relationship between the voltages used to program the ReRAM cells (i.e., the voltages used to program the ReRAM cells). Therefore, Figure 1 An example graph is shown showing the read and program voltages of a ReRAM cell with a distribution between fast and slow cells relative to the switching time, which indicates the disturbance time. The horizontal axis 110 of graph 100 shows the applied voltage. The vertical axis 120 of graph 100 shows the disturbance time, or switching time, typically expressed on a logarithmic scale. Therefore, it should be understood that a ReRAM cell exhibits a time-voltage dilemma, as the switching time is an exponential function of the applied voltage.

[0004] like Figure 1As shown, cells can have different characteristics. Fast memory cells, depicted by curve FAST 140, will experience low interference time; that is, they will be disturbed for a shorter period of time compared to slow memory cells. On the other hand, slow memory cells, depicted by curve SLOW 130, will have very slow read speeds. The logarithmic scale indicates that there can be one or more orders of magnitude difference in read performance between fast and slow memory cells, which may exist on the same ReRAM memory array.

[0005] Figure 2A The graph 200A is shown, where curves 230A, 240A, 250A, 260A, and 270A are used to apply multiple read voltages V to the ReRAM array, respectively. d (0.9V, 0.8V, 0.7V, 0.6V, and 0.5V), the horizontal axis represents the interference time 220A, shown on a logarithmic scale, and the vertical axis represents the percentage of failed units 210A (shown between 0% and 100%). The reading time was gradually increased while simultaneously measuring the number of switching units, per V. d Create a graph. Consider graph 230A showing a nominal Gaussian distribution; however, at levels up to approximately 10... -6 The existence of outliers in the time frame indicates that in V... d At 0.9V, approximately 25% of the cells switch over in a short period. For comparison, a theoretical curve of 235A is added to represent the case where no outliers are present. At lower V... d At, for example, 0.8V, curve 240A has a lower percentage of initial switching, approximately 15%, and the interference time increases to approximately 10. -4 As shown in the figure, V d The lower the value, see curves 250A, 260A, and 270A, the smaller the percentage of cell transitions. This presents a problem because it means that fast memory will suffer from low-interference time, while resilient memory will be slow.

[0006] Figure 2B This is diagram 200B, showing the distribution of abnormal ReRAM cells and nominal ReRAM cells in the ReRAM array. The horizontal axis 210B depicts the number of reads required to switch a cell, i.e., how many reads will cause the cell to switch from its initial state "1" or "0" to the opposite state "0" or "1," respectively. The vertical axis 220B shows the distribution of cells in a given V array. read The probability of handover is shown in graph 230B, which illustrates the handover probability of anomalous cells, while graph 240B illustrates the handover probability of nominal cells. It can be seen that there is a gap of 250B between the number of reads representing anomalous cells and nominal cells. This implies that the handover probability is bimodal.

[0007] Figure 2C Plot 200C shows the distribution of read voltage versus interference time for SLOW 230C and FAST 240C ReRAM cells. For the SLOW 235C and FAST 245C distributions, plot 200C is now provided. Figure 2B The bimodal distribution is shown. They are represented as follows: the horizontal axis 210 is the read voltage, and the vertical axis 220C shows the disturbance time, i.e., the time it takes for a cell to switch from its current state to its other possible state.

[0008] Providing a solution that overcomes read interference in ReRAM cells would be advantageous. Summary of the Invention

[0009] Several exemplary embodiments of the present invention are summarized below. This summary is provided to facilitate the reader in gaining a basic understanding of these embodiments and does not limit the scope of this disclosure. This summary is not an extensive overview of all contemplated embodiments and is neither intended to identify key or essential elements of all embodiments nor to depict the scope of any or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that follows. For convenience, the terms "some embodiments" or "certain embodiments" may be used herein to refer to a single embodiment or multiple embodiments of this disclosure.

[0010] Some embodiments disclosed herein include a method for initializing a resistive random access memory (ReRAM) against read interference, the method comprising: programming all ReRAM cells of the ReRAM to an initial state at a first programming voltage; performing a clear operation on all ReRAM cells, wherein the clear voltage is an absolute value lower than the first programming voltage, and wherein the clear operation is performed for a predetermined time period longer than the switching time of a first group of ReRAM cells subject to read interference after a first predetermined number of reads and a second group of ReRAM cells subject to read interference after a second predetermined number of reads, wherein the first predetermined number of reads is less than the second predetermined number of reads; and performing a read operation on all ReRAM cells to determine which ReRAM cells have been affected by read interference, wherein the read is performed at an absolute voltage lower than the absolute voltage value of the clear operation.

[0011] Some embodiments disclosed herein also include control logic for the ReRAM configured to resolve read interference of the ReRAM cells. This control logic includes: processing circuitry; an input / output (I / O) interface communicatively connected to the processing circuitry, wherein the I / O interface includes at least control signals for the ReRAM; and a memory communicatively connected to the processing circuitry, the memory containing instructions that, when executed by the processing circuitry, configure the control logic to: program all ReRAM cells of the ReRAM to an initial state of a first programming voltage; perform a clear operation on all ReRAM cells, wherein the clear voltage is an absolute value lower than the first programming voltage, and wherein the clear operation is performed for a predetermined time period longer than the switching time between a first group of ReRAM cells subject to read interference after a first predetermined number of reads and a second group of ReRAM cells subject to read interference after a second predetermined number of reads, wherein the first predetermined number of reads is less than the second predetermined number of reads; and perform a read operation on all ReRAM cells to determine which ReRAM cells have been affected by read interference, wherein the read operation is performed at an absolute voltage lower than the absolute voltage value of the clear operation.

[0012] Some embodiments disclosed herein also include a ReRAM configured to resolve read interference of ReRAM cells, the control logic comprising: a ReRAM cell array; a word line decoder communicatively connected to the ReRAM cell array using at least one word line; a bit line / select line decoder communicatively connected to the ReRAM cell array using at least one bit line and at least one select line; control logic communicatively connected to the word line decoder and the bit line / select line decoder, the control logic comprising: processing circuitry; an input / output (I / O) interface communicatively connected to the processing circuitry, wherein the I / O interface includes at least control signals for the ReRAM; and a memory communicatively connected to the processing circuitry, the memory containing instructions that, when executed by the processing circuitry, control the ReRAM. The control logic is configured as follows: programming all ReRAM cells of the ReRAM to an initial state at a first programming voltage; performing a clear operation on all ReRAM cells, wherein the clear voltage is an absolute value lower than the first programming voltage, and wherein the clear operation is performed for a predetermined time period, the predetermined time period being longer than the switching time of a first group of ReRAM cells that are read-interferenced after a first predetermined number of reads and a second group of ReRAM cells that are read-interferenced after a second predetermined number of reads, wherein the first predetermined number of reads is less than the second predetermined number of reads; and performing a read operation on all ReRAM cells to determine which ReRAM cells have been affected by read interference, wherein the read is performed at an absolute voltage lower than the absolute voltage value of the clear operation. Attached Figure Description

[0013] The subject matter disclosed herein is specifically pointed out and expressly claimed in the claims of the application. The foregoing and other objects, features, and advantages of the disclosed embodiments will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figure 1 This is a graph showing the relationship between the read and program voltages and switching times for ReRAM cells distributed between fast and slow cells, and also showing the interference time.

[0015] Figure 2A The graph shows the application of multiple read voltages Vd on the ReRAM array relative to the disturbance time and the percentage of failed cells.

[0016] Figure 2B This is a distribution diagram of abnormal ReRAM cells and nominal ReRAM cells in a ReRAM array.

[0017] Figure 2C To display the distribution of slow and fast ReRAM cells relative to read voltage and interference time.

[0018] Figure 3 This is a diagram illustrating the use of a clear voltage to identify abnormal cells in a ReRAM, according to one embodiment.

[0019] Figure 4 This is a timing diagram of the operation of initializing a ReRAM cell according to one embodiment, including set, clear, and read operations.

[0020] Figure 5 This is a timing diagram of the operation of initializing a ReRAM cell according to one embodiment, including reset, clear, and read operations.

[0021] Figure 6 This is a ReRAM with control logic for controlling the initialization process, according to one embodiment.

[0022] Figure 7 Control logic for executing the initialization process of ReRAM is configured according to one embodiment.

[0023] Figure 8 This is a flowchart of the initialization of a ReRAM cell according to one embodiment, including set, clear, and read operations.

[0024] Figure 9 This is a flowchart of the initialization of a ReRAM cell according to one embodiment, including reset, clear, and read operations.

[0025] Figure 10 A graph for determining the required clearing voltage according to one embodiment. Detailed Implementation

[0026] It is important to note that the embodiments disclosed herein are merely examples of the many advantageous uses of the inventive teachings herein. Generally, the statements in this specification do not necessarily limit any of the different claims. Furthermore, some statements may apply to some inventive features but not to others. Generally, unless otherwise stated, a singular element may be plural, and vice versa, without loss of generality. In the accompanying drawings, the same numerals refer to the same parts in several views.

[0027] Resistive random access memory (ReRAM) is susceptible to read interference, which arises from the fact that read and programming operations use the same voltage polarity, but different voltages. After multiple reads, the number of reads can vary depending on the characteristics of each cell, with abnormal cells switching noticeably after far fewer reads than others. Therefore, a clear operation follows the process of setting or resetting the ReRAM cell. The clear operation involves applying a clear voltage greater than the read voltage but less than the programming voltage. Subsequently, a read operation is performed to identify those ReRAM cells that have switched from their expected state. In one embodiment, a reprogramming operation is performed to fix the resistive filament of the ReRAM cells identified as suffering from read interference.

[0028] Figure 3 This is an example graph 300 describing the identification of abnormal cells in ReRAM using a clear voltage, according to one embodiment. Graph 300 includes a horizontal axis 310 displaying the read voltage and a vertical axis 320 displaying the disturbance time on a logarithmic scale. ReRAM cells can have either the slow characteristic shown in curve 330 or the fast characteristic shown in curve 340. Both the slow ReRAM cells shown in curve 335 and the fast ReRAM cells shown in curve 340 are distributed. This distribution appears across the entire length of each curve 330 and curve 340. The programming voltage for the ReRAM cell can be set at V... prog 370. According to one embodiment, the intersection point 385 of the voltage point and the slow curve 370 determines the clearing time T. clean 390. This further allows for the determination of V. clean 360 voltage, where it is related to T clean The intersection point 380 of 390 is fixed at the gap between distribution diagrams 335 and 345. Voltage V clean The absolute value is higher than the voltage V. read However, the absolute value is lower than the voltage V. prog V can be established on the distribution edge that satisfies the fast curve 340. clean-min and V satisfying the slow distribution 330 edge clean-max between.

[0029] Figure 4 This is an example timing diagram 400 for initializing ReRAM cells according to one embodiment, including set 430, clear 440, and read 450 operations. The vertical axis 410 represents the applied voltage, not necessarily scaled. The horizontal axis 420 represents time, not necessarily scaled. According to one embodiment, the ReRAM cells are trained by first performing a set operation 430, i.e., bringing the filaments of the ReRAM cells to their set state or low-resistance state (LRS) of the ReRAM cells. The read voltage in this case is a voltage less than 0V. The clear operation 440 is applied, which includes applying a voltage of V at the value described herein. clean Voltage. V clean The absolute value is greater than the reading voltage V. read Apply V clean For a period of time T clean ReRAM cells that currently tend to read interference were trained. This is because it is used for T clean The initialization time is greater than the time required to read the fast ReRAM cells that are experiencing read interference, but insufficient to read the slow ReRAM cells that are experiencing read interference. A subsequent read operation 450 is performed to determine which ReRAM cells have suffered read interference and therefore were not found in their expected set values ​​or LRS. In one embodiment, reprogramming 460 can be performed to set those ReRAM cells that have already suffered read interference. This initialization process for the ReRAM array ensures improved performance of the entire array and reduces the likelihood of early read interference.

[0030] Figure 5 This is an example timing diagram 500 for initializing ReRAM cells according to one embodiment, including reset 530, clear 540, and read 550 operations. The vertical axis 510 represents the applied voltage and is not necessarily scaled. The horizontal axis 520 represents time and is not necessarily scaled. According to one embodiment, the cells of the ReRAM memory are trained by first performing a reset operation 530, i.e., bringing the filaments of the ReRAM cells to their reset or high-resistance state (HRS) of the ReRAM cells. In this case, the read voltage is a voltage higher than 0V. The clear operation 540 is applied, which includes applying V at the value described herein. clean Voltage. V clean The absolute value is greater than the reading voltage V. read Apply V clean For a period of time T clean ReRAM cells that currently tend to read interference were trained. This is because it is used for T cleanThe time taken is longer than the time required to read the fast ReRAM cells that are experiencing read interference, but not long enough to read the slow ReRAM cells that are experiencing read interference. A subsequent read operation 550 is performed to determine which ReRAM cells have suffered read interference and are therefore not found in their expected reset values ​​or HRS. In one embodiment, reprogramming 560 can be performed to reset those ReRAM cells that have already suffered read interference. This initialization process for the ReRAM array ensures improved performance of the entire array and reduces the likelihood of early read interference. Those skilled in the art will readily recognize that... Figure 5 The described reset procedure is used with Figure 4 The opposite voltage scheme is described.

[0031] Figure 6 This is an example ReRAM 600 with control logic 640 controlling the initialization process according to one embodiment. ReRAM 600 includes a ReRAM array 610, which consists of ReRAM cells (not shown) connected in rows and columns in one or more ways known in the art. Any ReRAM cell, word-line (WL) decoder 620, and bit-line (BL) / select-line (SL) decoder 630 are used under the control of control logic 640 for setting, resetting, programming, clearing, or reading. Control logic 640 is communicatively connected to WL decoder 620 via interface 641. WL decoder 620 is communicatively connected to ReRAM array 610 via multiple word lines 622-WL-m, where "m" is an integer equal to or greater than "1". Control logic 640 is also communicatively connected to BL / SL decoder 630 via interface 642. The SL / BL decoder 630 is communicatively connected to the ReRAM array 610 via bit line 632-BL-n and select line 632-SL-n, where "n" is an integer equal to or greater than "1". Read and write operations of the ReRAM 600 are performed using the data interface 633 provided from the BL / SL decoder 630. Control logic 640 is configured to provide the necessary control signals, and in some embodiments, the necessary voltages, to perform the operations described herein.

[0032] Figure 7Example control logic 640 is provided for a ReRAM 600 configured to perform an initialization process according to one embodiment. Processing circuitry 643 is communicatively connected to memory 644 via, for example, but not limited to, bus 647. Memory 644 may contain a portion dedicated to code 645 stored in memory 644. When the code contained in code memory 645 is executed by processing circuitry 643, ReRAM 600 is configured to perform as described herein. Memory 644 may include volatile memory, such as, but not limited to, non-volatile memory (RAM). Memory 644 may include non-volatile memory (NVM), such as, but not limited to, flash memory, read-only memory (ROM), and other types of NVM. Memory may include any combination of volatile and non-volatile memory. Input / output (I / O) interface 646 is communicatively connected to bus 647. I / O interface 646 provides control of WL decoder 620 using interface 641 and control of BL / SL decoder 630 using interface 642. In addition, interface 648 can provide, for example but not limited to, external communication, to receive various command signals from ReRAM 600 to control its operation, and to provide output signals as needed.

[0033] Processing circuitry 643 may be implemented as one or more hardware logic components and circuits. Illustrative types of hardware logic components that may be used, such as, but not limited to, include field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), specific standard products (ASSPs), system-on-a-chip systems (SOCs), general-purpose microprocessors, microcontrollers, digital signal processors (DSPs), etc., whether general-purpose or special-purpose processors, or any other hardware logic component capable of performing computational or other information operations. It should also be understood that while control circuitry 640 is shown as operating using processing circuitry 643 with instructions stored in memory 644, other embodiments of control circuitry 640 are possible and are specifically included as embodiments of the invention. For example, but not limited to, control circuitry 640 may include a combination of digital and analog circuitry (not shown) that provides control signals at least at interfaces 641, 642, which configure ReRAM 600 for an initialization process to achieve the same overall result. The control circuit 640 is configured to perform the ReRAM initialization operation, which is described in more detail herein.

[0034] Figure 8 This is an example flowchart 800 of the initialization of a ReRAM cell according to one embodiment, including set, clear, and read operations. In S810, for example, a set operation of the ReRAM cell is performed on the ReRAM cell of ReRAM 600. In the set operation, all ReRAM cells in the ReRAM array, such as ReRAM array 610, are expected to be LRS associated with logic "1".

[0035] In S820, a clearing operation is performed. This is done by applying a clearing voltage V to the ReRAM array cells. clean The clearing operation is performed using a voltage selected within a predetermined voltage range as explained herein. It should be noted that for proper operation according to the invention, it is necessary to maintain |V prog |>|V clean |>|V read These voltages can be provided by control circuit 640, WL decoder 620, and BL / SL decoder 630. During the predetermined time period T... cleanA clearing operation is performed within this time period. During this period, all ReRAM cells that were prematurely switched due to read interference have been switched, but most other cells have not yet been switched (see also [other details]). Figure 3 (and related text).

[0036] In S830, ReRAM cells are read to check which cells were affected by the clear operation in S820.

[0037] In S840, it is checked whether all ReRAM cells in the ReRAM array are in the set state. If not, execution continues to S850; otherwise, execution terminates. In one embodiment, instead of checking whether all ReRAM cells are set, a threshold number of ReRAM cells, such as, but not limited to, 99.99% or no more than 0.01% failures, is used to determine when the process can be terminated. In one embodiment, ReRAM cells determined to be inoperable are mapped to valid cells for use.

[0038] In S850, the ReRAM cell that has shown failure is reprogrammed, i.e., placed in reset or HRS as expected, instead of set or LRS. Execution then continues to S830. In one embodiment, execution terminates once reprogramming occurs. In yet another embodiment, in V... prog Reprogramming can be performed at the location; however, without departing from the scope of the invention, it may be possible to perform reprogramming at a higher V. prog These units are reprogrammed under a voltage of |V reprog |>|V prog |

[0039] Figure 9 This is an example flowchart 900 of the initialization of a ReRAM cell according to one embodiment, including reset, clear, and read operations. In S910, for example, a ReRAM cell reset operation is performed on a ReRAM cell of ReRAM 600. In the reset operation, all ReRAM cells in the ReRAM array (e.g., ReRAM array 610) are expected to be HRS associated with logic "0".

[0040] In S920, a clearing operation is performed. This is done by applying a clearing voltage V to the ReRAM array cells. clean To perform the clearing operation, clear the voltage V clean It is selected using a predetermined voltage range as explained herein. It should be noted that for proper operation according to the invention, it is necessary to maintain |V prog |>|V clean |>|V readThese voltages can be provided by control circuit 640, WL decoder 620, and BL / SL decoder 630. During the predetermined time period T... clean The clearing operation is performed within the timeframe during which all ReRAM cells that were prematurely switched due to read interference have been switched, but most other cells have not yet been switched (see also...). Figure 3 (and related texts, etc.).

[0041] In S930, the ReRAM cells are read to check which cells were affected by the clear operation in S920.

[0042] In S840, it is checked whether all ReRAM cells in the ReRAM array are in a reset state. If not, execution continues to S950; otherwise, execution terminates. In one embodiment, instead of checking whether all ReRAM cells are set, a threshold number of ReRAM cells is used to determine when the process can be terminated, such as, but not limited to, 99.99% or no more than 0.01% failures. In one embodiment, ReRAM cells determined to be inoperable are mapped to valid cells for use.

[0043] In S950, the ReRAM cell that has shown failure is reprogrammed, i.e., placed in set or LRS as expected, instead of reset or HRS. Execution then continues to S930. In one embodiment, execution terminates once reprogramming occurs. In yet another embodiment, in V... prog Reprogramming can be performed at the location; however, without departing from the scope of the invention, it may be possible to perform reprogramming at a higher V. prog These units are reprogrammed under a voltage of |V reprog |>|V prog |。 A higher |I can also be used. reprog |>|I prog |。I reporg and V reprog This higher value can enhance "weak" ReRAM cells that exhibit read interference.

[0044] In one embodiment, only one polarity (positive or negative) is used for reading. If V read If V > 0, the reset unit will be affected by the read operation. read If V is less than 0, the set unit is affected by the read operation. Therefore, V read >0 (respectively V) read <0) does not affect LRS, while V read A value less than 0 does not affect HRS. When setting and resetting are used simultaneously, the value depends on the value used. read The polarity of the value is cleared only once after setting or resetting.

[0045] Figure 10 A graph 10000 shows the determination of the required clearing voltage according to one embodiment. The graphs 230A, 240A, 250A, 260A, and 270A discussed with respect to Figure 2 represent different voltages. read Read interference at values ​​(0.9V, 0.8V, 0.7V, 0.6V, and 0.5V). As can be seen in curve 230A, approximately 25% of the ReRAM cells experience read interference at V... read At 0.9V, read interference is encountered, but this changes after approximately 1 microsecond (1010), crossing curve 230A at 1012, where the number of read interference cells begins to increase. At the same time (1010), for V... read =0.8V, of which only about 15% of the ReRAM cells exhibit read interference 1011, until the ReRAM cells begin to be read-interfered again for a longer period of time, approximately 10 microseconds 1020, crossing curve 240A at 1021, where the number of cells being read-interfered begins to increase. Therefore, a trade-off is shown between a longer read interference time and a lower number of interfered ReRAM cells. Therefore, in this example, V read Choosing a value between 0.8V and 0.7V makes sense to optimize the number of ReRAM cells that need to be reprogrammed and to reduce the longer read interference time. Other considerations may be applied without departing from the scope of this invention.

[0046] All examples and conditional language described herein are intended for educational purposes to help the reader understand the principles of the disclosed embodiments and the concepts contributed by the inventors to advance the field, and should be understood as not being limited to such specifically enumerated examples and conditions. Furthermore, all statements regarding the principles, aspects, and embodiments of the disclosed embodiments, as well as specific examples thereof, are intended to cover their structural and functional equivalents. Moreover, it is intended that such equivalents include both currently known equivalents and those developed in the future, i.e., any element developed that performs the same function, regardless of its structure.

[0047] It should be understood that the use of terms such as "first," "second," etc., to refer to any element herein does not generally limit the number or order of these elements. Rather, these names are generally used herein as a convenient way to distinguish two or more elements or instances of elements. Therefore, references to the first and second elements do not imply that only two elements can be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise stated, a group of elements includes one or more elements.

[0048] As used herein, the phrase “at least one” followed by a list of items indicates that any of the listed items may be used alone, or any combination of two or more of the listed items may be used. For example, if a system is described as including “at least one of A, B, and C”, then the system may include a single A, a single B; a single C; 2A; 2B; 2C; 3A; a combination of A and B; a combination of B and C; a combination of A and C; a combination of A, B, and C; a combination of 2A and C; a combination of A, 3B, and 2C; and so on.

Claims

1. A method for initializing a resistive random access memory (ReRAM) to counteract read interference, the method comprising: All ReRAM cells of the ReRAM are programmed to their initial state at the first programming voltage; A clear operation is performed on all the ReRAM cells, wherein the clear voltage is at an absolute value lower than the first programming voltage, and wherein the clear operation is performed for a predetermined time period, the predetermined time period being longer than the switching time of the first group of ReRAM cells that are read and disturbed after a first predetermined number of reads and the second group of ReRAM cells that are read and disturbed after a second predetermined number of reads, wherein the first predetermined number of reads is less than the second predetermined number of reads; as well as A read operation is performed on all the ReRAM cells to determine which of the ReRAM cells have been affected by read interference, wherein the read is performed at an absolute voltage lower than the absolute voltage value of the clear operation.

2. The method according to claim 1, wherein, The initial state is either the low-resistivity state (LRS) or the high-resistivity state (HRS).

3. The method according to claim 2, wherein, Programming to LRS is a set operation.

4. The method according to claim 2, wherein, Programming to HRS is a reset operation.

5. The method according to claim 1, further comprising: Reprogramming is performed on those ReRAM cells in the first group of ReRAM cells.

6. The method according to claim 5, wherein, The reprogramming shall be performed using a reprogramming voltage that is at least higher in absolute value than the programming voltage.

7. The method according to claim 5, wherein, Reprogramming should be performed using a reprogramming current whose absolute value is higher than the programming current.

8. Control logic for a resistive random access memory (ReRAM), the control logic being configured to resolve read interference of ReRAM cells in the ReRAM, the control logic comprising: Processing circuitry; The input / output I / O interface is communicatively connected to the processing circuit, wherein the I / O interface includes at least the control signals of the ReRAM; as well as A memory communicatively connected to the processing circuit contains instructions that, when executed by the processing circuit, configure the control logic to: program all ReRAM cells of the ReRAM to an initial state at a first programming voltage; perform a clear operation on all the ReRAM cells, wherein the clear voltage is an absolute value lower than the first programming voltage, and wherein the clear operation is performed for a predetermined time period, the predetermined time period being longer than the switching time of a first group of ReRAM cells that were read-interferenced after a first predetermined number of reads and a second group of ReRAM cells that were read-interferenced after a second predetermined number of reads, wherein the first predetermined number of reads is less than the second predetermined number of reads; and perform a read operation on all the ReRAM cells to determine which ReRAM cells have been affected by read interference, wherein the read is performed at an absolute voltage lower than the absolute voltage value of the clear operation.

9. The control logic according to claim 8, wherein, The initial state is either the low-resistivity state (LRS) or the high-resistivity state (HRS).

10. The control logic according to claim 9, wherein, Programming to LRS is a set operation.

11. The control logic according to claim 9, wherein, Programming to HRS is a reset operation.

12. The control logic according to claim 8, wherein, The memory also contains instructions that, when executed by the processing circuitry, configure the control logic to reprogram those ReRAM cells of the first group of ReRAM cells.

13. The control logic according to claim 12, wherein, The reprogramming is performed using a reprogramming voltage whose absolute value is higher than the programming voltage.

14. The control logic according to claim 12, wherein, The reprogramming shall be performed using a reprogramming current whose absolute value is higher than the programming current.

15. A resistive random access memory (ReRAM) configured to resolve read interference in the ReRAM cells, the control logic comprising: ReRAM cell array; A word line decoder is communicatively connected to the ReRAM cell array using at least one word line; A bit line / select line decoder is communicatively connected to the ReRAM cell array using at least one bit line and at least one select line; Control logic communicatively connected to the word line decoder and the bit line / select line decoder includes: processing circuitry; an input / output (I / O) interface communicatively connected to the processing circuitry, wherein the I / O interface includes at least control signals for the ReRAM; and a memory communicatively connected to the processing circuitry, the memory containing instructions that, when executed by the processing circuitry, configure the control logic to: program all ReRAM cells of the ReRAM to an initial state at a first programming voltage; perform a clear operation on all the ReRAM cells, wherein the clear voltage is an absolute value lower than the first programming voltage, and wherein the clear operation is performed for a predetermined time period, the predetermined time period being longer than the switching time of a first group of ReRAM cells that are read-interferenced after a first predetermined number of reads and a second group of ReRAM cells that are read-interferenced after a second predetermined number of reads, wherein the first predetermined number of reads is less than the second predetermined number of reads; and perform a read operation on all the ReRAM cells to determine which ReRAM cells have been affected by read interference, wherein the read is performed at an absolute voltage lower than the absolute voltage value of the clear operation.

16. The ReRAM according to claim 15, wherein, The initial state is either the low-resistivity state (LRS) or the high-resistivity state (HRS).

17. The ReRAM according to claim 16, wherein, Programming to LRS is a set operation.

18. The ReRAM according to claim 16, wherein, Programming to HRS is a reset operation.

19. The ReRAM according to claim 15, wherein, The memory also contains instructions that, when executed by the processing circuitry, configure the control logic to reprogram those ReRAM cells of the first group of ReRAM cells.

20. The ReRAM according to claim 19, wherein, The reprogramming shall be performed using a reprogramming voltage that is at least higher in absolute value than the programming voltage.

21. The ReRAM according to claim 19, wherein, The reprogramming shall be performed using a reprogramming current whose absolute value is higher than the programming current.

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