Display module and display device

Abstract

The invention provides a display module and a display device.The display module comprises a display panel, a backlight module and a shading part, the display panel comprises a peripheral circuit unit located in a frame area, the backlight module is arranged on the light-in side of the display panel, and the shading part is arranged between the display panel and the backlight module, so that the display panel is more compact in structure; the orthographic projection of the peripheral circuit unit on the reference plane is located in the orthographic projection of the shading piece on the reference plane, and the shading piece can shade light of the backlight module and prevent the light emitted by the backlight module from irradiating the peripheral circuit unit; therefore, the semiconductor device in the peripheral circuit unit can be prevented from generating leakage current under the strong light irradiation of the backlight module, so that the stability of the display module can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display module and display device. Background Technology

[0002] With the development of display technology, flat panel display technologies such as liquid crystal displays have become mainstream in display technology due to their advantages such as high image quality, power saving, thin body and wide range of applications. They are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, and desktop computers.

[0003] Currently, most liquid crystal display devices are backlit liquid crystal display devices, which include a backlight module and a liquid crystal display panel integrated with the backlight module. The bezel area of ​​the liquid crystal display panel is equipped with peripheral circuit units. When the transistors in the peripheral circuit units are illuminated by the strong light from the backlight module, photo-induced leakage current will be generated, affecting the normal display of the display module and reducing the stability of the display module.

[0004] Therefore, it is necessary to provide a display module and display device to improve this deficiency. Summary of the Invention

[0005] The embodiments of this application provide a display module and a display device that can improve the stability of the display module.

[0006] To achieve the above objectives, according to a first aspect of this application, a display module is provided, having a display area and a border area disposed around the display area, the display module comprising:

[0007] The display panel includes peripheral circuit units located in the frame area;

[0008] A backlight module is disposed on the light-incident side of the display panel;

[0009] A light-shielding component is disposed between the display panel and the backlight module, and is located in the bezel area;

[0010] The orthographic projection of the peripheral circuit unit on the reference plane is located within the orthographic projection of the light-shielding member on the reference plane, and the reference plane is the plane where the light-emitting surface of the display panel is located.

[0011] Optionally, in the direction from the border area to the display area, the distance between the peripheral circuit unit and the display area is greater than the distance between the light shield and the display area.

[0012] Optionally, the bezel area includes a first sub-area and a second sub-area disposed on both sides of the display area, and the peripheral circuit unit includes a gate driving circuit unit located in the first sub-area and / or the second sub-area;

[0013] The orthographic projection of the gate drive circuit unit on the reference plane is located within the orthographic projection of the light-shielding member on the reference plane.

[0014] Optionally, in the direction from the first sub-region to the display area, the distance between the gate driving circuit unit and the display area is greater than or equal to 0.9 mm and less than or equal to 1.1 mm.

[0015] Optionally, the display panel further includes a plurality of virtual electrodes located in the first sub-region and the second sub-region, the virtual electrodes being disposed on the side of the gate driving circuit unit near the display area;

[0016] The orthographic projection of the virtual electrode onto the reference plane at least partially overlaps with the orthographic projection of the light-shielding member onto the reference plane.

[0017] Optionally, the display panel further includes a common voltage signal line and multiple scan lines disposed between the virtual electrode and the display area, wherein the common voltage signal line is disposed on the side of the scan lines closer to the display area;

[0018] Wherein, in the direction from the first sub-region to the display area, the ratio of the distance between the gate driving circuit unit and the scan line to the distance between the scan line and the display area is greater than or equal to 0.8 and less than or equal to 4.

[0019] Optionally, the border area includes a third sub-area and a fourth sub-area located on both sides of the display area, and the peripheral circuit unit includes a multiplexed circuit unit located in the third sub-area;

[0020] The orthographic projection of the multiplexing circuit unit on the reference plane is located within the orthographic projection of the light-shielding member on the reference plane.

[0021] Optionally, in the direction from the third sub-region to the display area, the distance between the multiplexing circuit unit and the display area is greater than or equal to 0.9 mm and less than or equal to 1.1 mm.

[0022] Optionally, the display panel further includes a common voltage signal line, which is partially disposed between the multiplexing circuit unit and the display area;

[0023] Specifically, in the direction from the third sub-region to the display area, the ratio of the distance between the multiplexing circuit unit and the common voltage signal line to the distance between the common voltage signal line and the display area is greater than or equal to 2 and less than or equal to 6.5.

[0024] Optionally, the peripheral circuit unit includes an electrostatic discharge protection circuit unit located in the fourth sub-region;

[0025] The orthographic projection of the electrostatic protection circuit unit on the reference plane is located within the orthographic projection of the light-shielding member on the reference plane.

[0026] Optionally, in the direction from the fourth sub-region to the display area, the distance between the electrostatic protection circuit and the display area is greater than or equal to 0.9 mm and less than or equal to 2 mm.

[0027] Optionally, the display panel further includes a common voltage signal line located in the bezel area, the common voltage signal line being disposed on the side of the peripheral circuit unit closer to the display area;

[0028] The common voltage signal line has a line width greater than or equal to 100 micrometers and less than or equal to 300 micrometers.

[0029] Optionally, the display panel further includes multiple scan lines, wherein the scan lines are partially disposed between the electrostatic discharge protection circuit unit and the common voltage signal line;

[0030] In the direction from the fourth sub-region to the display area, the center distance between two adjacent scan lines is greater than or equal to 17 micrometers and less than or equal to 25 micrometers.

[0031] Optionally, in the direction from the fourth sub-region to the display area, the distance between the scan line closest to the common voltage signal line and the common voltage signal line is greater than or equal to 10 micrometers and less than or equal to 260 micrometers.

[0032] Optionally, in the direction from the border area to the display area, the distance between the light-shielding member and the display area is greater than or equal to 0.5 mm and less than or equal to 1 mm.

[0033] According to a second aspect of this application, a display device is provided, including the display module as described above.

[0034] In the display module of this application embodiment, by setting a light shield between the display panel and the backlight module, and making the orthographic projection of the peripheral circuit unit on the reference plane located within the orthographic projection of the light shield on the reference plane, the light shield can block the light of the backlight module and prevent the light emitted by the backlight module from shining on the peripheral circuit unit. This can avoid the semiconductor devices in the peripheral circuit unit from generating leakage current under the strong light of the backlight module, thereby improving the stability of the display module.

[0035] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0038] Figure 1 A top view of a display module provided for an embodiment of this application;

[0039] Figure 2 The display module provided for the embodiments of this application is along Figure 1 The cross-sectional view along the A-A' direction shown;

[0040] Figure 3 A partial schematic diagram of the first sub-region of a display module provided for an embodiment of this application;

[0041] Figure 4 A circuit diagram of a gate drive circuit unit in a display module provided for an embodiment of this application;

[0042] Figure 5 A partial schematic diagram of the third sub-region of a display module provided for an embodiment of this application;

[0043] Figure 6 A circuit diagram of a multiplexed circuit unit in a display module provided for an embodiment of this application;

[0044] Figure 7 A partial schematic diagram of the fourth sub-region of the display module provided in an embodiment of this application;

[0045] Figure 8 A circuit diagram of an electrostatic discharge protection circuit unit in a display module provided for an embodiment of this application;

[0046] Figure 9 A schematic diagram of a display device provided for an embodiment of this application.

[0047] Explanation of reference numerals in the attached figures:

[0048] 1. Display panel; 11. Array substrate; 101. Clock signal line; 102. Ground signal line; 103. Virtual electrode; 104. Common voltage signal line; 105. Scan line; 106. Data signal output line; 107. Data line; 108. Control signal line; 110. Peripheral circuit unit; 111. Gate drive circuit unit; 1111. Pull-up control module; 1112. Pull-up module; 1113. Pull-down module; 1114. Pull-down control module; 112. Multiplexing circuit unit; 113. Electrostatic discharge (ESD) protection circuit unit; 1130. ESD protection circuit; 1131. Source ESD protection circuit; 1132. Gate ESD protection circuit; 12. Opposite substrate;

[0049] 2. Backlight module;

[0050] 3. Light-shielding components;

[0051] AA, Display area; NA, Border area; NA1, First sub-area; NA2, Second sub-area; NA3, Third sub-area; NA4, Fourth sub-area;

[0052] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; Cboost, bootstrap capacitor;

[0053] 100, Display module; 200, Housing; 1000, Display device. Detailed Implementation

[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0055] This application provides a display module having a display area and a bezel area surrounding the display area. The display module includes a display panel, a backlight module, and a light-shielding member. The display panel includes peripheral circuit units located in the bezel area. The backlight module is disposed on the light-incident side of the display panel. The light-shielding member is disposed between the display panel and the backlight module, and is located in the bezel area. The orthographic projection of the peripheral circuit units onto a reference plane, and the orthographic projection of the light-shielding member onto the reference plane, are located within the light-shielding member. The reference plane is the plane containing the light-emitting surface of the display panel.

[0056] In the embodiments of this application, by setting a light shield between the display panel and the backlight module, and making the orthographic projection of the peripheral circuit unit on the reference plane located within the orthographic projection of the light shield on the reference plane, the light shield can block the light from the backlight module and prevent the light emitted by the backlight module from shining on the peripheral circuit unit. This can prevent the semiconductor devices in the peripheral circuit unit from generating leakage current under the strong light of the backlight module, thereby improving the stability of the display module.

[0057] Please see Figure 1 , Figure 1 This is a top view of a display module provided in an embodiment of this application. The display module 100 has a display area AA and a border area NA disposed around the display area AA. The display area AA is the area for displaying an image, and the display area AA may have multiple sub-pixels and pixel driving circuit units for driving the sub-pixels. The border area NA does not display an image and is the area for placing peripheral circuit units, which may include, but are not limited to, gate driving circuit units.

[0058] Please see Figure 2 , Figure 2 The display module provided for the embodiments of this application is along Figure 1 The cross-sectional view along the A-A' direction shown shows that the display module 100 includes a display panel 1, a backlight module 2, and a light shield 3. The display panel 1 includes a peripheral circuit unit 110 located in the bezel area NA. The backlight module 2 is disposed on the light-incident side of the display panel 1. The light shield 3 is disposed between the display panel 1 and the backlight module 2 and is located in the bezel area NA.

[0059] In the embodiments of this application, by providing a light shield 3 between the display panel 1 and the backlight module 2, and making the orthographic projection of the peripheral circuit unit 110 on the reference plane located within the orthographic projection of the light shield 3 on the reference plane, the light shield 3 can block the light from the backlight module 2 and prevent the light emitted by the backlight module 2 from shining on the peripheral circuit unit. This can prevent the semiconductor devices in the peripheral circuit unit 110 from generating leakage current under the strong light of the backlight module 2, thereby improving the stability of the display module.

[0060] In some embodiments, such as Figure 2 As shown, the display panel 1 is a liquid crystal display panel. The display panel 1 includes an array substrate 11, a counter substrate 12 disposed opposite to the array substrate 11, and a liquid crystal layer (not shown in the figure) disposed between the array substrate 11 and the counter substrate 12. The array substrate 11 includes a first substrate and a driving circuit layer (not shown in the figure) disposed on the first substrate. The driving circuit layer includes a pixel driving circuit unit located in the display area AA and a peripheral circuit unit located in the border area NA.

[0061] In some embodiments, the material of the light-shielding member 3 includes an opaque elastic material, which may include foam or rubber. Both sides of the light-shielding member 3 are adhesive, and the light-shielding member 3 has a closed annular structure to bond and fix the display panel 1 and the backlight module 2 to the corresponding bezel area NA. On one hand, the light-shielding member 3 can act as a physical buffer, preventing collisions between the display panel 1 and the backlight module 2 and ensuring the stability of the display module 100 in dynamic environments. On the other hand, the light-shielding member 3 can also act as a sealant, dustproof, light-shielding, and heat-insulating agent, preventing dust and other particles from entering between the display panel 1 and the backlight module 2, and preventing strong light emitted by the backlight module 2 from irradiating the peripheral circuit unit, causing leakage current in the semiconductor devices of the peripheral circuit unit.

[0062] In some embodiments, in the direction from the border area NA to the display area AA, the distance between the peripheral circuit unit 110 and the display area AA is greater than the distance between the light shield 3 and the display area AA.

[0063] like Figure 2 As shown, both the peripheral circuit unit 110 and the light-shielding member 3 are spaced apart from the display area AA. In the direction from the border area NA to the display area AA, the distance between the peripheral circuit unit 110 and the display area AA is a first distance w1, and the distance between the light-shielding member 3 and the display area AA is a second distance w2. The first distance w1 is greater than the second distance w2. Compared to the light-shielding member 3, the peripheral circuit unit 110 is farther from the display area AA, which ensures that the light-shielding member 3 can completely block the peripheral circuit unit 110, preventing the light emitted by the backlight module from shining on the peripheral circuit unit 110.

[0064] In some embodiments, combined with Figure 1 and Figure 3 As shown, Figure 3 This is a partial schematic diagram of the first sub-region of the display module provided in an embodiment of the present application. The border region NA includes a first sub-region NA1 and a second sub-region NA2 disposed on both sides of the display region AA. The first sub-region NA1 and the second sub-region NA2 are respectively disposed on opposite sides of the display region AA in the first direction X. The peripheral circuit unit 110 includes at least one gate driving circuit unit 111.

[0065] In some embodiments, the peripheral circuit unit 110 includes a gate driving circuit unit 111, which is disposed in the first sub-region NA1 or the second sub-region NA1.

[0066] In some embodiments, the peripheral circuit unit 110 includes two gate drive circuit units 111, with a gate drive circuit unit 111 provided in the first region NA1 and the second sub-region NA2.

[0067] In some embodiments, combined with Figure 2 and Figure 3 As shown, the gate drive circuit unit 111 includes multiple transistors, and the orthographic projection of the gate drive circuit unit 111 on the reference plane lies within the orthographic projection of the light shield 3 on the reference plane. Thus, the light shield 3 can be used to shield the gate drive circuit unit 111 to prevent leakage current from the transistors in the gate drive circuit unit 111 under the illumination of the backlight module.

[0068] In some embodiments, combined with Figure 3 As shown, in the direction from the first sub-region NA1 to the display area AA, the distance between the gate driving circuit unit 111 and the display area AA is greater than or equal to 0.9 mm and less than or equal to 1.1 mm. For example, the distance between the gate driving circuit unit 111 and the display area AA can be 0.9 mm, 0.91 mm, 0.93 mm, 0.95 mm, 0.97 mm, 0.99 mm, 1 mm, 1.02 mm, 1.04 mm, 1.06 mm, 1.08 mm, or 1.1 mm, etc.

[0069] Combination Figure 3 As shown, the display panel also includes a clock signal line 101 and a ground signal line 102 disposed in the first sub-region NA1 and the second sub-region NA2. The clock signal line 101 is located on the side of the gate driving circuit unit 111 away from the display area AA, and the ground signal line 102 is located on the side of the clock signal line 101 away from the gate driving circuit unit 111. If the distance between the gate driving circuit unit 111 and the display area AA is too small, it will increase the risk of light from the backlight module shining on the gate driving circuit unit 111. If the distance between the gate driving circuit unit 111 and the display area AA is too large, it will not only cause the width of the bezel area NA of the display module to be too large, but also make the distance between the ground signal line 102 and the edge of the array substrate 11 too small. Since the edge of the array substrate 11 is provided with a cutting groove, if the distance between the ground signal line 102 and the cutting groove is too small, it will not only increase the risk of cracks in the ground signal line 102 during the cutting process, but also increase the risk of edge encapsulation failure of the display panel. This embodiment limits the distance between the gate drive circuit unit 111 and the display area AA to between 0.9 mm and 1.1 mm. This not only prevents the light from the backlight module from shining on the gate drive circuit unit 111, but also prevents the ground signal line GND from cracking during the cutting process, and ensures that the packaging performance of the display panel is not affected.

[0070] In some embodiments, the gate driving circuit unit includes multiple cascaded gate driving circuits. The multiple cascaded gate driving circuits output scan pulse signals in row order in response to the control of the clock signal, and turn on the transistors of each row in row order to write the data signal to the corresponding sub-pixel.

[0071] Combination Figure 4 As shown, Figure 4 The circuit diagram of the gate drive circuit unit in the display module provided in the embodiment of this application includes a pull-up control module 1111, a pull-up module 1112, a pull-down module 1113, a pull-down sustaining module 1114 and a bootstrap capacitor Cboost.

[0072] like Figure 4 As shown, the pull-up control module 1111 includes a first transistor T1, the pull-up module 1112 includes a second transistor T2 and a third transistor T3, the pull-down module 1113 includes a fourth transistor T4 and a fifth transistor T5, and the pull-down sustaining module 1114 includes a sixth transistor T6 and a seventh transistor T7. The gate and first electrode of the first transistor T1 are connected to the (N-1)th level scan signal G(N-1). The second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the gate of the sixth transistor T6 at the first node Qa. The second electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3 and the first plate of the bootstrap capacitor Cboost at the second node Qb. The gate of the second transistor T2 is connected to a DC high-potential signal VGH. The first electrode of the third transistor T3 is electrically connected to the Nth level clock signal Ck(N). The second electrode of transistor T3, the second plate of bootstrap capacitor Cboost, and the first electrode of fifth transistor T5 are electrically connected to the output terminal G(N) of the Nth level scan signal; the gates of fourth transistor T4 and fifth transistor T5, the first electrodes of sixth transistor T6 and seventh transistor T7 are electrically connected to the third node P; the second electrodes of fourth transistor T4, fifth transistor T5, and sixth transistor T6 are all connected to the DC low-voltage signal VGL; the gate and second electrode of seventh transistor T7 are both connected to the N+1 level clock signal CK(N+1).

[0073] In some embodiments, the transistors in the gate drive circuit are all low-temperature polycrystalline silicon thin-film transistors (LTPS). In other embodiments, the type of transistor in the gate drive circuit is not limited to the LTPS in the above embodiments, but may also be a metal-oxide-semiconductor (MOS) thin-film transistor (MOST). The gate drive circuit may also include both LTPS and MOST.

[0074] It should be noted that, Figure 4 This illustration only shows one type of circuit structure of the gate drive circuit unit in the display module and does not represent the actual circuit structure of the gate drive circuit unit in the application. The circuit structure of the gate drive circuit unit can be replaced with the circuit structure of the gate drive circuit unit in the existing display panel to achieve the same or similar function, and there are no restrictions here.

[0075] In some embodiments, combined with Figure 3 As shown, the display panel 1 also includes a plurality of virtual electrodes 103 located in the first sub-region NA1 and the second sub-region NA2. The virtual electrodes 103 are disposed on the side of the gate drive circuit unit 111 near the display area AA. The virtual electrodes 103 are floating electrodes and do not receive electrical signals, so as to shield against static electricity and prevent the gate drive circuit unit 111 from being damaged by static electricity and thus failing.

[0076] In some embodiments, combined with Figure 2 and Figure 3 As shown, the orthographic projection of the virtual electrode 103 on the reference plane at least partially overlaps with the orthographic projection of the light-shielding member 3 on the reference plane. For example, the orthographic projection of the virtual electrode 103 on the reference plane and the orthographic projection of the light-shielding member 3 on the reference plane may partially overlap or completely overlap. By further moving the distribution range of the light-shielding member 3 closer to the display area AA, the distance between the light-shielding member 3 and the display area AA is reduced, and the coverage range of the light-shielding member 3 is increased. This allows the light-shielding member 3 to not only block the peripheral circuit unit 110 but also the virtual electrode 103. Even if the contact position of the light-shielding member 3 is offset, it can still ensure that the peripheral circuit unit 110 is within the coverage range of the light-shielding member 3, preventing the light from the backlight module from shining on the peripheral circuit unit 110.

[0077] In some embodiments, the orthogonal projection of the light-shielding member 3 on the reference plane completely covers the orthogonal projection of the virtual electrode 103 on the reference plane, which can further increase the coverage of the light-shielding member 3 and further reduce the risk of light from the backlight module illuminating the peripheral circuit unit 110 due to the offset of the light-shielding member 3.

[0078] In some embodiments, such as Figure 3 As shown, the display panel 1 also includes a common voltage signal line 104 and multiple scan lines 105 partially disposed between the virtual electrode 103 and the display area AA. The common voltage signal line 104 is disposed on the side of the scan line 105 close to the display area AA. In the direction from the first sub-region NA1 to the display area AA, the ratio of the distance between the gate drive circuit unit 111 and the scan line 105 to the distance between the scan line 105 and the display area AA is greater than or equal to 0.8 and less than or equal to 4.

[0079] like Figure 3As shown, the distance between the gate driving circuit unit 111 and the scan line 105 is the third distance w3, and the distance between the scan line 105 and the display area AA is the fourth distance w4. The ratio of the third distance w3 to the fourth distance w4 can be 0.8, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, or 4, etc. It should be noted that if the ratio of the third distance w3 to the fourth distance w4 is too large, the width of the first sub-region NA1 and the second sub-region NA2 will be too large; if the ratio of the third distance w3 to the fourth distance w4 is too small, the risk of light from the backlight module illuminating the gate driving circuit unit 111 will increase. In this embodiment, by limiting the ratio of the third distance w3 to the fourth distance w4 to between 0.8 and 4, the risk of light from the backlight module illuminating the gate driving circuit unit 111 can be reduced without increasing the width of the first sub-region NA1 and the second sub-region NA2.

[0080] In some embodiments, the distance between the gate driving circuit unit 111 and the scan line 105 is greater than or equal to 200 micrometers and less than or equal to 450 micrometers, and the distance between the scan line 105 and the display area AA is greater than or equal to 100 micrometers and less than or equal to 300 micrometers. For example, the distance between the gate driving circuit unit 111 and the scan line 105 can be 200 micrometers, 250 micrometers, 300 micrometers, 350 micrometers, 400 micrometers, or 450 micrometers, etc., and the distance between the scan line 105 and the display area AA can be 100 micrometers, 150 micrometers, 200 micrometers, 250 micrometers, or 300 micrometers, etc.

[0081] In some embodiments, such as Figure 1 As shown, the border area NA includes a third sub-area NA3 and a fourth sub-area NA4 located on both sides of the display area AA. The third sub-area NA3 and the fourth sub-area NA4 are located on opposite sides of the display area AA in the second direction Y, which is perpendicular to the first direction X.

[0082] In some embodiments, combined with Figure 1 and Figure 5 As shown, Figure 5 This is a partial schematic diagram of the third sub-region of a display module provided in an embodiment of this application. The peripheral circuit unit 110 includes a multiplexing circuit unit 112. The multiplexing circuit unit 112 is used to connect the few output terminals of the source drive circuit to multiple data lines in a time-division multiplexing manner. The multiplexing circuit unit 112 includes multiple transistors. The multiplexing circuit unit 112 is located in the third sub-region NA3. The orthographic projection of the multiplexing circuit unit 112 on the reference plane is located within the orthographic projection of the light shield 3 on the reference plane. In this way, the light shield 3 can be used to shield the multiplexing circuit unit 112 to prevent the transistors in the multiplexing circuit unit 112 from generating leakage current under the illumination of the backlight module.

[0083] In some embodiments, in the direction from the third sub-region NA3 to the display area AA, the distance between the multiplexing circuit unit 112 and the display area AA is greater than or equal to 0.9 mm and less than or equal to 1.1 mm. For example, the distance between the multiplexing circuit unit 112 and the display area AA can be 0.9 mm, 0.91 mm, 0.93 mm, 0.95 mm, 0.97 mm, 0.99 mm, 1 mm, 1.02 mm, 1.04 mm, 1.06 mm, 1.08 mm, or 1.1 mm, etc.

[0084] It should be noted that if the distance between the multiplexing circuit unit 112 and the display area AA is too small, the risk of light from the backlight module shining into the multiplexing circuit unit 112 will increase; if the distance between the multiplexing circuit unit 112 and the display area AA is too large, the width of the third sub-area NA3 will be too large. This embodiment, by limiting the distance between the multiplexing circuit unit 112 and the display area AA to between 0.9 mm and 1.1 mm, can prevent light from the backlight module from shining into the multiplexing circuit unit 112 without increasing the width of the third sub-area NA3, thereby reducing the leakage current of the transistors in the multiplexing circuit unit 112, further reducing the power consumption of the display module, and improving the stability of the display module.

[0085] In some embodiments, the display panel further includes a common voltage signal line 104, which is partially disposed between the multiplexing circuit unit 112 and the display area AA. In the direction from the third sub-region NA3 to the display area AA, the ratio of the distance between the multiplexing circuit unit 112 and the common voltage signal line 104 to the distance between the common voltage signal line 104 and the display area AA is greater than or equal to 2 and less than or equal to 6.5.

[0086] like Figure 5 As shown, the distance between the multiplexing circuit unit 112 and the common voltage signal line 104 is the fifth distance d5, and the distance between the common voltage signal line 104 and the display area AA is the sixth distance d6. The ratio of the fifth distance d5 to the sixth distance d6 can be 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, or 6.5, etc. It should be noted that if the ratio of the fifth distance d5 to the sixth distance d6 is too large, the width of the third sub-region NA3 will be too large; if the ratio of the fifth distance d5 to the sixth distance d6 is too small, the risk of light from the backlight module illuminating the gate driving circuit unit 111 will increase. In this embodiment, by limiting the ratio of the fifth distance d5 to the sixth distance d6 to between 2 and 6.5, the risk of light from the backlight module illuminating the multiplexing circuit unit 112 can be reduced without increasing the width of the third sub-region NA3.

[0087] In some embodiments, the distance between the multiplexing circuit unit 112 and the common voltage signal line 104 is greater than or equal to 400 micrometers and less than or equal to 650 micrometers, and the distance between the common voltage signal line 104 and the display area AA is greater than or equal to 100 micrometers and less than or equal to 200 micrometers. For example, the distance between the multiplexing circuit unit 112 and the common voltage signal line 104 can be 400 micrometers, 450 micrometers, 500 micrometers, 550 micrometers, 600 micrometers, or 650 micrometers, etc., and the distance between the common voltage signal line 104 and the display area AA can be 100 micrometers, 120 micrometers, 140 micrometers, 150 micrometers, 160 micrometers, 180 micrometers, or 200 micrometers, etc.

[0088] In some embodiments, such as Figure 6 As shown, Figure 6 This is a circuit diagram of a multiplexing circuit unit in a display module provided in an embodiment of this application. The multiplexing circuit unit 112 includes multiple eighth transistors T8. The array substrate 11 includes multiple data signal output lines 106 located in the third sub-region NA3 and multiple data lines 107 located in the third sub-region NA3 and the display area AA. One end of the data signal output line 106 is connected to the source driving circuit, and the other end is connected to the first electrode of the corresponding eighth transistor T8 in the multiplexing circuit unit 112. One end of the data line 107 is connected to the second electrode of the corresponding eighth transistor T8, and the other end of the data line 107 extends to the display area and is electrically connected to the driving transistor of the corresponding sub-pixel. The gate of the eighth transistor T8 is connected to the corresponding control signal line 108. Each data signal output line 106 can be electrically connected to multiple data lines 107 through multiple eighth transistors T8. The eighth transistor T8 can selectively control the conduction and cutoff of the line between the data signal output line 106 and the corresponding data line 107 in response to the control signal transmitted by the control signal line 108.

[0089] In some embodiments, combined with Figure 1 , Figure 2 and Figure 7 As shown, Figure 7 This is a partial schematic diagram of the fourth sub-region of the display module provided in an embodiment of this application. The peripheral circuit unit 110 further includes an electrostatic discharge (ESD) protection circuit unit 113, which includes a plurality of transistors. The ESD protection circuit unit 113 is located in the fourth sub-region NA4, and its orthographic projection on the reference plane lies within the orthographic projection of the light-shielding member 3 on the reference plane. In this way, the light-shielding member 3 can be used to shield the ESD protection circuit unit 113 to prevent the transistors in the ESD protection circuit unit 113 from generating leakage current under the illumination of the backlight module.

[0090] In some embodiments, in the direction from the fourth sub-region NA4 to the display area AA, the distance between the electrostatic discharge protection circuit unit 113 and the display area AA is greater than or equal to 0.9 mm and less than or equal to 2 mm.

[0091] like Figure 7 As shown, in the direction from the fourth sub-region NA4 to the display area AA, the distance between the electrostatic discharge protection circuit unit 113 and the display area AA is the seventh distance w7. The seventh distance w7 can be 0.9 mm, 1 mm, 1.2 mm, 1.4 mm, 1.6 mm, 1.8 mm, or 2 mm, etc. It should be noted that if the distance between the electrostatic discharge protection circuit unit 113 and the display area AA is too small, it will increase the risk of light from the backlight module shining on the electrostatic discharge protection circuit unit 113; if the distance between the electrostatic discharge protection circuit unit 113 and the display area AA is too large, it will result in the width of the fourth sub-region NA4 being too large. In this embodiment, by limiting the distance between the electrostatic discharge protection circuit unit 113 and the display area AA to between 0.9 mm and 2 mm, it is possible to prevent light from the backlight module from shining on the electrostatic discharge protection circuit unit 113 without increasing the width of the fourth sub-region NA4, thereby reducing the leakage current of the transistors in the electrostatic discharge protection circuit unit 113, further reducing the power consumption of the display module, and improving the stability of the display module.

[0092] In some embodiments, such as Figure 7 As shown, the common voltage signal line 104 is located on the side of the electrostatic protection circuit unit 113 near the display area AA. The line width of the common voltage signal line 104 is greater than or equal to 100 micrometers and less than or equal to 300 micrometers.

[0093] It should be noted that if the linewidth of the common voltage signal line 104 is too large, it will result in an excessively large width of the fourth sub-region NA4; if the linewidth of the common voltage signal line 104 is too small, it will not only increase the impedance of the common voltage signal line 104, but also make the electrostatic discharge protection circuit unit 113 too close to the display area AA, increasing the risk of light from the backlight module shining on the electrostatic discharge protection circuit. This embodiment, by limiting the linewidth of the common voltage signal line 104 to between 100 and 300 micrometers, can reduce the risk of light from the backlight module shining on the electrostatic discharge protection circuit unit 113 without increasing the width of the fourth sub-region NA4 or the impedance of the common voltage signal line 104, thereby further improving the stability of the display module.

[0094] In some embodiments, such as Figure 8 As shown, Figure 8The circuit diagram of the electrostatic discharge (ESD) protection circuit unit in the display module provided in the embodiment of this application is shown. The ESD protection circuit unit 113 includes a plurality of ESD protection circuits 1130. Each of the ESD protection circuits 1130 includes a ninth transistor T9 and a tenth transistor T10. The first electrode and gate of the ninth transistor T9 are both connected to a DC low-voltage signal line VGL. The first electrode and gate of the tenth transistor T10 are both connected to a DC high-voltage signal line. The second electrode of the ninth transistor T9 is electrically connected to the second electrode of the tenth transistor T10.

[0095] In some embodiments, combined with Figure 7 and Figure 8 As shown, the multiple electrostatic discharge (ESD) protection circuits 1130 include multiple source ESD protection circuits 1131 and multiple gate ESD protection circuits 1132. Taking the source ESD protection circuit as an example, the second electrodes of the ninth transistor T9 and the tenth transistor T10 in the source ESD protection circuit 1131 are both electrically connected to the data line 107. The source ESD protection circuit 1131 instantly releases the high voltage of electrostatic discharge, which can prevent the source drive circuit chip from being damaged by electrostatic discharge.

[0096] The gate electrostatic discharge protection circuit 1132 has a similar structure to the source electrostatic discharge protection circuit. The difference is that the second electrodes of the ninth transistor T9 and the tenth transistor T10 in the gate electrostatic discharge protection circuit 1132 are electrically connected to the clock signal line 101 or other lines. The gate electrostatic discharge protection circuit 1132 releases the high voltage of electrostatic discharge instantly, which can prevent the scan line or the gate node of the transistor from being damaged by electrostatic discharge and failing.

[0097] In some embodiments, multiple scan lines 105 are partially disposed between the electrostatic discharge protection circuit unit 113 and the common voltage signal line 104. In the direction from the fourth sub-region NA4 to the display area AA, the center distance between two adjacent scan lines 105 located in the fourth sub-region NA4 is greater than or equal to 17 micrometers and less than or equal to 25 micrometers.

[0098] like Figure 8 As shown, in the direction from the fourth sub-region NA4 to the display area AA, the center distance between two adjacent scan lines 105 located in the fourth sub-region NA4 is the eighth distance w8. The eighth distance w8 can be 17 micrometers, 19 micrometers, 21 micrometers, 23 micrometers, or 25 micrometers, etc. It should be noted that the center of scan line 105 refers to the geometric center of scan line 105.

[0099] It should be noted that if the center distance between two adjacent scan lines 105 located in the fourth sub-region NA4 is too large, the width of the fourth sub-region NA4 will be too large; if the center distance between two adjacent scan lines 105 located in the fourth sub-region NA4 is too small, the electrostatic discharge protection circuit unit 113 will be too close to the display area AA, increasing the risk of light from the backlight module irradiating the electrostatic discharge protection circuit unit 113. This embodiment, by limiting the center distance between two adjacent scan lines 105 located in the fourth sub-region NA4 to between 17 micrometers and 25 micrometers, can reduce the risk of light from the backlight module irradiating the electrostatic discharge protection circuit unit 113 without increasing the width of the fourth sub-region NA4.

[0100] In some embodiments, combined with Figure 2 and Figure 3 As shown, in the direction from the first sub-region NA1 to the display area AA, the distance between the light-shielding member 3 and the display area AA is greater than or equal to 0.5 mm and less than or equal to 1 mm. For example, the distance between the light-shielding member 3 and the display area AA can be 0.5 mm, 0.6 mm, 0.8 mm, 0.9 mm, or 1 mm, etc., as long as it is ensured that the distance between the light-shielding member 3 and the display area AA is less than the distance between the peripheral circuit unit 110 and the display area AA.

[0101] Based on the display module provided in the above embodiments of this application, embodiments of this application also provide a display device. Please refer to [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic diagram of a display device provided in an embodiment of this application. The display device 1000 includes a display module 100 and a housing 200, with the display module 100 disposed on the housing 200. The display module 100 can be any of the display modules provided in the above embodiments. The display device provided in the embodiments of this application can achieve the same technical effects as the display modules provided in any of the above embodiments, and will not be described in detail here.

[0102] In some embodiments, the display device may be an in-vehicle display device, such as a head-up display.

[0103] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display module and a display device. The display module includes a display panel, a backlight module, and a light shield. The display panel includes peripheral circuit units located in the bezel area. The backlight module is disposed on the light-incident side of the display panel. By providing a light shield between the display panel and the backlight module, and making the orthographic projection of the peripheral circuit units on the reference plane located within the orthographic projection of the light shield on the reference plane, the light shield can block the light from the backlight module and prevent the light emitted by the backlight module from shining on the peripheral circuit units. This can avoid the semiconductor devices in the peripheral circuit units from generating leakage current under the strong light of the backlight module, thereby improving the stability of the display module.

[0104] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0105] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0106] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0107] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display module, characterized in that, The display module includes a display area and a border area surrounding the display area. The display panel includes peripheral circuit units located in the frame area; A backlight module is disposed on the light-incident side of the display panel; A light-shielding component is disposed between the display panel and the backlight module, and is located in the bezel area; The orthographic projection of the peripheral circuit unit on the reference plane is located within the orthographic projection of the light-shielding member on the reference plane, and the reference plane is the plane where the light-emitting surface of the display panel is located.

2. The display module as described in claim 1, characterized in that, In the direction from the border area to the display area, the distance between the peripheral circuit unit and the display area is greater than the distance between the light-shielding member and the display area.

3. The display module as described in claim 1, characterized in that, The frame area includes a first sub-area and a second sub-area disposed on both sides of the display area, and the peripheral circuit unit includes a gate driving circuit unit located in the first sub-area and / or the second sub-area; The orthographic projection of the gate drive circuit unit on the reference plane is located within the orthographic projection of the light-shielding member on the reference plane.

4. The display module as described in claim 3, characterized in that, In the direction from the first sub-region to the display area, the distance between the gate driving circuit unit and the display area is greater than or equal to 0.9 mm and less than or equal to 1.1 mm.

5. The display module as described in claim 3, characterized in that, The display panel further includes a plurality of virtual electrodes located in the first sub-region and the second sub-region, the virtual electrodes being disposed on the side of the gate driving circuit unit near the display area; The orthographic projection of the virtual electrode onto the reference plane at least partially overlaps with the orthographic projection of the light-shielding member onto the reference plane.

6. The display module as described in claim 5, characterized in that, The display panel also includes a common voltage signal line and multiple scan lines disposed between the virtual electrode and the display area, wherein the common voltage signal line is disposed on the side of the scan line closer to the display area; Wherein, in the direction from the first sub-region to the display area, the ratio of the distance between the gate driving circuit unit and the scan line to the distance between the scan line and the display area is greater than or equal to 0.8 and less than or equal to 4.

7. The display module as described in any one of claims 1 to 6, characterized in that, The border area includes a third sub-area and a fourth sub-area located on both sides of the display area, and the peripheral circuit unit includes a multiplexed circuit unit located in the third sub-area; The orthographic projection of the multiplexing circuit unit on the reference plane is located within the orthographic projection of the light-shielding member on the reference plane.

8. The display module as described in claim 7, characterized in that, In the direction from the third sub-region to the display area, the distance between the multiplexing circuit unit and the display area is greater than or equal to 0.9 mm and less than or equal to 1.1 mm.

9. The display module as described in claim 7, characterized in that, The display panel also includes a common voltage signal line, which is partially disposed between the multiplexing circuit unit and the display area; Specifically, in the direction from the third sub-region to the display area, the ratio of the distance between the multiplexing circuit unit and the common voltage signal line to the distance between the common voltage signal line and the display area is greater than or equal to 2 and less than or equal to 6.

5.

10. The display module as described in claim 7, characterized in that, The peripheral circuit unit includes an electrostatic protection circuit unit located in the fourth sub-region; The orthographic projection of the electrostatic protection circuit unit on the reference plane is located within the orthographic projection of the light-shielding member on the reference plane.

11. The display module as described in claim 10, characterized in that, In the direction from the fourth sub-region to the display area, the distance between the electrostatic protection circuit and the display area is greater than or equal to 0.9 mm and less than or equal to 2 mm.

12. The display module as described in claim 10, characterized in that, The display panel also includes a common voltage signal line located in the bezel area, and the common voltage signal line is disposed on the side of the peripheral circuit unit closer to the display area; The common voltage signal line has a line width greater than or equal to 100 micrometers and less than or equal to 300 micrometers.

13. The display module as described in claim 12, characterized in that, The display panel also includes multiple scan lines, some of which are disposed between the electrostatic protection circuit unit and the common voltage signal line; In the direction from the fourth sub-region to the display area, the center distance between two adjacent scan lines is greater than or equal to 17 micrometers and less than or equal to 25 micrometers.

14. The display module as described in claim 13, characterized in that, In the direction from the fourth sub-region to the display area, the distance between the scan line closest to the common voltage signal line and the common voltage signal line is greater than or equal to 10 micrometers and less than or equal to 260 micrometers.

15. The display module as described in any one of claims 1 to 6, characterized in that, In the direction from the border area to the display area, the distance between the light-shielding member and the display area is greater than or equal to 0.5 mm and less than or equal to 1 mm.

16. A display device, characterized in that, Includes the display module as described in any one of claims 1 to 15.

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