Reconfigurable electronic equipment testing system based on software-defined communication interface

Abstract

The application belongs to the technical field of testing, and particularly relates to a software-defined communication interface reconfigurable electronic equipment test system. The technical scheme is as follows: the software-defined communication interface reconfigurable electronic equipment test system comprises an upper computer software platform and a lower computer hardware platform; the upper computer software platform is a user-oriented drive-free transparent transmission control system, and the upper computer software platform takes an industrial computer as a carrier, is responsible for communication with a user and an interface system, supports protocol command issuing and data receiving; the lower computer hardware platform is a hardware system reconfigured based on a software-defined communication interface, and the lower computer hardware platform is responsible for protocol conversion and interface configuration, and realizes communication with a product under test; the lower computer hardware platform adopts an FPGA chip-level platform to integrate multiple types of interfaces, and supports multiple communication protocols. The application provides a software-defined communication interface reconfigurable electronic equipment test system.

Description

Technical Field

[0001] This invention belongs to the field of testing technology, and specifically relates to a reconfigurable electronic equipment testing system based on a software-defined communication interface. Background Technology

[0002] An Automated Test System (ATS) consists of three parts: Automated Test Equipment (ATE), Test Procedure Set (TPS), and Software Development Kit (TPS). The ATE is a crucial component of the ATS, containing hardware devices such as test instruments, fixtures, switch matrices, and communication interfaces. Among these, the communication interface is an indispensable hardware device, serving as the bridge connecting the instruments, the product under test, and the fixtures. Current communication interfaces suffer from the following problems:

[0003] First, the variety of communication interface devices makes management and maintenance difficult: Due to the diversity of the products being tested, the testing requirements for each product are not the same, and different requirements correspond to different communication interfaces, including common asynchronous LVDS, synchronous LVDS, 429, 422, 485, CAN, digital IO, 1553, SPI and other interfaces. The computer's built-in LAN port, RS232 serial port and USB interface cannot meet the testing requirements, resulting in a wide variety of communication interface devices for automatic testing systems. Due to the mixed nature of the research and development units, their technical and service levels vary, making it inconvenient for later maintenance and upgrades.

[0004] Second, the communication interface suffers from tight hardware / software coupling and insufficient software-defined capabilities: Insufficient software-defined capabilities prevent the testing system from meeting the requirements of Industry 4.0 in terms of flexibility, scalability, and miniaturization. Currently, the functional roles of various testing interface devices are primarily determined by the hardware system, rather than the software running on the device. For example, there are numerous different types of interface devices in the field, each with its own customized hardware system tailored to its specific operating scenario, coupled with dedicated system software. Therefore, these devices are hardware-centric, and their functions are mainly determined by the characteristics of the hardware system; that is, the device's functionality is primarily defined by its hardware, not its software.

[0005] Industry 4.0 requires systems to flexibly adapt to changes in production and business processes. However, the control functions of equipment heavily rely on the underlying hardware system. Adjusting equipment functions sometimes requires simultaneous adjustments to the hardware system configuration, making it difficult to quickly adapt to changes in production and business. Secondly, when new business needs arise, equipment functionality cannot be quickly expanded by loading software; new hardware must be added, and dedicated software on the equipment must be debugged, making the entire process very lengthy. Therefore, the system's scalability is poor. Finally, due to the tight coupling between functions and hardware systems, a large number of different types of equipment need to be deployed on-site, occupying a significant amount of space. Therefore, it is difficult to realize the vision of miniaturization in Industry 4.0 systems.

[0006] If the functions of control devices are defined by software, and the software determines the device's role and control functions, then the role and function of the control device can be flexibly and quickly changed by loading different software. Furthermore, a single device can run multiple software programs and simultaneously possess multiple roles and functions, thereby improving the system's flexibility, scalability, and miniaturization. However, traditional devices employ a tightly coupled software / hardware development approach, with hardware as the core and software heavily reliant on the underlying hardware. This results in insufficient software definition capabilities for the device, becoming a major technical challenge for the system.

[0007] Third, the tightly coupled software / hardware test interface devices have poor portability and scheduling capabilities: due to the special nature and closed nature of the hardware system, it is difficult for applications to be migrated and scheduled on different devices, which seriously hinders the interoperability and flexibility of the system.

[0008] The equipment adopts an integrated hardware and software development model. Its hardware system is customized according to the working scenario. The hardware systems of different types of equipment usually have significant differences, and it is difficult to migrate the program on one type of equipment to another type of equipment.

[0009] The complexity of electronic information equipment testing and the diversity of test objectives place higher demands on the portability and scalability of communication interfaces in automated testing systems. Furthermore, since the cost of communication interfaces accounts for a large portion of the overall development cost of automated testing systems, it is essential to research reconfigurable communication interface technologies to improve the reusability of communication interfaces, thereby reducing development costs and increasing development efficiency. Summary of the Invention

[0010] In order to solve the above-mentioned problems in the existing technology, the purpose of this invention is to provide a reconfigurable electronic equipment testing system based on a software-defined communication interface.

[0011] The technical solution adopted in this invention is as follows:

[0012] A reconfigurable electronic equipment testing system based on a software-defined communication interface includes a host computer software platform and a slave computer hardware platform.

[0013] The host computer software platform is a user-oriented, driverless, transparent transmission control system. The host computer software platform uses an industrial computer as a carrier and is responsible for communicating with users and interface systems, supporting the issuance of protocol commands and the reception of data.

[0014] The lower-level hardware platform is a hardware system reconstructed based on a software-defined communication interface. The lower-level hardware platform is responsible for protocol conversion and interface configuration to enable communication with the product under test. The lower-level hardware platform uses an FPGA chip-level platform to integrate multiple types of interfaces and supports multiple communication protocols.

[0015] This invention constructs a low-cost communication interface testing platform prototype, which can adapt to a variety of interfaces. First, it has a rich variety of interfaces, covering common interface types. Second, it has a large number of interfaces, which can meet the interface requirements of different tested devices.

[0016] This invention studies the construction technology of test communication interface IP core based on SOC, the functional reconstruction technology and hardware design technology of test communication interface, the driverless test communication interface control technology and software development technology, and through the characteristics of FPGA, realizes a test platform that can quickly adapt to new communication protocols through software updates and configurations without changing the hardware, so as to meet the testing needs of multiple types of multi-interface devices.

[0017] As a preferred embodiment of the present invention, the FPGA chip of the FPGA chip-level platform communicates with the host computer software platform through an external Ethernet interface bus.

[0018] As a preferred embodiment of the present invention, the communication between the FPGA chip and the host computer software platform includes valid data, clock signals, and control signals; the control signals are used to select and set relevant parameters for various types of interface data paths integrated in the FPGA chip; the clock signals are used to adjust the communication rate between the Ethernet interface and the FPGA chip; and the valid data is transmitted between the Ethernet interface and the FPGA chip through a packing and unpacking method that conforms to the Ethernet transmission format.

[0019] As a preferred embodiment of the present invention, the FPGA chip-level platform FPGA chip is connected to various types of external interfaces on the FPGA chip platform through custom external pins, and communicates with the terminal device through a dedicated interface cable. The communication content includes valid data, clock or control signals.

[0020] As a preferred embodiment of the present invention, for the bus interface that works synchronously with the FPGA chip, the data transmitted by the external device is collected in real time through the combined action of clock signal and control signal, and then processed or uploaded into the corresponding data path of the FPGA chip.

[0021] As a preferred embodiment of the present invention, for the bus interface that works asynchronously with the FPGA chip, the data transmitted by the external device is first collected in real time through the control signal, and then the clock signal is generated inside the FPGA chip for synchronization before the corresponding data path is processed or uploaded.

[0022] As a preferred embodiment of the present invention, the host computer software platform includes a data acquisition layer, a protocol management and adaptation layer, and a test business management layer;

[0023] Data acquisition layer: Communicates according to the selected protocol, informs the lower-level hardware platform of the data format and communication protocol of the product under test, parses, processes and stores the data transmitted from the lower-level hardware platform for test business data analysis;

[0024] Protocol Management and Adaptation Layer: Establish protocol templates and configure several protocols in the system;

[0025] Test Business Management Layer: Manages test business, communicates with the lower-level hardware platform, and supports the issuance of protocol commands and the reception of data.

[0026] As a preferred embodiment of the present invention, the protocol management and adaptation layer enables the addition and modification of protocols, selection of protocol combinations, selection of protocol templates based on the test object, and automatic matching of data formats.

[0027] As a preferred embodiment of the present invention, the lower-level hardware platform includes an interface control layer, an interface array layer, and a power supply layer;

[0028] Interface control layer: Software-defined functions are implemented using FPGA. By virtualizing traditional interface devices into software instances to build an abstraction layer, it supports automatic identification of the connected interface type, protocol conversion, automatic protocol matching, communication scheduling, and communication with the host computer software platform and interface array layer.

[0029] Interface array layer: It supports expansion by pre-setting several general communication protocols and communicates with the multi-protocol communication scheduling control unit through the PCI interface bus;

[0030] Power layer: Converts 220V AC to the voltage required by the lower-level hardware platform.

[0031] As a preferred embodiment of the present invention, the power supply layer includes an EMI filter and an AC / DC conversion unit; the EMI filter suppresses electromagnetic interference, reduces the impact of power supply noise on the device and the electromagnetic influence of the device on the outside; the AC / DC conversion unit converts 220V AC into the voltage required by the internal modules.

[0032] The beneficial effects of this invention are as follows:

[0033] 1. This invention combines FPGA with communication interface testing, realizing software definition of the communication interface. By loading different software on the same hardware platform, the role and function of the control communication interface device can be flexibly changed. It can quickly reconstruct communication interface test equipment for various types and models of products, improving the flexibility and scalability of the equipment, turning communication interface test equipment from dedicated to general purpose, improving the utilization rate of test equipment, and solving the problem of redundant construction of test equipment.

[0034] 2. This invention enables driverless transparent transmission for users. Users do not need to worry about the communication details of the underlying hardware and software. For new devices, users do not need to install drivers. The device can automatically recognize and establish a communication connection, realizing unimpeded data transmission.

[0035] 3. The manufacturing cost of communication interface testing in this invention is reduced by more than 50%. At the same time, it breaks the technical barrier that foreign companies monopolize mainstream interface testing equipment, realizes the localization of testing equipment, and enhances independent innovation capabilities. Attached Figure Description

[0036] Figure 1 This is a system structure diagram of the present invention;

[0037] Figure 2 Overall architecture diagram of the present invention;

[0038] Figure 3 This is a block diagram of the logic implementation of the lower-level hardware platform. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention. It should be noted that, unless otherwise specified, the embodiments and features described in the embodiments of the invention can be combined with each other.

[0041] like Figure 1 As shown, the software-defined communication interface-based reconfigurable electronic equipment testing system of this embodiment includes a host computer software platform and a slave computer hardware platform.

[0042] The host computer software platform is a set of driverless multi-interface control software for the platform's control system, which is realized through the key technology of "user-oriented driverless transparent transmission technology". The host computer software platform uses an industrial control computer as a carrier and is responsible for communicating with users and interface systems, supporting the issuance of protocol commands and the reception of data.

[0043] The lower-level hardware platform is the interface system of the platform, and is a hardware system. It realizes the softwareization of the hardware platform through the key technology of "software-defined communication interface reconstruction technology". The lower-level hardware platform is responsible for protocol conversion and interface configuration to realize communication with the product under test. The lower-level hardware platform adopts an FPGA chip-level platform to integrate multiple types of interfaces and supports multiple communication protocols.

[0044] The lower-level hardware platform is equipped with a master board, on which a core board and inherent interfaces are set. The core board realizes the softwareization of the hardware platform through the key technology of "software-defined communication interface reconstruction technology". The inherent interface is connected to the general cable interface, and the interface system is connected to the adapter system. Test product 1, test product 2... test product N are respectively connected to the general cable interface, the extended cable interface of the adapter system, and the test instrument.

[0045] This invention constructs a low-cost communication interface testing platform prototype, which can adapt to a variety of interfaces. First, it has a rich variety of interfaces, covering common interface types. Second, it has a large number of interfaces, which can meet the interface requirements of different tested devices.

[0046] This invention studies the construction technology of test communication interface IP core based on SOC, the functional reconstruction technology and hardware design technology of test communication interface, the driverless test communication interface control technology and software development technology, and through the characteristics of FPGA, realizes a test platform that can quickly adapt to new communication protocols through software updates and configurations without changing the hardware, so as to meet the testing needs of multiple types of multi-interface devices.

[0047] Specifically, such as Figure 2As shown, the host computer software platform includes a data acquisition layer, a protocol management and adaptation layer, and a test business management layer;

[0048] Data acquisition layer: Communicates according to the selected protocol, informs the lower-level hardware platform of the data format and communication protocol of the product under test, parses, processes and stores the data transmitted from the lower-level hardware platform for test business data analysis;

[0049] Protocol Management and Adaptation Layer: Establishes protocol templates, configures several protocols in the system, enables the addition and modification of protocols, selects protocol combinations, selects protocol templates based on test objects, and automatically matches data formats;

[0050] Test Business Management Layer: Manages test business, communicates with the lower-level hardware platform, and supports the issuance of protocol commands and the reception of data.

[0051] In summary, the functions of the data acquisition layer include data storage, data parsing, communication management, data standardization, data transmission and reception, and lower-level machine management; the functions of the protocol management and adaptation layer include protocol template management, IP core library management, test task matching, virtual device management, test template management, and test data packet management; and the functions of the test business management layer include test task management, test result management, system management, test data management, test object management, and comprehensive data analysis.

[0052] Specifically, such as Figure 2 As shown, the lower-level hardware platform includes an interface control layer, an interface array layer, and a power layer;

[0053] Interface control layer: Software-defined functions are implemented using FPGA. By virtualizing traditional interface devices into software instances to build an abstraction layer, it supports automatic identification of the connected interface type, protocol conversion, automatic protocol matching, communication scheduling, and communication with the host computer software platform and interface array layer.

[0054] Interface array layer: It supports expansion by pre-setting several general communication protocols and communicates with the multi-protocol communication scheduling control unit through the PCI interface bus;

[0055] Power supply layer: Converts 220V AC to the voltage required by the lower-level hardware platform; the power supply layer includes an EMI filter and an AC / DC conversion unit; the EMI filter suppresses electromagnetic interference, reduces the impact of power supply noise on the equipment and the electromagnetic influence of the equipment on the outside; the AC / DC conversion unit converts 220V AC to the voltage required by the internal modules.

[0056] In summary, the interface control layer functions include protocol adaptation, virtual device management, communication scheduling and control, protocol gateway, protocol conversion, communication monitoring, interface polling, host computer communication management, host computer protocol management, host computer command management, self-test management, and operation status management; the interface array layer includes CAN main cable interface, LVDS main cable interface, 429 main cable interface, 422 main cable interface, 485 main cable interface, 1553 main cable interface, SPI main cable interface, digital IO main cable interface, R5232 interface, LAN interface, USB interface, and other main cable interfaces; the power layer functions include power adaptation, power management, and power interface.

[0057] like Figure 3 As shown, this invention considers designing the lower-level hardware platform as an FPGA chip-level platform, integrating various types of interface circuits into the FPGA chip. The board only provides interfaces for the FPGA chip to communicate with the upper-level software platform and the interface array, respectively. The specific communication scheme is as follows:

[0058] 1) Communication between the FPGA chip-level platform and the host computer software platform:

[0059] The FPGA chip in the FPGA chip-level platform communicates with the host computer software platform via an external Ethernet interface bus. The communication between the FPGA chip and the host computer software platform includes valid data, clock signals, and control signals. Control signals are used to select and set parameters for various types of interface data paths integrated in the FPGA chip. Clock signals are used to adjust the communication rate between the Ethernet interface and the FPGA chip. Valid data is transmitted between the Ethernet interface and the FPGA chip using a packetization and unpacking method conforming to the Ethernet transmission format.

[0060] 2) Communication between the FPGA chip-level platform and the interface array:

[0061] The FPGA chip-level platform connects to various types of external interfaces on the FPGA chip platform through custom external pins, and communicates with terminal devices through dedicated interface cables. The communication content includes valid data, clock or control signals.

[0062] For bus interfaces that operate synchronously with FPGA chips, clock signals and control signals work together to collect data transmitted from external devices in real time, which is then processed or uploaded to the corresponding data path of the FPGA chip.

[0063] For bus interfaces that work asynchronously with FPGA chips, data transmitted from external devices is first acquired in real time through control signals, and then a clock signal is generated inside the FPGA chip for synchronization before the corresponding data path is processed or uploaded.

[0064] The lower-level hardware platform has three functions: First, to communicate with various external buses and control the corresponding states of discrete quantities as required; second, to communicate with the upper-level software platform, transmitting data obtained from the external bus to the upper-level software platform in real time via the network port, and obtaining corresponding control information from the upper-level software platform; and third, to load the corresponding software code according to the interface reconstruction requirements of the upper-level software platform to realize the bus interface reconstruction.

[0065] like Figure 3 As shown, the power input is 12V. The connections between the ARM and the driver circuit, between the ARM and the FPGA, and between the FPGA and the driver circuit are all TTL level. The connections between the ARM and the driver circuit include the Ethernet port (TTL level), CAN interface 1 (TTL level), CAN interface 2, UART1 (TTL level RS422-1), and UART2; the connections between the ARM and the FPGA include the spare line, FMC bus, UART3, and SPI; the connections between the FPGA and the driver circuit include LVDS1, LVDS2, discrete inputs, and SPI; the connections between the driver circuit and external systems include a switch, CAN bus 1, CAN bus 2, RS422 bus 1, RS422 bus 2, LVDS bus 1, LVDS bus 2, discrete inputs, and SDI bus.

[0066] The primary communication method between the FPGA and ARM is FMC mode, where the FPGA acts as the ARM's SRAM memory, reading and writing asynchronously. UART and SPI are backup methods, secured by reserving a few spare lines. FPGA code loading is controlled by the ARM; when interface reconfiguration is required, the ARM loads the corresponding FPGA code.

[0067] Among them, FPGA stands for Field Programmable Gate Array, ARM is a type of processor, UART is for Universal Asynchronous Receiver / Transmitter, LVDS is for Low Voltage Differential Signaling, and SPI is for Serial Peripheral Interface.

[0068] This invention is not limited to the above-described optional embodiments. Anyone can derive other various forms of products under the guidance of this invention. However, regardless of any changes made in their shape or structure, any technical solution that falls within the scope of the claims of this invention shall be protected by this invention.

Claims

1. A software-defined communication interface reconfigurable electronic equipment test system, characterized in that: The application relates to a test system for a product under test, which comprises an upper computer software platform and a lower computer hardware platform. The upper computer software platform is a user-oriented control system based on driver-free transparent transmission, and the upper computer software platform takes an industrial computer as a carrier, is responsible for communication with a user and an interface system, supports protocol command issuing and data receiving, and the like. The lower computer hardware platform is a hardware system based on software-defined communication interface reconstruction, and the lower computer hardware platform is responsible for protocol conversion and interface configuration, realizes communication with a product under test, and the like. The upper computer software platform comprises a data acquisition layer, a protocol management and adaptation layer and a test service management layer. The data acquisition layer communicates according to a selected protocol, informs the lower computer hardware platform of a data format and a communication protocol of the product under test, analyzes and processes data transmitted by the lower computer hardware platform, and stores the data for test service data analysis. The protocol management and adaptation layer establishes a protocol template and configures a plurality of protocols in the system. The test service management layer manages test services, communicates with the lower computer hardware platform, supports protocol command issuing and data receiving, and the like. The lower computer hardware platform comprises an interface control layer, an interface array layer and a power supply layer. The interface control layer realizes software-defined functions by using an FPGA, constructs an abstraction layer by virtualizing traditional interface equipment into software instances, supports automatic identification of connected interface types, protocol conversion, protocol automatic matching, communication scheduling, and the like, and maintains communication with the upper computer software platform and the interface array layer. The interface array layer supports expansion by preconfiguring a plurality of general communication protocols, and communicates with a multi-protocol communication scheduling control unit through a PCI interface bus. The power supply layer converts 220V AC voltage into voltage required by the lower computer hardware platform.

2. The software defined communication interface reconfigurable electronic equipment test system of claim 1, wherein: The FPGA chip of the FPGA chip-level platform communicates with the upper computer software platform through an external Ethernet interface bus.

3. The software defined communication interface reconfigurable electronic equipment test system of claim 2, wherein: The communication content of the FPGA chip and the upper computer software platform comprises effective data, a clock signal and a control signal, the control signal is used for gating and setting relevant parameters of a plurality of types of interface data paths integrated in the FPGA chip, the clock signal is used for adjusting the communication rate of the Ethernet interface and the FPGA chip, and the effective data is transmitted between the Ethernet interface and the FPGA chip through packing and unpacking in conformity with an Ethernet transmission format.

4. The software defined communication interface reconfigurable electronic equipment test system of claim 1, wherein: The FPGA chip of the FPGA chip-level platform is connected to a plurality of types of external interfaces of the FPGA chip platform through self-defined external pins, and communicates with terminal equipment through interface special cables, and the communication content comprises effective data, a clock signal or a control signal.

5. The software defined communication interface reconfigurable electronic equipment test system of claim 4, wherein: For a bus interface working in a synchronous mode with the FPGA chip, the clock signal and the control signal are used for real-time acquisition of data transmitted by external equipment, and the data is processed or uploaded in a corresponding data path of the FPGA chip.

6. The software defined communication interface reconfigurable electronic equipment test system of claim 4, wherein: For a bus interface working in an asynchronous mode with the FPGA chip, the control signal is used for real-time acquisition of data transmitted by external equipment, and the data is processed or uploaded in a corresponding data path of the FPGA chip after being synchronized through a clock signal generated in the FPGA chip.

7. The software defined communication interface reconfigurable electronic equipment test system of claim 1, wherein: The protocol management and adaptation layer realizes addition and modification of protocols, selects protocol combination, selects protocol template according to test objects, and automatically matches data formats.

8. The software defined communication interface reconfigurable electronic equipment test system of claim 1, wherein: The power supply layer comprises an EMI filter and an AC / DC conversion unit; the EMI filter suppresses electromagnetic interference and reduces the influence of power supply noise on the equipment and the electromagnetic influence of the equipment on the outside; the AC / DC conversion unit converts 220V alternating voltage into the voltage required by the internal module.

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