Data caching method and device, electronic equipment and storage medium
By calculating the cache pass rate and a preset pass rate threshold, the eviction policy of the LRU queue is controlled, which solves the problem of low cache hit rate when the LRU cache has limited memory area, and achieves higher cache hit rate and data access efficiency.
Patent Information
- Application Number
- CN202510737806.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-04
- Publication Date
- 2025-10-31
AI Technical Summary
When the memory area is limited, the existing LRU cache leads to frequent eviction and registration during the cache registration process, resulting in a low cache hit rate, or even a complete cache miss in extreme cases.
By calculating the cache penetration rate and combining it with a preset penetration rate threshold, it is determined whether to evict the tail element of the LRU queue and write the target data to the head of the queue to avoid cache penetration.
It improved the cache hit rate, reduced cache misses, and improved data access efficiency.
Smart Images
Figure CN120873017A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing technology, and in particular to a data caching method, apparatus, electronic device, and storage medium. Background Technology
[0002] Remote Direct Memory Access (RDMA) allows computers on a network to exchange data in main memory without involving the processor, cache, or operating system of any single computer. Like Local Direct Memory Access (DMA), RDMA improves throughput and performance, and is therefore widely used.
[0003] During communication, for each I / O request, it's necessary to register and deregister the memory region used by the peer's RDMA. Registration / deregistration is a CPU-intensive operation, reducing performance. To improve performance, a common industry practice is to introduce an LRU (Least Recently Used) cache. When a memory region needs to be registered, if it's found in the cache, the found memory region is used directly for RDMA transfer. When the LRU cache capacity is insufficient, the cache at the tail of the LRU cache is released to make room for newly registered memory regions.
[0004] When memory areas are limited and LRU caches are insufficient, the actual stable cache registration is a sequential registration process of memory areas, which may lead to situations where caches are evicted in sequence and then registered in sequence again. In extreme cases, all caches may be missed. Summary of the Invention
[0005] Embodiments of this disclosure provide a data caching method, apparatus, electronic device, and storage medium.
[0006] In a first aspect, embodiments of this disclosure provide a data caching method, comprising: in response to receiving a data read / write request, parsing the data read / write request and determining target data; in response to determining that the target data is not stored in memory, determining a cache pass rate, wherein the cache pass rate is the ratio of the amount of data to be registered in memory to the amount of data stored in a preset cache queue; based on the cache pass rate and a preset pass rate threshold, determining whether the tail element of the preset cache queue needs to be evicted; in response to determining that the tail element needs to be evicted, evicting the tail element, and writing the target data into memory and inserting the target data into the head of the preset cache queue.
[0007] Secondly, embodiments of this disclosure provide a data caching device, comprising: a data determination unit configured to, in response to receiving a data read / write request, parse the data read / write request and determine target data; a throughput determination unit configured to, in response to determining that the target data is not stored in memory, determine a cache throughput rate, wherein the cache throughput rate is the ratio of the amount of data to be registered in memory to the amount of data stored in a preset cache queue; an eviction determination unit configured to, based on the cache throughput rate and a preset throughput rate threshold, determine whether the tail element of the preset cache queue needs to be evicted; and a data caching unit configured to, in response to determining that the tail element needs to be evicted, evict the tail element, write the target data into memory, and insert the target data into the head of the preset cache queue.
[0008] Thirdly, embodiments of this disclosure provide an electronic device including a memory, a processor, a bus, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the data caching method as described in the first aspect.
[0009] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the data caching method as described in the first aspect.
[0010] By applying the technical solution disclosed herein, when a data read / write request is received, the request can be parsed to determine the target data. If the cache is not hit, the cache penetration rate is determined. Further, based on a preset penetration rate threshold, it is determined whether the tail element of a preset cache queue needs to be evicted. If the tail element needs to be evicted, it is evicted, the target data is written to the cache, and the target data is inserted at the head of the preset cache queue. By using the cache penetration rate parameter, cache penetration is avoided, significantly improving the cache hit rate.
[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0012] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:
[0013] Figure 1 This is a flowchart illustrating an embodiment of the data caching method disclosed herein;
[0014] Figure 2 This is a flowchart illustrating another embodiment of the data caching method disclosed herein;
[0015] Figure 3 This is a flowchart illustrating a specific implementation of the data caching method disclosed herein;
[0016] Figure 4 This is a schematic diagram of the structure of one embodiment of the data caching device of this disclosure;
[0017] Figure 5 This is a schematic diagram of the structure of an embodiment of the electronic device disclosed herein. Detailed Implementation
[0018] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of this disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.
[0019] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0020] Where there is no conflict, the embodiments and features described herein can be combined with each other.
[0021] To make the technical solutions and advantages of this disclosure clearer, the following description, in conjunction with the accompanying drawings and specific embodiments, will provide a more detailed account of this disclosure.
[0022] Figure 1 A flow 100 of one embodiment of the data caching method of this disclosure is shown. For example... Figure 1 As shown, the data caching method in this embodiment may include the following steps:
[0023] Step 101: In response to receiving a data read / write request, parse the data read / write request and determine the target data.
[0024] In this embodiment, the execution body of the data caching method can receive data read / write requests. These requests can be sent by applications performing RDMA communication. The data read / write requests may include information such as the address of the memory region where the target data is located.
[0025] Step 102: In response to determining that the target data is not stored in the cache, determine the cache pass rate.
[0026] Upon receiving a data read / write request, it can be determined whether the target data is stored in the cache. If it is, it's called a cache hit, and the target data can be read from the cache. If it's not, it's called a cache miss, and the cache pass rate can be determined. Here, the cache pass rate refers to the proportion of requests that fail to retrieve data from the cache and instead directly access the database. Specifically, the cache pass rate reflects the proportion of cache invalidations, i.e., the proportion of requests that fail to retrieve data from the cache and directly access the database. The cache pass rate can be determined by calculating the ratio of the number of read / write requests that miss the cache to the total number of read / write requests.
[0027] Step 103: Based on the cache throughput and the preset throughput threshold, determine whether to evict the tail element of the preset cache queue.
[0028] After determining the cache pass rate, it can be compared with a preset pass rate threshold to determine whether the tail element of the preset cache queue needs to be evicted. Specifically, if the cache pass rate is greater than or equal to the preset pass rate threshold, it is considered that the cache pass rate is too high, meaning there are too many cache misses. In this case, the tail element of the preset cache queue does not need to be evicted. The preset cache queue can be an LRU (Least Recently Used) queue, where the element at the head of the queue is the most recently used element, and the element at the tail of the queue is the least recently used element. If the tail element is the least recently used element, it can be evicted when the eviction condition is met.
[0029] Step 104: In response to determining the tail element of the elimination queue, write the target data into the cache and insert the target data into the head of the preset cache queue.
[0030] If the last element is evicted, a position is considered freed up in the LRU queue, which can be used to store the target data. At this point, the target data can be written to the cache and inserted at the head of the pre-defined cache queue.
[0031] The data caching method provided in the above embodiments of this disclosure can parse data read / write requests upon receipt to determine the target data. If the cache is not hit, the cache penetration rate is determined. Further, based on a preset penetration rate threshold, it is determined whether the tail element of a preset cache queue needs to be evicted. If the tail element needs to be evicted, it is evicted, the target data is written to the cache, and the target data is inserted at the head of the preset cache queue. By using the cache penetration rate parameter, cache penetration is avoided, significantly improving the cache hit rate.
[0032] See also Figure 2 This illustrates a flow 200 of another embodiment of the data caching method according to this disclosure. For example... Figure 2 As shown, the data caching method in this embodiment may include the following steps:
[0033] Step 201: In response to receiving a data read / write request, parse the data read / write request and determine the target data.
[0034] Step 202: In response to determining that the target data is not stored in the cache, determine the cache pass rate.
[0035] Step 203: In response to determining that the cache pass rate is greater than or equal to a preset pass rate threshold, determine not to eliminate the tail element.
[0036] In this embodiment, if the cache pass rate is greater than or equal to a preset pass rate threshold, the cache pass rate is considered too high, meaning there are too many cache misses. In this case, it is not necessary to evict the tail element of the preset cache queue.
[0037] Step 204: In response to determining that the cache throughput is less than a preset throughput threshold, determine whether the preset delay eviction flag is a preset value.
[0038] If the cache throughput is less than the preset throughput threshold, it can be further determined whether the preset delayed eviction flag is a preset value. Here, the preset delayed eviction flag is used to indicate whether delayed eviction is enabled in the preset cache queue. If the preset delayed eviction flag is a preset value, it means that delayed eviction is not enabled in the preset cache queue.
[0039] Step 205: In response to determining that the preset delay elimination flag is a preset value, it is determined that the tail element does not need to be eliminated.
[0040] If the preset delayed eviction flag is the preset value, it means that the preset cache queue has not enabled delayed eviction, and the tail element does not need to be evicted.
[0041] Step 206: In response to determining that the preset delay elimination flag is not a preset value, determine whether the tail element of the queue has an elimination start time.
[0042] If the preset delayed eviction flag is not a preset value, it means that the preset cache queue has delayed eviction enabled, and it can be determined whether the tail element has a corresponding eviction start time. Here, the eviction start time can be understood as the time when the eviction countdown of the tail element begins, or it can be understood as the expiration time.
[0043] Step 207: In response to determining that the tail element of the queue has an elimination start time, determine whether to eliminate the tail element of the queue based on the elimination start time.
[0044] If the last element in the queue has a corresponding elimination start time, then it can be determined whether to eliminate the last element based on that start time. Specifically, if the elimination start time represents the start time of the elimination countdown, then it can be determined whether the countdown has ended at the current moment; if it has, the last element can be eliminated. If the elimination start time represents the expiration time, then it can be determined whether the current moment has exceeded the expiration time; if it has, the last element can be eliminated.
[0045] Step 208: In response to determining that the tail element does not have a corresponding elimination start time, determine not to eliminate the tail element and set the elimination start time for the tail element.
[0046] If the tail element does not have a corresponding eviction start time, then the tail element will not be evicted, and an eviction start time will be set for it. Specifically, the time when the data read / write request is received can be used as the eviction start time, or the current time can be used as the eviction start time, or a preset time after the current time can be used as the eviction start time.
[0047] Step 209: In response to determining that the target data is stored in the cache, read the target data from the cache and insert the target data into the head of the preset cache queue.
[0048] If the target data is stored in the cache, i.e., the cache is hit, the target data can be read directly from the cache and inserted into the head of the preset cache queue.
[0049] Step 210: In response to determining that the tail element will not be evicted, register and deregister the memory region where the target data is located on the read / write path.
[0050] If it is not necessary to eliminate the tail element, the target data memory area can be registered and deregistered on the read / write path.
[0051] Can be combined Figure 3 To further understand this embodiment, Figure 3In the process, upon receiving a new data read / write request, it determines whether the cache has been hit. If the cache has been hit, the target data is read from the cache and moved to the head of the LRU queue. If the cache has not been hit, it determines whether to skip writing to the cache based on the cache pass rate and a preset pass rate threshold. If yes, the read / write request continues to be processed, and memory registration and deregistration are performed on the I / O path. If not, it checks whether the delayed eviction flag is at a preset value. If yes, the read / write request continues to be processed, and memory registration and deregistration are performed on the I / O path. If not, it further checks whether the tail element of the LRU queue has a corresponding eviction start time. If no corresponding eviction start time is provided, an eviction start time is set for the tail element of the LRU queue. If a corresponding eviction start time is provided, it further determines whether the current eviction start time has been exceeded. If it has, the tail element is evicted, a new memory is registered, and inserted at the head of the LRU queue.
[0052] The data caching method provided in the above embodiments of this disclosure can control the updating of data in the LRU queue through two parameters: cache penetration rate and delayed eviction time, thereby avoiding cache penetration and greatly improving the cache hit rate.
[0053] Further reference Figure 4 As an implementation of the methods shown in the above figures, this disclosure provides an embodiment of a data caching device, which is similar to... Figure 2 Corresponding to the method embodiments shown, this device can be specifically applied to various electronic devices.
[0054] like Figure 4 As shown, the data caching device 400 of this embodiment includes: a data determination unit 401, a transmittance determination unit 402, an elimination judgment unit 403, and a data caching unit 404.
[0055] The data determination unit 401 is configured to parse the data read / write request and determine the target data in response to receiving the data read / write request.
[0056] The throughput determination unit 402 is configured to determine the cache throughput in response to determining that no target data is stored in memory. The cache throughput is the ratio of the amount of data to be registered in memory to the amount of data stored in a preset cache queue.
[0057] The eviction determination unit 403 is configured to determine whether the tail element of the preset cache queue needs to be evicted based on the cache throughput and a preset throughput threshold.
[0058] Data caching unit 404 is configured to, in response to determining that the tail element needs to be evicted, evict the tail element, write the target data to memory, and insert the target data into the head of a preset cache queue.
[0059] In addition, an electronic device is also proposed in the technical solution of this application.
[0060] Figure 5 A schematic diagram of the structure of an electronic device provided in one embodiment of the present disclosure is shown.
[0061] like Figure 5 As shown, the electronic device may include a processor 501, a memory 502, a bus 503, and a computer program stored in the memory 502 and executable on the processor 501. The processor 501 and the memory 502 communicate with each other via the bus 503. When the processor 501 executes the computer program, it implements the steps of the above method, including, for example: in response to receiving a data read / write request, parsing the data read / write request and determining the target data; in response to determining that the target data is not stored in memory, determining a cache pass-through rate, wherein the cache pass-through rate is the ratio of the amount of data to be registered in memory to the amount of data stored in a preset cache queue; based on the cache pass-through rate and a preset pass-through rate threshold, determining whether the tail element of the preset cache queue needs to be evicted; in response to determining that the tail element needs to be evicted, evicting the tail element, writing the target data into memory, and inserting the target data into the head of the preset cache queue.
[0062] In addition, one embodiment of this disclosure also provides a non-transitory computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it implements the steps of the above-described method, including, for example,: in response to receiving a data read / write request, parsing the data read / write request and determining the target data; in response to determining that the target data is not stored in memory, determining a cache pass rate, wherein the cache pass rate is the ratio of the amount of data to be registered in memory to the amount of data stored in a preset cache queue; based on the cache pass rate and a preset pass rate threshold, determining whether the tail element of the preset cache queue needs to be evicted; in response to determining that the tail element needs to be evicted, evicting the tail element, writing the target data into memory, and inserting the target data into the head of the preset cache queue.
[0063] In summary, the technical solution disclosed herein can parse data read / write requests upon receipt to determine the target data. If the cache is not hit, the cache penetration rate is determined. Further, based on a preset penetration rate threshold, it is determined whether the tail element of a preset cache queue needs to be evicted. If the tail element needs to be evicted, it is evicted, the target data is written to the cache, and the target data is inserted at the head of the preset cache queue. By using the cache penetration rate parameter, cache penetration is avoided, significantly improving the cache hit rate.
[0064] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A data caching method, comprising: In response to receiving a data read / write request, the data read / write request is parsed to determine the target data; In response to determining that the target data is not stored in memory, a cache pass rate is determined, wherein the cache pass rate is the ratio of the amount of data to be registered in memory to the amount of data stored in a preset cache queue; Based on the cache throughput and the preset throughput threshold, determine whether the tail element of the preset cache queue needs to be evicted; In response to determining that the tail element needs to be evicted, the tail element is evicted, the target data is written to memory, and the target data is inserted at the head of the preset cache queue.
2. The method according to claim 1, wherein, The step of determining whether the tail element of the preset cache queue needs to be evicted based on the cache throughput and a preset throughput threshold includes: In response to determining that the cache pass rate is greater than or equal to the preset pass rate threshold, it is determined that the tail element does not need to be evicted.
3. The method according to claim 2, wherein, The step of determining whether the tail element of the preset cache queue needs to be evicted based on the cache throughput and a preset throughput threshold includes: In response to determining that the cache throughput is less than the preset throughput threshold, determine whether the preset delay eviction time is a preset value; In response to determining that the preset delay elimination time is a preset value, it is determined that the tail element does not need to be eliminated.
4. The method according to claim 3, wherein, The step of determining whether the tail element of the preset cache queue needs to be evicted based on the cache throughput and a preset throughput threshold includes: In response to determining that the preset delay elimination time is not a preset value, determine whether the tail element of the queue corresponds to an elimination start time; In response to determining that the tail element corresponds to an elimination start time, the system determines whether the tail element needs to be eliminated based on the elimination start time.
5. The method according to claim 4, wherein, The step of determining whether the tail element of the preset cache queue needs to be evicted based on the cache throughput and a preset throughput threshold includes: In response to determining that the tail element does not have a corresponding elimination start time, it is determined that the tail element does not need to be eliminated, and an elimination start time is set for the tail element.
6. The method according to claim 1, wherein, The method further includes: In response to determining that the target data is stored in memory, the target data is read from the memory region and inserted into the head of the preset cache queue.
7. The method according to claim 2, wherein, The method further includes: In response to determining that the tail element does not need to be evicted, the target data is registered and deregistered on the read / write path.
8. A data caching device, comprising: The data determination unit is configured to, in response to receiving a data read / write request, parse the data read / write request and determine the target data; The throughput determination unit is configured to determine a cache throughput in response to determining that the target data is not stored in memory, wherein the cache throughput is the ratio of the amount of data to be registered in memory to the amount of data stored in a preset cache queue; The eviction determination unit is configured to determine whether the tail element of the preset cache queue needs to be evicted based on the cache throughput and a preset throughput threshold. The data caching unit is configured to, in response to determining that the tail element needs to be evicted, evict the tail element, write the target data to memory, and insert the target data at the head of the preset cache queue.
9. An electronic device comprising a memory, a processor, a bus, and a computer program stored in the memory and executable on the processor, wherein, When the processor executes the computer program, it implements the data caching method as described in any one of claims 1 to 7.
10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the data caching method as described in any one of claims 1 to 7.