Integrated circuit time sequence optimization method and device, electronic equipment and storage medium

Abstract

The invention provides an integrated circuit time sequence optimization method and device, electronic equipment and a storage medium, and is applied to the technical field of computers.The integrated circuit time sequence optimization method comprises the steps that after registers of an integrated circuit are extracted, a target register set is determined based on the registers of the integrated circuit; the target register set comprises at least two target registers, and a time sequence path exists between any two target registers, counting target parameters related to time sequence performance on the time sequence path to which each target register belongs, and adjusting the time sequence path to which each target register belongs based on the target parameters, the time sequence path optimization is carried out on the target registers in the target register set, the overall workload of the optimization design can be reduced, the optimization process is carried out on the target registers where time sequence violation is prone to occurring, the optimization effect is more obvious, and therefore the time sequence optimization efficiency is improved on the whole, and the integrated circuit design period is shortened.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to an integrated circuit timing optimization method, apparatus, electronic device, and storage medium. Background Technology

[0002] In the existing design approach of integrated circuits, in order to further improve the performance of integrated circuits, after the integrated circuit design is completed, it is necessary to optimize the integrated circuit in many aspects. Since timing performance directly affects the main operating frequency of the integrated circuit and has a direct impact on the overall performance of the integrated circuit, timing optimization is the most important part of integrated circuit design.

[0003] However, as integrated circuits become larger and larger, the amount and complexity of logic in integrated circuits increase significantly, making timing optimization work increasingly arduous. Therefore, how to improve the timing optimization efficiency of integrated circuits and shorten the integrated circuit design cycle has become one of the problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, this application aims to provide an integrated circuit timing optimization method, apparatus, electronic device, and storage medium to improve the timing optimization efficiency of integrated circuits and shorten the integrated circuit design cycle.

[0005] In a first aspect, this application provides an integrated circuit timing optimization method, comprising:

[0006] Extract the registers of the integrated circuit;

[0007] A target register set is determined based on the registers of the integrated circuit, the target register set including at least two target registers, and a timing path exists between any two target registers;

[0008] Collect the target parameters related to timing performance on the timing path to which each target register belongs;

[0009] Adjust the timing path of each target register based on the target parameters.

[0010] In one alternative implementation, determining the target register set based on the registers of the integrated circuit includes:

[0011] The registers of the integrated circuit are divided into multiple register groups by taking any two registers as a group, and a target register group is identified in the multiple register groups, wherein there is a timing path between the two registers in the target register group;

[0012] The target register set is determined based on the target register group.

[0013] In one optional implementation, the step of dividing the registers of the integrated circuit into multiple register groups by grouping any two registers together and identifying the target register group among the multiple register groups includes:

[0014] Create an orthogonal table, wherein the row and column cells of the orthogonal table are the registers of the integrated circuit;

[0015] The registers of the integrated circuit are divided into multiple register groups by taking any orthogonal combination of row units and column units as a register group;

[0016] If there is a timing path between two registers in any of the aforementioned register groups, the register group is determined as the target register group and the orthogonality value is marked as the first value.

[0017] If there is no timing path between two registers in any of the register groups, the orthogonality value corresponding to that register group is marked as the second value.

[0018] In one optional implementation, determining the target register set based on the target register group includes:

[0019] Adjust the positions of the cells in each row of the orthogonal table according to the order of the number of the first value in the same row from most to least;

[0020] Adjust the positions of the cells in each column of the orthogonal table according to the order of the number of the first value in the same column from most to least;

[0021] The set of registers corresponding to the target rectangular sub-table within the orthogonal table is taken as the target register set, and each orthogonal value within the target rectangular sub-table is a first value.

[0022] In one alternative implementation, the process of identifying the target register set includes:

[0023] If path detection and timing detection are configured between two registers in any of the aforementioned register groups, then the register group is determined to be the target register group.

[0024] If no path detection is configured between two registers in any of the aforementioned register groups, or if no timing detection is configured, then the register group is determined to be a non-target register group.

[0025] In one optional implementation, the target parameters related to timing performance on the timing path to which each of the target registers belongs are statistically analyzed, including:

[0026] Identify the key timing paths in the timing paths to which each of the target registers belongs, wherein the key timing paths start with one of the target registers and end with the other target register;

[0027] Statistically analyze the target parameters related to timing performance on the key timing path.

[0028] In one optional implementation, adjusting the timing path to which each of the target registers belongs based on the target parameters includes:

[0029] The target registers whose target parameters are greater than a preset parameter threshold are identified as critical registers.

[0030] Adjust the timing path to which the critical register belongs.

[0031] In one alternative implementation, during the logic design phase, the target parameter includes the number of logic levels or the number of logic operation units.

[0032] In one optional implementation, adjusting the timing path to which the critical register belongs includes:

[0033] Adjust the number of logic levels or logic operation units in the timing path to which the key register belongs.

[0034] In one optional implementation, the extraction of the integrated circuit's registers includes:

[0035] After completing the logic synthesis of the integrated circuit, the gate netlist of the integrated circuit is obtained;

[0036] Extract all registers from the gate netlist.

[0037] In one optional implementation, adjusting the timing path to which the critical register belongs includes:

[0038] During the physical design phase, the physical distance of the timing path to which the critical register belongs is adjusted, and / or the clock bifurcation position of the timing path to which the critical register belongs is adjusted.

[0039] In one optional implementation, adjusting the timing path to which the critical register belongs includes:

[0040] During the physical design phase, the key registers with the largest target parameters among the key registers are identified as high-priority registers.

[0041] Prioritize the placement and routing resources of the high-priority registers.

[0042] In one optional implementation, the extraction of the integrated circuit's registers includes:

[0043] After completing static timing analysis of the integrated circuit, extract all registers of the integrated circuit or extract the registers in the integrated circuit that have timing violations.

[0044] Secondly, this application provides an integrated circuit timing optimization device, comprising:

[0045] Extraction unit, used to extract the registers of the integrated circuit;

[0046] A determining unit is configured to determine a target register set based on the registers of the integrated circuit, the target register set including at least two target registers, and a timing path existing between any two of the target registers;

[0047] The statistics unit is used to count the target parameters related to timing performance on the timing path to which each of the target registers belongs;

[0048] An optimization unit is used to adjust the timing path to which each of the target registers belongs based on the target parameters.

[0049] Thirdly, this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein the processor executes the computer program to implement the steps of the integrated circuit timing optimization method as described in any embodiment of the first aspect of this application.

[0050] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the integrated circuit timing optimization method as described in any embodiment of the first aspect of this application.

[0051] Based on the above, the integrated circuit timing optimization method provided in this application, after extracting the registers of the integrated circuit, determines a target register set based on the registers of the integrated circuit. This target register set includes at least two target registers, and a timing path exists between any two target registers. Target parameters related to timing performance are statistically analyzed on the timing paths to which each target register belongs. Based on these target parameters, the timing paths to which each target register belongs are adjusted to optimize the timing characteristics of the integrated circuit. In an integrated circuit, if a timing path exists between any two registers in the set, it indicates that the timing units and logic units in the corresponding circuit structure are coupled together, making it highly susceptible to timing errors. Currently, timing violations are a problem, and the more registers in the set, the greater the likelihood and severity of timing violations. Congestion is also more likely to occur during the placement and routing phase. Compared to related technologies that optimize the timing of the entire integrated circuit, this application optimizes the timing path of target registers within the target register set. This not only significantly reduces the number of registers, thereby reducing the overall workload of the optimization design, but also, since the optimization process is carried out on target registers that are prone to timing violations, the optimization effect is more obvious. The timing characteristics of the integrated circuit are more likely to meet the design requirements, thereby improving the overall timing optimization efficiency and shortening the integrated circuit design cycle. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a flowchart of an integrated circuit timing optimization method provided in this application.

[0054] Figure 2 This is a schematic diagram of a timing path in an integrated circuit.

[0055] Figure 3 This is a schematic diagram of another timing path in an integrated circuit.

[0056] Figure 4 This is a flowchart of another integrated circuit timing optimization method provided in this application.

[0057] Figure 5 This is a flowchart of another integrated circuit timing optimization method provided in this application.

[0058] Figure 6 This is a structural block diagram of an integrated circuit timing optimization device provided in this application.

[0059] Figure 7 This is a schematic diagram of the structure of an electronic device provided in this application. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0061] To address the issues of low efficiency in integrated circuit timing optimization and long integrated circuit design cycles in related technologies, this application provides an integrated circuit timing optimization method. This method determines a target register set based on the registers of the integrated circuit. This target register set includes at least two target registers, and a timing path exists between any two target registers. Compared to related technologies that perform timing optimization on the entire integrated circuit, this application optimizes the timing paths of target registers within the target register set. This not only significantly reduces the number of registers, thereby reducing the overall workload of the optimization design, but also, because the optimization process targets target registers prone to timing violations, the optimization effect is more pronounced. The timing characteristics of the integrated circuit are more likely to meet design requirements, thus improving the overall timing optimization efficiency and shortening the integrated circuit design cycle.

[0062] The integrated circuit timing optimization method provided in this application is applied to electronic devices, such as laptops, personal computers (PCs), and tablets. It can also be other electronic devices capable of running applications corresponding to the integrated circuit timing optimization method provided in this application; these will not be listed here. In some cases, it can also be applied to network-side servers. See [link to application details]. Figure 1 As shown, the integrated circuit timing optimization method provided in this application includes the following steps.

[0063] S100, Extract the registers of the integrated circuit.

[0064] Registers are a crucial component of integrated circuits (ICs). They enable various functions such as fast data access, instruction execution, and operational state management. Furthermore, based on their operating principles, ICs can be categorized into combinational logic circuits and sequential logic circuits. Combinational logic circuits output only the current input and lack memory functionality. Sequential logic circuits, in addition to basic logic gates, include registers and other storage elements to retain past information. Their steady-state output depends not only on the current input but also on the states formed by past inputs. Each sequential logic circuit corresponds to a timing path, and the start and end points of these paths are defined by registers. Each timing path corresponds to a starting register (called the start register) and an ending register (called the end register). Timing optimization in ICs is based on the registers within the IC.

[0065] Based on the above, the integrated circuit timing optimization method provided in this embodiment first extracts the registers in the integrated circuit. In one optional implementation, the registers can be extracted based on the gate netlist after the logic synthesis of the integrated circuit is completed. In another optional implementation, the registers can be extracted based on the results of the static timing analysis after the placement and routing of the integrated circuit is completed. These two methods can be applied to the timing optimization of integrated circuits at different design stages. The specific optimization process will be elaborated in subsequent content with specific embodiments, and will not be detailed here. Of course, the registers of the integrated circuit can also be extracted at other stages, which, without exceeding the core idea of ​​this application, also fall within the scope of protection of this application. As for the specific method of extracting registers, it can be implemented with reference to related technologies, such as designing a dedicated script file and extracting the registers in the integrated circuit by executing the script file. This application does not limit the specific extraction process of registers.

[0066] S110. Determine the target register set based on integrated circuit registers.

[0067] Among the registers included in an integrated circuit, the target register is determined. The set of target registers is called the target register set. The target register set includes at least two target registers, and there is a timing path between any two target registers. For example, the target register set includes target register A, target register B, and target register C. There is a timing path between target register A and target register B, a timing path between target register A and target register C, a timing path between target register B and target register C, and so on. When the target register set includes other numbers of target registers, the above requirements should also be met.

[0068] In one optional implementation, when determining whether a timing path exists between any two registers, the system can first determine whether path detection is configured between the two registers based on the timing constraint file of the integrated circuit or other design documents. If path detection is configured, it further determines whether timing detection is configured between the two registers. If timing detection is configured, it is determined that a timing path exists between them. Conversely, if no path detection is configured between the two registers, or if path detection is configured but timing detection is not, it can be determined that no timing path exists between them. Path detection refers to the process of identifying the critical path of signal transmission in the integrated circuit, while timing detection is the process of verifying whether the integrated circuit can meet all timing constraints at a specific clock frequency, ensuring that data is sampled and transmitted at the correct time. In practical applications, specific detection requirements are recorded in relevant documents. In this step, the system can determine whether path detection and timing detection are configured by accessing the relevant documents.

[0069] Based on the above, after extracting the registers of the integrated circuit, by grouping any two registers together and traversing all possible combinations, the registers of the integrated circuit can be divided into multiple register groups. If there is a timing path between two registers in any register group, and this register group is taken as the target register group, multiple target register groups can be obtained by traversing all register groups. The process of identifying the target register group is similar to the previous embodiment, that is, if path detection and timing detection are configured between two registers in any register group, the register group is determined to be a target register group; conversely, if there is no path detection or timing detection configured between two registers in any register group (regardless of whether path detection is configured), the register group is determined not to be a target register group. After determining the target register group, the target register set can be determined based on the obtained target register group, ensuring that there is a timing path between any two target registers in the obtained target register set.

[0070] In practical applications, integrated circuits contain a large number of registers. To improve the efficiency of creating a target register set, this application provides a preferred implementation method that uses orthogonal tables to create the target register set. An orthogonal table is a mathematical and statistical tool used for efficiently designing experiments or optimizing combinatorial tests. Through orthogonality, it can reduce the number of statistical operations and cover all possible parameter combinations. Based on this, the specific process of this embodiment is as follows:

[0071] First, an orthogonal array is created, where the row and column cells represent the registers of the integrated circuit. Assume the integrated circuit has N registers (N > 1), i.e., RegA, RegB, ..., RegN. These N registers are used as the row and column cells of the orthogonal array. In one optional implementation, the registers in the row cells are used as the starting registers, and the registers in the column cells are used as the ending registers. In another optional implementation, the registers in the row cells can also be used as the ending registers, and correspondingly, the registers in the column cells can also be used as the ending registers. In practical applications, the choice of which to use is flexible and will not affect the final filtering results.

[0072] Based on the above premise, by taking any orthogonal combination of row and column units as a register group, the registers of the integrated circuit can be divided into multiple register groups. Referring to the aforementioned content, if there is a timing path between two registers in any register group, the register group is determined as the target register group, and the orthogonality value corresponding to the register group is marked as the first value, such as 1. Conversely, if there is no timing path between two registers in any register group, the orthogonality value corresponding to the register group is marked as the second value, such as 0. After traversing all register groups, the statistical results shown in Table 1 can be obtained.

[0073] Table 1

[0074]

[0075] As can be seen from the creation process in Table 1, the connection relationship between any two registers can be accurately and simply represented by the table. That is, if the orthogonality value of any two registers is 1, it indicates that there is a timing path between them. Conversely, if the orthogonality value of any two registers is 0, it indicates that there is no timing path between them.

[0076] In one alternative implementation, when filling in the orthogonal table above, a set of fan-out registers corresponding to each register in the integrated circuit can be created. Taking register A as an example, assuming there are m registers (m≥1) that are fan-out registers of register A, the set can be obtained. By iterating through all registers, we can obtain the set corresponding to each register. Based on this, when filling in the orthogonal table, for each register, we can fill in the corresponding orthogonal value according to the register in the set corresponding to that register. This setting can avoid the omission of registers and improve the efficiency of determining the register set.

[0077] After completing the orthogonal table, the target register set can be determined based on the obtained orthogonal table. In one optional implementation, firstly, the positions of the row cells in the orthogonal table are adjusted according to the order of the number of first values ​​in the same row from most to least, that is, the row cells are reordered according to the order of the number of first values ​​in the same row. Further, the positions of the column cells in the orthogonal table are adjusted according to the order of the number of first values ​​in the same column from most to least, that is, the column cells are reordered according to the order of the number of first values ​​in the same column. Of course, it is also feasible to adjust the column cells first and then adjust the row cells. After the complete orthogonal table is adjusted, the target rectangular sub-table in the orthogonal table is identified. All orthogonal values ​​in the target rectangular sub-table are the first values, and the set of registers corresponding to the target rectangular sub-table in the orthogonal table is taken as the target register set.

[0078] Taking RegA-RegJ, a total of 10 registers, as an example, the orthogonal table filled in according to the above method can be shown in Table 2.

[0079] Table 2

[0080] RegA RegB RegC RegD RegE RegF RegG RegH RegI RegJ RegA 1 1 1 0 1 1 1 1 1 1 RegB 1 0 1 0 1 0 0 1 0 0 RegC 1 1 1 0 1 1 1 1 1 0 RegD 0 0 0 0 0 0 0 0 0 0 RegE 1 1 1 0 1 1 1 1 0 0 RegF 1 0 1 0 1 0 0 0 0 0 RegG 1 0 1 0 1 0 1 1 0 0 RegH 1 1 1 0 1 0 1 1 0 0 RegI 1 0 1 0 0 0 0 0 0 0 RegJ 1 0 0 0 0 0 0 0 0 0

[0081] Furthermore, after sorting the row and column cells of Table 2 according to the above method, the results can be seen in Table 3.

[0082] Table 3

[0083] RegA RegC RegE RegH RegG RegB RegF RegI RegJ RegD RegA 1 1 1 1 1 1 1 1 1 0 RegC 1 1 1 1 1 1 1 1 0 0 RegE 1 1 1 1 1 1 1 0 0 0 RegH 1 1 1 1 1 1 0 0 0 0 RegG 1 1 1 1 1 0 0 0 0 0 RegB 1 1 1 1 0 0 0 0 0 0 RegF 1 1 1 0 0 0 0 0 0 0 RegI 1 1 0 0 0 0 0 0 0 0 RegJ 1 0 0 0 0 0 0 0 0 0 RegD 0 0 0 0 0 0 0 0 0 0

[0084] It should be noted that in practical applications, if the number of the first value in a row is the same as the number of the first value in another row, the order of the rows can be disregarded. Similarly, if the number of the first value in a column is the same as the number of the first value in another column, the order of the columns can also be disregarded.

[0085] According to the sorting results shown in Table 3, the orthogonal values ​​in the rectangular sub-tables corresponding to RegA, RegC, RegE, RegH and RegG are all 1, that is, the first value. Therefore, RegA, RegC, RegE and RegH can be identified as the target registers, and the set they form is the target register set.

[0086] Based on the actual circuit topology of the integrated circuit, if the target register set can be extracted and there is a timing path between any two target registers in the target register set, it means that the timing units and logic units in the circuit structure to which each target register belongs are coupled together. This circuit structure has a very high probability of timing violations and congestion in placement and routing. Furthermore, the larger the number of target registers in the target register set, the more serious the timing violations and placement and routing congestion will be, ultimately making it difficult for the integrated circuit timing to meet the design requirements.

[0087] In practical applications, there may be two typical timing path forms between target registers within the target register set. Specifically, taking... Figure 2 For example, when RegA is the starting register, the timing path between it and the ending register RegB is shown in Path1; when RegB is the starting register, the timing path between it and the ending register RegA is shown in Path2, forming a double loop path. Here, "logic" represents the combinational logic circuit used to implement the preset function. Based on this, if the timing of one path, Path1 or Path2, is easy to meet, the timing of the other path is usually difficult to meet. Furthermore, if the timing of both Path1 and Path2 cannot be met, then the useful skew method used in related technologies cannot be used to meet the timing requirements.

[0088] Furthermore, in combination Figure 3 As shown, RegA serves as both a start register and an end register. Starting from the output (Q) of RegA, the circuit passes through a series of combinational logic circuits and returns to the end, i.e., the input (D) of RegA. The resulting timing path can be described as follows: Figure 3 As shown in Path3, it corresponds to the first row of the first column in Table 1. Considering the specific timing path, this type of timing path can also be defined as a single loop-back path. In practical applications, the delay of a single loop-back path is usually quite large. However, since its clock signals are all on a common path, the delay problem cannot be solved by borrowing clock signals. In other words, single loop-back paths are also a challenge in the timing optimization process of integrated circuits.

[0089] Understandably, if the aforementioned double-loop and single-loop paths simultaneously occur between target registers in the target register set, the delay of such timing paths will directly determine the target clock frequency of the integrated circuit. When the delay exceeds the design threshold, such timing circuits will become timing bottlenecks for the integrated circuit. Furthermore, as the number of target registers in the target register set increases, the number of single-loop and double-loop paths may also increase. In addition, the connection relationships between the target registers within the target register set become sufficiently complex. In practical applications, it is difficult to improve the timing characteristics of the integrated circuit through conventional methods such as useful clock offsets. Such timing paths will inevitably cause timing violations. Therefore, this application takes the target registers in the target register set and their associated timing paths as optimization objects. By optimizing the timing characteristics of such timing paths, targeted and significant timing performance improvements can be achieved, resulting in a multiplier effect.

[0090] S120. Calculate the target parameters related to timing performance on the timing path to which each target register belongs.

[0091] After determining the target register set according to the aforementioned steps, the target parameters related to timing performance on the timing path to which each target register belongs are further counted. In conjunction with the integrated circuit timing performance analysis process in related technologies, there are many target parameters related to timing performance, such as the number of logic levels, the number of logic operation units, timing check values, and path length. These parameters can be used as the main indicators for optimizing the timing performance of integrated circuits at different design stages. The specifics will be elaborated in subsequent embodiments and will not be detailed here.

[0092] Here, the number of logic levels refers to the sum of the number of logic units between the starting and ending registers on a timing path. Too many logic levels may increase the latency of the timing path, causing timing violations. Excessive path length will also cause timing violations due to longer signal transmission times. Similarly, if the number of registers and logic units coupled to the preceding and following stages of the destination register is too large, the resulting distribution range will also increase the path length, leading to timing violations caused by excessive path length. Of course, in practical applications, clock unevenness can also cause timing violations, but this factor is beyond the scope of this application and will not be discussed in detail here.

[0093] It is understandable that for any target register, it is not only connected to other target registers within the target register set, but also to other registers outside the target register set. In other words, there are timing paths between the target register and other registers outside the target register set. If we were to statistically analyze the timing performance-related target parameters on the timing path to which each target register belongs, the amount of data to be processed would still be very large. To further improve the efficiency of timing analysis, this application provides a preferred implementation method. In the timing paths to which each target register belongs, key timing paths are further identified. A key timing path is a timing path that starts with one target register and ends with another target register. In other words, it is the timing path between any two target registers within the target register set. Based on this, the timing performance-related target parameters on each key timing path are further analyzed.

[0094] Furthermore, as a preferred implementation, the statistics of the target parameters can be achieved based on the aforementioned orthogonal table. Continuing the previous example, assume that the target rectangular sub-table obtained based on the orthogonal table is shown in Table 4.

[0095] Table 4

[0096] RegA RegC RegE RegH RegG RegA 1 1 1 1 1 RegC 1 1 1 1 1 RegE 1 1 1 1 1 RegH 1 1 1 1 1 RegG 1 1 1 1 1

[0097] As mentioned earlier, the registers within the target rectangular sub-table are the target registers, the set of all target registers is the target register set, and the timing path between any two target registers is the critical timing path.

[0098] Based on the above, the orthogonal table used for statistical connection relationships can be converted into an orthogonal table for statistical target parameters. That is, any orthogonal value is no longer used to indicate whether a timing path exists between two corresponding registers, but rather to statistically analyze the corresponding target parameters. Taking logic levels as an example, the statistical effect of using an orthogonal table to calculate the logic levels of the timing path between any two target registers is shown in Table 5.

[0099] Table 5

[0100] RegA RegC RegE RegH RegG RegA 25 24 23 22 22 RegC 23 22 21 20 20 RegE 22 21 21 19 18 RegH 18 18 17 18 17 RegG 17 16 16 16 16

[0101] As shown in Table 5, the orthogonal values ​​corresponding to any two target registers represent the logical order of the timing path between them. Therefore, the orthogonal table provides a clear visual representation of the target parameters for each key timing path, while also preventing data omissions during the statistical process, thus ensuring the effective implementation of subsequent optimization. Other target parameters can be statistically analyzed using the methods provided in this embodiment, and will not be detailed here.

[0102] S130. Adjust the timing path of each target register based on the target parameters.

[0103] Timing optimization of integrated circuits can be performed separately in the logic design and physical design phases. In the logic design phase, the main optimization objective is to reduce the number of logic levels in critical timing paths. In the physical design phase, the main optimization objectives are to adjust the physical distance between target registers and the consumption of placement and routing resources. Furthermore, for the aforementioned double-loop paths, the clock bifurcation positions of the double-loop paths can be adjusted while ensuring logical equivalence. Further optimization can be performed on a specific register within the target registers to adjust the overall timing characteristics of the integrated circuit in a point-to-surface manner. Specific timing optimization measures will be elaborated in subsequent embodiments and will not be detailed here.

[0104] It is understandable that in practical applications, the scale of integrated circuits is constantly expanding, and the number of target registers obtained by the aforementioned method may still be large, resulting in significant pressure for timing optimization. Therefore, this application further provides a preferred implementation method: configuring a preset parameter threshold for the target parameters. After extracting the target parameters corresponding to each target register, the magnitude of the obtained target parameters is compared with the preset parameter threshold. Target registers whose target parameters are greater than the preset parameter threshold are identified as critical registers, and the timing paths to which the critical registers belong are adjusted. Thus, by setting a preset parameter threshold, some registers in the target registers can be excluded, and timing optimization can be performed only on the critical registers, thereby effectively reducing the number of registers and corresponding timing paths, and further improving timing optimization efficiency. Of course, in practical applications, the specific value of the preset parameter threshold will vary depending on the specific target parameters selected. The specific value of the preset parameter threshold can be determined by referring to factors such as the statistical results of the target parameters, the number of target registers, and the requirements for timing optimization efficiency. This application does not limit the specific value of the preset parameter threshold.

[0105] In summary, in integrated circuits, if there is a timing path between any two registers in a set, it indicates that the timing units and logic units in the corresponding circuit structure are coupled together, making timing violations highly likely. Furthermore, the more registers in the set, the greater the probability and severity of timing violations, and the more likely congestion will occur during the placement and routing phase. Compared to related technologies that optimize the timing of the entire integrated circuit, this application optimizes the timing paths of target registers within the target register set. This not only significantly reduces the number of registers, thereby reducing the overall workload of the optimization design, but also, since the optimization process is focused on target registers prone to timing violations, the optimization effect is more significant. The timing characteristics of the integrated circuit are more likely to meet design requirements, thus improving the overall timing optimization efficiency and shortening the integrated circuit design cycle.

[0106] Furthermore, in related technologies, the complete design cycle of an integrated circuit can be divided into logic design and physical design. Logic design involves writing the corresponding logic code according to the application scenario, function, and related performance requirements of the integrated circuit, following relevant protocol standards. Physical design, on the other hand, converts the logic code from the logic design stage into gate circuits and, according to process requirements, completes the placement and routing of a large number of logic units on the silicon wafer. After feasibility verification, the wafer is fabricated and delivered to the process manufacturer for chip production.

[0107] In the current integrated circuit design flow, there is a clear separation between logic design and physical design: the logic design phase focuses primarily on functional implementation, while timing violations often only become apparent during the physical design phase (such as after placement and routing) through static timing analysis. However, with the increasing volume of logic code data, the iteration time in the physical design phase of VLSI is becoming increasingly longer. If timing violations and logic code quality issues are only discovered late in the physical design process, not only will timing optimization be required, but it may also lead to a complete overhaul of the logic code, consuming significant resources and potentially introducing new design risks due to repeated modifications.

[0108] To address the aforementioned issues, this application provides another integrated circuit timing optimization method, which not only improves timing optimization efficiency but also identifies logic code quality problems earlier, providing a reference for logic code modification.

[0109] For details, see Figure 4 As shown, the integrated circuit timing optimization method provided in this embodiment includes the following steps.

[0110] S200. After completing the logic synthesis of the integrated circuit, obtain the gate netlist of the integrated circuit and extract all registers in the gate netlist.

[0111] After the logic design phase of an integrated circuit is completed, the logic code provided in the logic design phase needs to be further synthesized. This process involves various operations in practical applications, which will not be detailed here. For specific implementation details, please refer to relevant technical implementations. After logic synthesis, the gate netlist of the integrated circuit is obtained. The gate netlist records a great deal of information related to the integrated circuit, such as the logic gate type and instantiation, the connection relationships between logic cells, timing constraints, power consumption information, and, of course, testability design circuitry, such as scan chain information. Based on the gate netlist, all registers in the integrated circuit can be extracted. The specific process of extracting registers can be implemented by editing corresponding scripts. This application does not limit the specific process of extracting all registers from the gate netlist.

[0112] S210. Determine the target register set based on integrated circuit registers.

[0113] In an alternative implementation, S210 may refer to Figure 1 The implementation of S110 in the illustrated embodiment will not be repeated here.

[0114] It should be noted that, as mentioned earlier, the existence of the target register set has a direct and significant impact on the timing performance of integrated circuits. Based on this, the presence or absence of a target register set in an integrated circuit can also serve as a preliminary evaluation indicator of the timing performance of the integrated circuit, and can also be used as a standard for detecting the quality of the integrated circuit's logic code. Specifically, if the corresponding target register set can be determined in this step, that is, if the target register set exists in the integrated circuit, it can be determined that there is room for further optimization of the logic code quality of the integrated circuit. Conversely, if the target register set is not determined in this step, it can be preliminarily determined that the possibility of timing problems caused by the target registers in the integrated circuit is low, and the possibility of such problems in the logic code quality is also low.

[0115] 220. Calculate the target parameters related to timing performance on the timing path to which each target register belongs.

[0116] As mentioned earlier, when optimizing the timing of integrated circuits during the logic design phase, the main optimization objective is to reduce the number of logic levels in the timing path. Therefore, the target parameters related to timing performance that need to be statistically analyzed in this embodiment can be the number of logic levels or the number of logic operation units. These logic operation units can be AND gates, OR gates, XOR gates, etc., which will not be detailed here. Of course, other target parameters that can be used for timing optimization during the logic design phase can also be statistically analyzed; these will not be listed here, and as long as they do not exceed the core idea of ​​this application, they also fall within the scope of protection of this application.

[0117] It is understandable that the same logical function can be implemented by different logical operation units. The number of logical operation units required by different implementation methods is different. By determining the number of logical operation units, the actual usage of the logical operation units can be determined. Thus, under the premise of keeping the logical function unchanged (i.e., logical equivalence), the specific implementation of the corresponding timing path can be changed by adjusting or replacing the logical operation units, thereby achieving the purpose of timing optimization.

[0118] For other related implementation methods of S220, please refer to Figure 1 The details of S120 in the illustrated embodiment will not be repeated here.

[0119] S230. Adjust the timing path of each target register based on the target parameters.

[0120] Based on the statistical results of S220, the timing paths of each target register are adjusted. When the target parameter is the number of logic levels, this means adjusting the number of logic levels in the timing paths of the target registers. For example, logic decoupling can be performed, moving identical logic functions along each timing path one stack forward or backward to reduce the number of logic levels in the target register's path. Another example is adding stations, which involves breaking the connections between some target registers in the target register set, while ensuring logical equivalence. Similarly, when the target parameter is the number of logic operation units (LOUs), the selection of LEUs and the implementation of specific logic functions are adjusted or changed, provided that logical equivalence is maintained. Of course, it is also feasible to adjust both the number of logic levels and the number of LEUs simultaneously.

[0121] Furthermore, when selecting key registers based on target registers, the same optimization measures can be applied to the key registers. The specific implementations of the logic decoupling and station addition methods mentioned in the aforementioned optimization measures can be found in relevant technologies and will not be detailed here.

[0122] For other related implementation methods of S230, please refer to Figure 1 The details of S130 in the illustrated embodiment will not be repeated here.

[0123] In summary, while effectively improving timing optimization efficiency and shortening the integrated circuit design cycle, the method provided in this application, compared to the prior art which performs logic code quality testing after placement and routing, can perform code quality testing immediately after logic synthesis. Therefore, it can complete the logic code quality testing as early as possible, effectively avoiding the discovery of logic code anomalies only after the completion of the entire physical design, and helping to further improve the design efficiency of integrated circuits.

[0124] Understandably, if the logic code of an integrated circuit is already determined, or if it is difficult to modify the logic code for other reasons, then the timing performance of the integrated circuit can only be optimized during the physical design phase. The integrated circuit timing optimization method provided in this application can also be applied to the physical design phase. Specifically, refer to... Figure 5 As shown in the figure, another integrated circuit timing optimization method provided in this embodiment specifically includes the following steps.

[0125] S300. After completing the static timing analysis of the integrated circuit, extract all registers of the integrated circuit or extract the registers in the integrated circuit that have timing violations.

[0126] According to the integrated circuit design rules in related technologies, after obtaining the gate netlist through logic synthesis, the physical design process, including placement and routing and static timing analysis, can be performed based on the gate netlist. The timing optimization method provided in this embodiment extracts all registers of the integrated circuit after static timing analysis. Alternatively, if the integrated circuit has too many registers or if it is desirable to improve optimization efficiency, only registers with timing violations can be extracted. In other words, the timing optimization method provided in this application can not only perform timing optimization for the entire integrated circuit but also for specific circuits with timing violations.

[0127] Static Timing Analysis (STA) is an input-independent timing verification technique that aims to find the worst-case delay of sequential logic circuits by traversing all timing paths and checking whether setup and hold times meet requirements. This analysis method primarily determines whether a design can operate at the required frequency by analyzing the maximum and minimum sequential logic path delays. This approach is very convenient, especially in large integrated circuits, as it significantly reduces simulation workload and time costs. STA, combined with formal verification, ensures the timing correctness of digital systems. The main purpose of STA is to increase the system's operating frequency and stability by reducing metastability and optimizing the synthesis, mapping, placement, and routing of control logic to decrease logic and routing delays, thereby increasing the operating frequency.

[0128] More importantly, STA analysis can traverse every timing path in an integrated circuit. Therefore, as an optional implementation, one can first obtain the timing constraint file of the integrated circuit and the gate netlist after logic synthesis. Based on the timing constraint file, static timing analysis can be performed on the gate netlist of the integrated circuit to obtain the corresponding analysis results. Finally, the start register and end register corresponding to each timing path in the integrated circuit can be extracted from the obtained analysis results. As for the specific execution process of static timing analysis, it can be implemented with reference to relevant technologies, and will not be detailed here.

[0129] S310, Determine the target register set based on integrated circuit registers.

[0130] In one alternative implementation, the specific implementation of S310 can be referred to Figure 1 The details of S110 in the illustrated embodiment will not be repeated here.

[0131] S320: Calculate the target parameters related to timing performance on the timing path to which each target register belongs.

[0132] During the physical design phase, there are multiple target parameters related to the timing performance of the timing path to which the target register belongs, such as the number of logic levels, timing check values, and path length. The timing check value can be a timing violation value or other similar parameters. Of course, the target parameters can also include other parameters related to the timing performance of the timing path, which will not be detailed here. In practical applications, one or more of the aforementioned target parameters can be selected for statistical analysis, and the specific parameters can be determined based on the actual optimization requirements.

[0133] For the specific statistical process of the target parameters, please refer to... Figure 1 The implementation of S120 in the illustrated embodiment will not be repeated here.

[0134] S330: Adjust the timing path of each target register based on the target parameters.

[0135] During the physical design phase, there are several ways to adjust the timing performance of the timing path to which the target register belongs. In one optional implementation, the physical distance of the timing path to which the target register belongs can be adjusted, or the clock bifurcation position of the timing path to which the target register belongs can be adjusted. For example, the starting and ending registers of a double loop path can be controlled to bifurcate as late as possible. Of course, both the physical distance and the clock bifurcation position of the timing path to which the target register belongs can be adjusted simultaneously. The specific adjustment process can be found in relevant technical implementations and will not be detailed here. Furthermore, when selecting critical registers based on the target register, the above optimization measures can also be applied to the critical registers, which will also not be detailed here.

[0136] In another alternative implementation, during the physical design phase, this application designates the key registers with the largest target parameters among the key registers as high-priority registers and prioritizes the placement and routing resources of these high-priority registers. If the target parameters are statistically analyzed using an orthogonal table, the high-priority registers are those located in the upper left corner of the orthogonal table. Based on this, when different target parameters are selected, optimization can be performed on the corresponding extreme value data, such as maximum path delay, maximum logic level, and farthest path distance. Optimization is then carried out around the high-priority registers, including but not limited to the following processing measures:

[0137] The high-priority register is the center, and other registers are laid out and routed around it.

[0138] Analyze the pre-stage inputs and post-stage outputs on the timing path of the high-priority register, and divide the associated registers into two groups: one group consists of registers not in the target register set, and the other group consists of registers in the target register set. For the target registers that are in the target register set and connected to the high-priority register, the timing path between them is processed separately, and the layout position is moved closer to the high-priority register or the driver unit with better driving performance is replaced.

[0139] When the target parameter is line delay, for the high-priority register with the largest line delay, the registers connected to the high-priority register are divided into two categories as described above: one group consists of registers not in the target register set, and the other group consists of registers in the target register set. For the target register that is in the target register set and connected to the high-priority register, the priority of the routing resources between it and the high-priority register is increased, for example, routing at a higher level, in order to reduce line delay and other performance issues.

[0140] Of course, other timing optimization measures that can be applied in the physical design phase can also be adopted, which will not be detailed here.

[0141] In summary, in addition to effectively improving timing optimization efficiency and shortening the integrated circuit design cycle, the timing optimization method provided in this embodiment can also optimize the timing performance of integrated circuits during the physical design stage, avoiding changes to the logic code of integrated circuits and other anomalies that may be caused by them, thus helping to further improve the design efficiency of integrated circuits.

[0142] The integrated circuit timing optimization apparatus provided by this invention is described below. This apparatus belongs to the same conceptual framework as the integrated circuit timing optimization method provided in the embodiments of this application. It can execute the integrated circuit timing optimization method provided in any embodiment of this application and possesses the corresponding functional modules and beneficial effects for executing the integrated circuit timing optimization method. Technical details not described in detail in this embodiment can be found in the integrated circuit timing optimization method provided in the embodiments of this application, and will not be repeated here.

[0143] See Figure 6 The integrated circuit timing optimization device provided in this application includes an extraction unit 10, a determination unit 20, a statistics unit 30, and an optimization unit 40.

[0144] Extraction unit 10 is used to extract the registers of the integrated circuit;

[0145] The determining unit 20 is used to determine a target register set based on the registers of the integrated circuit. The target register set includes at least two target registers, and there is a timing path between any two target registers.

[0146] The statistics unit 30 is used to count the target parameters related to timing performance on the timing path to which each target register belongs;

[0147] The optimization unit 40 is used to adjust the timing path of each target register based on the target parameters.

[0148] Below, for reference Figure 7 The electronic device provided in this embodiment of the invention may include: at least one processor 100, at least one communication interface 200, at least one memory 300, and at least one communication bus 400.

[0149] In this embodiment of the invention, the number of processor 100, communication interface 200, memory 300, and communication bus 400 is at least one, and the processor 100, communication interface 200, and memory 300 communicate with each other through communication bus 400; obviously, Figure 7 The communication connections shown for the processor 100, communication interface 200, memory 300, and communication bus 400 are optional.

[0150] Optionally, the communication interface 200 can be an interface of a communication module, such as the interface of a GSM module; the processor 100 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0151] The memory 300 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0152] Specifically, the processor 100 is used to execute the application program in the memory to implement the steps of the integrated circuit timing optimization method described above.

[0153] In some embodiments, this embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more instructions implementing the above steps are stored. When these one or more instructions are executed by one or more processors, the processors perform the integrated circuit timing optimization method described above. For specific implementation details, please refer to the foregoing description; further elaboration is not provided here.

[0154] In addition to the methods and apparatus described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the integrated circuit timing optimization methods according to various embodiments of this application as described above.

[0155] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0156] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0157] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0158] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0159] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0160] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0161] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A timing optimization method for integrated circuits, characterized in that, include: Extract the registers of the integrated circuit; A target register set is determined based on the registers of the integrated circuit, the target register set including at least two target registers, and a timing path exists between any two target registers; Collect the target parameters related to timing performance on the timing path to which each target register belongs; Adjust the timing path of each target register based on the target parameters.

2. The method according to claim 1, characterized in that, Determining the target register set based on the registers of the integrated circuit includes: The registers of the integrated circuit are divided into multiple register groups by taking any two registers as a group, and a target register group is identified in the multiple register groups, wherein there is a timing path between the two registers in the target register group; The target register set is determined based on the target register group.

3. The method according to claim 2, characterized in that, The step of dividing the registers of the integrated circuit into multiple register groups by grouping any two registers together and identifying the target register group among the multiple register groups includes: Create an orthogonal table, wherein the row and column cells of the orthogonal table are the registers of the integrated circuit; The registers of the integrated circuit are divided into multiple register groups by taking any orthogonal combination of row units and column units as a register group; If there is a timing path between two registers in any of the aforementioned register groups, the register group is determined as the target register group and the orthogonality value is marked as the first value. If there is no timing path between two registers in any of the register groups, the orthogonality value corresponding to that register group is marked as the second value.

4. The method according to claim 3, characterized in that, Determining the target register set based on the target register group includes: Adjust the positions of the cells in each row of the orthogonal table according to the order of the number of the first value in the same row from most to least; Adjust the positions of the cells in each column of the orthogonal table according to the order of the number of the first value in the same column from most to least; The set of registers corresponding to the target rectangular sub-table within the orthogonal table is taken as the target register set, and each orthogonal value within the target rectangular sub-table is a first value.

5. The method according to claim 2, characterized in that, The process of identifying the target register set includes: If path detection and timing detection are configured between two registers in any of the aforementioned register groups, then the register group is determined to be the target register group. If no path detection is configured between two registers in any of the aforementioned register groups, or if no timing detection is configured, then the register group is determined to be a non-target register group.

6. The method according to claim 1, characterized in that, The target parameters related to timing performance on the timing path to which each target register belongs are statistically analyzed, including: Identify the key timing paths in the timing paths to which each of the target registers belongs, wherein the key timing paths start with one of the target registers and end with the other target register; Statistically analyze the target parameters related to timing performance on the key timing path.

7. The method according to claim 1, characterized in that, Adjusting the timing path of each target register based on the target parameters includes: The target registers whose target parameters are greater than a preset parameter threshold are identified as critical registers. Adjust the timing path to which the critical register belongs.

8. The method according to claim 7, characterized in that, During the logic design phase, the target parameters include the number of logic levels or the number of logic operation units.

9. The method according to claim 8, characterized in that, Adjusting the timing path to which the critical register belongs includes: Adjust the number of logic levels or logic operation units in the timing path to which the key register belongs.

10. The method according to claim 8, characterized in that, The extraction of the integrated circuit registers includes: After completing the logic synthesis of the integrated circuit, the gate netlist of the integrated circuit is obtained; Extract all registers from the gate netlist.

11. The method according to claim 7, characterized in that, Adjusting the timing path to which the critical register belongs includes: During the physical design phase, the physical distance of the timing path to which the critical register belongs is adjusted, and / or the clock bifurcation position of the timing path to which the critical register belongs is adjusted.

12. The method according to claim 7, characterized in that, Adjusting the timing path to which the critical register belongs includes: During the physical design phase, the key registers with the largest target parameters among the key registers are identified as high-priority registers. Prioritize the placement and routing resources of the high-priority registers.

13. The method according to claim 11 or 12, characterized in that, The extraction of the integrated circuit registers includes: After completing static timing analysis of the integrated circuit, extract all registers of the integrated circuit or extract the registers in the integrated circuit that have timing violations.

14. An integrated circuit timing optimization device, characterized in that, include: Extraction unit, used to extract the registers of the integrated circuit; A determining unit is configured to determine a target register set based on the registers of the integrated circuit, the target register set including at least two target registers, and a timing path existing between any two of the target registers; The statistics unit is used to count the target parameters related to timing performance on the timing path to which each of the target registers belongs; An optimization unit is used to adjust the timing path to which each of the target registers belongs based on the target parameters.

15. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, characterized in that, When the processor executes the computer program, it implements the steps of the integrated circuit timing optimization method as described in any one of claims 1 to 13.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the integrated circuit timing optimization method as described in any one of claims 1 to 13.

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