Digital back-end noise interference reduction winding method, device, equipment and medium

Abstract

The application provides a wire winding method, device, equipment and medium for reducing noise interference in a digital back end, the method comprising: obtaining coordinate information of a first port and a second port to determine a wire winding area; analyzing a plurality of sub-areas in the wire winding area based on a pre-set scanning mode to create layout blocking according to device density and create wire winding blocking according to wire winding congestion; obtaining physical information of existing devices in the wire winding area and creating device layout blocking based on the physical information; inserting at least one buffer unit between the first port and the second port in an area avoiding the layout blocking and the device layout blocking; and connecting the first port, the buffer unit and the second port by wire winding in an area avoiding the wire winding blocking to form a final connection path. In this way, the buffer unit is less affected by noise interference from surrounding devices, the wire winding is less affected by noise from other intersecting wire windings, and the performance index of the chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit wiring technology, and in particular to a digital back-end noise interference reduction winding method, device, equipment and medium. BACKGROUND

[0002] Winding technology is essential in the manufacture of integrated circuits. Winding technology is usually good for short distance winding, but for winding with long physical distance, complex physical environment and high delay requirement, related technology is difficult to control, which will cause the buffer unit to be disturbed by the noise of surrounding devices, the winding to be affected by the noise of surrounding other cross winding, and the system delay to not meet the design requirements, so that the chip is difficult to achieve better performance indicators, and even leads to chip design failure. SUMMARY

[0003] Therefore, the purpose of the present application is to provide a digital back-end noise interference reduction winding method, device, equipment and medium, which can reduce the noise interference of the buffer unit, reduce the influence of the winding on the surrounding other cross winding noise, and improve the performance indicators of the chip.

[0004] In a first aspect, an embodiment of the present application provides a digital back-end noise interference reduction winding method, which comprises: obtaining coordinate information of a first port and a second port to determine a winding area; analyzing a plurality of sub-areas in the winding area based on a pre-set scanning mode to create layout barriers according to device density and winding barriers according to winding congestion; obtaining physical information of existing devices in the winding area and creating device layout barriers based on the physical information; inserting at least one buffer unit between the first port and the second port in a region avoiding the layout barriers and the device layout barriers; and connecting the first port, the buffer unit and the second port by winding in a region avoiding the winding barriers to form a final connection path.

[0005] In a preferred embodiment of the present application, the above-mentioned analysis of a plurality of sub-areas based on a pre-set scanning mode comprises: moving from the first port to the second port with a window of a pre-set size and a pre-set step length, and successively analyzing the sub-area covered by the window.

[0006] In a preferred embodiment of the present application, the above-mentioned creation of layout barriers according to device density comprises: determining the device density value in each sub-area; comparing the device density value with a pre-set density threshold value; and creating a layout barrier in the corresponding sub-area if the device density value is greater than the density threshold value.

[0007] In the preferred embodiment of the present application, the creation of the routing blockage according to the routing congestion includes: determining a horizontal routing congestion value and a vertical routing congestion value in each sub-region; comparing the horizontal routing congestion value and the vertical routing congestion value with a pre-set congestion threshold value respectively; and creating a routing blockage in the corresponding sub-region if the horizontal routing congestion value or the vertical routing congestion value is greater than the congestion threshold value.

[0008] In the preferred embodiment of the present application, the creation of the device layout blockage based on the physical information includes: identifying the boundary size of each existing device in the routing region; and generating a corresponding device layout blockage region based on the boundary size of each existing device.

[0009] In the preferred embodiment of the present application, the insertion of the at least one buffer unit between the first port and the second port includes: selecting an initial placement position for the buffer unit; determining whether the initial placement position overlaps with the layout blockage or the device layout blockage; and reselecting the placement position until the placement position does not overlap with the layout blockage or the device layout blockage if the initial placement position overlaps with the layout blockage or the device layout blockage.

[0010] In the preferred embodiment of the present application, the method further includes: connecting the first port, the buffer unit and the second port by routing to form a final connection path, including: planning a preliminary routing path from the first port to the second port through the buffer unit; determining whether the preliminary routing path passes through the routing blockage; and adjusting the routing path to avoid all the routing blockages to form the final connection path if the preliminary routing path passes through the routing blockage.

[0011] In the second aspect, the embodiments of the present application further provide a routing device for reducing noise interference in a digital back end, including: a routing region determination module configured to obtain coordinate information of a first port and a second port to determine a routing region; a sub-region analysis module configured to analyze a plurality of sub-regions in the routing region based on a pre-set scanning mode to create a layout blockage according to device density and create a routing blockage according to routing congestion; a device layout blockage creation module configured to obtain physical information of existing devices in the routing region and create a device layout blockage based on the physical information; a buffer unit insertion module configured to insert at least one buffer unit between the first port and the second port in a region avoiding the layout blockage and the device layout blockage; and a connection path formation module configured to connect the first port, the buffer unit and the second port by routing in a region avoiding the routing blockage to form a final connection path.

[0012] In the third aspect, the embodiments of the present application further provide an electronic device including a processor and a memory, the memory storing computer executable instructions capable of being executed by the processor, and the processor executes the computer executable instructions to implement the digital back end routing method for reducing noise interference in the first aspect.

[0013] In a fourth aspect, the embodiments of the present application further provide a computer readable storage medium, which stores computer executable instructions. When the computer executable instructions are invoked and executed by a processor, the computer executable instructions cause the processor to implement the wire winding method for reducing noise interference in a digital back end of the first aspect.

[0014] The embodiments of the present application bring the following beneficial effects:

[0015] The embodiments of the present application provide a wire winding method for reducing noise interference in a digital back end, an apparatus, a device and a medium. The coordinate information of a first port and a second port is obtained to determine a wire winding area. In the wire winding area, a plurality of sub-areas are analyzed based on a pre-set scanning mode to create a layout block according to a device density and create a wire winding block according to a wire winding congestion. The physical information of an existing device in the wire winding area is obtained, and a device layout block is created based on the physical information. In the area avoiding the layout block and the device layout block, at least one buffer unit is inserted between the first port and the second port. In the area avoiding the wire winding block, the first port, the buffer unit and the second port are connected by wire winding to form a final connection path. In this way, the buffer unit is less affected by the noise interference of surrounding devices, the wire winding is less affected by the noise of surrounding other cross-wire windings, and the performance index of the chip is improved.

[0016] Other features and advantages of the present disclosure will be described in the following description, or can be learned from the description, or can be determined without doubt, or can be known by implementing the above-mentioned technologies of the present disclosure.

[0017] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can also obtain other drawings without creative labor based on these drawings.

[0019] Figure 1 A flowchart of a wire winding method for reducing noise interference in a digital back end provided by the embodiments of the present application is shown in the figure;

[0020] Figure 2 A flowchart of another wire winding method for reducing noise interference in a digital back end provided by the embodiments of the present application is shown in the figure;

[0021] Figure 3 A winding mode schematic diagram provided for an embodiment of the present application;

[0022] Figure 4 Another winding mode schematic diagram provided for an embodiment of the present application;

[0023] Figure 5 A structure schematic diagram of a winding device for reducing noise interference of a digital back end provided for an embodiment of the present application;

[0024] Figure 6 A structure schematic diagram of an electronic device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0025] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0026] Winding technology is essential in the manufacture of integrated circuits. Winding technology is usually good for short-distance winding, but for winding with a long physical distance, a complex physical environment and a high delay requirement, the related technology is difficult to control, which can cause the buffer unit to be disturbed by the noise of surrounding devices, the winding to be affected by the noise of other crossing windings, and the system delay to not meet the design requirement, so that the chip is difficult to achieve better performance indicators, and even leads to the failure of chip design.

[0027] Based on this, the winding method, device, equipment and medium for reducing noise interference of a digital back end provided by the embodiments of the present application can determine the winding area by obtaining the coordinate information of the first port and the second port. In the winding area, a plurality of sub-areas are analyzed based on a pre-set scanning mode to create a layout block according to the device density and create a winding block according to the winding congestion. The physical information of the existing devices in the winding area is obtained, and the device layout block is created based on the physical information. In the area avoiding the layout block and the device layout block, at least one buffer unit is inserted between the first port and the second port. In the area avoiding the winding block, the first port, the buffer unit and the second port are connected by winding to form a final connection path. In this way, the buffer unit is less disturbed by the noise of surrounding devices, the winding is less affected by the noise of other crossing windings, and the performance indicators of the chip are improved.

[0028] For the convenience of understanding the present embodiment, first of all, a digital back-end noise interference reduction winding method disclosed by the present embodiment is introduced in detail.

[0029] Embodiment 1

[0030] The present embodiment provides a digital back-end noise interference reduction winding method, Figure 1 A flow chart of the digital back-end noise interference reduction winding method provided by the present embodiment is shown in FIG. 1. Figure 1 As shown in the figure, the digital back-end noise interference reduction winding method can include the following steps:

[0031] Step S101, coordinate information of a first port and a second port is obtained to determine a winding area.

[0032] The first port and the second port are pre-specified ports that need to be connected and wound, and the first port and the second port have their own coordinate information. Through the coordinate information, the area between the two ports, i.e. the winding area, can be obtained.

[0033] Step S102, in the winding area, a plurality of sub-areas are analyzed based on a pre-set scanning mode to create a layout block according to the device density, and a winding block is created according to the winding congestion.

[0034] The window of the preset size and the preset step length are used to move from the first port to the second port, and the sub-areas covered by the window are analyzed one by one.

[0035] Step S103, physical information of the existing devices in the winding area is obtained, and a device layout block is created based on the physical information.

[0036] The physical information can include the boundary size.

[0037] Specifically, creating a device layout block based on physical information can include: identifying the boundary size of each existing device in the winding area; and generating a corresponding device layout block area based on the boundary size of each existing device.

[0038] Step S104, at least one buffer unit is inserted between the first port and the second port in the area avoiding the layout block and the device layout block.

[0039] Specifically, inserting at least one buffer unit between the first port and the second port can include: selecting an initial placement position for the buffer unit; determining whether the initial placement position overlaps with the layout block or the device layout block; and if the initial placement position overlaps with the layout block or the device layout block, reselecting the placement position until the placement position does not overlap with the layout block or the device layout block.

[0040] Step S105, in the area avoiding the wire blocking, connecting the first port, the buffer unit and the second port by wire to form the final connection path.

[0041] Specifically, connecting the first port, the buffer unit and the second port by wire to form the final connection path can include: planning a preliminary wire path from the first port to the second port through the buffer unit; determining whether the preliminary wire path passes through the wire blocking; if the preliminary wire path passes through the wire blocking, adjusting the wire path to avoid all wire blockings to form the final connection path.

[0042] The wire method for reducing noise interference of the digital back end provided by the embodiment of the application can determine the wire area by obtaining the coordinate information of the first port and the second port. In the wire area, a plurality of sub-areas are analyzed based on a pre-set scanning mode to create layout blockings according to device density and wire blockings according to wire congestion. The physical information of the existing devices in the wire area is obtained, and device layout blockings are created based on the physical information. In the area avoiding the layout blockings and the device layout blockings, at least one buffer unit is inserted between the first port and the second port. In the area avoiding the wire blockings, the first port, the buffer unit and the second port are connected by wire to form the final connection path. In this way, the buffer unit is less affected by the noise interference of the surrounding devices, the wire is less affected by the noise of the surrounding other crossing wires, and the performance index of the chip is improved.

[0043] Embodiment 2

[0044] The embodiment of the application also provides another wire method for reducing noise interference of the digital back end; the method is implemented on the basis of the method of the above-mentioned embodiment; the method focuses on describing the specific implementation mode of analyzing a plurality of sub-areas based on a pre-set scanning mode to create layout blockings according to device density and wire blockings according to wire congestion.

[0045] Figure 2 The flowchart of another wire method for reducing noise interference of the digital back end provided by the embodiment of the application is shown in Figure 2 The analysis of a plurality of sub-areas based on a pre-set scanning mode to create layout blockings according to device density and wire blockings according to wire congestion can include the following steps:

[0046] Step S201, starting from the first port, moving to the second port with a window of a pre-set size and a pre-set step length, and successively analyzing the sub-area covered by the window.

[0047] Specifically, the analysis on the plurality of sub-regions based on the preset scanning mode can include: starting from a first port, moving to a second port with a preset size window and a preset step length, and successively analyzing the sub-regions covered by the window.

[0048] The preset size can be 10um*10um, the preset step length can be 10um, and the moving from the first port to the second port can be a stepwise lateral displacement of 10um and a stepwise longitudinal displacement of 10um between the first port and the second port.

[0049] Step S202, determine the device density value in each sub-region.

[0050] The device density value can be determined by the following formula: device density value=(single device area*device number) / (10um*10um).

[0051] Step S203, compare the device density value with a preset density threshold value.

[0052] The density threshold value can be 30%.

[0053] Step S204, if the device density value is greater than the density threshold value, create a layout block in the corresponding sub-region.

[0054] When the device density value is greater than 30%, a layout block is created in the corresponding sub-region, and the sub-region can be understood as a window.

[0055] Step S205, determine the lateral wire congestion value and the longitudinal wire congestion value in each sub-region.

[0056] The grid point spacing value of each layer of metal is obtained, and the grid point spacing values of the layers of metal are the same, and the number of lateral wires and longitudinal wires is the same, and the lateral wire congestion value is determined by the following formula: lateral wire congestion value=(device port number*device number)*grid point spacing value / (2*10um*metal layer number); and the longitudinal wire congestion value is determined by the following formula: longitudinal wire congestion=(device port number*device number)*grid point spacing value / (2*10um*metal layer number.

[0057] Step S206, compare the lateral wire congestion value and the longitudinal wire congestion value with a preset congestion threshold value, respectively.

[0058] The congestion threshold value can be 30%.

[0059] Step S207, if the lateral wire congestion value or the longitudinal wire congestion value is greater than the congestion threshold value, create a wire block in the corresponding sub-region.

[0060] When the lateral wire congestion value or the longitudinal wire congestion value is greater than 30%, a wire blocking is created in the corresponding sub-area, which can be understood as a window.

[0061] Further, when a window creates both a layout blocking and a wire blocking, it is called a mixed blocking.

[0062] As an embodiment of the present application, Figure 3 A wire layout provided by an embodiment of the present application is shown in FIG. 1, which includes two ports, four buffer units, one layout blocking area, two wire blocking areas, and nine mixed blocking areas. Figure 3 As shown in FIG. 1, the wire layout includes two ports, four buffer units, one layout blocking area, two wire blocking areas, and nine mixed blocking areas. The two ports include a first port 11 and a second port 12. The four buffer units include a first buffer 21, a second buffer 22, a third buffer 23, and a fourth buffer 24. The wire includes a first wire 41, a second wire 42, a third wire 43, a fourth wire 44, and a fifth wire 45. The first buffer 21, the second buffer 22, the third buffer 23, and the fourth buffer 24 are arranged between the first port 11 and the second port 12, and are away from the layout blocking area and the mixed blocking area. The first port 11 is connected to the first buffer 21 through the first wire 41. The first buffer 21 is connected to the second buffer 22 through the second wire 42. The second buffer 22 is connected to the third buffer 23 through the third wire 43. The second buffer 22 is connected to the third buffer 23 through the fourth wire 44. The fourth buffer 24 is connected to the second port 12 through the fifth wire 45. The wires are away from the wire blocking area and the mixed blocking area.

[0063] The coordinates of the first port 11 are (10, 60). The coordinates of the second port 12 are (60, 10). The coordinates of the first buffer 21 are (25, 55). The coordinates of the second buffer 22 are (25, 35). The coordinates of the third buffer 23 are (35, 25). The coordinates of the fourth buffer 24 are (45, 15).

[0064] As an embodiment of the present application, Figure 4 Another wire layout provided by an embodiment of the present application is shown in FIG. 2, which includes two ports, four buffer units, one layout blocking area, two wire blocking areas, and nine mixed blocking areas. Figure 4As shown, the layout blocking window is represented by a right diagonal line (\), the routing blocking window is represented by a left diagonal line ( / ), and the mixed blocking window is represented by a cross line (x). The module 25 is an original device between two ports, and a module layout blocking needs to be created according to the coordinates of the module 25. The top-right vertex coordinate of the module 25 is (25, 35), and the center point coordinate of the second buffer 22 is the coordinate of the second buffer 22, that is, (25, 35). The range of the second buffer 22 overlaps the range of the module 25, so the second buffer 22 needs to avoid the module layout blocking of the range where the module 25 is located. At this time, the coordinate of the second buffer 22 is (35, 25). After the second buffer 22 is moved, the second buffer 22 is connected to the first buffer 21 through the sixth routing 46 and connected to the third buffer 23 through the seventh routing 47.

[0065] Embodiment 3

[0066] Corresponding to the above method embodiment, the embodiment of the application provides a routing device for reducing noise interference of a digital back end, Figure 5 A structure diagram of the routing device for reducing noise interference of the digital back end provided by the embodiment of the application is shown in the figure. Figure 5 As shown, the routing device for reducing noise interference of the digital back end can include:

[0067] The routing area determination module 301 is configured to obtain coordinate information of the first port and the second port to determine a routing area.

[0068] The sub-area analysis module 302 is configured to analyze a plurality of sub-areas in the routing area based on a pre-set scanning mode to create a layout blocking according to device density and create a routing blocking according to routing congestion.

[0069] The device layout blocking creation module 303 is configured to obtain physical information of an existing device in the routing area and create a device layout blocking based on the physical information.

[0070] The buffer unit insertion module 304 is configured to insert at least one buffer unit between the first port and the second port in a region avoiding the layout blocking and the device layout blocking.

[0071] The connection path forming module 305 is configured to connect the first port, the buffer unit and the second port through routing in a region avoiding the routing blocking to form a final connection path.

[0072] The wire winding device for reducing noise interference of the digital back end provided by the embodiment of the present application can determine a wire winding area by obtaining coordinate information of the first port and the second port. In the wire winding area, a plurality of sub-areas are analyzed based on a preset scanning mode to create layout blocks according to device density and create wire winding blocks according to wire winding congestion. Physical information of existing devices in the wire winding area is obtained, and device layout blocks are created based on the physical information. In the area avoiding the layout blocks and the device layout blocks, at least one buffer unit is inserted between the first port and the second port. In the area avoiding the wire winding blocks, the first port, the buffer unit and the second port are connected by wire winding to form a final connection path. In this way, the buffer unit is less affected by noise interference from surrounding devices, the wire winding is less affected by noise from other crossing wire windings, and the performance index of the chip is improved.

[0073] In some embodiments, the sub-area analysis module is further configured to analyze the sub-areas covered by the window in a preset size and a preset step length, starting from the first port and moving towards the second port.

[0074] In some embodiments, the sub-area analysis module is further configured to determine a device density value in each sub-area, compare the device density value with a preset density threshold value, and create a layout block in the corresponding sub-area if the device density value is greater than the density threshold value.

[0075] In some embodiments, the sub-area analysis module is further configured to determine a horizontal wire winding congestion value and a vertical wire winding congestion value in each sub-area, compare the horizontal wire winding congestion value and the vertical wire winding congestion value with a preset congestion threshold value, and create a wire winding block in the corresponding sub-area if the horizontal wire winding congestion value or the vertical wire winding congestion value is greater than the congestion threshold value.

[0076] In some embodiments, the device layout block creation module is further configured to identify a boundary size of each existing device in the wire winding area, and generate a corresponding device layout block area based on the boundary size of each existing device.

[0077] In some embodiments, the buffer unit insertion module is further configured to select an initial placement position for the buffer unit, determine whether the initial placement position overlaps with the layout block or the device layout block, and reselect the placement position until the placement position does not overlap with the layout block or the device layout block if the initial placement position overlaps with the layout block or the device layout block.

[0078] In some embodiments, the connection path formation module is further configured to plan a preliminary wire winding path from the first port to the second port through the buffer unit, determine whether the preliminary wire winding path passes through the wire winding block, and adjust the wire winding path to avoid all wire winding blocks to form a final connection path if the preliminary wire winding path passes through the wire winding block.

[0079] The device provided by the embodiments of the present application has the same implementation principle and generated technical effects as the foregoing method embodiments. For brevity, the part of the device embodiments not mentioned in the foregoing method embodiments can be referred to the corresponding content in the foregoing method embodiments.

[0080] Embodiment 4

[0081] The embodiments of the present application also provide an electronic device for running the winding method for reducing noise interference of the digital back end. Figure 6 As shown in the structural schematic diagram of an electronic device, the electronic device includes a memory 400 and a processor 401, wherein the memory 400 is configured to store one or more computer instructions, and the one or more computer instructions are executed by the processor 401 to implement the winding method for reducing noise interference of the digital back end.

[0082] Further, Figure 6 As shown in the structural schematic diagram of an electronic device, the electronic device further includes a bus 402 and a communication interface 403, and the processor 401, the communication interface 403 and the memory 400 are connected through the bus 402.

[0083] The memory 400 can include a high-speed random access memory (RAM) and can also include a non-volatile memory, for example, at least one disk memory. The communication connection between the system network element and at least one other network element is implemented through at least one communication interface 403 (which can be wired or wireless), and the Internet, a wide area network, a local area network, a metropolitan area network, etc. can be used. The bus 402 can be an ISA bus, a PCI bus or an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For brevity, Figure 6 In the foregoing description, only one bidirectional arrow is used to represent the bus, but it does not mean that there is only one bus or only one type of bus.

[0084] The processor 401 can be an integrated circuit chip having a signal processing capability. In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware in the processor 401 or the instruction in the form of software. The processor 401 described above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. Each method, step and logic block diagram disclosed in the embodiment of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiment of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium in the art. The storage medium is located in the memory 400, and the processor 401 reads the information in the memory 400, and combines the hardware to complete the steps of the method of the above embodiment.

[0085] The embodiment of the present application also provides a computer readable storage medium, the computer readable storage medium stores computer executable instructions, when the computer executable instructions are called and executed by the processor, the computer executable instructions cause the processor to realize the above-mentioned digital back-end noise interference reduction winding method, for specific implementation, please refer to the method embodiment, and here is no more.

[0086] The computer program product provided by the embodiment of the present application for carrying out the winding method of the digital back-end noise interference reduction method includes a computer readable storage medium storing non-volatile program codes executable by the processor. The instructions included in the program code can be used to execute the method described in the foregoing method embodiment, and for specific implementation, please refer to the method embodiment, and here is no more.

[0087] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiment, and here is no more.

[0088] In several embodiments provided by the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. The described device embodiments are merely schematic, and for example, the division of the units is only a logical function division, and there can be another division manner in actual implementation; for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, or the among different units, can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electric, mechanical or other forms.

[0089] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. In actual implementation, some or all of the units can be selected according to the actual needs to achieve the purposes of the embodiments of the present application.

[0090] In addition, each function unit in the various embodiments of the present application can be integrated in one processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in one unit.

[0091] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art, or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, and various media that can store program codes.

[0092] Finally, it should be noted that the above-described embodiments are merely specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, but not to limit the present application, and the protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still make modifications or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features therein, within the technical range disclosed by the present application. The modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A winding method for reducing noise interference in a digital back-end system, characterized in that, The method includes: Obtain the coordinate information of the first and second ports to determine the winding area; Within the winding area, multiple sub-regions are analyzed based on a pre-set scanning method to create layout barriers according to device density and winding barriers according to winding congestion. Obtain the physical information of existing devices within the winding area, and create device layout barriers based on the physical information; In the area that avoids the layout obstruction and device layout obstruction, at least one buffer unit is inserted between the first port and the second port; In the area that avoids the obstruction of the winding, the first port, the buffer unit and the second port are connected by winding to form the final connection path; The first port and the second port are pre-specified ports that need to be connected and wound. The first port and the second port have their own coordinate information. The area between the two ports, i.e. the winding area, is obtained through the coordinate information. The analysis of multiple sub-regions based on a pre-set scanning method includes: Using a window of a preset size and a preset step size, the system moves from the first port to the second port, and analyzes the sub-regions covered by the window one by one. The preset size is 10um×10um, the preset step size is 10um, and the movement from the first port to the second port is achieved by taking a stepwise horizontal displacement of 10um and a vertical displacement of 10um. In the area between the first port and the second port, the movement starts from one port and scans stepwise to the other port. The creation of a winding barrier based on winding congestion includes: Determine the lateral and longitudinal winding congestion values ​​within each sub-region; The lateral winding congestion value and the longitudinal winding congestion value are compared with the preset congestion thresholds respectively; If the lateral winding congestion value or the longitudinal winding congestion value is greater than the congestion threshold, a winding block is created in the corresponding sub-region.

2. The method according to claim 1, characterized in that, The creation of layout barriers based on device density includes: Determine the device density value for each sub-region; The device density value is compared with a preset density threshold. If the device density value is greater than the density threshold, a layout barrier is created in the corresponding sub-region.

3. The method according to claim 1, characterized in that, The creation of device layout barriers based on the physical information includes: Identify the boundary dimensions of each existing device within the winding region; Based on the boundary dimensions of each existing device, a corresponding device layout blocking region is generated.

4. The method according to claim 1, characterized in that, Inserting at least one buffer unit between the first port and the second port includes: Select an initial placement position for the buffer unit; Determine whether the initial placement position overlaps with the layout obstruction or device layout obstruction; If the initial placement position overlaps with the layout barrier or device layout barrier, the placement position is reselected until the placement position does not overlap with the layout barrier or device layout barrier.

5. The method according to claim 1, characterized in that, The step of connecting the first port, the buffer unit, and the second port via a winding to form the final connection path includes: Plan the initial winding path from the first port through the buffer unit to the second port; Determine whether the preliminary winding path passes through the winding obstruction; If the initial winding path passes through the winding obstruction, the winding path is adjusted to avoid all winding obstructions, thus forming the final connection path.

6. A winding device for reducing noise interference in a digital back-end system, characterized in that, The device is used to implement the winding method for reducing noise interference in a digital back-end according to any one of claims 1 to 5, the device comprising: The winding area determination module is used to obtain the coordinate information of the first port and the second port to determine the winding area; The sub-region analysis module is used to analyze multiple sub-regions within the winding area based on a pre-set scanning method, in order to create layout barriers based on device density and winding barriers based on winding congestion. The device layout barrier creation module is used to obtain the physical information of existing devices in the winding area and create device layout barriers based on the physical information. A buffer unit insertion module is used to insert at least one buffer unit between the first port and the second port in an area that avoids the layout obstruction and device layout obstruction. A connection path forming module is used to form a final connection path by connecting the first port, the buffer unit, and the second port by winding in an area that avoids the winding obstruction.

7. An electronic device, characterized in that, It includes a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, the processor executing the computer-executable instructions to implement the winding method for reducing noise interference in a digital back-end according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions that, when invoked and executed by a processor, cause the processor to implement the winding method for reducing noise interference in the digital back-end as described in any one of claims 1 to 5.

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