Defective pixel area detection method, equipment and program product

Abstract

The embodiment of the invention provides a dead pixel area detection method and device and a program product, and the method comprises the steps: predicting the wafer morphology of a plurality of global layout samples with different technological parameters through a dead pixel prediction model, determining a predicted dead pixel area based on the predicted morphology data corresponding to the plurality of global layout samples, and carrying out the detection of the dead pixel area. And carrying out dead pixel verification on the predicted dead pixel region, selecting a dead pixel region sample from the predicted dead pixel region based on a result of the dead pixel verification, training a dead pixel prediction model based on actual morphology data and process parameters of the dead pixel region sample, and carrying out dead pixel prediction on a plurality of local regions of the target wafer through the trained dead pixel prediction model. According to the method, the prediction process parameters corresponding to the actual morphology data of each local area and the wafer morphology of the global layout under the prediction process parameters are predicted, and the defective pixel area is determined based on the wafer morphology corresponding to each local area, so that the tiny process difference existing between different local areas is effectively captured, and the detection precision is higher.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method, device and program product for detecting defective areas. Background Technology

[0002] In the field of semiconductor technology, defect detection is a very important detection method.

[0003] Current methods for detecting defective areas typically involve extracting graphic features related to defective areas from images of the wafer, and then determining the presence of defective areas based on these extracted features.

[0004] However, this current solution only provides a static test result for a single wafer and cannot accurately detect defective areas on the wafer. Summary of the Invention

[0005] This application provides a method, device, and program for detecting defective areas, so as to effectively improve the detection accuracy of defective areas.

[0006] In a first aspect, embodiments of this application provide a method for detecting defective pixel regions, including:

[0007] By using a defect prediction model, the wafer morphology of multiple global layout samples with different process parameters is predicted, and the predicted morphology data corresponding to multiple global layout samples is obtained.

[0008] Based on the predicted topography data corresponding to multiple global map samples, the predicted bad spot regions corresponding to multiple global map samples are determined.

[0009] Bad point verification is performed on the predicted bad point regions corresponding to multiple global map samples, and bad point region samples are selected from the predicted bad point regions corresponding to multiple global map samples based on the results of bad point verification.

[0010] Based on the actual morphology data and process parameters of the defective region samples on the actual wafer, the defective prediction model is trained to learn the mapping relationship between the wafer morphology and the process parameters, and the trained defective prediction model is obtained.

[0011] The trained defect prediction model predicts the actual morphology data of each local region of the target wafer and the corresponding prediction process parameters, as well as the wafer morphology of the global layout of the target wafer under the corresponding prediction process parameters in each local region.

[0012] Based on the wafer morphology corresponding to each local region, the defective areas of the target wafer are determined.

[0013] Secondly, embodiments of this application provide a defective pixel region detection device, comprising:

[0014] The sample morphology prediction module is used to predict the wafer morphology of multiple global layout samples with different process parameters through a bad pixel prediction model, and obtain the predicted morphology data corresponding to multiple global layout samples.

[0015] The sample bad pixel prediction module is used to determine the predicted bad pixel regions corresponding to multiple global map samples based on the predicted topography data corresponding to multiple global map samples.

[0016] The sample bad pixel verification module is used to verify the bad pixels in the predicted bad pixel regions corresponding to multiple global map samples, and select bad pixel region samples from the predicted bad pixel regions corresponding to multiple global map samples based on the bad pixel verification results.

[0017] The model training module is used to train the defect prediction model based on the actual morphology data and process parameters of the defect region samples on the actual wafer, learn the mapping relationship between the wafer morphology and process parameters, and obtain the trained defect prediction model.

[0018] The model prediction module is used to predict the predicted process parameters corresponding to the actual morphology data of each local region of the target wafer through the trained bad pixel prediction model, and to predict the wafer morphology of the global layout of the target wafer under the predicted process parameters corresponding to each local region.

[0019] The defect detection module is used to determine the defect area of ​​the target wafer based on the wafer morphology corresponding to each local region.

[0020] Thirdly, embodiments of this application provide a defective region detection device, which includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor. When the program or instructions are executed by the processor, they implement the steps of the defective region detection method of any embodiment of this application.

[0021] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored. When the program or instructions are executed by a processor, they implement the steps of the bad pixel region detection method of any embodiment of this application.

[0022] Fifthly, embodiments of this application provide a computer program product in which instructions, when executed by a processor of an electronic device, enable the electronic device to perform the steps of the dead pixel region detection method of any embodiment of this application.

[0023] The technical solution provided in this application has at least the following beneficial effects:

[0024] The technical solution provided in this application uses a defect prediction model to predict the wafer morphology of multiple global layout samples with different process parameters. Based on the predicted morphology data corresponding to the multiple global layout samples, the predicted defect regions corresponding to the multiple global layout samples are determined. Defect verification is performed on the predicted defect regions corresponding to the multiple global layout samples. Based on the results of the defect verification, defect region samples are selected from the predicted defect regions corresponding to the multiple global layout samples. This allows regions with insufficient prediction accuracy to be identified as defect region samples for training the defect prediction model, effectively improving the prediction accuracy of the defect prediction model. Furthermore, the trained defect prediction model can then be used to predict the defect location of each local region within the multiple local regions. The method yields the predicted process parameters corresponding to the actual morphology data of the local area, and uses a defect prediction model to predict the wafer morphology of the target wafer when the global layout is fabricated under the influence of the predicted process parameters corresponding to the local area for each local area. Based on the predicted wafer morphology corresponding to each local area, the defect areas of the target wafer are determined. Compared with other schemes that can only provide one static detection result for a target wafer, this application embodiment can detect the detection results of potentially the same or different defect areas for different local areas. This is equivalent to dynamically providing the dynamic detection results corresponding to the process of different local areas for a target wafer, effectively capturing the subtle process differences between different local areas and achieving higher detection accuracy.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a flowchart illustrating a method for detecting defective areas provided in one embodiment of this application;

[0028] Figure 2 A flowchart illustrating a method for detecting defective areas provided in another embodiment of this application;

[0029] Figure 3 A flowchart illustrating a method for detecting defective areas provided in another embodiment of this application;

[0030] Figure 4 A flowchart illustrating a method for detecting defective areas provided in another embodiment of this application;

[0031] Figure 5 This is a schematic diagram of a defect region detection device provided in one embodiment of this application;

[0032] Figure 6 This is a schematic diagram of a defect detection device provided in one embodiment of this application. Detailed Implementation

[0033] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0034] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0035] The acquisition, storage, use, and processing of data in this application comply with relevant national laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.

[0036] With the development of semiconductor technology, manufacturing processes are gradually moving towards smaller process nodes. The smaller the process node, the denser and more complex the patterns on the wafer. For wafers with such dense and complex patterns, detecting defective areas is a crucial means of improving yield. Current defect detection methods typically extract defect-related pattern features from wafer images and then determine the presence of defects based on these features. However, this method currently only provides a static detection result for a single wafer and cannot accurately detect defective areas. Therefore, how to more accurately detect defective areas on wafers is a critical problem that urgently needs to be solved.

[0037] Based on the aforementioned technical problems, this application provides a method, device, and program product for detecting defective areas. The technical solution provided in this application pre-trains a defective area prediction model to learn the mapping relationship between wafer morphology and process parameters. Then, it acquires actual morphology data of multiple local regions of the target wafer. Using the defective area prediction model, it predicts the corresponding process parameters for each local region. Thus, the defective area prediction model can predict the wafer morphology of the target wafer when the global layout is fabricated under the influence of the predicted process parameters corresponding to that local region. Based on the predicted wafer morphology for each local region, the defective area of ​​the target wafer is determined. Compared to other solutions that only provide a static detection result for a single target wafer, this application dynamically predicts the possible morphology of the target wafer under different local regions' processes, and determines the defective area accordingly. This effectively captures subtle process differences between different local regions, resulting in higher detection accuracy.

[0038] The application scenarios of the technical solutions provided in this application are not limited. For example, defective areas can be detected on the wafer after exposure in the photolithography process, after etching, or after the wafer fabrication is completely completed. The application scenarios described in the above embodiments of this application are for the purpose of more clearly illustrating the technical solutions of this application and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will understand, with the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems. The defective area detection method provided in the embodiments of this application can be applied to various application scenarios that require the determination of defective areas on the wafer.

[0039] In practical applications, the entity executing the defective pixel region detection method of this application embodiment can be an electronic device. The electronic device can be, for example, a desktop computer, a laptop computer, or other terminal device; it can also be a single server or a server in a server cluster; or it can be a defect scanning device. This application does not strictly limit the entity executing the technical solution of this embodiment, and the entity can be flexibly selected according to the actual application scenario and requirements.

[0040] This application provides a specific embodiment of a method, device, and program product for detecting defective areas. First, the method for detecting defective areas will be introduced.

[0041] Figure 1 The flowchart of a method for detecting bad pixel regions provided in one embodiment of this application includes steps S101-S106.

[0042] S101: By using a bad pixel prediction model, the wafer morphology of multiple global layout samples with different process parameters is predicted, and the predicted morphology data corresponding to multiple global layout samples is obtained.

[0043] The bad pixel prediction model can be built based on machine learning or deep learning algorithms. For example, the bad pixel prediction model can be built using one or more models such as convolutional neural network model, graph neural network model, and Bayesian neural network.

[0044] Before training the bad pixel prediction model, multiple global layout samples with different process parameters can be obtained through various methods. In some embodiments, experimental design can be used to adjust the process parameters within a controllable range to generate global layout samples with different parameter sets. In other embodiments, global layout samples with different process parameter sets can be selected from historical production data. Each global layout sample corresponds to a set of process parameters that includes numerous process parameters. In the process parameter sets corresponding to different global layout samples, at least one process parameter has a different value.

[0045] The defect prediction model simulates the wafer generation process of each global layout sample under the influence of its process parameters, and obtains the predicted morphology data corresponding to each global layout sample.

[0046] S102: Based on the predicted topography data corresponding to multiple global map samples, determine the predicted bad spot regions corresponding to multiple global map samples.

[0047] For example, features related to bad points can be extracted from the shape prediction data corresponding to each global map sample, and the region where the feature that meets the bad point judgment condition is located can be used as the predicted bad point region.

[0048] S103: Perform bad point verification on the predicted bad point regions corresponding to multiple global map samples, and select bad point region samples from the predicted bad point regions corresponding to multiple global map samples based on the bad point verification results.

[0049] In this application embodiment, there are multiple verification methods for verifying the predicted bad spot regions corresponding to the global layout sample. For example, in some embodiments, bad spot verification can be performed by comparing the actual topography data of the actual wafer with the predicted topography data of the predicted bad spot region; in other embodiments, bad spot verification can be performed by comparing the known real bad spot regions of the global layout sample with the predicted bad spot regions.

[0050] Taking the verification of bad spots using actual wafer topography data as an example, the processing steps of S103 include: S1031-S1032.

[0051] S1031: For each predicted defective region, obtain the region predicted topography data of the predicted defective region from the predicted topography data of the global layout sample corresponding to the predicted defective region, and obtain the region actual topography data of the predicted defective region from the actual topography data of the actual wafer corresponding to the predicted defective region.

[0052] S1032: For each predicted bad spot region, compare the predicted topographic data of the region with the actual topographic data of the region. If the comparison result does not meet the model output conditions, select the predicted bad spot region as the bad spot region sample.

[0053] In the embodiments of steps S1031-S1032, by using the actual morphology data of the actual wafer, the predicted bad spot regions corresponding to the global layout samples are verified for bad spots. This can more accurately identify regions with insufficient prediction accuracy as bad spot region samples to continue training the bad spot prediction model and improve the prediction accuracy of the bad spot prediction model.

[0054] S104: Based on the actual morphology data and process parameters of the defective region samples on the actual wafer, train the defective prediction model to learn the mapping relationship between the wafer morphology and the process parameters, and obtain the trained defective prediction model.

[0055] In steps S101-S104, by performing bad point verification on the predicted bad point regions corresponding to the global map samples, regions with insufficient prediction accuracy can be identified from the predicted bad point regions as bad point region samples to train the bad point prediction model, effectively improving the prediction accuracy of the bad point prediction model.

[0056] For example, a process model that has not been trained on multiple global layout samples can be used as the initial defect prediction model. After training through the above steps S101-S104, a trained defect prediction model can be obtained.

[0057] If the difference between the predicted topographic data and the actual topographic data of each predicted bad spot region satisfies the model output conditions, then the trained bad spot prediction model can be obtained.

[0058] In some embodiments, the model output condition may include a shape difference threshold. Based on the comparison result, the difference between the predicted shape data of the predicted bad spot area and the actual shape data of the area is determined. If the difference is less than the shape difference threshold, the model output condition is met; otherwise, the model output condition is not met.

[0059] In other embodiments, the model output condition may include feature point matching degree. Based on the comparison result, the matching degree between the predicted topographic data of the predicted bad spot area and the actual topographic data of the area is determined. If the matching degree is greater than the feature point matching degree, the model output condition is satisfied; otherwise, the model output condition is not satisfied.

[0060] In some embodiments, the trained process model can be directly used as the defect prediction model. In other embodiments, a more efficient defect prediction model can be built on the process model through methods such as model ensemble, data augmentation, and physical constraint embedding.

[0061] The above content describes an exemplary training process for the defect prediction model involved in this application. The process model involved in the above training process can be trained using the actual morphology data and process parameters of the wafer sample.

[0062] S105: Using the trained defect prediction model, predict the predicted process parameters corresponding to the actual morphology data of each local region of the target wafer, and predict the wafer morphology of the global layout of the target wafer under the predicted process parameters corresponding to each local region.

[0063] The target wafer can be a physically manufactured wafer. There can be one or more target wafers, and the wafer surface exhibits a complex morphology, with significant differences in morphology under different processes.

[0064] In some embodiments, actual topographic data of multiple local areas of the target wafer can be collected one by one using measurement equipment. Topographic data is data used to describe the surface topography of the wafer, and can be represented as two-dimensional or three-dimensional data, with the specific dimension depending on the measurement and representation method. For example, topographic data can be represented as two-dimensional numerical data to describe the surface topography of the wafer, such as graphic contour data reflected by quantitative parameters such as linewidth and depth.

[0065] A local region is a portion of the target wafer. The size of the local region can be set according to the needs of the actual application scenario. In some embodiments, the local region can be represented as an exposure area (Shot) or a chip area (Die). In step S105, the actual morphology data of each of one or more exposure areas and one or more chip areas of the target wafer can be obtained. An exposure area is the area covered by a single exposure of the target wafer by the lithography machine in the photolithography process. A chip area, also known as a die, is an independent single chip area on the target wafer. An exposure area can contain multiple chip areas.

[0066] By acquiring the actual morphological data of each exposed area or each chip area of ​​the target wafer, the true morphological condition of each area can be more accurately reflected, providing a reliable data foundation for subsequent prediction of process parameters. After predicting the process parameters for each exposed area or chip area, the potential defective areas that may arise during wafer fabrication under the influence of these predicted process parameters can be predicted for each area. By detecting the corresponding defective areas separately for different exposed areas or chip areas, defect detection accuracy is effectively improved.

[0067] A global layout is a detailed layout diagram designed for the entire target wafer, containing the location and geometric information of various circuit elements, interconnects, functional modules, etc. on the target wafer.

[0068] The global layout can be obtained from wafer design files or related databases. In some embodiments, the global layout can be an initial global design layout, or an optimized layout obtained by optical proximity correction (OPC) of the global design layout. By performing optical proximity correction on the global design layout, the graphics are optimized and adjusted, such as moving edges and adding extra polygons, which can compensate for errors that may occur during the photolithography process, making the final pattern on the wafer closer to the design requirements.

[0069] In practical applications, the execution of step S101 can be triggered by a user request or by a specified event, and this application embodiment does not impose any restrictions on this.

[0070] For example, when a user is preparing to use an electron beam inspection device to scan and image a target wafer, the user can send an upload request through the user interface of the electronic device, requesting the upload of the actual topographic data of a local area of ​​the target wafer and the global layout of the target wafer. The electronic device responds to the user's upload request and obtains the actual topographic data and global layout uploaded by the user.

[0071] For example, in response to the scanning task of the electron beam detection equipment about to scan and image the target wafer, the electronic device can automatically control the measurement equipment to collect the actual morphology data of a local area of ​​the target wafer and automatically obtain the global layout of the target wafer from the relevant database.

[0072] In some embodiments of this application, in step S105, the actual topographic data of the target region of the target wafer can be measured using a measurement device. The measurement device may include one or more of the following: a critical dimension scanning electron microscope (CD-SEM), an atomic force microscope (AFM), or an X-ray measurement device. Obtaining the actual topographic data of a local area using the measurement device improves detection efficiency.

[0073] Process parameters are quantifications of process conditions, which can be expressed as specific values ​​or ranges, used to precisely control the wafer fabrication process. There are numerous process parameters for wafer fabrication, and different process stages have different parameters. For example, in the photolithography stage, process parameters may include: light source-related parameters, photoresist-related parameters, development-related parameters, etc. The process parameters in the embodiments of this application can be represented as a collection of numerous process parameters. The defect prediction model learns the bidirectional mapping relationship between wafer morphology and process parameters. Based on this mapping relationship, it can predict the corresponding process parameters from the wafer morphology, and it can also predict the corresponding process morphology from the process parameters. Predicted process parameters are the process parameters calculated by the defect prediction model based on the mapping relationship between wafer morphology and process parameters, using the actual morphology data of a local area.

[0074] In step S105, the defect prediction model can predict the wafer morphology of the global layout under the predicted process parameters for each local region. The predicted wafer morphology corresponding to a local region is based on the mapping relationship between wafer morphology and process parameters. It is obtained by simulating the photolithography process for the global layout and the predicted process parameters of the local region, and predicting the overall wafer morphology of the target wafer. This morphology data can be represented as a two-dimensional numerical type.

[0075] S106: Based on the wafer morphology under the predicted process parameters corresponding to each local region, determine the defective areas of the target wafer.

[0076] The defective region is a region where defects may exist, determined based on wafer morphology prediction data. A defect is a location where a function fails due to a defect. It is understood that regions containing defects are usually accompanied by specific morphological features. Based on this, regions exhibiting specific morphologies can be identified as defective regions based on wafer morphology prediction data. The defective regions identified in this step are indirectly derived from the prediction of wafer morphology and may not actually exist on the actual target wafer. In some embodiments, the defective region may correspond to explicit defective descriptive information to describe the details and type of the defect; in other embodiments, the defective region may not have explicit defective descriptive information, and the presence of defects may be indicated solely by the overall region of the defective region.

[0077] For example, the process of determining the defective region of a target wafer based on a predicted wafer morphology corresponding to a local area may include: extracting defect-related features from the predicted wafer morphology. For example, features such as critical dimension changes and height differences of the wafer surface pattern can be calculated. Based on the extracted features, it is determined whether there are features that meet the defect determination criteria, and the region containing the features that meet the defect determination criteria is designated as the defective region. The defect determination criteria can be set based on the wafer's quality requirements and process specifications. For example, when the critical dimension of the pattern in a certain region exceeds a preset deviation range, that region can be determined as a defective region. In the case of a region being determined as a defective region, the location and related features of the defective region can be recorded, thereby achieving defective region localization.

[0078] In steps S101-S104, after acquiring the actual morphology data of multiple local regions of the target wafer, the defect prediction model is used to predict the predicted process parameters corresponding to the actual morphology data of each local region. Thus, the defect prediction model can be used to predict the wafer morphology of the target wafer when the global layout is fabricated under the influence of the predicted process parameters corresponding to the local region. Based on the predicted wafer morphology corresponding to each local region, the defect areas of the target wafer can be determined. Compared with other schemes that can only provide one static detection result for a target wafer, the embodiments of this application can detect the detection results of potentially the same or different defect areas for different local regions. This is equivalent to dynamically providing the dynamic detection results corresponding to the process of different local regions for a target wafer, effectively capturing the small process differences between different local regions, and achieving higher detection accuracy.

[0079] Figure 2 The training process of the process model for a defect region detection method provided in another embodiment of this application includes steps S201-S204.

[0080] S201: Acquire images of multiple wafer samples.

[0081] A wafer sample can be a physically real, already fabricated wafer.

[0082] In some embodiments, prior to S201, wafers with various processes can be prepared using a variety of different process parameters as wafer samples.

[0083] S202: Extract the actual morphology data of multiple wafer samples from images of multiple wafer samples.

[0084] For example, the process of extracting actual topographic data from an image of a wafer sample may include:

[0085] The images of the wafer samples are preprocessed using methods such as noise reduction, contrast enhancement, and coordinate alignment.

[0086] Contour extraction is performed on the preprocessed image to obtain the actual shape data.

[0087] More specifically, image processing algorithms (such as edge detection and morphological analysis) can be used to quantify morphological features such as line width, step height, and sidewall angle to obtain actual morphological data.

[0088] S203: Based on the actual morphology data and process parameters of multiple wafer samples, the process model is trained to learn the mapping relationship between wafer morphology and process parameters, and the trained process model is obtained.

[0089] For example, the process of training a process model based on actual morphology data and process parameters of multiple wafer samples can include:

[0090] Input the actual morphology data of the wafer sample into the process model;

[0091] Predict the process parameters corresponding to the actual morphology data using a process model;

[0092] Calculate the loss value between the predicted value and the actual value of the process parameters;

[0093] Based on the loss value, the parameters of the process model are adjusted using a model optimization algorithm;

[0094] For multiple wafer samples, repeat the above process until the process model reaches the preset number of training iterations or the loss value converges to the preset loss threshold, thus obtaining the trained process model.

[0095] The loss value can be calculated using any loss function. For example, mean squared error can be used as the loss function. Model optimization algorithms can include, for example, stochastic gradient descent, the Adam algorithm, etc.

[0096] S204: Based on the trained process model, a defect prediction model is obtained.

[0097] In this embodiment, by using the actual morphology data and process parameters of multiple wafer samples, the process model is trained to learn the mapping relationship between wafer morphology and process parameters. This enables the process model to predict process parameters based on wafer morphology, and to predict wafer morphology based on process parameters. Consequently, a defect prediction model with higher prediction accuracy can be obtained based on the trained process model.

[0098] For example, before step S201, an initial process model can be constructed based on the photolithography model. Then, through steps S201-S204, the initial process model can be trained using a large amount of actual wafer morphology data and process parameters to obtain a trained process model. The photolithography model is used to simulate the photolithography process and predict crystal morphology. In this embodiment, the process model establishes a mapping relationship between process parameters and wafer morphology based on photolithography modeling technology.

[0099] In some embodiments, the lithography model can be used as a pre-module of the process model. Accurate lithographic imaging based on the lithography model lays the foundation for the process model to predict the wafer morphology. Specifically, a multilayer perceptron can be added to the lithography model to construct the process model. This allows for the simulation of the lithography process based on the lithography model to predict the wafer morphology, and further learning of the mapping relationship between process parameters and wafer morphology using the multilayer perceptron. A multilayer perceptron can be understood as a type of neural network.

[0100] In some embodiments, to establish a more accurate process model, a calibration process for the lithography model may be included before establishing the process model. This includes: firstly, sampling the layout pattern of the global design layout to generate a sampling point file containing the coordinate information of the sampling points; then, based on the sampling point file, automatically locating the sampling points on the wafer, acquiring images of the sampling point positions using a measurement device, and extracting actual topographic data from the images; comparing the topographic data predicted by the lithography model with the actual topographic data, iterating the model parameters of the lithography model based on the comparison results to minimize the prediction error of the lithography model, and finally obtaining a lithography model that achieves the target accuracy.

[0101] In some embodiments of this application, to further improve the accuracy of defect detection, after step S106, defect detection can be performed on any one or more defect regions in the target wafer. Based on the defect detection results, the actual defect regions are determined, and the defect prediction model is further trained based on the actual morphology of the actual defect regions. Specifically, as... Figure 3 As shown in the figure, the defective area detection method provided in this application embodiment may further include steps S107 to S109 after step S106.

[0102] S107: Detect the actual bad areas on the target wafer from the bad area region of the target wafer.

[0103] For example, defect detection can be performed on any one or more defective regions in a target wafer, and the true defective regions can be determined based on the defect detection results. The form in which the defect detection results are presented is not limited; for example, it can be presented as a Boolean result indicating whether it is a true defective region, or as a numerical result indicating the probability of a defective region. For Boolean-type defect detection results, regions that are true defective regions can be directly selected based on the true value. For defect detection results based on the probability of a defective region, regions that are true defective regions can be selected based on a comparison between the probability of a defective region and a preset defective region threshold.

[0104] For minor surface defects, if their location does not affect the function of critical circuits, their probability of being defective is low and they do not reach the preset defect threshold, so they can not be considered defective. However, for defects located in critical circuit areas, their probability of being defective is high and they can be identified as real defective if they reach the preset defect threshold.

[0105] S108: Obtain the actual morphological data and process parameters of the real defective area.

[0106] The process of extracting the actual topographic data of any region on the wafer can be referred to the relevant descriptions in other embodiments, and will not be repeated here.

[0107] S109: Continue training the defect prediction model using the actual morphology data and process parameters of the real defect area to obtain an updated defect prediction model.

[0108] Figure 3 The steps and processing procedures of the prediction model not described in detail in the illustrated embodiments can be referred to the relevant descriptions in other embodiments, and will not be repeated here.

[0109] In this embodiment, the defect prediction model is further trained based on the actual morphology of the real defect area determined by the defect detection results, forming a closed loop of model training and model optimization. This enables the defect prediction model to continuously adapt to the detection of new defects as process fluctuations occur, effectively improving the accuracy of defect detection.

[0110] In some embodiments of this application, to further improve the accuracy and efficiency of defective region detection, the local region includes an exposure region or a chip region. For example, actual topographic data of each exposure region or each chip region of the target wafer can be obtained. Then, a defective region prediction model can be used to predict the predicted process parameters corresponding to the actual topographic data of each exposure region or each chip region. Next, for each exposure region or each chip region, the wafer topography of the global layout under the predicted process parameters corresponding to that local region is predicted. Finally, based on the predicted wafer topography corresponding to each exposure region or each chip region, the defective region of the target wafer is determined.

[0111] In the above embodiments, since the potential defective areas of the target wafer are predicted for each exposure area or each chip area when the global layout is fabricated under the influence of its corresponding process parameters, the actual topographic data of each exposure area or chip area of ​​the target wafer can be input into the defective area prediction model one by one during the entire inspection process. This allows for the prediction of the potential defective areas of the target wafer under the predicted process parameters for each exposure area or chip area. Compared to other schemes that can only provide one static inspection result for a single target wafer, this embodiment can detect multiple defective areas that may be the same or different for different exposure areas or chip areas. This is equivalent to dynamically providing dynamic inspection results for different defective areas for a single target wafer, resulting in higher detection accuracy.

[0112] Figure 4 This is a flowchart illustrating a method for detecting defective areas provided in another embodiment of this application. Figure 5 As shown, in the defective area detection method provided in this application embodiment, the local area includes the exposure area or the chip area, and the method specifically includes steps S401-S405.

[0113] S401: Using measurement equipment, measure and obtain images of each exposure area or each chip area of ​​the target wafer.

[0114] For example, measurement equipment can be used to measure multiple exposure areas or multiple chip areas of the target wafer area by area to obtain the actual morphology data of each exposure area or each chip area.

[0115] S402: Extract the actual morphology data of each exposure area or chip area from the image of each exposure area or chip area.

[0116] S403: Using a bad pixel prediction model, predict the predicted process parameters corresponding to the actual morphology data of each exposure area or each chip area.

[0117] In this step, the actual topographic data of each exposure area or each chip area can be input into the bad pixel prediction model area by area, so that the bad pixel prediction model can predict bad pixels area by area.

[0118] In some embodiments, before predicting the predicted process parameters corresponding to the actual topography data of each local region using the trained bad pixel prediction model, the method further includes:

[0119] Determine the target chip type corresponding to this local region;

[0120] Based on the chip model correspondence, a bad pixel prediction model corresponding to the target chip type is determined as a bad pixel prediction model used to predict the prediction process parameters and wafer morphology of the local area. The chip model correspondence includes the correspondence between bad pixel prediction models of different chip types and different parameter scales.

[0121] For example, to improve defect detection efficiency, the chip type corresponding to each region can be determined based on the actual topographic data of each exposure area or each chip region. Different chip types correspond to defect prediction models with different parameter scales. Thus, the actual topographic data of each exposure area or each chip region can be input into the corresponding defect prediction model for the chip type to predict defect areas, effectively improving defect detection efficiency. More advanced chip types correspond to defect prediction models with larger parameter scales.

[0122] Furthermore, after the defect prediction model has been pre-trained to learn the mapping relationship between wafer morphology and process parameters, the method also includes:

[0123] The trained bad pixel prediction model is scaled to obtain bad pixel prediction models with different parameter scales, and a correspondence is established between different chip types and bad pixel prediction models with different parameter scales.

[0124] This embodiment, by establishing the correspondence between chip type and defect prediction models with different parameter scales, can maximize the improvement of model prediction efficiency while ensuring detection accuracy.

[0125] S404: Using a defect prediction model, the global layout of the target wafer is predicted for each exposure area or each chip area under the corresponding predicted process parameters, thus obtaining the predicted wafer morphology for each exposure area or each chip area.

[0126] S405: Determine the defective areas of the target wafer based on the predicted wafer morphology corresponding to each exposure area or each chip area.

[0127] For the processing procedures not described in detail in steps S401-S405 above, please refer to the relevant descriptions in other embodiments, which will not be repeated here.

[0128] In the embodiments of steps S401-S405, since the potential defective areas of the target wafer are predicted for each exposure area or chip area when the global layout is fabricated under the influence of its corresponding process parameters, the actual topographic data of each exposure area or chip area of ​​the target wafer can be input into the defective area prediction model one by one during the entire inspection process to predict the potential defective areas of the target wafer under the process parameters of each exposure area or chip area. Compared with other schemes that can only provide one static inspection result for a target wafer, the embodiments of this application can detect multiple defective areas that may be the same or different for different exposure areas or chip areas, which is equivalent to dynamically providing dynamic inspection results for different defective areas for a target wafer, resulting in higher inspection accuracy.

[0129] In one embodiment of this application, defect detection is achieved through three stages, combining the implementation methods of the above-described multiple embodiments.

[0130] In the first stage, various wafer samples are prepared using different process parameters; then, images of the wafer samples are acquired using a scanning electron microscope; next, contour extraction is performed on the acquired images to obtain the actual morphology data of the wafer samples; then, the actual morphology data of the wafer samples and the corresponding process parameters are used to train a process model based on a photolithography model, so that the process model learns the mapping relationship between the wafer morphology and the process parameters.

[0131] In the second stage, the process model obtained in the first stage is first used; then, the process model is used to predict the bad spot region on the global layout sample with different process parameters; then, the predicted bad spot region topography data is compared with the actual bad spot region topography data on the actual wafer to confirm the bad spot; next, for bad spot regions with inaccurate prediction, the actual bad spot region topography data and process parameters are input into the process model to continue training to obtain the bad spot prediction model.

[0132] In the third stage, for the target wafer to be inspected for defects, the actual topographic data of each exposure area or chip area is first collected on the target wafer using measurement equipment; then, for each exposure area or chip area, the actual topographic data of the exposure area or chip area and the global layout are input into the defect prediction model to predict the defect area.

[0133] This embodiment comprehensively utilizes metrology technology and process simulation modeling technology. In the above three stages, the actual morphology of the exposure area or chip area of ​​the wafer is back-inferred through the defect prediction model to obtain the predicted process parameters. Based on the predicted process parameters, the predicted data of the overall wafer morphology of the target wafer is forward-inferred. Based on the predicted data of the wafer morphology, the defect area on the target wafer is determined, thereby improving the efficiency and accuracy of defect area detection.

[0134] Based on the defective pixel region detection method provided in the above embodiments, this application also provides specific implementation methods of the defective pixel region detection device, please refer to the following embodiments.

[0135] Figure 5 This is a schematic diagram of a defective pixel region detection device according to an embodiment of this application. The defective pixel region detection device 500 includes:

[0136] The sample morphology prediction module 501 is used to predict the wafer morphology of multiple global layout samples with different process parameters through a bad spot prediction model, and obtain the predicted morphology data corresponding to multiple global layout samples.

[0137] The sample bad spot prediction module 502 is used to determine the predicted bad spot region corresponding to multiple global map samples based on the predicted topography data corresponding to multiple global map samples.

[0138] The sample bad pixel verification module 503 is used to verify bad pixels in the predicted bad pixel regions corresponding to multiple global map samples, and select bad pixel region samples from the predicted bad pixel regions corresponding to multiple global map samples based on the bad pixel verification results.

[0139] The model training module 504 is used to train the defect prediction model based on the actual morphology data and process parameters of the defect region samples on the actual wafer to learn the mapping relationship between the wafer morphology and process parameters, and obtain the trained defect prediction model.

[0140] The model prediction module 505 is used to predict the predicted process parameters corresponding to the actual morphology data of each local region of the target wafer through the trained bad pixel prediction model, and to predict the wafer morphology of the global layout of the target wafer under the predicted process parameters corresponding to each local region.

[0141] The defect determination module 506 is used to determine the defect area of ​​the target wafer based on the wafer morphology corresponding to each local region.

[0142] In one embodiment, the sample defect verification module is configured to, for each predicted defect region, obtain the region predicted topography data of the predicted defect region from the predicted topography data of the global layout sample corresponding to the predicted defect region, and obtain the region actual topography data of the predicted defect region from the actual topography data of the actual wafer corresponding to the predicted defect region; for each predicted defect region, compare the region predicted topography data and the region actual topography data of the predicted defect region, and select the predicted defect region as the defect region sample if the comparison result does not meet the model output conditions.

[0143] In one embodiment, the apparatus further includes a process model training module, used to acquire images of multiple wafer samples before predicting the wafer morphology of multiple global layout samples with different process parameters using a defect prediction model; extract actual morphology data of multiple wafer samples from the images of multiple wafer samples; train a process model to learn the mapping relationship between wafer morphology and process parameters based on the actual morphology data of multiple wafer samples and process parameters, thereby obtaining a trained process model; and obtain a defect prediction model based on the trained process model.

[0144] In one embodiment, the defective region detection device may further include a model optimization module, which is used to detect the actual defective region on the target wafer from the defective region of the target wafer after determining the defective region of the target wafer; obtain the actual morphology data and process parameters of the actual defective region; and continue to train the defective prediction model using the actual morphology data and process parameters of the actual defective region to obtain an updated defective prediction model.

[0145] In one embodiment, the local area includes: an exposure area or a chip area.

[0146] In one embodiment, the defect determination module is used to determine the defect area of ​​the target wafer based on the predicted wafer morphology corresponding to each exposure area or each chip area.

[0147] In one embodiment, the defective region detection device further includes a model selection module, which is used to determine the target chip type corresponding to the local region before predicting the predicted process parameters corresponding to the actual morphology data of each local region; and to determine the defective prediction model corresponding to the target chip type based on the chip model correspondence, as the defective prediction model used to predict the predicted process parameters and wafer morphology of the local region. The chip model correspondence includes the correspondence between different chip types and defective prediction models with different parameter scales.

[0148] In one embodiment, the model selection module is further configured to obtain bad pixel prediction models with different parameter scales by performing model scaling on the bad pixel prediction model, and to establish a correspondence between different chip types and bad pixel prediction models with different parameter scales.

[0149] Figure 6 This is a schematic diagram of the structure of a defect detection device provided in another embodiment of this application.

[0150] The defect detection device may include a processor 601 and a memory 602 storing computer program instructions.

[0151] Specifically, the processor 601 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0152] Memory 602 may include mass storage for data or instructions. For example, and not limitingly, memory 602 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 602 may include removable or non-removable (or fixed) media. Where appropriate, memory 602 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 602 is non-volatile solid-state memory.

[0153] In a particular embodiment, memory 602 includes read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0154] The processor 601 reads and executes computer program instructions stored in the memory 602 to implement any of the dead pixel region detection methods in the above embodiments.

[0155] In one example, the defect detection device may further include a communication interface 603 and a bus 610. For example, Figure 6 As shown, the processor 601, memory 602, and communication interface 603 are connected through bus 610 and complete communication with each other.

[0156] The communication interface 603 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0157] Bus 610 includes hardware, software, or both, that couples components of an online data traffic metering device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 610 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0158] Furthermore, in conjunction with the defective region detection methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. This computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the defective region detection methods in the above embodiments.

[0159] This application also provides a computer program product, including a computer program, which, when executed, implements any of the dead pixel region detection methods described in the above embodiments.

[0160] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0161] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0162] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0163] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0164] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for detecting defective pixel regions, characterized in that, include: By using a bad pixel prediction model, the wafer morphology of multiple global layout samples with different process parameters is predicted, and the predicted morphology data corresponding to the multiple global layout samples is obtained. Based on the predicted topography data corresponding to the multiple global map samples, the predicted bad spot regions corresponding to the multiple global map samples are determined. Bad point verification is performed on the predicted bad point regions corresponding to the multiple global map samples, and bad point region samples are selected from the predicted bad point regions corresponding to the multiple global map samples based on the bad point verification results. Based on the actual morphology data and process parameters of the defective region samples on the actual wafer, the defective prediction model is trained to learn the mapping relationship between the wafer morphology and the process parameters, and the trained defective prediction model is obtained. The trained defect prediction model predicts the actual morphology data of each local region of the target wafer and the corresponding predicted process parameters, as well as the wafer morphology of the global layout of the target wafer under the predicted process parameters of each local region. Based on the wafer morphology corresponding to each local region, the defective areas of the target wafer are determined.

2. The method according to claim 1, characterized in that, Perform bad pixel verification on the predicted bad pixel regions corresponding to the multiple global layout samples, and select bad pixel region samples from the predicted bad pixel regions corresponding to the multiple global layout samples based on the bad pixel verification results, including: For each predicted defective region, the predicted topography data of the region is obtained from the predicted topography data of the global layout sample corresponding to the predicted defective region, and the actual topography data of the region is obtained from the actual topography data of the actual wafer corresponding to the predicted defective region. For each predicted bad spot region, the predicted topographic data of the region and the actual topographic data of the region are compared. If the comparison result does not meet the model output conditions, the predicted bad spot region is selected as the bad spot region sample.

3. The method according to claim 1, characterized in that, Before predicting the wafer morphology of multiple global layout samples with different process parameters using a bad pixel prediction model, the method further includes: Acquire images of multiple wafer samples; Extract the actual morphology data of the multiple wafer samples from the images of the multiple wafer samples; Based on the actual morphology data and process parameters of the multiple wafer samples, the process model is trained to learn the mapping relationship between wafer morphology and process parameters, and the trained process model is obtained. Based on the trained process model, the defect prediction model is obtained.

4. The method according to claim 1, characterized in that, After determining the defective region of the target wafer, the method further includes: From the defective areas of the target wafer, detect the actual defective areas on the target wafer; Obtain the actual morphological data and process parameters of the actual defective area; The defect prediction model is further trained using the actual morphology data and process parameters of the real defect area to obtain an updated defect prediction model.

5. The method according to any one of claims 1-4, characterized in that, The local area includes: the exposure area or the chip area.

6. The method according to claim 5, characterized in that, Based on the wafer morphology corresponding to each local region, the defect region of the target wafer is determined, including: Based on the predicted wafer morphology corresponding to each of the exposure areas or each of the chip areas, the defective areas of the target wafer are determined.

7. The method according to claim 1, characterized in that, Before predicting the predicted process parameters corresponding to the actual topographic data of each of the local regions, the method further includes: Determine the target chip type corresponding to this local region; Based on the chip model correspondence, a bad pixel prediction model corresponding to the target chip type is determined as a bad pixel prediction model for predicting the prediction process parameters and wafer morphology of the local area. The chip model correspondence includes the correspondence between bad pixel prediction models of different chip types and different parameter scales.

8. The method according to claim 7, characterized in that, After obtaining the trained bad pixel prediction model, the method further includes: The defect prediction model is scaled to obtain defect prediction models with different parameter scales, and a correspondence is established between different chip types and defect prediction models with different parameter scales.

9. A defective pixel area detection device, characterized in that, The device includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor. When the program or instructions are executed by the processor, they implement the steps of the dead pixel region detection method as described in any one of claims 1-8.

10. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device performs the dead pixel region detection method as described in any one of claims 1-8.

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