Wafer acceptance test data analysis method and device, medium and electronic equipment

Abstract

The invention provides a wafer acceptance test data analysis method and device, a medium and electronic equipment, and the method comprises the steps: carrying out the initial segmentation of to-be-recognized wafer acceptance test data according to a feature wafer number and a feature test point number, and obtaining a plurality of initial data regions; by identifying the feature identifier in each initial data area, the segmentation logic corresponding to the wafer acceptance test data provided by different wafer factories can be determined, so that the wafer acceptance test data segmentation is accurately completed, the accuracy of subsequent target data extraction is guaranteed, and the accuracy of wafer acceptance test data extraction is improved. Therefore, the accuracy of the analysis report generated based on the target data is ensured. The wafer receiving test data provided by different wafer factories can be automatically identified, the dependence on manpower is eliminated, the manpower cost is reduced, the uniformity of analysis report formats is improved, and the check is more convenient.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing, and more specifically, to a method, apparatus, medium, and electronic device for analyzing wafer test data. Background Technology

[0002] Wafer Acceptance Test (WAT) is an electrical test performed on wafers before they leave the factory. The results of WAT can reflect the overall process quality of a wafer batch; therefore, identifying and analyzing WAT data plays a crucial role in monitoring the quality stability of chip products and tracing anomalies.

[0003] When manufacturing related products, companies may use wafers from different foundries, thus requiring the identification and analysis of wafer acceptance test data from these different foundries. However, the formats of wafer acceptance test data from different foundries are not the same, necessitating different processing logics and methods when processing wafer acceptance test data from different sources. This process is typically performed manually by experienced test personnel, requiring significant manpower and time, and the accuracy of the identification results cannot be guaranteed. Summary of the Invention

[0004] The purpose of this invention is to provide a wafer acceptance test data analysis method, apparatus, medium, and electronic device to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a method for analyzing wafer acceptance test data, the method comprising: The test data of the wafer to be identified is initially segmented based on the feature wafer number and feature test point number to obtain multiple initial data regions. The feature identifiers of each of the initial data regions are identified, and the segmentation logic corresponding to the test data of the wafer to be identified is determined based on the identification results. The segmentation logic includes segmentation points corresponding to various types of target data regions. The test data of the wafer to be identified is further segmented according to the segmentation logic to obtain multiple target data regions, and feature extraction is performed in the target data regions to obtain the corresponding target data. Based on the target data, an analysis report corresponding to the test data of the wafer to be identified is generated.

[0006] By identifying the feature identifiers in each initial data region, the segmentation logic corresponding to wafer acceptance test data provided by different wafer fabs can be determined, thereby accurately completing the wafer acceptance test data segmentation and ensuring the accuracy of subsequent target data extraction, which in turn ensures the accuracy of the analysis report generated based on the target data. It can automatically identify wafer acceptance test data provided by different wafer fabs, eliminating reliance on manual labor, reducing labor costs, improving the uniformity of analysis report formats, and making them easier to view.

[0007] Optionally, the identification result includes feature identifiers in each of the initial data regions, and the step of determining the segmentation logic corresponding to the test data of the wafer to be identified based on the identification result includes any of the following: Determine whether there is a unique feature identifier corresponding to any wafer fab in the identification results. If there is a unique feature identifier corresponding to any wafer fab, then use the segmentation logic of the wafer fab corresponding to the unique feature identifier as the segmentation logic corresponding to the test data of the wafer to be identified. Determine whether any wafer fab has a specified feature identifier corresponding to the i-th initial data region among the feature identifiers of the i-th initial data region. If any wafer fab has a specified feature identifier corresponding to the i-th initial data region, then use the segmentation logic of the wafer fab corresponding to the specified feature identifier as the segmentation logic corresponding to the test data of the wafer to be identified.

[0008] The segmentation logic corresponding to the test data of the wafer to be identified can be quickly and accurately determined to ensure the accuracy of the segmentation results, thereby ensuring the accuracy of the target data extraction results.

[0009] Optionally, the method further includes: obtaining a list of primary identifiers corresponding to each wafer fab, wherein the list of primary identifiers includes a suspected identifier corresponding to the wafer fab and the initial data region to which the suspected identifier belongs; Compare each of the primary identifier lists to determine the first type of identifier list, and use the first type of target identifier in the first type of identifier list as the unique feature identifier of the wafer fab to which the first type of identifier list belongs; Wherein, the first type of identifier list is a list of primary identifiers including at least one first type of target identifier, and the first type of target identifier is a suspected identifier that exists only in the first type of identifier list.

[0010] Remove all identified unique feature identifiers from the second category identifier list, where the second category identifier list is a list of primary identifiers excluding the first category identifier list; Compare the suspected identifiers belonging to the i-th initial data region in the j-th second-class identifier list. If a second-class target identifier exists, then the second-class target identifier is used as the designated feature identifier for the i-th initial data region of the wafer fab to which the j-th second-class identifier list belongs. Among them, the second type of target identifier is different from any suspected identifier in the i-th initial data region in other second type identifier lists, and 1≤j≤the total number of second type identifier lists.

[0011] Accurately setting the unique feature identifier corresponding to the wafer fab and / or the specified feature identifier of the i-th initial data region ensures the correct segmentation logic, thereby guaranteeing the accuracy of subsequent data.

[0012] Optionally, generating an analysis report corresponding to the test data of the wafer to be identified based on the target data includes: adding the target data to a first worksheet according to standardized processing logic; drawing a chart based on the content of the first worksheet to obtain a test data chart; and summarizing the first worksheet and the test data chart to generate the analysis report.

[0013] An analysis report is generated by summarizing the first worksheet and test data graphs, further enhancing the convenience and comprehensiveness of viewing the analysis report.

[0014] In a second aspect, embodiments of the present invention provide a wafer acceptance test data analysis apparatus, the apparatus comprising: The first processing unit is used to perform initial segmentation of the test data of the wafer to be identified based on the feature wafer number and the feature test point number, to obtain multiple initial data regions. The first processing unit is further configured to identify feature identifiers in each of the initial data regions, and determine the segmentation logic corresponding to the test data of the wafer to be identified based on the identification results, wherein the segmentation logic includes segmentation points corresponding to various types of target data regions; The first processing unit is further configured to perform secondary segmentation on the test data of the wafer to be identified according to the segmentation logic to obtain multiple target data regions, and to perform feature extraction in the target data regions to obtain the corresponding target data; The second processing unit is used to generate an analysis report corresponding to the test data of the wafer to be identified based on the target data.

[0015] Thirdly, embodiments of the present invention provide a storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.

[0016] Fourthly, embodiments of the present invention provide an electronic device, the electronic device comprising: a processor and a memory, the memory being used to store one or more programs; when the one or more programs are executed by the processor, the above-described method is implemented.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0020] Figure 2 This is one of the flowcharts illustrating the wafer acceptance test data analysis method provided in an embodiment of the present invention.

[0021] Figure 3 This is the second flowchart illustrating the wafer acceptance test data analysis method provided in this embodiment of the invention.

[0022] Figure 4 This is a schematic diagram of a wafer acceptance test data analysis device provided in an embodiment of the present invention.

[0023] In the diagram: 10-Processor; 11-Memory; 12-Bus; 13-Communication interface; 301-First processing unit; 302-Second processing unit. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0026] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0027] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0028] This invention provides an electronic device, which may be a computer device, a mobile phone device, or a server device. Please refer to... Figure 1 This is a schematic diagram of the structure of an electronic device. The electronic device includes a processor 10, a memory 11, and a bus 12. The processor 10 and the memory 11 are connected via the bus 12. The processor 10 is used to execute executable modules, such as computer programs, stored in the memory 11.

[0029] Processor 10 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the wafer receiving test data analysis method can be completed through integrated logic circuits in the hardware or software instructions within processor 10. The aforementioned processor 10 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0030] The memory 11 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage.

[0031] Bus 12 can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. Figure 1 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus 12 or one type of bus 12.

[0032] The memory 11 is used to store programs, such as programs corresponding to a wafer acceptance test data analysis device. The wafer acceptance test data analysis device includes at least one software functional module that can be stored in the memory 11 in the form of software or firmware, or embedded in the operating system (OS) of the electronic device. Upon receiving an execution instruction, the processor 10 executes the program to implement the wafer acceptance test data analysis method.

[0033] The electronic device provided in this embodiment of the invention may further include a communication interface 13. The communication interface 13 is connected to the processor 10 via a bus.

[0034] It should be understood that, Figure 1 The structure shown is only a partial schematic diagram of the electronic device; the electronic device may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof.

[0035] The wafer acceptance test data analysis method provided in this embodiment of the invention can be applied to, but is not limited to, [various applications]. Figure 1 For the specific process of the electronic devices shown, please refer to [link / reference]. Figure 2 The wafer acceptance test data analysis includes: S21, S22, S23 and S24, which are described in detail below.

[0036] S21. Based on the feature wafer number and feature test point number, the test data of the wafer to be identified is initially segmented to obtain multiple initial data regions.

[0037] The feature wafer number is the user-specified wafer number, and the feature test site number is the user-specified test site number. It should be understood that all wafer acceptance test data provided by wafer fabs includes both the feature wafer number and the feature test site number.

[0038] S22, identify the feature identifiers in each initial data region, and determine the segmentation logic corresponding to the test data of the wafer to be identified based on the identification results.

[0039] The segmentation logic includes the segmentation points corresponding to various types of target data regions.

[0040] It should be understood that by identifying the feature identifiers in each initial data region, the wafer fab to which the wafer acceptance test data belongs is determined based on the identification results, and thus the corresponding segmentation logic for the wafer acceptance test data is determined. Each wafer fab corresponds to a set of segmentation logic. By identifying the feature identifiers, wafer acceptance test data from different wafer fabs can be automatically identified, and their corresponding segmentation logic can be determined, thereby ensuring the accuracy and consistency of the final identification results.

[0041] S23. Based on the segmentation logic, the test data of the wafer to be identified is segmented a second time to obtain multiple target data regions, and feature extraction is performed in the target data regions to obtain the corresponding target data.

[0042] The target data includes test item name, test data, wafer number, site number, test upper and lower thresholds, data unit, batch information, etc.

[0043] It should be noted that the feature extraction rules for different types of target data regions may be different. In order to accurately obtain all the target data, it is necessary to first perform secondary segmentation on the test data of the wafer to be identified to obtain different types of target data regions, and then perform feature extraction according to the corresponding feature extraction rules to obtain the target data.

[0044] S24. Based on the target data, generate an analysis report corresponding to the test data of the wafer to be identified.

[0045] In the wafer acceptance test data analysis method provided in this embodiment of the invention, by identifying the feature identifiers in each initial data region, the segmentation logic corresponding to wafer acceptance test data provided by different wafer fabs can be determined, thereby accurately completing the wafer acceptance test data segmentation and ensuring the accuracy of subsequent target data extraction, which in turn ensures the accuracy of the analysis report generated based on the target data. It can automatically identify wafer acceptance test data provided by different wafer fabs, eliminating reliance on manual labor, reducing labor costs, improving the uniformity of the analysis report format, and making it easier to view.

[0046] In an optional implementation, the identification result includes feature identifiers in each initial data region. Based on this, regarding how to quickly and accurately determine the segmentation logic corresponding to the test data of the wafer to be identified, ensuring the accuracy of the segmentation result, and thus ensuring the accuracy of the target data extraction result, this embodiment of the invention also provides an optional implementation, please refer to the following. Determining the segmentation logic corresponding to the test data of the wafer to be identified based on the identification result includes: S222 or S223, specifically described below.

[0047] S222, determine whether there is a unique feature identifier corresponding to any wafer fab in the identification result. If there is a unique feature identifier corresponding to any wafer fab, then use the segmentation logic of the wafer fab corresponding to the unique feature identifier as the segmentation logic corresponding to the test data of the wafer to be identified.

[0048] The unique identifier indicates that it appears only in the wafer acceptance test data of one wafer fab, and is not included in the wafer acceptance test data of other wafer fabs.

[0049] It should be understood that if there is a unique identifier corresponding to any wafer fab, then the wafer fab corresponding to the unique identifier is the wafer fab corresponding to the test data of the wafer to be identified.

[0050] S223, determine whether there is a specified feature identifier for the i-th initial data region in the feature identifier of any wafer fab corresponding to the i-th initial data region. If there is a specified feature identifier for the i-th initial data region in any wafer fab, then use the segmentation logic of the wafer fab corresponding to the specified feature identifier as the segmentation logic corresponding to the test data of the wafer to be identified.

[0051] Where 1 ≤ i ≤ the total number of initial data regions.

[0052] The specified feature identifier of the i-th initial data region indicates that only one wafer fab's wafers accept the test data including the specified feature identifier in the i-th initial data region. Other initial data regions of wafers from other wafer fabs may exist.

[0053] It should be understood that if there exists a specified feature identifier for any wafer fab corresponding to the i-th initial data region, then the wafer fab corresponding to the specified feature identifier is the wafer fab corresponding to the test data of the wafer to be identified.

[0054] In one alternative implementation, the identification results are determined by traversal to determine whether there is a unique feature identifier corresponding to any wafer fab, and whether there is a specified feature identifier corresponding to the i-th initial data region among the feature identifiers of the i-th initial data region.

[0055] It should be understood that different wafer fabs may provide wafer acceptance test data containing many identical or similar feature identifiers. If the unique feature identifier corresponding to the wafer fab and / or the specified feature identifier for the i-th initial data region are not set accurately, it may lead to incorrect segmentation logic, thereby affecting the accuracy of subsequent data. Therefore, this embodiment of the invention also provides an optional implementation method, please refer to... Figure 3 The wafer acceptance test data analysis method also includes: S11, S12, S13 and S14, which are described in detail below.

[0056] S11, obtain the list of primary identifiers corresponding to each wafer fab.

[0057] The initial identifier list includes potential identifiers corresponding to the wafer fab and the initial data areas to which these potential identifiers belong. Potential identifiers are those included in all wafer acceptance test data provided by the wafer fab. The initial identifier list can be automatically generated by extracting identifiers from all wafer acceptance test data provided by the wafer fab using a language recognition model. Alternatively, the initial identifier list can be manually compiled.

[0058] S12, compare each primary identifier list to determine the first type of identifier list, and use the first type of target identifier in the first type of identifier list as the unique feature identifier of the wafer fab to which the first type of identifier list belongs; The first category of identifiers is a list of primary identifiers that includes at least one primary target identifier. The primary target identifier is a suspected identifier that exists only in the first category of identifiers (and does not appear in other primary identifier lists).

[0059] S13, remove all determined unique feature identifiers from the second type of identifier list, where the second type of identifier list is the list of primary identifiers excluding the first type of identifier list.

[0060] S14. Compare the suspected identifiers belonging to the i-th initial data region in the j-th second-class identifier list. If a second-class target identifier exists, then use the second-class target identifier as the designated feature identifier for the i-th initial data region of the wafer fab to which the j-th second-class identifier list belongs.

[0061] Among them, the second type of target identifier is different from any suspected identifier in the i-th initial data region in other second type identifier lists (excluding the j-th second type identifier list) (belonging only to the i-th initial data region in the j-th second type identifier list), and 1≤j≤the total number of second type identifier lists.

[0062] Building upon the preceding text, to further enhance the convenience and comprehensiveness of viewing the analysis report, this embodiment of the invention also provides an optional implementation method, please refer to the following. S24, Based on the target data, generate an analysis report corresponding to the test data of the wafer to be identified, including: S241, S242, and S243, which are described in detail below.

[0063] S241, add the target data to the first worksheet according to the standardized processing logic.

[0064] S242, draw a chart based on the contents of the first worksheet to obtain the test data chart.

[0065] The test data plots include, but are not limited to, box plots, scatter plots, and histograms.

[0066] S243, summarize the first worksheet and test data graph to generate an analysis report.

[0067] Optionally, the test item names in the first worksheet are adjusted according to the corresponding mapping rules to obtain the second worksheet, which is then combined with the test data graph to generate an analysis report.

[0068] In this embodiment of the invention, the target data is added to the first worksheet according to the standardized processing logic. Even if the wafers from different wafer fabs receive the test data, the format of the first worksheet obtained after processing according to the standardized processing logic is uniform, ensuring the consistency of the data structure, facilitating the consistency of subsequent analysis report generation, and making observation easier.

[0069] In an optional implementation, the target data includes test item name, test data, wafer number, test point number, test upper and lower thresholds, data unit, and batch information. S241, the target data is added to the first worksheet according to the standardized processing logic, including: S241A, S241B, S241C, and S241D, which are described in detail below.

[0070] S241A, based on the original layout information in the test data of the wafer to be identified, adds test item names to the first worksheet and arranges them.

[0071] The original layout information includes the original layout positions of various target data in the test data of the wafer to be identified.

[0072] S241B, combining the arrangement of test item names with the original arrangement information, adds the test data, test upper and lower thresholds, and data units to the first worksheet.

[0073] S241C, corresponding to the test data and original layout information already added in the first worksheet, adds the wafer number and test point number to the first worksheet.

[0074] S241D: Add batch information and test date to a specified area in the first worksheet.

[0075] For example, the first row of the first worksheet is sorted by test item name, the second and third rows are sorted by upper and lower thresholds, and from the fourth row onwards, they are sorted by wafer number, test point number, and corresponding test data, and so on.

[0076] Please refer to Table 1 below, which is an example of the first worksheet.

[0077] Table 1

[0078] In an optional implementation, the wafer acceptance test data analysis method further includes: S25, which is described in detail below.

[0079] S25. Based on the wafer fab name, batch information, and generation time of the analysis report, the analysis report is named and saved.

[0080] Building upon the preceding text, this invention provides an optional implementation method for accurately obtaining segmentation logic, ensuring the accuracy of segmentation results, and thus guaranteeing the accuracy of subsequent target data extraction results. Please refer to the following description. The segmentation logic corresponding to the test data received by the wafer to be identified is determined based on the identification results, including steps S225, S227, and S229, which are specifically described below.

[0081] S225, determine the wafer fab to which the test data of the wafer to be identified belongs based on the identification results.

[0082] Optionally, if the identification result contains a unique feature identifier corresponding to any wafer fab, the wafer fab to which the test data of the wafer to be identified belongs is the wafer fab corresponding to the unique feature identifier in the identification result; if the feature identifier of the i-th initial data region in the identification result contains a specified feature identifier corresponding to the i-th initial data region, the wafer fab to which the test data of the identified wafer belongs is the wafer fab corresponding to the specified feature identifier of the i-th initial data region. Please refer to the relevant content of S222 and S223 above for details, which will not be elaborated here.

[0083] S227, Based on the coordinate mapping relationship of the wafer fab, determine the interval coordinates of various types of target data in the test data of the wafer to be identified.

[0084] The coordinate mapping relationship includes the mapping relationship between various types of target data and interval coordinates in the test data of the wafer to be identified.

[0085] For example, when the wafer fab is A, the data within the coordinate range D3~BD3 is defined as "test item name", the data within the coordinate range D20~BD300 is defined as "test data", and so on; when the wafer fab is B, the data within the coordinate range H10~AH10 is defined as "test item name", the data within the coordinate range H15~AH350 is defined as "test data", and so on.

[0086] S229. Based on the interval coordinates corresponding to the target data, determine the segmentation point corresponding to the target data area, and then determine the segmentation logic corresponding to the test data of the wafer to be identified.

[0087] The dividing point corresponding to the target data region can be the endpoint of the interval coordinate.

[0088] Building upon the previous steps, to further ensure the accuracy of the segmentation results, the test data of the wafer to be identified can be converted into initial Excel data. At this point, the interval coordinates are the distribution coordinates of the target data in the Excel table. Then, the segmentation is performed according to the coordinate information in the Excel table to ensure the accuracy of the segmentation results.

[0089] Please see Figure 4 , Figure 4 The present invention provides a wafer acceptance test data analysis device, which is optionally applied to the electronic device described above.

[0090] The wafer acceptance test data analysis device includes: a first processing unit 301 and a second processing unit 302.

[0091] The first processing unit 301 is used to perform initial segmentation of the test data of the wafer to be identified according to the feature wafer number and the feature test point number, so as to obtain multiple initial data regions. The first processing unit 301 is also used to identify the feature identifiers in each initial data region, and determine the segmentation logic corresponding to the test data of the wafer to be identified based on the identification results. The segmentation logic includes segmentation points corresponding to various types of target data regions. The first processing unit 301 is also used to perform secondary segmentation of the test data of the wafer to be identified according to the segmentation logic to obtain multiple target data regions, and to extract features in the target data regions to obtain the corresponding target data; The second processing unit 302 is used to generate an analysis report corresponding to the test data of the wafer to be identified based on the target data.

[0092] Optionally, the second processing unit 302 may execute S24 and S25 as described above, and the first processing unit 301 may execute other steps in the above method embodiments.

[0093] It should be noted that the wafer acceptance test data analysis device provided in this embodiment can execute the method flow shown in the above method flow embodiment to achieve the corresponding technical effects. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments.

[0094] This invention also provides a storage medium storing computer instructions and programs, which, when read and executed, perform the wafer acceptance test data analysis method described above. The storage medium may include memory, flash memory, registers, or a combination thereof.

[0095] The following provides an electronic device, which may be a computer device, a mobile phone device, or a server device. This electronic device is as follows: Figure 1 As shown, the wafer acceptance test data analysis method described above can be implemented. Specifically, the electronic device includes: a processor 10, a memory 11, and a bus 12. The processor 10 may be a CPU. The memory 11 is used to store one or more programs, which, when executed by the processor 10, execute the wafer acceptance test data analysis method of the above embodiment.

[0096] In summary, the wafer acceptance test data analysis method, apparatus, medium, and electronic device provided by this invention initially segment the wafer acceptance test data to be identified based on the characteristic wafer number and characteristic test point number, obtaining multiple initial data regions. By identifying the feature identifiers in each initial data region, the segmentation logic corresponding to the wafer acceptance test data provided by different wafer fabs can be determined, thereby accurately completing the wafer acceptance test data segmentation and ensuring the accuracy of subsequent target data extraction, i.e., ensuring the accuracy of the analysis report generated based on the target data. It can automatically identify wafer acceptance test data provided by different wafer fabs, eliminating reliance on manual labor, reducing labor costs, improving the uniformity of the analysis report format, and making it easier to view.

[0097] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0098] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for analyzing wafer acceptance test data, characterized in that, The method includes: The test data of the wafer to be identified is initially segmented based on the feature wafer number and feature test point number to obtain multiple initial data regions. The feature identifiers in each of the initial data regions are identified, and the segmentation logic corresponding to the test data of the wafer to be identified is determined based on the identification results. The segmentation logic includes segmentation points corresponding to various types of target data regions. The test data of the wafer to be identified is further segmented according to the segmentation logic to obtain multiple target data regions, and feature extraction is performed in the target data regions to obtain the corresponding target data. Based on the target data, an analysis report corresponding to the test data of the wafer to be identified is generated.

2. The wafer acceptance test data analysis method as described in claim 1, characterized in that, The identification result includes feature identifiers in each of the initial data regions, and the step of determining the segmentation logic corresponding to the test data of the wafer to be identified based on the identification result includes any of the following: Determine whether there is a unique feature identifier corresponding to any wafer fab in the identification results. If there is a unique feature identifier corresponding to any wafer fab, then use the segmentation logic of the wafer fab corresponding to the unique feature identifier as the segmentation logic corresponding to the test data of the wafer to be identified. Determine whether any wafer fab has a specified feature identifier corresponding to the i-th initial data region among the feature identifiers of the i-th initial data region. If any wafer fab has a specified feature identifier corresponding to the i-th initial data region, then use the segmentation logic of the wafer fab corresponding to the specified feature identifier as the segmentation logic corresponding to the test data of the wafer to be identified.

3. The wafer acceptance test data analysis method as described in claim 2, characterized in that, The method further includes: Obtain the initial identifier list corresponding to each wafer fab, the initial identifier list including the suspected identifier corresponding to the wafer fab and the initial data area to which the suspected identifier belongs; Compare each of the primary identifier lists to determine the first type of identifier list, and use the first type of target identifier in the first type of identifier list as the unique feature identifier of the wafer fab to which the first type of identifier list belongs; The first type of identifier list is a list of primary identifiers that includes at least one first type of target identifier, and the first type of target identifier is a suspected identifier that exists only in the first type of identifier list.

4. The wafer acceptance test data analysis method as described in claim 3, characterized in that, The method further includes: Remove all identified unique feature identifiers from the second category identifier list, where the second category identifier list is a list of primary identifiers excluding the first category identifier list; Compare the suspected identifiers belonging to the i-th initial data region in the j-th second-class identifier list. If a second-class target identifier exists, then the second-class target identifier is used as the designated feature identifier for the i-th initial data region of the wafer fab to which the j-th second-class identifier list belongs. Among them, the second type of target identifier is different from any suspected identifier in the i-th initial data region in other second type identifier lists, and 1≤j≤the total number of second type identifier lists.

5. The wafer acceptance test data analysis method as described in claim 1, characterized in that, The step of generating an analysis report corresponding to the test data of the wafer to be identified based on the target data includes: The target data is added to the first worksheet according to the standardized processing logic; Based on the content of the first worksheet, a chart is drawn to obtain the test data graph; The analysis report is generated by summarizing the first worksheet and the test data graph.

6. The wafer acceptance test data analysis method as described in claim 5, characterized in that, The target data includes test item name, test data, wafer number, test point number, test upper and lower thresholds, data unit, and batch information. Adding the target data to the first worksheet according to standardized processing logic includes: Based on the original layout information in the test data of the wafer to be identified, the test item name is added to the first worksheet and arranged. Based on the arrangement of the test item names and the original arrangement position information, the test data, the upper and lower thresholds of the test, and the data unit are added to the first worksheet; Based on the test data already added to the first worksheet and the original layout information, add the wafer number and the test point number to the first worksheet; Add the batch information and test date to the designated area in the first worksheet.

7. The wafer acceptance test data analysis method as described in claim 1, characterized in that, The step of determining the segmentation logic corresponding to the test data of the wafer to be identified based on the identification result includes: Based on the identification results, determine the wafer fab to which the test data of the wafer to be identified belongs; Based on the coordinate mapping relationship of the wafer fab, the interval coordinates of various types of target data in the test data of the wafer to be identified are determined, wherein the coordinate mapping relationship includes the mapping relationship between various types of target data and interval coordinates in the test data of the wafer to be identified; Based on the interval coordinates corresponding to the target data, the segmentation point corresponding to the target data region is determined, and then the segmentation logic corresponding to the test data of the wafer to be identified is determined.

8. A wafer acceptance test data analysis device, characterized in that, The device includes: The first processing unit is used to perform initial segmentation of the test data of the wafer to be identified based on the feature wafer number and the feature test point number, to obtain multiple initial data regions. The first processing unit is further configured to identify feature identifiers in each of the initial data regions, and determine the segmentation logic corresponding to the test data of the wafer to be identified based on the identification results, wherein the segmentation logic includes segmentation points corresponding to various types of target data regions; The first processing unit is further configured to perform secondary segmentation on the test data of the wafer to be identified according to the segmentation logic to obtain multiple target data regions, and to perform feature extraction in the target data regions to obtain the corresponding target data; The second processing unit is used to generate an analysis report corresponding to the test data of the wafer to be identified based on the target data.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method as described in any one of claims 1-7.

10. An electronic device, characterized in that, include: Processor and memory, the memory being used to store one or more programs; When the one or more programs are executed by the processor, the method as described in any one of claims 1-7 is implemented.

Images