Nand flash read voltage axis prediction method and device, and storage medium

Abstract

The application discloses a NAND flash read voltage axis prediction method and device and a storage medium. The method comprises the following steps: performing characteristic testing on different types of NAND under different working conditions, and obtaining corresponding voltage axis data and characteristic parameters thereof; cleaning and normalizing the obtained data; constructing a GRUM model comprising a first GRU branch and a second GRU branch, cross-fusing to form a final GRUM prediction model, obtaining actual programming / erasing cycles and actual data retention time of a target NAND flash, inputting the final GRUM prediction model for prediction, and outputting a best read voltage axis prediction value of the target NAND flash. The application can better capture and process the nonlinear relationship and space-time dependence of NAND flash data, thereby improving the prediction accuracy.

Description

Technical Field

[0001] This application relates to NAND flash memory read voltage axis prediction technology, and more particularly to a NAND flash memory read voltage axis prediction method and apparatus, computer storage medium, and electronic device. Background Technology

[0002] With the widespread adoption of SSDs (Solid State Drives), NAND Flash, as the core storage medium, directly impacts the overall performance of SSDs. However, as NAND flash technology continues to advance and the physical size of storage cells shrinks, the reliability issues of NAND flash are becoming increasingly prominent. Therefore, accurately predicting the characteristics of NAND flash and optimizing storage system design and usage strategies has become a current research hotspot.

[0003] Traditional methods for predicting NAND flash memory characteristics primarily rely on empirical models and simplified mathematical models. While these methods can reflect the characteristics of NAND flash memory to some extent, their prediction accuracy is limited because they cannot fully account for complex factors in actual operating conditions, such as temperature, voltage fluctuations, and usage patterns. Furthermore, with the continuous development of NAND flash memory technology, the limitations of traditional methods are becoming increasingly apparent, failing to meet the ever-growing demands for data storage.

[0004] Currently, several methods for predicting NAND flash memory characteristics based on machine learning algorithms have been proposed. These methods mainly utilize machine learning models such as neural networks, support vector machines, and random forests to model and predict key parameters of NAND flash memory, such as threshold voltage distribution, erase / write cycles, and data retention time. However, existing technologies still have some shortcomings. For example, some methods only focus on single characteristics such as NAND flash memory signal detection or lifetime prediction, failing to comprehensively consider multiple key characteristics of NAND flash memory; while some methods employ neural network models, their model structures are relatively simple and cannot fully capture the complex nonlinear relationships in NAND flash memory characteristics. Furthermore, most current technologies use pre-trained offline models and methods, which cannot achieve dynamic real-time adjustment of predictions and are difficult to adapt to the aging and changing operating conditions of NAND flash memory, resulting in limited prediction accuracy and adaptability in practical applications. Summary of the Invention

[0005] This application provides a method and apparatus for predicting the read voltage axis of NAND flash memory, a storage medium, and an electronic device, so as to at least solve the above-mentioned technical problems existing in the prior art.

[0006] According to a first aspect of this application, a method for predicting the read voltage axis of NAND flash memory is provided, comprising:

[0007] Perform characteristic tests on different types of NAND under different operating conditions to obtain the corresponding voltage axis data and characteristic parameters;

[0008] The acquired data is cleaned and normalized.

[0009] A GRUM model containing a first GRU branch and a second GRU branch is constructed. The first type of data in the normalized data is input into the first GRU branch for training to obtain the first GRU model. The second type of data in the normalized data is input into the second GRU branch for training to obtain the second GRU model. The outputs of the first GRU model and the outputs of the second GRU model are cross-fused to form the final GRUM prediction model.

[0010] Obtain the actual programming / erasing cycle and actual data retention time of the target NAND flash memory, input them into the final GRUM prediction model for prediction, and output the optimal read voltage axis prediction value of the target NAND flash memory.

[0011] In some alternative implementations, the method further includes:

[0012] During the idle period of the target NAND flash memory, perform multiple read operations and collect feedback on the actual voltage axis value;

[0013] The actual voltage axis value of the feedback is used to train the final GRUM prediction model online, and the weight parameters of the final GRUM prediction model are updated.

[0014] In some alternative implementations, the method further includes:

[0015] The output of the second GRU model is used as a feature representation, and the best read voltage axis prediction value of NAND is output through the fully connected layer structure of the final GRUM prediction model.

[0016] Obtain the actual measured value of the NAND read voltage axis, evaluate the prediction result of the voltage axis prediction using the actual measured value, and adjust the parameters and weights of the final GRUM prediction model as the updated GRUM prediction model.

[0017] In some optional implementations, both the first GRU branch and the second GRU branch include a reset gate, an update gate, a candidate hidden state, and a final hidden state, which have the same structure and independent parameters, wherein:

[0018] The reset door is implemented through the following model:

[0019]

[0020] x tThe input for the current data step is t, where t is the time step and h is the time step. t h represents the hidden state at the current time step. t-1 Let W be the hidden state at the previous time step, σ() represent the activation function, and Wxr be the weight matrix input to the reset gate. hr Let b be the weight matrix from the hidden state to the reset gate. r To reset the gate's bias vector;

[0021] The update gate is implemented using the following model:

[0022]

[0023] W xz W is the weight matrix input to the update gate. hz Let b be the weight matrix from the hidden state to the update gate. z To update the bias vector of the gate;

[0024] The candidate hidden state is represented as follows:

[0025]

[0026] tanh() is the hyperbolic tangent activation function, W xh W is the weight matrix input to the candidate hidden state. hh Let r be the weight matrix from the hidden state to the candidate state. t For the reset gate, ⊙ represents element-wise multiplication, b h is the bias vector of the candidate hidden state;

[0027] The final hidden state is represented as follows:

[0028]

[0029] Z t To update the door, This is the candidate hidden state.

[0030] In some alternative implementations, the final GRUM prediction model includes a fully connected layer and an output layer, wherein:

[0031] The formula for a fully connected layer is:

[0032]

[0033] l is the layer index. The output of the l-th layer is linear. The activation output of layer (l-1) Let σ be the bias vector of the l-th layer, and let σ() represent the activation function.

[0034] The formula for the output layer is as follows:

[0035]

[0036] The GRUM prediction model output is represented by sigmoid(), which is an activation function that compresses the output to the range (0,1). This is the output layer weight matrix. This is the output layer bias vector.

[0037] According to a second aspect of this application, a NAND flash memory read voltage axis prediction device is provided, comprising:

[0038] The acquisition unit is used to perform characteristic tests on different types of NAND under different operating conditions and acquire the corresponding voltage axis data and its characteristic parameters.

[0039] The normalization unit is used to clean and normalize the acquired data.

[0040] The building unit is used to build a GRUM model that includes a first GRU branch and a second GRU branch. The first type of data in the normalized data is input into the first GRU branch for training to obtain the first GRU model. The second type of data in the normalized data is input into the second GRU branch for training to obtain the second GRU model. The outputs of the first GRU model and the outputs of the second GRU model are cross-fused to form the final GRUM prediction model.

[0041] The output unit is used to obtain the actual programming / erasing cycle and actual data retention time of the target NAND flash memory, input them into the final GRUM prediction model for prediction, and output the optimal read voltage axis prediction value of the target NAND flash memory.

[0042] In some alternative implementations, the building unit is further configured to perform multiple read operations and collect feedback actual voltage axis values ​​during idle periods of the target NAND flash memory; and to use the feedback actual voltage axis values ​​to train the final GRUM prediction model online, thereby updating the weight parameters of the final GRUM prediction model.

[0043] In some optional implementations, the building unit is further configured to use the output of the second GRU model as a feature representation, output the best read voltage axis prediction value of NAND through the fully connected layer structure of the final GRUM prediction model; obtain the actual measured value of the read voltage axis of NAND, evaluate the prediction result of the voltage axis prediction value using the actual measured value, and adjust the parameters and weights of the final GRUM prediction model as the updated GRUM prediction model.

[0044] In some optional implementations, both the first GRU branch and the second GRU branch include a reset gate, an update gate, a candidate hidden state, and a final hidden state, which have the same structure and independent parameters, wherein:

[0045] The reset door is implemented through the following model:

[0046]

[0047] x t The input for the current data step is t, where t is the time step and h is the time step. t h represents the hidden state at the current time step. t-1 Let W be the hidden state at the previous time step, σ() represent the activation function, and Wxr be the weight matrix input to the reset gate. hr Let b be the weight matrix from the hidden state to the reset gate. r To reset the gate's bias vector;

[0048] The update gate is implemented using the following model:

[0049]

[0050] W xz W is the weight matrix input to the update gate. hz Let b be the weight matrix from the hidden state to the update gate. z To update the bias vector of the gate;

[0051] The candidate hidden state is represented as follows:

[0052]

[0053] tanh() is the hyperbolic tangent activation function, W xh W is the weight matrix input to the candidate hidden state. hh Let r be the weight matrix from the hidden state to the candidate state. t For the reset gate, ⊙ represents element-wise multiplication, b h is the bias vector of the candidate hidden state;

[0054] The final hidden state is represented as follows:

[0055]

[0056] Z t To update the door, This is the candidate hidden state.

[0057] In some alternative implementations, the final GRUM prediction model includes a fully connected layer and an output layer, wherein:

[0058] The formula for a fully connected layer is:

[0059]

[0060] l is the layer index. The output of the l-th layer is linear. The activation output of layer (l-1) Let σ be the bias vector of the l-th layer, and let σ() represent the activation function.

[0061] The formula for the output layer is as follows:

[0062]

[0063] The GRUM prediction model output is represented by sigmoid(), which is an activation function that compresses the output to the range (0,1). This is the output layer weight matrix. This is the output layer bias vector.

[0064] According to a third aspect of this application, a non-transitory computer-readable storage medium is provided that stores computer instructions for causing a computer to perform the steps of the NAND flash memory read voltage axis prediction method.

[0065] According to a fourth aspect of this application, an electronic device is provided, comprising:

[0066] At least one processor; and

[0067] A memory communicatively connected to the at least one processor; wherein,

[0068] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the steps of the NAND flash memory read voltage axis prediction method.

[0069] The technical solution of this application, by constructing a GRUM model, fully considers the multidimensional characteristics of NAND flash memory and its complex relationship with read voltage, achieving accurate prediction of the optimal read voltage axis for NAND. This application can better capture and process the nonlinear relationships and spatiotemporal dependencies of NAND flash memory data, thereby improving prediction accuracy. The GRUM model of this application can adaptively learn the characteristic differences between different NAND flash memory chips, enabling the model to maintain high prediction performance even when facing new types or batches of NAND flash memory. This helps reduce the cost of retraining and debugging the model in different application scenarios. Through an online training mechanism, the model can continuously adjust its parameters based on feedback data from actual read operations, thereby better adapting to the dynamic changes of NAND flash memory. This ensures that the model maintains high performance and high reliability during long-term operation. The efficient computational power and dynamic adjustment mechanism of the GRUM model enable the system to significantly reduce power consumption while maintaining high performance. By optimizing the read voltage axis in real time, unnecessary read operations and error corrections are reduced, thereby improving the system's energy efficiency ratio, making it particularly suitable for power-sensitive applications such as mobile devices and embedded systems.

[0070] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0071] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, wherein:

[0072] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0073] Figure 1 A flowchart illustrating the NAND flash memory read voltage axis prediction method according to an embodiment of this application is shown;

[0074] Figure 2 A schematic diagram illustrating the implementation flow of the NAND flash memory read voltage axis prediction method according to an embodiment of this application is shown;

[0075] Figure 3 A schematic diagram of the structure of a GRUM unit according to an embodiment of this application is shown;

[0076] Figure 4 A schematic diagram of GRUM model generation according to an embodiment of this application is shown;

[0077] Figure 5A schematic diagram illustrating the online training and dynamic adjustment process according to an embodiment of this application is shown;

[0078] Figure 6 A schematic diagram of the composition structure of the NAND flash memory read voltage axis prediction device according to an embodiment of this application is shown;

[0079] Figure 7 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0080] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0081] NAND flash memory voltage axis prediction involves dynamically analyzing and predicting the read voltage axis of memory cells to accurately determine the logical state of data within those cells, thereby improving read accuracy and reliability. Especially with the increasing interference and wider threshold voltage distribution caused by continuous process node shrinkage, voltage axis prediction technology has become a key means of improving NAND flash memory performance and lifespan. Its core lies in using statistical models or machine learning algorithms to model voltage distribution characteristics and continuously optimizing the prediction model based on actual read data to adapt to different operating conditions and aging effects. The following specific examples illustrate the essence of the technical solution in this application.

[0082] Figure 1 A flowchart illustrating the NAND flash memory read voltage axis prediction method according to an embodiment of this application is shown, as follows: Figure 1 As shown, the NAND flash memory read voltage axis prediction method of this application embodiment includes the following processing steps:

[0083] Step 101: Perform characteristic tests on different types of NAND under different operating conditions to obtain the corresponding voltage axis data and characteristic parameters.

[0084] In this embodiment, the optimal read voltage axis characteristic test was obtained for various types of NAND flash memory under different aging and operating conditions, and the characteristic parameters and results were recorded. The characteristic parameters include at least the number of erase (PE) cycles, data retention (RET) time, and threshold voltage (VTH). The NAND flash memory has PE cycles ranging from 1,000 to 10,000 cycles; the NAND flash memory has a data retention (RET) time spanning from 1 hour to 1 year; and the NAND flash memory has a VTH distribution with no more than 7 threshold voltage curves.

[0085] In this application embodiment, different types of NAND flash memory include at least: NAND flash memory manufactured using one of the following processes: single-layer cell (SLC), multi-layer cell (MLC), three-layer cell (TLC), and four-layer cell (QLC).

[0086] Step 102: Clean the acquired data and perform normalization.

[0087] In this embodiment, the acquired data is preprocessed to remove outliers and inconsistent data points, ensuring the accuracy of subsequent analysis.

[0088] Step 103: Construct a GRUM model that includes a first GRU branch and a second GRU branch. Input the first type of data from the normalized data into the first GRU branch for training to obtain the first GRU model. Input the second type of data from the normalized data into the second GRU branch for training to obtain the second GRU model. Cross-fuse the outputs of the first GRU model and the second GRU model to form the final GRUM prediction model.

[0089] In this embodiment of the application, the relevant data features of PE are input into the first GRU model, and the data features of RET are input into the second GRU model.

[0090] Both the first GRU branch and the second GRU branch include a reset gate, an update gate, a candidate hidden state, and a final hidden state. They have the same structure, but their parameters are independent of each other.

[0091] The reset door is implemented through the following model:

[0092]

[0093] x t The input for the current data step is t, where t is the time step and h is the time step. t h represents the hidden state at the current time step. t-1 Let W be the hidden state at the previous time step, σ() represent the activation function, and Wxr be the weight matrix input to the reset gate. hr Let b be the weight matrix from the hidden state to the reset gate. r To reset the gate's bias vector;

[0094] The update gate is implemented using the following model:

[0095]

[0096] W xz W is the weight matrix input to the update gate. hz Let b be the weight matrix from the hidden state to the update gate.z To update the bias vector of the gate;

[0097] The candidate hidden state is represented as follows:

[0098]

[0099] tanh() is the hyperbolic tangent activation function, W xh W is the weight matrix input to the candidate hidden state. hh Let r be the weight matrix from the hidden state to the candidate state. t For the reset gate, ⊙ represents element-wise multiplication, b h is the bias vector of the candidate hidden state;

[0100] The final hidden state is represented as follows:

[0101]

[0102] Z t To update the door, This is the candidate hidden state.

[0103] The final GRUM prediction model consists of a fully connected layer and an output layer. The GRUM prediction model is formed by fusing the first GRU branch and the second GRU branch. This fusing can be additive fusing, dot product fusing, or additive fusing after assigning appropriate weight values. Specifically:

[0104] The formula for a fully connected layer is:

[0105]

[0106] l is the layer index. The output of the l-th layer is linear. The activation output of layer (l-1) Let σ be the bias vector of the l-th layer, and let σ() represent the activation function.

[0107] The formula for the output layer is as follows:

[0108]

[0109] The GRUM prediction model output is represented by sigmoid(), which is an activation function that compresses the output to the range (0,1). This is the output layer weight matrix. This is the output layer bias vector.

[0110] Step 104: Obtain the actual programming / erasing cycle and actual data retention time of the target NAND flash memory, input them into the final GRUM prediction model for prediction, and output the optimal read voltage axis prediction value of the target NAND flash memory.

[0111] In this embodiment, the GRUM model training phase first initializes the weights and biases of the neural network. Then, forward propagation is performed during training, with training data input into the network. Through linear and nonlinear transformations between layers, the predicted output is finally obtained. The mean squared error is then used as a loss function to calculate the difference between the network's predicted output and the true label. The gradient of the model parameters using the loss function is used for backpropagation to guide the update of the network weights. Finally, the Adam optimization algorithm is used to update the network weights based on the gradient information obtained from backpropagation. This process is iterative, with each iteration consisting of one forward propagation and one backpropagation, followed by weight updates.

[0112] In this embodiment, during the idle period of the target NAND flash memory, multiple read operations are performed and the actual voltage axis value is collected. The actual voltage axis value is used to train the final GRUM prediction model online and update the weight parameters of the final GRUM prediction model.

[0113] In this embodiment of the application, the method further includes: using the output of the second GRU model as a feature representation, outputting the best read voltage axis prediction value of NAND through the fully connected layer structure of the final GRUM prediction model; obtaining the actual measured value of the read voltage axis of NAND, evaluating the prediction result of the voltage axis prediction value using the actual measured value, and adjusting the parameters and weights of the final GRUM prediction model as the updated GRUM prediction model.

[0114] In this embodiment, by constructing a GRUM model, the multidimensional characteristics of NAND flash memory and its complex relationship with read voltage are fully considered, achieving accurate prediction of the optimal read voltage axis for NAND. Compared to traditional methods, this invention can better capture and process the nonlinear relationships and spatiotemporal dependencies of NAND flash memory data, thereby improving prediction accuracy. The GRUM model can adaptively learn the characteristic differences between different NAND flash memory chips, enabling the model to maintain high prediction performance even when facing new types or batches of NAND flash memory. This improved generalization ability helps reduce the cost of retraining and debugging the model in different application scenarios.

[0115] Figure 2 A schematic diagram illustrating the implementation flow of the NAND flash memory read voltage axis prediction method according to an embodiment of this application is shown, as follows: Figure 2 As shown, the specific processing steps include the following:

[0116] Data collection phase: First, by simulating different working conditions and usage environments, the optimal read voltage axis of various NAND models under different PE and RET conditions is collected.

[0117] Data preprocessing stage: The collected data is preprocessed to remove outliers and inconsistent data points, ensuring the accuracy of subsequent analysis.

[0118] GRUM Model Construction: First, GRUM is a variant model based on GRU with multi-branch cross-fusion. The unit structure of GRUM is as follows: Figure 3 As shown, different input features are fed into the corresponding training paths, and the training results of the P branch are fed back to the R branch as historical data to continue being passed down. The outputs of the two branches are cross-fused to form the final GRUM model. Figure 4 As shown.

[0119] Training and Optimization Phases: The model training phase begins by initializing the weights and biases of the neural network. Then, forward propagation is performed during training. Training data is input into the network, and through linear and non-linear transformations between layers, the predicted output is obtained. The mean squared error is then used as the loss function to calculate the difference between the network's predicted output and the true label. The gradient of the model parameters using the loss function is then used for backpropagation to guide the update of the network weights. Finally, the Adam optimization algorithm is used to update the network weights based on the gradient information obtained from backpropagation. This process is iterative, with each iteration consisting of one forward propagation and one backpropagation, followed by weight updates.

[0120] Online training and dynamic tuning phase: During idle periods of the NAND flash memory, multiple read operations are performed to collect feedback voltage axis values. These feedback values ​​are used to train the GRUM model online, re-acquire weight values, and further optimize the model's predictive performance. The overall process of online training and dynamic tuning is as follows: Figure 5 As shown.

[0121] Prediction Output and Evaluation Stage: Known NAND operating conditions (PE cycles and RET duration) are used as input. The output of the last GRU branch is then used as a feature representation. The optimal read voltage axis prediction value for the NAND is output through structures such as fully connected layers. Finally, the prediction results are evaluated by comparing them with actual measurements to verify the accuracy and robustness of the prediction model.

[0122] Figure 6 A schematic diagram of the composition structure of the NAND flash memory read voltage axis prediction device according to an embodiment of this application is shown, as follows: Figure 6 As shown, the NAND flash memory read voltage axis prediction device according to an embodiment of this application includes:

[0123] The acquisition unit 60 is used to perform characteristic tests on different types of NAND under different operating conditions and acquire the corresponding voltage axis data and its characteristic parameters.

[0124] Normalization unit 61 is used to clean and normalize the acquired data;

[0125] The construction unit 62 is used to construct a GRUM model that includes a first GRU branch and a second GRU branch. The first type of data in the normalized data is input into the first GRU branch for training to obtain the first GRU model. The second type of data in the normalized data is input into the second GRU branch for training to obtain the second GRU model. The outputs of the first GRU model and the outputs of the second GRU model are cross-fused to form the final GRUM prediction model.

[0126] Output unit 63 is used to obtain the actual programming / erasing cycle and actual data retention time of the target NAND flash memory, input them into the final GRUM prediction model for prediction, and output the optimal read voltage axis prediction value of the target NAND flash memory.

[0127] In this embodiment, the construction unit 62 is further configured to perform multiple read operations and collect feedback actual voltage axis values ​​during the idle period of the target NAND flash memory; use the feedback actual voltage axis values ​​to train the final GRUM prediction model online, and update the weight parameters of the final GRUM prediction model. The construction unit 62 is also configured to use the output of the second GRU model as a feature representation, output the best read voltage axis prediction value of the NAND through the fully connected layer structure of the final GRUM prediction model; obtain the actual measured value of the NAND read voltage axis, evaluate the prediction result of the voltage axis prediction value using the actual measured value, and adjust the parameters and weights of the final GRUM prediction model as the updated GRUM prediction model.

[0128] In this embodiment, both the first GRU branch and the second GRU branch include a reset gate, an update gate, a candidate hidden state, and a final hidden state. They have the same structure and their parameters are independent of each other.

[0129] The reset door is implemented through the following model:

[0130]

[0131] x t The input for the current data step is t, where t is the time step and h is the time step. t h represents the hidden state at the current time step. t-1 Let W be the hidden state at the previous time step, σ() represent the activation function, and Wxr be the weight matrix input to the reset gate. hr Let b be the weight matrix from the hidden state to the reset gate.r To reset the gate's bias vector;

[0132] The update gate is implemented using the following model:

[0133]

[0134] W xz W is the weight matrix input to the update gate. hz Let b be the weight matrix from the hidden state to the update gate. z To update the bias vector of the gate;

[0135] The candidate hidden state is represented as follows:

[0136]

[0137] tanh() is the hyperbolic tangent activation function, W xh W is the weight matrix input to the candidate hidden state. hh Let r be the weight matrix from the hidden state to the candidate state. t For the reset gate, ⊙ represents element-wise multiplication, b h is the bias vector of the candidate hidden state;

[0138] The final hidden state is represented as follows:

[0139]

[0140] Z t To update the door, This is the candidate hidden state.

[0141] The final GRUM prediction model consists of a fully connected layer and an output layer, where:

[0142] The formula for a fully connected layer is:

[0143]

[0144] l is the layer index. The output of the l-th layer is linear. The activation output of layer (l-1) Let σ be the bias vector of the l-th layer, and let σ() represent the activation function.

[0145] The formula for the output layer is as follows:

[0146]

[0147] The GRUM prediction model output is represented by sigmoid(), which is an activation function that compresses the output to the range (0,1). This is the output layer weight matrix. This is the output layer bias vector.

[0148] In an exemplary embodiment, each processing unit in the NAND flash memory read voltage axis prediction device of this application embodiment may be implemented by one or more central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components.

[0149] Regarding the apparatus in the above embodiments, the specific manner in which each module and unit performs its operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0150] According to embodiments of this application, this application also describes an electronic device and a readable storage medium.

[0151] Figure 7 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0152] like Figure 7As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 802 or a computer program loaded from storage unit 808 into random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0153] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of monitors, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0154] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the NAND flash memory read voltage axis prediction method. For example, in some embodiments, the NAND flash memory read voltage axis prediction method can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the NAND flash memory read voltage axis prediction method described above can be performed. Alternatively, in other embodiments, the computing unit 801 may be configured by any other suitable means (e.g., by means of firmware) to perform the steps of the NAND flash read voltage axis prediction method.

[0155] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0156] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0157] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0158] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0159] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0160] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0161] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0162] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0163] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for predicting the read voltage axis of NAND flash memory, characterized in that, The method includes: Perform characteristic tests on different types of NAND under different operating conditions to obtain the corresponding voltage axis data and characteristic parameters; The acquired data is cleaned and normalized. A GRUM model containing a first GRU branch and a second GRU branch is constructed. The first type of data in the normalized data is input into the first GRU branch for training to obtain the first GRU model. The second type of data in the normalized data is input into the second GRU branch for training to obtain the second GRU model. The outputs of the first GRU model and the outputs of the second GRU model are cross-fused to form the final GRUM prediction model. The first type of data includes relevant data features of PE, and the second type of data includes data features of RET. Obtain the actual programming / erasing cycle and actual data retention time of the target NAND flash memory, input them into the final GRUM prediction model for prediction, and output the optimal read voltage axis prediction value of the target NAND flash memory; The output of the second GRU model is used as a feature representation, and the best read voltage axis prediction value of NAND is output through the fully connected layer structure of the final GRUM prediction model. Obtain the actual measured value of the NAND read voltage axis, evaluate the prediction result of the voltage axis prediction value using the actual measured value, and adjust the parameters and weights of the final GRUM prediction model as the updated GRUM prediction model. Both the first GRU branch and the second GRU branch include a reset gate, an update gate, a candidate hidden state, and a final hidden state. They have the same structure and their parameters are independent of each other. The reset door is implemented through the following model: x t The input for the current data step is t, where t is the time step and h is the time step. t h represents the hidden state at the current time step. t-1 Let W be the hidden state at the previous time step, σ() represent the activation function, and Wxr be the weight matrix input to the reset gate. hr Let b be the weight matrix from the hidden state to the reset gate. r To reset the gate's bias vector; The update gate is implemented using the following model: W xz W is the weight matrix input to the update gate. hz Let b be the weight matrix from the hidden state to the update gate. z To update the bias vector of the gate; The candidate hidden state is represented as follows: tanh() is the hyperbolic tangent activation function, W xh W is the weight matrix input to the candidate hidden state. hh Let r be the weight matrix from the hidden state to the candidate state. t For the reset gate, ⊙ represents element-wise multiplication, b h is the bias vector of the candidate hidden state; The final hidden state is represented as follows: Z t To update the door, This is the candidate hidden state.

2. The method according to claim 1, characterized in that, The method further includes: During the idle period of the target NAND flash memory, perform multiple read operations and collect feedback on the actual voltage axis value; The actual voltage axis value of the feedback is used to train the final GRUM prediction model online, and the weight parameters of the final GRUM prediction model are updated.

3. The method according to claim 1, characterized in that, The final GRUM prediction model includes a fully connected layer and an output layer, wherein: The formula for a fully connected layer is: l is the layer index. The output of the l-th layer is linear. The activation output of layer (l-1) Let σ be the bias vector of the l-th layer, and let σ() represent the activation function. The formula for the output layer is as follows: The GRUM prediction model output is represented by sigmoid(), which is an activation function that compresses the output to the range (0,1). This is the output layer weight matrix. This is the output layer bias vector.

4. A NAND flash memory read voltage axis prediction device, characterized in that, The device includes: The acquisition unit is used to perform characteristic tests on different types of NAND under different operating conditions and acquire the corresponding voltage axis data and its characteristic parameters. The normalization unit is used to clean and normalize the acquired data. A construction unit is used to construct a GRUM model containing a first GRU branch and a second GRU branch. First-class data from normalized data is input into the first GRU branch for training to obtain the first GRU model. Second-class data from normalized data is input into the second GRU branch for training to obtain the second GRU model. The outputs of the first GRU model and the second GRU model are cross-fused to form the final GRUM prediction model. The first-class data includes PE-related data features, and the second-class data includes RET-related data features. The output unit is used to obtain the actual programming / erasing cycle and actual data retention time of the target NAND flash memory, input them into the final GRUM prediction model for prediction, and output the best read voltage axis prediction value of the target NAND flash memory. The building unit is also used to take the output of the second GRU model as a feature representation, output the best read voltage axis prediction value of NAND through the fully connected layer structure of the final GRUM prediction model; obtain the actual measured value of the read voltage axis of NAND, evaluate the prediction result of the voltage axis prediction value using the actual measured value, and adjust the parameters and weights of the final GRUM prediction model as the updated GRUM prediction model. Both the first GRU branch and the second GRU branch include a reset gate, an update gate, a candidate hidden state, and a final hidden state. They have the same structure and their parameters are independent of each other. The reset door is implemented through the following model: x t The input for the current data step is t, where t is the time step and h is the time step. t h represents the hidden state at the current time step. t-1 Let W be the hidden state at the previous time step, σ() represent the activation function, and Wxr be the weight matrix input to the reset gate. hr Let b be the weight matrix from the hidden state to the reset gate. r To reset the gate's bias vector; The update gate is implemented using the following model: W xz W is the weight matrix input to the update gate. hz Let b be the weight matrix from the hidden state to the update gate. z To update the bias vector of the gate; The candidate hidden state is represented as follows: tanh() is the hyperbolic tangent activation function, W xh W is the weight matrix input to the candidate hidden state. hh Let r be the weight matrix from the hidden state to the candidate state. t For the reset gate, ⊙ represents element-wise multiplication, b h is the bias vector of the candidate hidden state; The final hidden state is represented as follows: Z t To update the door, This is the candidate hidden state.

5. The apparatus according to claim 4, characterized in that, The final GRUM prediction model includes a fully connected layer and an output layer, wherein: The formula for a fully connected layer is: l is the layer index. The output of the l-th layer is linear. The activation output of layer (l-1) Let σ be the bias vector of the l-th layer, and let σ() represent the activation function. The formula for the output layer is as follows: The GRUM prediction model output is represented by sigmoid(), which is an activation function that compresses the output to the range (0,1). This is the output layer weight matrix. This is the output layer bias vector.

6. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the steps of the NAND flash memory read voltage axis prediction method according to any one of claims 1 to 3.

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