Chip packaging structure and packaging method

Abstract

The chip packaging structure comprises a substrate, a chip and a first circuit, the chip and the first circuit are located on the two sides of the substrate in the thickness direction of the substrate respectively, the substrate comprises a through hole, a metal column formed in the through hole and a stress buffer layer located between the metal column and the through hole, and the stress buffer layer is located between the metal column and the through hole. One end of the metal column is electrically connected with the chip, and the other end of the metal column is electrically connected with the first circuit; the stress buffer layer is used for solving the problem of thermal stress between the metal columns and the through holes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging and testing, and more particularly to a chip packaging structure and packaging method. Background Technology

[0002] With the ever-increasing demands of electronic products, semiconductor packaging technology has evolved from two-dimensional to three-dimensional structures, which places higher requirements on high-density integration and stacked packaging. Currently, vertical interconnect structures are widely used in three-dimensional integrated packaging.

[0003] Vertical interconnect structures further include through-silicon vias (TSVs), through-hole vias (TVs), and through-hole vias (TVs). The coefficients of thermal expansion of silicon, molding compound, glass, and conductive metal materials differ significantly. During the packaging heating process, the difference in thermal expansion between the TV and metal materials creates thermal stress, causing varying degrees of deformation. Abnormal deformation can affect the packaging and electrical connections, for example, impacting the stability and reliability of the packaging structure and leading to electrical connection failures in the vertical interconnect structure. Summary of the Invention

[0004] One of the objectives of this invention is to provide a chip packaging structure to solve the technical problem of thermal stress between through-holes and metal pillars in the prior art.

[0005] One of the objectives of this invention is to provide a chip packaging method.

[0006] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a chip packaging structure, including a substrate, chips and a first circuit located on both sides of the substrate along its thickness direction, the substrate including a through hole, a metal pillar formed in the through hole and a stress buffer layer located between the metal pillar and the through hole, one end of the metal pillar being electrically connected to the chip and the other end being electrically connected to the first circuit.

[0007] As a further improvement of one embodiment of the present invention, the stress buffer layer and the metal column are aligned along the thickness direction and have the same height.

[0008] As a further improvement of one embodiment of the present invention, the end face of the metal pillar facing the first circuit and the surface of the substrate facing the first circuit are located on the same horizontal plane; the end face of the metal pillar facing the chip and the surface of the substrate facing the chip are located on the same horizontal plane.

[0009] As a further improvement of one embodiment of the present invention, the chip packaging structure includes a second line formed between the chip and the substrate, the second line being electrically connected to the chip and the metal pillar.

[0010] As a further improvement of one embodiment of the present invention, the end face of the metal pillar facing the first circuit and the surface of the substrate facing the first circuit are located on the same horizontal plane; the end face of the metal pillar facing the chip extends into the second circuit and is thus higher than the surface of the substrate facing the chip.

[0011] As a further improvement of one embodiment of the present invention, the second line includes a first wiring layer and a second wiring layer disposed along the thickness direction and electrically connected, the first wiring layer being close to the substrate and electrically connected to the substrate, and the second wiring layer being close to the chip and electrically connected to the chip.

[0012] As a further improvement of one embodiment of the present invention, the first wiring layer includes a dielectric layer and a metal layer, the second wiring layer includes a dielectric layer and a metal layer, the metal pillar is offset from the metal layer of the first wiring layer, and passes through the dielectric layer of the first wiring layer to be electrically connected to the metal layer of the second wiring layer.

[0013] As a further improvement of one embodiment of the present invention, the chip includes chip pads, and the chip package structure includes conductive bumps, the conductive bumps being electrically connected to the chip pads and the second circuit.

[0014] As a further improvement of one embodiment of the present invention, the chip packaging structure includes a first molding layer formed between the chip and the second circuit, the first molding layer encapsulating the conductive bump.

[0015] As a further improvement of one embodiment of the present invention, the chip includes a first dielectric film and a first pad formed on its surface, the first pad being exposed to the first dielectric film. As a further improvement of one embodiment of the present invention, the second line includes a second dielectric film and a second pad formed on its surface, the second pad being exposed to the second dielectric film; the first pad is mixed-bonded to the second pad.

[0016] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a chip packaging method, comprising the following steps: A substrate is provided, and a groove is formed on a first side of the substrate; A stress buffer layer is fabricated on the wall of the groove; A metal column is fabricated, and the metal column fills the groove; Provide a chip, and connect the substrate and the chip; A first circuit is formed on the second side of the substrate, the first and second sides of the substrate are disposed opposite to each other, and the metal pillars electrically connect the chip and the first circuit.

[0017] As a further improvement of one embodiment of the present invention, the fabrication of the stress buffer layer includes: filling a first side of the substrate with a stress buffer material; the stress buffer layer covers the surface of the substrate and the inner wall of the groove.

[0018] As a further improvement of one embodiment of the present invention, the fabrication of the metal pillar includes: fabricating a metal structure on a first side of the substrate, the metal structure including a metal pillar filling the groove, and the stress buffer layer being located between the metal pillar and the inner wall of the groove.

[0019] As a further improvement of one embodiment of the present invention, after fabricating the metal pillar, the process includes: fabricating a second circuit on a first side of the substrate, wherein the metal pillar is electrically connected to the second circuit.

[0020] As a further improvement of one embodiment of the present invention, the method of forming a groove on the first side of the substrate includes: first forming a first wiring layer on the first side of the substrate, and then forming a groove, wherein the groove extends through the first wiring layer to the substrate.

[0021] As a further improvement of one embodiment of the present invention, the fabrication of the stress buffer layer includes: filling the surface of the first wiring layer with a stress buffer material; the stress buffer layer covers the surface of the first wiring layer and the inner wall surface of the groove.

[0022] As a further improvement of one embodiment of the present invention, after fabricating the metal pillar, the process includes: fabricating a second wiring layer on a first side of the substrate, the second wiring layer being stacked on the first wiring layer and electrically connected to the first wiring layer, and the metal pillar being electrically connected to the second wiring layer.

[0023] As a further improvement of one embodiment of the present invention, a chip is provided, and connecting the substrate and the chip includes: the chip pads of the chip are connected to a second line by a soldering method, or the chip and the second line are connected by a hybrid bonding method.

[0024] As a further improvement of one embodiment of the present invention, before forming the first line on the second side of the substrate, the method includes: grinding the second side of the substrate, forming the groove into a through hole, and exposing the metal post on the second side of the substrate to electrically connect the first line. Compared with the prior art, the present invention provides a chip packaging structure, wherein the substrate includes a through hole, a metal pillar formed in the through hole, and a stress buffer layer located between the metal pillar and the through hole. The stress buffer layer is used to alleviate the large difference in the coefficient of thermal expansion between the metal pillar material and the through hole material, and to reduce the stress caused by temperature changes. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the chip packaging structure in the first embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of the chip packaging structure in the second embodiment of the present invention.

[0027] Figure 3 This is a schematic diagram of the chip packaging structure in the third embodiment of the present invention.

[0028] Figure 4 This is a schematic flowchart of a chip packaging method according to one embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram of a method for providing a chip in the first embodiment of the present invention.

[0030] Figure 6 This is a schematic diagram of a method for providing a substrate in the first embodiment of the present invention.

[0031] Figure 7 This is a schematic diagram of the method for fabricating a stress buffer layer and a metal pillar in the first embodiment of the present invention.

[0032] Figure 8 This is a schematic diagram of the connection between the chip and the substrate in the first embodiment of the present invention.

[0033] Figure 9 This is a schematic diagram of a method for manufacturing a first circuit according to the first embodiment of the present invention.

[0034] Figure 10 This is a schematic diagram of a method for connecting a substrate and a circuit board and encapsulating them according to the first embodiment of the present invention.

[0035] Figure 11 This is a schematic diagram of a method for providing a chip in the second embodiment of the present invention.

[0036] Figure 12 This is a schematic diagram of a method for providing a substrate in the second embodiment of the present invention.

[0037] Figure 13 This is a schematic diagram of the method for fabricating a stress buffer layer and a metal pillar in the second embodiment of the present invention.

[0038] Figure 14 This is a schematic diagram of the connection between the chip and the substrate in the second embodiment of the present invention.

[0039] Figure 15 This is a schematic diagram of the method for manufacturing the first circuit in the second embodiment of the present invention.

[0040] Figure 16 This is a schematic diagram of a method for connecting a substrate and a circuit board and encapsulating them according to the second embodiment of the present invention.

[0041] Figure 17This is a schematic diagram of a method for providing a chip in the third embodiment of the present invention.

[0042] Figure 18 This is a schematic diagram of a method for providing a substrate according to the third embodiment of the present invention.

[0043] Figure 19 This is a schematic diagram of the method for fabricating a stress buffer layer and a metal pillar in the third embodiment of the present invention.

[0044] Figure 20 This is a schematic diagram of the connection between the chip and the substrate in the third embodiment of the present invention.

[0045] Figure 21 This is a schematic diagram of the method for manufacturing the first circuit in the third embodiment of the present invention.

[0046] Figure 22 This is a schematic diagram of a method for connecting a substrate and a circuit board and encapsulating them according to the third embodiment of the present invention. Detailed Implementation

[0047] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0048] It should be noted that the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," "third," "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0049] The terms “connection,” “connected to,” or any other variations are intended to encompass various relative positions where a connection exists, including both direct and indirect connections. A direct connection can be formed through a pneumatic conduit, while an indirect connection can be formed through devices such as valves or sensors, through pneumatic components such as brake control units, or through any other medium such as air.

[0050] Please see Figure 1This is a schematic diagram of a chip packaging structure 100 provided in the first embodiment of the present invention. The chip packaging structure 100 includes a substrate 10, a chip 20 and a first circuit 30 respectively located on both sides of the substrate 10 along its thickness direction. The substrate 10 includes a through hole 11, a metal pillar 12 formed in the through hole 11, and a stress buffer layer 13 located between the metal pillar 12 and the through hole 11. One end of the metal pillar 12 is electrically connected to the chip 20, and the other end is electrically connected to the first circuit 30.

[0051] The metal pillar 12 is equivalent to a vertical interconnect structure, used to realize the electrical connection between the chip 20 and the second line 30. The metal pillar 12 is preferably a copper pillar. The substrate 10 can be made of silicon, glass, ceramic, etc. It is known that the substrate 10 material and the metal pillar 12 have different coefficients of thermal expansion. When the temperature changes, thermal stress is generated between the substrate 10 and the metal pillar 12, affecting the stability and electrical function of the chip package structure 100. In this application, a stress buffer layer 13 is provided between the metal pillar 12 and the through hole 11 to alleviate the difference in the coefficients of thermal expansion between the materials of the metal pillar 12 and the through hole 11, and reduce the stress caused by temperature changes. In a specific embodiment, the stress buffer layer 13 material can be a polymer or a composite.

[0052] Understandably, the stress buffer layer 13 serves as a barrier to prevent unwanted penetration between the two materials, maintaining a clear and stable interface; it can also prevent defects in the substrate 10, such as cracks in the substrate 10 extending to the metal pillar 12. The stress buffer layer 13 also provides mechanical support, offering additional mechanical strength and stability.

[0053] The stress buffer layer 13 and the metal pillar 12 are aligned along the thickness direction and are at the same height. The stress buffer layer 13 completely covers the outer periphery of the metal pillar 12, thus completely separating the metal pillar 12 and the through-hole 11. The end face of the metal pillar 12 facing the first circuit 30 and the end face of the stress buffer layer 13 facing the first circuit 30 are located on the same horizontal plane. The end face of the metal pillar 12 facing the chip 20 and the end face of the stress buffer layer 13 facing the chip 20 are located on the same horizontal plane.

[0054] In one embodiment, the end face of the metal pillar 12 facing the first line 30 and the surface of the substrate 10 facing the first line 30 are on the same horizontal plane. One end of the metal pillar 12 and the stress buffer layer 13 is flush with the surface of the substrate 10, so that they do not protrude into the first line 30. The end face of the metal pillar 12 facing the chip 20 and the surface of the substrate 10 facing the chip 20 are on the same horizontal plane. The other end of the metal pillar 12 and the stress buffer layer 13 is also flush with the other surface of the substrate 10, so that they do not protrude toward the chip 20.

[0055] Combination Figure 1, 3 As shown, in the first and third embodiments of this application, the metal pillar 12 and the stress buffer layer 13 are completely located within the substrate 10, as long as the stress buffer layer 13 can completely enclose the metal pillar 12.

[0056] In one embodiment, the chip package structure 100 includes a second line 40 formed between the chip 20 and the substrate 10, the second line 40 electrically connecting the chip 20 and the metal pillar 12. The substrate 10 includes a first side and a second side opposite to each other. It is understood that the first side of the substrate 10 corresponds to one of its surface surfaces and the space it occupies, and the second side of the substrate 20 corresponds to its other surface surface and the space it occupies.

[0057] The second line 40 and the chip 20 are disposed on the first side of the substrate 10, and the first line 30 is disposed on the second side of the substrate 20. More specifically, the second line 40 and the first line 30 are formed on the first and second side surfaces of the substrate 10, and the two ends of the metal pillar 12 are electrically connected to the second line 40 and the first line 30, respectively. The chip 20 is disposed on the side of the second line 40 facing away from the substrate 10, and the chip 20 is electrically connected to the second line 40, thereby being electrically connected to the first line 30 through the metal pillar 12.

[0058] The end face of the metal pillar 12 facing the first line 30 and the surface of the substrate 10 facing the first line 30 are located on the same horizontal plane; the end face of the metal pillar 12 facing the chip 20 extends into the second line 40, thus being higher than the surface of the substrate 10 facing the chip 20. Figure 2 As shown, the difference between the second embodiment and the first embodiment of this application is that the metal pillar 12 and the stress buffer layer 13 extend into the second line 40 on the end face of the chip, which is beneficial for the second line 40 to form a finer metal line. The chip packaging method will be described in detail below.

[0059] In the second embodiment of this application, the second line 40 is close to the chip 20, and the corresponding line layer has higher precision requirements. Therefore, a metal pillar 12 and a stress buffer layer 13 are provided to protrude into the second line 40. In other embodiments, the metal pillar 12 and the stress buffer layer 13 may also be provided to protrude into the first line 30 as needed, or the metal pillar 12 and the stress buffer layer 13 may protrude into both the first line 30 and the second line 40 simultaneously.

[0060] The second line 40 includes a plurality of wiring layers arranged along the thickness direction and electrically connected. Each wiring layer includes a dielectric layer and a metal layer. The metal pillar 12 passes through at least one dielectric layer of the wiring layer and is staggered from the metal layer of the wiring layer. The metal pillar 12 may optionally pass through the dielectric layer of a single wiring layer or through the dielectric layers of multiple wiring layers, but it must be staggered from the metal layer of the wiring layer it passes through to prevent interference with the metal layer.

[0061] The plurality of wiring layers include a first wiring layer 41 and a second wiring layer 42 disposed along the thickness direction and electrically connected. The first wiring layer 41 is close to and electrically connected to the substrate 10, and the second wiring layer 42 is close to and electrically connected to the chip 20. It is understood that the first wiring layer 41 may optionally include a single layer or multiple layers of wiring layers, with the multiple layers stacked sequentially. The second wiring layer 42 may optionally include a single layer or multiple layers of wiring layers, with the multiple layers stacked sequentially.

[0062] The first wiring layer 41 includes a dielectric layer and a metal layer, and the second wiring layer 42 includes a dielectric layer and a metal layer. The metal pillar 12 is offset from the metal layer of the first wiring layer 41 and passes through the dielectric layer of the first wiring layer 41 to be electrically connected to the metal layer of the second wiring layer 42. Figure 2 As shown, the metal pillar 12 and the stress buffer layer 13 pass through the first wiring layer 41. The common end face of the metal pillar 12 and the stress buffer layer 13 facing the chip 20 is flush with the end face of the first wiring layer 41, which can achieve higher precision wiring requirements.

[0063] Combination Figure 1 , 2 As shown, in the first and second embodiments of this application, except for the inconsistent protrusion heights of the metal pillar 12 and the stress buffer layer 13, the other structures are consistent.

[0064] Combination Figure 1 , 3 As shown, in the first and third embodiments of this application, the only difference between the bonding connection method of chip 20 and second line 40 is that the other structures are the same.

[0065] In one embodiment, the chip 20 includes chip pads 21, and the chip package structure 100 includes conductive bumps 50, the conductive bumps 50 electrically connecting the chip pads 21 and the second line 40. Figure 1 As shown, the conductive bump 50 can be a solder ball. The conductive bump 50 is formed on the chip pad 21, and at least a portion of the metal layer of the second line 40 is exposed to form a micro pad 401. The conductive bump 50 electrically connects the chip pad 21 and the micro pad 401. In this way, the chip 20 and the second line 40 are bonded together by soldering.

[0066] Combination Figure 1 As shown, the chip 20 includes chip pads 21 and a first dielectric film 22, with the chip pads 21 exposed to the first dielectric film 22. A first molding compound 60 fills the space between the first dielectric film 22 and the second circuit 40 and encapsulates the conductive bumps 50.

[0067] The chip package structure 100 includes a first molding compound 60 formed between the chip 20 and the second line 40, the first molding compound 60 encapsulating the conductive bump 50. Figure 1 As shown, the conductive bump 50 has a certain height. After the chip 20 is soldered to the second line 40, a gap is formed between the chip 20 and the second line 40. The first molding compound 60 fills the gap and thus wraps the conductive bump 50. The first molding compound 60 includes chip pads 21 and micro pads 401.

[0068] Specifically, the first molding layer 60 encapsulates the first side of the molding substrate 10, covering the surface of the second line 40, encapsulating the conductive bumps 50, and encapsulating the chip 20.

[0069] In one embodiment, the chip 20 includes a first dielectric film 22 and a first pad 23 formed on its surface, the first pad 23 being exposed to the first dielectric film 22. Figure 3 As shown, chip 20 includes chip pad 21, and a first pad 23 is further formed on chip pad 21. The first pad 23 is similar to the conductive bump 50 in the first embodiment, except that the conductive bump 50 in the first embodiment is preferably a solder ball, which is connected to the surface of the second line 40 by soldering. In the third embodiment, the first pad 23 is preferably a copper layer, and the surface of the first pad 23 is flush with the surface of the first dielectric film 22 for hybrid bonding connection with the second line 40.

[0070] The second line 40 includes a second dielectric film 43 formed on its surface and a second pad 44, the second pad 44 being exposed to the second dielectric film 43; the first pad 23 is co-bonded to the second pad 44. Figure 3 As shown, the second line 40 includes a first wiring layer 41 and a second wiring layer 42. A second dielectric film 43 and a second pad 44 are formed on the surface of the second wiring layer 42. The second pad 44 is electrically connected to the metal layer of the second wiring layer 42.

[0071] The surface of the second pad 44 is flush with the surface of the second dielectric film 43. The first pad 23 is mixed-bonded to the second pad 44, and the first dielectric film 22 and the second dielectric film 43 are attached together. In this way, the chip 20 and the second line 40 are mixed-bonded together.

[0072] Combination Figure 3 As shown, in the third embodiment, the chip packaging structure 100 also includes a first molding layer 60. In this case, the first molding layer 60 does not need to fill the space between the chip 20 and the second line 40, but only needs to cover the surface of the second line 40 and wrap the chip 20.

[0073] Combination Figure 1-3As shown, the chip packaging structure 100 includes a circuit board 70, metal bumps 80 electrically connecting the circuit board 70 and the first circuit line 30, and a second molding compound 90. The metal bumps 80 can be solder balls, which solder the first circuit line 30 and the circuit board 70 together. The circuit board 70 is located on the side of the first circuit line 30 facing away from the substrate 10. The second molding compound 90 completely encapsulates the circuit board 70, the substrate 10, and the first molding compound 90, enhancing the stability and reliability of the chip packaging structure.

[0074] Combination Figure 1-3 As shown in the specific embodiment, the chip packaging structure 100 includes, from bottom to top, a circuit board 70, a metal bump 80, a first line 30, a substrate 10, a second line 40, and a chip 20, and is encapsulated twice to form a first encapsulation layer 60 and a second encapsulation layer 90, respectively.

[0075] This application includes a chip packaging method for fabricating the chip packaging structure 100 in the above-described technical solution, combined with... Figure 4-10 As shown, in the first embodiment of this application, the chip packaging method includes the following steps: S1: Provide a substrate 10, and form a groove 101 on a first side of the substrate 10; combine Figure 6 As shown, the substrate 10 can be selected from silicon wafers, glass, and ceramics. The grooves 101 can be fabricated by chemical etching, laser cutting, or mechanical cutting. The through-holes 11 in the final chip package structure 100 are obtained by subsequent grinding of the grooves 101.

[0076] S2: Fabricate a stress buffer layer 13, which is formed on the wall of the groove 101. The stress buffer layer 13 may be a polymer or a composite, and is mainly used to relieve thermal stress between the metal pillar 12 and the through hole 11.

[0077] Fabricating the stress buffer layer 13 includes: filling a stress buffer material 130 on the first side of the substrate 10, the stress buffer material 130 covering the surface of the substrate 10 and filling the groove 101, removing a portion of the stress buffer material located in the groove 101, and obtaining the stress buffer layer 13; Figure 7 As shown, at this time, the stress buffer layer 13 covers the surface of the substrate 10 and the inner wall of the groove 101. During subsequent packaging, the stress buffer layer 13 covering the surface of the substrate 10 may be further ground away, or it may be retained as needed.

[0078] S3: Fabricate metal pillars 12, which fill the grooves 101; the metal pillars 12 are preferably copper pillars, used to realize vertical conductive interconnection of the chip package structure 100.

[0079] Combination Figure 7As shown, fabricating the metal pillar 12 includes: fabricating a metal structure 120 on a first side of the substrate 10, the metal structure 120 including the metal pillar 12 filling the groove 101, and the stress buffer layer 13 located between the metal pillar 12 and the inner wall of the groove 101. It can be understood that the stress buffer layer 13 is first fabricated within the groove 101, then the metal pillar 12 is fabricated. After the stress buffer layer 13 completely covers the inner wall of the groove 101, the metal pillar 12 then fills the groove 101. Thus, the stress buffer layer 13 is completely spaced between the metal pillar 12 and the groove 101.

[0080] Combination Figure 7 As shown, a stress buffer layer 13 is fabricated before manufacturing the metal structure 130. In the first embodiment of this application, the stress buffer layer 13 covers the surface of the substrate and the inner wall of the groove 101. Therefore, other metal structures besides the metal pillar 12 are also formed on the stress buffer layer 13. In other embodiments, if only the stress buffer layer 13 located on the inner wall of the groove 101 is retained when fabricating the stress buffer layer 13, then other metal structures besides the metal pillar 12 are formed on the surface of the substrate 10.

[0081] After fabricating the metal pillar 12, the process includes grinding the first side of the substrate 10, retaining the stress buffer layer 13 and the metal pillar 12 located within the groove. During the fabrication of the stress buffer layer 13 and the metal pillar 12 within the groove 101, a stress buffer layer 13 and a metal structure are also formed on the surface of the substrate 10, which need to be removed by grinding to expose the surface of the substrate 10. It is understood that the top faces of the metal pillar 12 and the stress buffer layer 13 within the groove 101 are necessarily located on the same horizontal plane, and are also on the same horizontal plane as the surface of the first side of the substrate 10.

[0082] After fabricating the metal pillar 12, the process includes: fabricating a second line 40 on a first side of the substrate 10, wherein the metal pillar 12 is electrically connected to the second line 40. Figure 8 As shown, fabricating the second circuit 40 includes sequentially fabricating multiple wiring layers on the first side surface of the substrate 10. The uppermost wiring layer has outwardly exposed micro pads 401 for electrical connection with the chip 20.

[0083] In the first embodiment of this application, since the stress buffer layer 13 is prefabricated, the temperature range that the stress buffer layer 13 can withstand needs to be considered before selecting the manufacturing process of the second circuit 40.

[0084] S4: Provide chip 20, connecting the substrate 10 and chip 20. (Combined) Figure 5 As shown, chip 20 includes chip pads 21 and a first dielectric film 22. The chip pads 21 are exposed to the first dielectric film 22. Conductive bumps 50 are formed on the chip pads 21, preferably solder balls. Figure 8As shown, chip 20 is connected to micro pad 401 by conductive bump 50. The welding process is simple and low cost.

[0085] After connecting the substrate 10 and the chip 20, a first molding compound 60 is formed on a first side of the substrate 10. Figure 8 As shown, the fabrication of the first molding layer 60 specifically includes: filling with molding material, the molding material filling between the chip 20 and the second circuit 40, wrapping the conductive bump 50 and completely wrapping the chip 20 upwards.

[0086] Combination Figure 8 As shown, after the first molding layer 60 is fabricated, a back plate 110 is provided on the surface of the first molding layer 60. The back plate 110 can be used as a heat dissipation back plate or as a carrier plate. In subsequent steps, when operating the second side of the substrate 10, it is used to support the substrate 10. When used as a carrier plate, it needs to be separated later.

[0087] S5: A first line 30 is formed on the second side of the substrate 10. The first and second sides of the substrate 10 are arranged opposite to each other. The metal pillar 12 electrically connects the chip 20 and the first line 30. The two ends of the metal pillar 12 are electrically connected to the first line 30 and the second line 40, respectively. The second line 40 is then electrically connected to the chip 20 through a conductive bump 50.

[0088] Combination Figure 9 As shown, before fabricating the first line 30 on the second side of the substrate 10, the process includes: grinding the second side of the substrate 10, forming the groove 101 into a through hole 11, and exposing the metal pillar 12 on the second side of the substrate 10 to electrically connect the first line 30.

[0089] It can be seen that after the second side of the polished substrate 10 is polished, the metal pillar 12 and the stress buffer layer 13 are exposed on the second side of the substrate and their end faces are located on the same horizontal plane. The end faces of the metal pillar 12 and the stress buffer layer 13 are also located on the same horizontal plane as the surface of the second side of the substrate 10.

[0090] It is known that the metal pillar 12 and stress buffer layer 13 formed in the through hole 11 by the encapsulation process of this application are completely aligned and of equal height along the thickness direction.

[0091] Combination Figure 9 As shown, after the first line 30 is formed on the second side of the substrate 10, the process includes: providing a circuit board 70, forming a metal bump 80, and electrically connecting the circuit board 70 and the first line 30 through the metal bump 80. A second molding compound 90 is formed to integrally mold the circuit board 70, the substrate 10, and the first molding compound 60.

[0092] Combination Figure 11-16As shown, the second embodiment of this application has most of the same steps as the first embodiment, and the identical parts will not be repeated, while the different parts will be described in detail. The difference between the second embodiment and the first embodiment is that in the second embodiment, the metal pillar 12 and the stress buffer layer 13 extend into the second wiring layer 40, thus the manufacturing process is different. Specifically, the chip packaging method includes the following steps: S1: Provide a substrate 10, and form a groove 101 on a first side of the substrate 10; combine Figure 12 As shown, this step differs from the first embodiment; the substrate 10 can be selected from silicon wafers, glass, and ceramics. The groove 101 can be fabricated using methods such as chemical etching, laser cutting, and mechanical cutting. The through-holes 11 in the final chip package structure 100 are obtained by subsequent grinding of the groove 101.

[0093] The process of creating a groove 101 on the first side of the substrate 10 includes: first creating a first wiring layer 41 on the first side of the substrate 10, and then creating a groove 101, wherein the groove 101 extends through the first wiring layer 41 to the substrate 10.

[0094] Combination Figure 12 As shown, the difference between the second embodiment and the first embodiment of this application is that: before forming the groove 101, a first wiring layer 41 is first fabricated on the substrate 10. The first wiring layer 41 can be a single-layer wiring layer or a multi-layer wiring layer. Then, the groove 101 is fabricated on the substrate 10 and the first wiring layer 41. In this way, the fabrication process of the first wiring layer 41 does not need to consider the temperature range that the stress buffer layer 13 can withstand. The first wiring layer 41 can preferably be fabricated using a damascus copper process, and the line fineness of the first wiring layer 41 can be controlled to 0.2 micrometers.

[0095] In other embodiments, if the second line 40 requires high line fineness precision as a whole, the groove 101 and stress buffer layer 13 can be made after the second line 40 is formed.

[0096] S2: Fabricate a stress buffer layer 13, which is formed on the wall of the groove 101; the stress buffer layer 13 may be a polymer or a composite, and is mainly used to relieve the thermal stress between the metal pillar 12 and the through hole 11.

[0097] Fabricating the stress buffer layer 13 includes: filling the surface of the first wiring layer 41 with stress buffer material 130; covering the surface of the first wiring layer 41 and filling the groove 101 with stress buffer material 130; and removing a portion of the stress buffer material 130 located within the groove 101 to obtain the stress buffer layer 13. Figure 13As shown, the stress buffer layer 13 covers the surface of the first wiring layer 41 and the inner wall of the groove 101. It can be seen that the manufacturing method is the same as the first embodiment, except that in the first embodiment, the stress buffer material 130 is filled in the surface of the substrate 10 and the groove 101, while in the second embodiment, the stress buffer material 130 is filled in the surface of the first wiring layer 41 and the groove 101.

[0098] S3: Fabricate metal pillars 12, which fill the grooves 101. The metal pillars 12 are preferably copper pillars, used to achieve vertical conductive interconnection of the chip packaging structure 100. The specific fabrication method is the same as that in the first embodiment, and will not be repeated here.

[0099] After fabricating the metal pillar 12, the process includes grinding the first side of the substrate 10, retaining the stress buffer layer 13 and the metal pillar 12 located in the groove, so that the top end faces of the metal pillar 12 and the stress buffer layer 13 in the groove 101 are located on the same horizontal plane. Unlike the first embodiment, in this case, the top end faces of the metal pillar 12 and the stress buffer layer 13 are higher than the surface of the first side of the substrate 10, and the top end faces of the metal pillar 12 and the stress buffer layer 13 should be located on the same horizontal plane as the surface of the first wiring layer 41.

[0100] After fabricating the metal pillar 12, the process includes: fabricating a second wiring layer 42 on a first side of the substrate 10, the second wiring layer 42 being stacked on and electrically connected to the first wiring layer 41, and the metal pillar 12 being electrically connected to the second wiring layer 42. Figure 14 It can be seen that this is equivalent to continuing to create a second wiring layer 42 on the first wiring layer 41. The second wiring layer 42 can be a single wiring layer or a multi-layer wiring layer.

[0101] In the first embodiment, a groove 101, a stress buffer layer 13, and metal pillars 12 are first fabricated on the substrate 10, followed by the fabrication of a first wiring layer 41 and a second wiring layer 42. In the second embodiment, a first wiring layer 41 is first fabricated on the substrate 10, a groove 101 is fabricated together with the first wiring layer 41 and the substrate 10, followed by the fabrication of the stress buffer layer 13 and the metal pillars 12, and then the fabrication of the second wiring layer 42. In the second embodiment, the fabrication of the first wiring layer 41 precedes that of the stress buffer layer 13, therefore the temperature range that the stress buffer layer 13 withstands does not need to be considered.

[0102] In other embodiments, if the chip package structure 100 requires higher precision first and second wiring layers or even more other wiring layers, the first and second wiring layers and more other wiring layers can be fabricated first, and then the groove 101 can be fabricated together on the wiring layers and the substrate, and then the stress buffer layer 13 can be fabricated. In short, the manufacturing process of the stress buffer layer 13 needs to be moved to the later stage.

[0103] S4: Provide chip 20, connecting the substrate 10 and chip 20; combine Figure 11 , 14 As shown, the chip 20 and the second line 40 are connected by welding through conductive bumps 50, and then the first molding layer 60 is formed, which is the same as the first embodiment, and will not be described again here.

[0104] S5: A first line 30 is formed on the second side of the substrate 10. The first and second sides of the substrate 10 are arranged opposite to each other. The metal pillar 12 is electrically connected to the chip 20 and the first line 30.

[0105] Combination Figure 15 As shown, before fabricating the first line 30 on the second side of the substrate 10, the process includes: grinding the second side of the substrate 10, forming the groove 101 into a through hole 11, and exposing the metal pillar 12 on the second side of the substrate 10 to electrically connect the first line 30.

[0106] After grinding the second side of the substrate 10, the metal pillar 12 and the stress buffer layer 13 are exposed on the second side of the substrate, and their end faces are located on the same horizontal plane. The end faces of the metal pillar 12 and the stress buffer layer 13 are also located on the same horizontal plane as the surface of the second side of the substrate 10. In the second embodiment of this application, the metal pillar 12 and the stress buffer layer 13 formed in the through hole 11 are also completely aligned and at the same height along the thickness direction.

[0107] Combination Figure 16 As shown, after the first line 30 is formed on the second side of the substrate 10, the process includes: providing a circuit board 70, forming a metal bump 80, and electrically connecting the circuit board 70 and the first line 30 through the metal bump 80. A second molding compound 90 is formed to integrally mold the circuit board 70, the substrate 10, and the first molding compound 60.

[0108] Combination Figure 17-22 The chip packaging method of the third embodiment shown includes the following steps: providing a substrate 10, forming a groove 101 on a first side of the substrate 10; forming a stress buffer layer 13, the stress buffer layer 13 being formed on the wall of the groove 101; forming a metal pillar 12, the metal pillar 12 filling the groove 101; providing a chip 20, connecting the substrate 10 and the chip 20; forming a first line 30 on a second side of the substrate 10, the first side and the second side of the substrate 10 being disposed opposite to each other, the metal pillar 12 electrically connecting the chip 20 and the first line 30.

[0109] The difference between the third embodiment and the first embodiment of this application lies in the provision of a chip 20 and the method of connecting the substrate 10 and the chip 20. The third embodiment connects the two using a hybrid bonding method. Figure 17As shown, chip 20 includes chip pads 21 and a first dielectric film 22, the first dielectric film 22 exposing chip pads 21 to facilitate the fabrication of first pads 23 on chip pads 21.

[0110] The first pad 23 is similar to the conductive bump 50 in the first embodiment, except that the conductive bump 50 in the first embodiment is preferably a solder ball, formed on the chip pad 21 by soldering. In the third embodiment, the first pad 23 is preferably a copper layer, formed by electroplating copper.

[0111] Combination Figure 20 As shown, after fabricating the metal pillar 12, the process includes: fabricating a second circuit 40 on a first side of the substrate 10, with the metal pillar 12 electrically connected to the second circuit 40. Connecting the substrate 10 and the chip 20 actually involves connecting the second circuit 40 and the chip 20. In the first embodiment, the conductive bump 50 is connected to the micropad 401 exposed by the second circuit 40 via soldering.

[0112] Combination Figure 20 As shown, in the third embodiment, fabricating the second circuit 40 includes fabricating a first wiring layer 41, a second wiring layer 42, and continuing to fabricate a second dielectric film 43 and a second pad 44 on the second wiring layer 42; or, fabricating the second circuit 40 includes fabricating a first wiring layer 41, and continuing to fabricate a second dielectric film 43 and a second pad 44 on the first wiring layer 41.

[0113] It is understood that regardless of the number of wiring layers included in the second line 40, this application only requires fabricating a second dielectric film 43 and a second pad 44 on the top layer. Furthermore, the second dielectric film 43 needs to expose the second pad 44. Thus, the first pad 23 and the second pad 44 can be connected using a hybrid bonding method, with the first dielectric film 22 covering and connecting the second dielectric film 43. Using a hybrid bonding method can reduce the bonding pitch and decrease the package size of the chip package structure 100.

[0114] It is understood that, in the third embodiment, when the first molding layer 60 is formed, the first molding layer 60 will not extend between the chip 20 and the second line 40.

[0115] The beneficial effects of the present invention are as follows: a stress buffer layer 13 is provided between the metal pillar 12 and the through hole 11 to alleviate the difference in thermal expansion coefficients between the materials of the metal pillar 12 and the through hole 11, thereby reducing the stress caused by temperature changes; the metal pillar 12 and the stress buffer layer 13 are completely aligned and of equal height along the thickness direction to completely separate the metal pillar 12 and the through hole 11.

[0116] This can be formed by referring to any of the technical solutions provided above, and will not be elaborated here.

[0117] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0118] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip packaging structure, characterized in that, The device includes a substrate, chips located on both sides of the substrate along its thickness direction, and a first circuit. The substrate includes a through-hole, a metal pillar formed in the through-hole, and a stress buffer layer located between the metal pillar and the through-hole. One end of the metal pillar is electrically connected to the chip, and the other end is electrically connected to the first circuit.

2. The chip packaging structure according to claim 1, characterized in that, The stress buffer layer and the metal pillar are aligned along the thickness direction and are at the same height.

3. The chip packaging structure according to claim 1, characterized in that, The end face of the metal pillar facing the first circuit and the surface of the substrate facing the first circuit are located on the same horizontal plane; the end face of the metal pillar facing the chip and the surface of the substrate facing the chip are located on the same horizontal plane.

4. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure includes a second line formed between the chip and the substrate, the second line being electrically connected to the chip and the metal pillar.

5. The chip packaging structure according to claim 4, characterized in that, The end face of the metal pillar facing the first circuit and the surface of the substrate facing the first circuit are located on the same horizontal plane; the end face of the metal pillar facing the chip extends into the second circuit, thus being higher than the surface of the substrate facing the chip.

6. The chip packaging structure according to claim 4, characterized in that, The second line includes a plurality of wiring layers arranged along the thickness direction and electrically connected. Each wiring layer includes a dielectric layer and a metal layer. The metal pillar passes through at least one dielectric layer of the wiring layer and is staggered from the metal layer of the wiring layer.

7. The chip packaging structure according to claim 6, characterized in that, The plurality of wiring layers include a first wiring layer and a second wiring layer, the first wiring layer being close to and electrically connected to the substrate, and the second wiring layer being close to and electrically connected to the chip; the metal pillars passing through the dielectric layer of the first wiring layer and electrically connected to the metal layer of the second wiring layer.

8. The chip packaging structure according to claim 4, characterized in that, The chip includes chip pads, and the chip package structure includes conductive bumps, which electrically connect the chip pads and the second circuit.

9. The chip packaging structure according to claim 8, characterized in that, The chip packaging structure includes a first molding layer formed between the chip and the second circuit, the first molding layer encapsulating the conductive bumps.

10. The chip packaging structure according to claim 4, characterized in that, The chip includes a first dielectric film formed on its surface and a first pad, the first pad being exposed to the first dielectric film.

11. The chip packaging structure according to claim 10, characterized in that, The second line includes a second dielectric film formed on its surface and a second pad, the second pad being exposed to the second dielectric film; the first pad is mixed-bonded to the second pad.

12. A chip packaging method, characterized in that, Includes the following steps: A substrate is provided, and a groove is formed on a first side of the substrate; A stress buffer layer is fabricated on the wall of the groove; A metal column is fabricated, and the metal column fills the groove; Provide a chip, and connect the substrate and the chip; A first circuit is formed on the second side of the substrate, the first and second sides of the substrate are disposed opposite to each other, and the metal pillars electrically connect the chip and the first circuit.

13. The chip packaging method according to claim 12, characterized in that, Fabricating a stress buffer layer includes: filling a first side of the substrate with a stress buffer material; the stress buffer layer covers the surface of the substrate and the inner wall of the groove.

14. The chip packaging method according to claim 12, characterized in that, Fabricating the metal pillar includes: fabricating a metal structure on a first side of the substrate, the metal structure including a metal pillar filling the groove, and the stress buffer layer being located between the metal pillar and the inner wall of the groove.

15. The chip packaging method according to claim 12, characterized in that, After fabricating the metal pillar, the process includes: fabricating a second circuit on a first side of the substrate, wherein the metal pillar is electrically connected to the second circuit.

16. The chip packaging method according to claim 12, characterized in that, The process of creating a groove on the first side of the substrate includes: first creating a first wiring layer on the first side of the substrate, and then creating a groove that extends through the first wiring layer to the substrate.

17. The chip packaging method according to claim 16, characterized in that, Fabricating a stress buffer layer includes: filling the surface of the first wiring layer with a stress buffer material; the stress buffer layer covers the surface of the first wiring layer and the inner wall of the groove.

18. The chip packaging method according to claim 16, characterized in that, After fabricating the metal pillar, the process includes: fabricating a second wiring layer on a first side of the substrate, the second wiring layer being stacked on the first wiring layer and electrically connected to the first wiring layer, and the metal pillar being electrically connected to the second wiring layer.

19. The chip packaging method according to claim 12, characterized in that, Providing a chip, and connecting the substrate and the chip includes: the chip pads of the chip being connected to a second circuit by soldering, or the chip and the second circuit being connected by a hybrid bonding method.

20. The chip packaging method according to claim 12, characterized in that, Before fabricating the first line on the second side of the substrate, the process includes: grinding the second side of the substrate, forming the groove into a through hole, and exposing the metal post on the second side of the substrate to electrically connect the first line.

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