Multi-core rotating traveling wave oscillator

Abstract

Techniques, circuits, and systems relating to a multi-core rotating traveling wave oscillator (RTWO) are provided. The multi-core RTWO includes at least two metal layers and a plurality of RTWO cores such that each core includes a set of differential signal conductors interleaved across the metal layers to optimize space and reduce parasitic effects. The relative position configuration of the differential signal conductors varies over a range of directionality and / or orientation. In an embodiment, an oscillator output signal is generated by the multi-core RTWO; the frequency of this oscillator output signal is adjusted based on a comparison of its phase with the phase of a reference signal, e.g., within a phase-locked loop circuit.

Description

Technical Field

[0001] This invention relates to a multi-core rotating traveling wave oscillator and method. Background Technology

[0002] In various oscillator designs, rotating traveling wave oscillators (RTWOs) are commonly used to generate well-aligned multiphase clock signals for many high-speed digital, analog, and mixed-signal circuits. RTWOs are typically constructed using differential circular transmission lines and cross-coupled inverters or latches that operate in series to recover the energy dissipated as the square wave travels along the loop, thereby sustaining the oscillation.

[0003] In many applications (e.g., all-digital phase-locked loops (AD-PLLs)), RTWO provides seamless integration with time-to-digital converters (TDCs), facilitating the generation of digital phase relationship information without excessive calibration. This integration maintains precise control over the oscillator frequency and phase, enabling accurate clock generation and synchronization among various system components. Summary of the Invention

[0004] In one embodiment, a multi-core rotating traveling wave oscillator (RTWO) includes at least two metal layers and a plurality of RTWO cores. Each of the plurality of RTWO cores includes a set of differential signal conductors such that the differential signal conductors for the plurality of RTWO cores are interleaved via at least two metal layers.

[0005] A set of differential signal conductors for each RTWO core can be oriented across a range of directions, such that the interleaved differential signal conductors have a first relative position configuration in which the interleaved differential signal conductors are substantially oriented in a first direction, and a different second relative position configuration in which the interleaved differential signal conductors are substantially oriented in a second direction. The range of directions can be up to 360 degrees. The first relative position configuration may include multiple conductors positioned within the inner portion of the interleaved differential signal conductors, while the second relative position configuration includes at least one of multiple conductors positioned within the outer portion of the interleaved differential signal conductors.

[0006] A first subset of differential signal conductors for multiple RTWO cores may have a first cross-sectional area, and a second subset of differential signal conductors for multiple RTWO cores may have a second cross-sectional area different from the first cross-sectional area. The differential signal conductors having the first cross-sectional area may be positioned on inner tracks of at least two metal layers, and the differential signal conductors having the second cross-sectional area may be positioned on outer tracks of at least two metal layers. The differential signal conductors having the first cross-sectional area may be positioned on a first metal layer of at least two metal layers, and the differential signal conductors having the second cross-sectional area may be positioned on a second metal layer of at least two metal layers.

[0007] A first subset of differential signal conductors for multiple RTWO cores may have a first spacing distance between the conductors, such that a second subset of differential signal conductors has a second spacing distance between the conductors that is different from the first spacing distance.

[0008] A multi-core RTWO can be configured to activate a first subset of the RTWO cores among the multiple RTWO cores in response to a control signal, while a second subset of the multiple RTWO cores remains inactive.

[0009] A multi-core RTWO can be configured to deactivate a first subset of multiple RTWO cores in response to a control signal, while a second subset of multiple RTWO cores continues to operate.

[0010] The plurality of RTWO cores may include N RTWO cores, such that each RTWO core occupies an area A of at least two metal layers, and the total area T of the multi-core RTWO occupies at least two metal layers is less than N×A.

[0011] In one embodiment, a system includes a multi-core rotating traveling wave oscillator (RTWO) and a phase-locked loop (PLL) circuit coupled to the RTWO. The multi-core RTWO may include at least two metal layers and a plurality of RTWO cores, such that each core includes a set of differential signal conductors, and that the differential signal conductors for the plurality of RTWO cores are interleaved via at least two metal layers. The PLL circuit stabilizes the frequency of the one or more RTWO signals generated by the RTWO by comparing the phase of one or more RTWO signals with a reference signal.

[0012] A set of differential signal conductors for each RTWO core can be oriented across a range of directions, such that the interleaved differential signal conductors have a first relative position configuration in which the interleaved differential signal conductors are substantially oriented in a first direction, and have different second relative position configurations in which the interleaved differential signal conductors are substantially oriented in a second direction. The range of directions can include 360 ​​degrees. The first relative position configuration may include multiple conductors positioned within the inner portion of the interleaved differential signal conductors, such that the second relative position configuration includes at least one of the multiple conductors positioned within the outer portion of the interleaved differential signal conductors.

[0013] A first subset of differential signal conductors for multiple RTWO cores may have a first cross-sectional area, such that a second subset of differential signal conductors for multiple RTWO cores has a second cross-sectional area different from the first cross-sectional area. The differential signal conductors having the first cross-sectional area may be positioned on inner rails of at least two metal layers, and the differential signal conductors having the second cross-sectional area may be positioned on outer rails of at least two metal layers.

[0014] A first subset of differential signal conductors for multiple RTWO cores may have a first spacing distance between the conductors, such that a second subset of differential signal conductors has a second spacing distance between the conductors that is different from the first spacing distance.

[0015] The system may additionally include a controller for selectively activating or deactivating a subset of one or more RTWO cores from a plurality of RTWO cores.

[0016] The plurality of RTWO cores may include N RTWO cores, such that each RTWO core occupies an area A of at least two metal layers, and the total area T of the multi-core RTWO occupies at least two metal layers is less than N×A.

[0017] In one embodiment, a method includes: generating an oscillator output signal using a multi-core rotating traveling wave oscillator (RTWO), the multi-core RTWO including at least two metal layers and a plurality of RTWO cores, each RTWO core including a set of differential signal conductors, and the differential signal conductors for the plurality of RTWO cores being interleaved via at least two metal layers; and adjusting the frequency of the oscillator output signal based on a comparison of the phase of the oscillator output signal with a reference signal. Attached Figure Description

[0018] The present disclosure will be better understood by referring to the accompanying drawings, which will make the many features and advantages of the disclosure clear to those skilled in the art. The same reference numerals are used in different drawings to indicate similar or identical items.

[0019] Figure 1 A simplified RTWO is shown, in which a square voltage wave travels along a differential circular transmission line.

[0020] Figure 2 A schematic version of the logic of an RTWO, comprising multiple latches distributed around a square path formed by differential transmission lines, is shown.

[0021] Figure 3 A comparative layout diagram is shown, according to some embodiments, of various configurations used to depict an area-efficient rotating traveling wave oscillator.

[0022] Figure 4 A cross-sectional view of four pairs of interleaved transmission lines configured for use in a multi-core RTWO configuration, according to some embodiments, is shown.

[0023] Figure 5 Two configurations for arranging differential signal conductors to cancel and equalize parasitic effects in multi-core RTWOs are shown according to some embodiments.

[0024] Figure 6Three alternative differential signal conductor configurations according to some embodiments are shown, wherein the metal layer track width and / or conductor spacing distance of the differential signal conductors are maintained while keeping the relative positions of these differential signal conductors.

[0025] Figure 7 A phase-locked loop circuit for generating frequency signals using a multi-core RTWO is shown according to some embodiments. Detailed Implementation

[0026] As used herein, phase noise refers to the random fluctuations in the phase of a signal compared to a perfect reference signal, which spread around the carrier frequency within a certain frequency range. These fluctuations are caused by short-term variations in the frequency of the oscillator that generates the signal, producing noise that manifests as phase jitter or timing instability in the output signal. Phase noise in oscillators and timing circuits can significantly affect the performance and reliability of communication systems, radar, and other electronic devices that rely on precise timing and signal integrity. High phase noise can degrade signal quality, reduce the signal-to-noise ratio, and ultimately limit the effectiveness of systems in which oscillators are used. Therefore, reducing phase noise is advantageous in the design of oscillators for high-frequency and high-precision applications.

[0027] Some applications require phase noise performance lower than that achievable with a single oscillator. Combining multiple coupled oscillators is a known method for reducing phase noise (random fluctuations in the signal phase). However, despite the advantages offered by multi-core RTWOs, practical implementations of these multi-core RTWOs face a major obstacle: the required silicon area is almost linearly proportional to the number of oscillators implemented. This ratio not only increases cost but also limits integration density, posing a significant challenge to incorporating RTWOs into compact system-on-chip (SoC) designs and other integrated circuits where space is extremely valuable.

[0028] Figure 1 A simplified RTWO 100 is shown, in which a square voltage wave 110 travels along a differential circular transmission line 105 that substantially forms a loop. In the depicted configuration, four cross-coupled inverters (latches) 120 recover the energy dissipated as the square wave 110 travels along the loop. This arrangement produces a single clock edge that sweeps across the loop formed by the differential transmission line 105 at a frequency depending on the electrical length of the loop.

[0029] Figure 2 A schematic version of the RTWO 100 is shown, in which a plurality of (twelve) latches 220 are distributed around a square path formed by differential transmission lines 205. The phase of the square wave (not shown) traveling along the differential transmission lines 205 is indicated at the midpoint of each side of the path of the square wave.

[0030] As understood, coupling N oscillators can reduce phase noise (PN) by up to ΔPN = 10 log n. 10 This multi-core oscillator configuration, while reducing phase noise, traditionally increases silicon area usage, posing significant design and economic challenges, especially with the continued growing demand for miniaturization and cost-effectiveness in electronic devices.

[0031] The implementations of the techniques, systems, and circuits described herein provide RTWO designs that overcome, for example, the limitations of conventional multi-core RTWOs in terms of silicon area usage, without compromising characteristics such as phase noise reduction and multiphase clock generation capabilities. Typically, in an RTWO formed via two or more metal layers, embodiments of the techniques described herein include multiple RTWO cores, each comprising a set of differential signal conductors such that the differential signal conductors for the multiple RTWO cores are interleaved via those metal layers. By utilizing interleaved differential transmission lines and employing magnetic and mutual inductive and / or capacitive coupling, the embodiments significantly reduce the area occupied by the multi-core RTWO on the silicon substrate. This advancement enables the realization of high-performance, scalable oscillators suitable for a wide range of applications, including but not limited to phase-locked loops (PLLs), analog and RF front-ends, and integrated system-on-a-chip (SoC).

[0032] In some embodiments, the interleaved transmission lines of the RTWO core are closely spaced, facilitating effective magnetic or mutual inductive and capacitive coupling between the lines. This approach eliminates the need for additional coupling tracks or devices, such as dedicated capacitors, resistors, or switches, traditionally used to achieve coupling between oscillator cores. By optimizing the spatial arrangement of the transmission lines, the embodiments offer a significant reduction in silicon area usage compared to conventional multi-core RTWO designs, where the area is substantially linearly proportional to the number of cores.

[0033] In some embodiments, the described techniques compensate for asymmetries between oscillator cores caused by the wiring of the combined transmission lines. For example, by interchanging the assigned transmission lines of individual RTWO cores throughout the transmission line ring, each associated transmission line traverses all possible locations along the ring, thereby maintaining overall symmetry and minimizing local mismatches. In some embodiments, the four interleaved differential transmission lines for a 4-core RTWO utilize two metal layers. By changing parameters such as track width or the distance between differential signals, the oscillator design can be optimized for different applications and performance requirements.

[0034] In various embodiments, the multi-core RTWO configuration described herein allows for individual core activation and deactivation, thereby providing adjustable performance and power consumption, and enabling the tailoring of oscillator cores to the specific needs of an application. For example, in scenarios requiring lower power consumption, a subset of RTWO cores can be activated (e.g., in response to a control signal from a controller) without significantly impacting the overall phase noise performance of the oscillator. Similarly, a first subset of RTWO cores can be deactivated (e.g., in response to a control signal from a controller), while a second subset of RTWO cores continues to operate. In some embodiments, such individually controllable RTWO cores increase oscillator resolution, for example, if the control signals for these RTWO cores are used for individual control (e.g., rather than parallel switching). As used herein, oscillator resolution refers to the smallest increment of frequency variation that can be achieved or distinguished by the associated oscillator, defining the accuracy and adjustability of the oscillator's output signal. Higher resolution in the oscillator allows for finer frequency tuning, which is advantageous in applications requiring improved frequency control (e.g., digital communications, signal processing, and precision instrumentation).

[0035] Figure 3 Comparative layout diagrams are shown, according to some embodiments, of various configurations of the RTWO used to depict comparative area efficiencies. In particular, Figure 3 The single-core RTWO 200, the conventional quad-core RTWO 310, and the improved quad-core RTWO 320 are shown according to embodiments described herein.

[0036] exist Figure 3 On the left, single-core RTWO 200 and above are mentioned in the article. Figure 1 and 2 The differential circular transmission line and associated circuitry operate in a manner described, the associated circuitry being designed to maintain oscillatory behavior through energy recovery as a wave travels along the transmission line.

[0037] exist Figure 3 At the center of the configuration, a typical 4-core RTWO configuration 310 comprises four distinct instances of single-core RTWO 200 arranged adjacently to form a 2×2 mesh layout. Each of these RTWO instances is coupled to each other via multiple pairing connections 312, thereby facilitating coherent operation between the instances of single-core RTWO 200 operating within the 4-core RTWO configuration 310. However, this conventional method of constructing 4-core RTWOs inherently consumes approximately four times or more the area of ​​a single-core RTWO 200 because area optimization is not considered when arranging the individual adjacent single-core RTWO cells.

[0038] exist Figure 3On the far right, a quad-core RTWO 320 is configured according to the technology disclosed herein. Unlike the conventional quad-core RTWO configuration 310, the improved quad-core RTWO 320 exhibits a significant reduction in silicon area consumption while maintaining the functional benefits of a multi-core RTWO configuration. This embodiment allows for the interleaved arrangement of transmission lines and efficient utilization of magnetic and mutual inductive and capacitive coupling between oscillator cores, thereby eliminating the need for additional coupling tracks or devices. Generally, in an RTWO comprising N cores, where each core occupies an area A of the associated metal layer, the improved multi-core RTWO occupies at least two metal layers that are substantially smaller than the total area T of N×A. Therefore, the quad-core RTWO 320 achieves a compact form factor with only a small increase in area overhead compared to the single-core RTWO 200.

[0039] Figure 4 The diagram shows a configuration according to some embodiments of a 4-core RTWO configuration 400 (e.g., Figure 3 The image shows a cross-sectional view of the staggered four pairs of transmission lines used in the 4-core RTWO 320 described in the figure. This arrangement depicts the structuring of differential signal pairs across two metal layers to improve space efficiency and optimize electromagnetic coupling between the multiple cores of the RTWO.

[0040] Conductors 410p, 420p, 420n, and 410n are arranged from left to right on the bottom metal layer. Conductors 410p and 410n form a differential signal pair, where 410p carries a positive phase and 410n carries a negative phase. Adjacent to them, 420p and 420n form another differential pair.

[0041] Conductors 430p, 440p, 440n, and 430n are positioned on the upper metal layer in a similar left-to-right orientation. Here, 430p and 430n form one differential pair, and 440p and 440n form another differential pair. The configuration of the top metal layer, mirroring the configuration of the bottom metal layer, employs vertical dimensions to accommodate the transmission lines.

[0042] The 'p' and 'n' suffixes indicate the role of the conductors in transmitting the positive and negative phases of the differential signal, respectively, ensuring that each pair transmits the differential signal efficiently with minimal loss and interference. The routing of these associated differential signals—whether internal or external, and across the top or bottom metal layers—facilitates a balanced electromagnetic field distribution and uniform signal propagation among the eight tracks, eliminating the need for coupling tracks (e.g., ...). Figure 3 The mating connection (312) or coupling device, such as a dedicated capacitor, resistor or switch.

[0043] In some scenarios, such configurations can cause variations in parasitic effects, such as those caused by capacitance toward the substrate or adjacent tracks, which can affect performance. As used herein, parasitic effects refer to unintended and generally undesirable passive properties that arise within electronic circuits due to the physical configuration of components and interconnects. These properties can include capacitance, inductance, and resistance occurring between conductors, through the substrate, or across insulating materials, and can affect circuit performance by introducing losses, noise, and unwanted feedback or interference. In the context of oscillators and other high-frequency electronic devices, parasitic effects can significantly impact the accuracy, efficiency, and stability of the device by unintentionally altering signal paths and timing.

[0044] Return to Figure 4 For example, the inner bottom differential conductors 420p and 420n experience different parasitic conditions than the outer top differential conductors 430p and 430n due to their proximity to other conductive elements and the substrate. Therefore, in some embodiments, to address these deviations and maintain balanced operation across the four nested transmission lines, the placement of the differential signals within the transmission line loop of each RTWO core varies along the loop. This variability ensures that each differential signal encounters all possible positions within the loop, thereby balancing the overall parasitic effects experienced by the system.

[0045] Figure 5 Two configurations for arranging differential signal conductors to cancel and equalize parasitic effects in a multi-core RTWO are depicted according to some embodiments. These configurations cancel and equalize parasitic effects, and the application of rotation schemes is shown to utilize the... Figure 4 The RTWO configuration 400 serves as a starting point to uniformly distribute parasitic effects across the oscillator. This first configuration 400 positions the oscillator in a west-facing orbit that spans two metal layers.

[0046] Scenario A outlines the sequence of relative conductor positions when RTWO rotates through the west, north, east, and south configurations:

[0047] ●The West (initial configuration 400) is characterized by top layer conductors 3p, 4p, 4n, 3n and bottom layer conductors 1p, 2p, 2n, 1n.

[0048] ● The North (configuration 510) is rearranged to the top metal layer: 4p, 1p, 1n, 4n, and to the bottom metal layer: 2p, 3p, 3n, 2n. Here, although the first relative position configuration 400 (West) includes conductors 2p, 2n positioned within the interleaved differential signal conductors, this second relative position configuration 510 (North) includes those conductors 2p, 2n positioned outside the interleaved differential signal conductors.

[0049] ● East (configuration 520) is rearranged to the top metal layer: 1p, 2p, 2n, 1n, and rearranged to the bottom metal layer: 3p, 4p, 4n, 3n.

[0050] ● South (configuration 530) is rearranged to the top metal layer: 2p, 3p, 3n, 2n, and the bottom metal layer: 4p, 1p, 1n, 4n.

[0051] Scenario B shows an alternative sequence starting from the same westward direction:

[0052] ● The West (400) maintains its initial arrangement, which has a top metal layer: 3p, 4p, 4n, 3n, and a bottom metal layer: 1p, 2p, 2n, 1n.

[0053] ●The North (configuration 560) is changed to the top metal layer: 1p, 2p, 2n, 1n, and the bottom metal layer: 3p, 4p, 4n, 3n.

[0054] ● East (configuration 570) Then rotate to the top metal layer: 2p, 1p, 1n, 2n, and the bottom metal layer: 4p, 3p, 3n, 4n.

[0055] ●South (configuration 580) ends with top metal layer: 4p, 3p, 3n, 4n and bottom metal layer: 2p, 1p, 1n, 2n.

[0056] These scenarios demonstrate how a rotationally asymmetric configuration achieves overall symmetry along the transmission line loop, ensuring that each differential signal occupies all potential locations across the four basic orientations (west, north, east, and south)—whether internal or external, and on the top or bottom metal layer. Thus, the RTWO core is configured for different locations across a 360-degree directional range. This reconfiguration of the relative positions of the interleaved differential signal conductors of a multi-core RTWO across such directional ranges is not limited to arrangements within a quad-core RTWO; in various embodiments, configurations involve a greater number of RTWO cores, for example, by adding more tracks to existing metal layers or incorporating additional metal layers.

[0057] In some embodiments, the track width or spacing of the differential signal conductors can also be varied to further mitigate and / or otherwise control parasitic effects between such conductors, for example by means similar to those described above. Figure 5 The configuration described and shown applies along the RTWO core ring to all RTWO cores.

[0058] Figure 6Three alternative differential signal conductor configurations are shown, which are designed to modify the track width and / or spacing of the differential signal conductors while maintaining the relative positions of these differential signal conductors, as described above. Figure 4 and 5 The configurations described in 400 depict unrestricted variations in the physical dimensions and spacing of the differential signal conductors in the RTWO to address the effects on capacitance and other parasitic effects, thereby improving the performance characteristics of the RTWO.

[0059] Conductor configuration 610 maintains the conductor thickness within conductor configuration 400. However, it introduces a significantly increased spacing between the center conductors, particularly between 4p and 4n on the top layer and between 2p and 2n on the bottom layer. This increased conductor spacing affects the parasitic profile and signal integrity of the oscillator without altering the conductor cross-sectional area.

[0060] In conductor configuration 620, the conductor size and spacing between conductors on the top metal layer remain substantially the same as in configuration 400, with each conductor having a substantially identical cross-sectional area. However, the conductors on the bottom metal layer have significantly reduced cross-sectional areas and correspondingly increased spacing between the tracks. These different conductor sizes and spacing within the RTWO structure affect the electrical properties of the RTWO structure, particularly its associated capacitance and parasitic effects.

[0061] Conductor configuration 630 also maintains the relative positions of the differential signal conductors as defined in configuration 400. However, the cross-sectional area of ​​the center conductors (4p and 4n on the top layer and 2p and 2n on the bottom layer) is significantly reduced relative to the cross-sectional area of ​​the outer conductors (3p and 3n on the top layer and 1p and 1n on the bottom layer). This arrangement also affects the capacitance and parasitic effects of the differential signal conductors, and thus affects the overall performance of the RTWO and the internal signal propagation of the RTWO.

[0062] It should be understood that the differences in conductor width and track spacing shown in configurations 610, 620, and 630 are merely examples, and additional configurations with such differences are utilized in various embodiments. Furthermore, this variation in conductor width and track spacing can be combined with configuration variations associated with directional offsets from west to north, east, and south, as described above regarding... Figure 5 The conductor configuration is described.

[0063] Figure 7A phase-locked loop (PLL) circuit 700 for generating frequency signals in a system incorporating a multi-core RTWO is illustrated according to some embodiments. The PLL circuit includes a multi-core RTWO 720 comprising at least two metal layers and a plurality of RTWO cores, such that, as described in more detail elsewhere herein, each core includes a set of differential signal conductors interleaved across the metal layers.

[0064] In the depicted embodiment, a reference signal 705 derived from a stable frequency source provides a reference frequency 707 to a phase detector 710. The phase detector 710 compares the phase of an oscillator output signal 712 from a multi-core RTWO 720 with the reference frequency 707 and generates an error signal 718 (which in various embodiments is a voltage, current, or digital signal) as an indication of any phase misalignment. This error signal 718 is then smoothed by a loop filter 730, which modulates the signal to generate a control signal 735. The control signal 735 is fed back to the multi-core RTWO 720, which adjusts the oscillation frequency of the control signal to reduce phase errors, thereby enhancing the stability and accuracy of the output signal. Figure 3 The multi-core RTWO 720, which operates in essentially the same way as the quad-core RTWO 320, not only provides the feedback oscillator output signal 712 to the phase detector 710, but also outputs a frequency signal 725 for subsequent use, such as in communications, signal processing, or other frequency-sensitive applications.

[0065] It should be noted that not all activities or elements described in the general description above are necessary. A particular activity or part of the apparatus may be unnecessary, and one or more additional activities may be performed in addition to those described, or one or more additional elements may be included in addition to those described. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. And, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of this disclosure as set forth in the following claims. Therefore, the specification and figures should be considered illustrative rather than restrictive, and all such modifications are contemplated to be included within the scope of this disclosure.

[0066] The benefits, other advantages, and problem-solving solutions described above with respect to specific embodiments are intended to be understood. However, these benefits, advantages, problem-solving solutions, and any features that may bring about or make more significant any benefit, advantage, or solution should not be construed as key, essential, or necessary features of any or all claims. Furthermore, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter can be modified and practiced in different but equivalent ways that will be apparent to those skilled in the art from the teachings herein. No limitation is intended to be made on the details of the constructions or designs shown herein other than those described in the appended claims. Therefore, it will be apparent that changes or modifications can be made to the specific embodiments disclosed above, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the appended claims.

Claims

1. A multi-core rotating traveling wave oscillator RTWO, characterized in that, include: At least two metal layers; as well as A plurality of RTWO cores, wherein each of the plurality of RTWO cores includes a set of differential signal conductors, and wherein the differential signal conductors for the plurality of RTWO cores are interleaved via the at least two metal layers.

2. The multi-core RTWO according to claim 1, characterized in that, The set of differential signal conductors for each RTWO core are oriented across a range of directions, and the staggered differential signal conductors for the plurality of RTWO cores have a first relative position configuration in which the staggered differential signal conductors are substantially oriented in a first direction, and a different second relative position configuration in which the staggered differential signal conductors are substantially oriented in a second direction.

3. The multi-core RTWO according to claim 2, characterized in that, The first relative positioning configuration includes a plurality of conductors positioned within the inner portion of the interleaved differential signal conductors for the plurality of RTWO cores, and wherein the second relative positioning configuration includes at least one of the plurality of conductors positioned within the outer portion of the interleaved differential signal conductors.

4. The multi-core RTWO according to claim 1, characterized in that, A first subset of the differential signal conductors for the plurality of RTWO cores has a first cross-sectional area, and a second subset of the differential signal conductors for the plurality of RTWO cores has a second cross-sectional area different from the first cross-sectional area.

5. The multi-core RTWO according to claim 1, characterized in that, A first subset of the differential signal conductors used for the plurality of RTWO cores has a first spacing distance between the conductors, and a second subset of the differential signal conductors has a second spacing distance between the conductors that is different from the first spacing distance.

6. A system, characterized in that, include: A multi-core rotating traveling wave oscillator (RTWO) includes at least two metal layers and a plurality of RTWO cores, wherein each core includes a set of differential signal conductors, and wherein the differential signal conductors for the plurality of RTWO cores are interleaved via the at least two metal layers; as well as A phase-locked loop (PLL) circuit coupled to the RTWO, the PLL circuit stabilizing the frequency of the one or more RTWO signals generated by the RTWO by comparing the phase of one or more RTWO signals with a reference signal.

7. The system according to claim 6, characterized in that, The set of differential signal conductors for each RTWO core are oriented across a range of directions, and the interleaved differential signal conductors for the plurality of RTWO cores have a first relative position configuration in which they are substantially oriented in a first direction, and have different second relative position configurations in which they are substantially oriented in a second direction.

8. The system according to claim 6, characterized in that, A first subset of the differential signal conductors for the plurality of RTWO cores has a first cross-sectional area, wherein a second subset of the differential signal conductors for the plurality of RTWO cores has a second cross-sectional area different from the first cross-sectional area, wherein the differential signal conductors having the first cross-sectional area are positioned on the inner orbits of the at least two metal layers, and wherein the differential signal conductors having the second cross-sectional area are positioned on the outer orbits of the at least two metal layers.

9. The system according to claim 6, characterized in that, The first subset of the differential signal conductors for the plurality of RTWO cores has a first cross-sectional area, wherein the second subset of the differential signal conductors for the plurality of RTWO cores has a second cross-sectional area different from the first cross-sectional area, wherein the first subset of the differential signal conductors for the plurality of RTWO cores has a first spacing distance between the conductors, and wherein the second subset of the differential signal conductors has a second spacing distance between the conductors different from the first spacing distance.

10. A method, characterized in that, include: An oscillator output signal is generated using a multi-core rotating traveling wave oscillator (RTWO), wherein the multi-core RTWO comprises at least two metal layers and multiple RTWO cores, each RTWO core comprising a set of differential signal conductors, and the differential signal conductors for the multiple RTWO cores are interleaved via the at least two metal layers; and The frequency of the oscillator output signal is adjusted based on a comparison between the phase of the oscillator output signal and a reference signal.

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