Chopper circuit applied to multi-channel time division multiplexing and application thereof

Abstract

The invention discloses a chopper circuit applied to multi-channel time division multiplexing and application of the chopper circuit. The circuit comprises a differential chopper circuit and a chopper clock signal enabling processing circuit. The chopper circuit and the time division multiplexing technology are combined, the gate end control characteristic of the chopper circuit is utilized, the chopper circuit is enabled, the chopper circuit can replace a multiplexer composed of transmission gates to carry out multi-channel time division multiplexing, the circuit complexity on a time division multiplexing path is simplified, and the time division multiplexing efficiency is improved. And the noise contribution of the chopper circuit to the whole circuit is further reduced.

Description

Technical Field

[0001] This invention relates to the field of neural signal acquisition, and in particular to a chopper circuit for multiplexing time-division multiplexing and its application. Background Technology

[0002] As living standards improve, people are paying more and more attention to their health. Neurological diseases are a major cause of loss of life in adults, causing approximately 9 million deaths each year.

[0003] Neurobiology shows that brain function is related to the electrical activity of a large number of neurons, and the monitoring and recording of neurophysiological activity is a recognized and effective medical treatment. Therefore, implantable neural electrical signal acquisition technology, which combines microelectronics, neuroscience, and information science, has become a research hotspot in both academia and industry. As a carrier of this technology, implantable biomedical chips offer advantages such as good portability, high sensitivity, small size, low power consumption, and long battery life.

[0004] In analog front-end circuit design, the preamplifier is the first stage of the system. It extracts the raw bioelectrical signals for subsequent circuit processing, and its performance directly affects the processing quality of the signals in the later stages. Especially in the design of preamplifiers for biomedical electrical signal processing, factors such as equivalent input noise voltage, common-mode rejection ratio, and the effects of temperature changes must be considered. With the continuous development of the biomedical field, research on high-performance bioelectrical signal preamplifiers has received considerable attention.

[0005] Chopper modulation is an effective method for reducing low-frequency noise in bioelectric signal preamplifiers. Based on signal modulation and demodulation, chopper modulation modulates flicker noise and DC offset outside the signal band while keeping the signal at its original frequency. Finally, a low-pass filter removes high-frequency noise, thus eliminating circuit offset and flicker noise. The chopper modulation and demodulation process can be described as follows: Before the input signal enters the circuit, a square wave modulation is used to symmetrically modulate the low-frequency signal to a high-frequency chopper frequency. This signal then enters the signal processing circuit and is superimposed on flicker noise. Since the two signals are in different frequency bands, the superimposed mixed signal undergoes a second chopper modulation. The high-frequency useful signal is demodulated back to the signal fundamental frequency, while the flicker noise and DC offset voltage, originally in the low-frequency band, are modulated to a high frequency. After chopper demodulation, the high-frequency flicker noise and circuit offset are filtered out by the low-pass filter.

[0006] Multi-channel time-division multiplexing technology is designed to effectively eliminate channel mismatch, reduce system power consumption, and reduce system complexity, but at the cost of increasing the circuit complexity of the signal path. Summary of the Invention

[0007] The purpose of this invention is to provide a chopper circuit for multiplexing time-division multiplexing and its application. The circuit combines a chopper circuit with time-division multiplexing technology. Utilizing the gate control characteristics of the chopper circuit, it is enabled to replace a multiplexer composed of transmission gates for multiplexing time-division multiplexing, simplifying the circuit complexity of the time-division multiplexing path and further reducing the noise contribution of the chopper circuit to the overall circuit.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A chopper circuit for multiplexing time division multiplexing includes one or more parallel channels, each channel comprising: The differential chopper circuit contains four pairs of complementary transmission gates, each pair consisting of NMOS and PMOS transistors. The gate terminals of the four pairs of transmission gates are controlled by two inverted clock signals CLK_N and CLK_P, so that the upper and lower pairs of transmission gates and the left and right pairs of transmission gates are alternately enabled, and the differential signal is transmitted from the input terminals IN_N and IN_P to the output terminals OUT_N and OUT_P in turn. The input signal is chopped and modulated by the alternating conduction to reduce low-frequency noise. The chopper clock signal enable processing circuit enables the clock signal according to the state of the enable signal EN, controlling the enable state of the chopper circuit: when EN is 0, the output shutdown signal turns off all four pairs of transmission gates; when EN is 1, the clock signal is transmitted normally to the gate terminals, so that the circuit alternately turns on the upper / lower and left / right transmission gates in each cycle.

[0009] The differential chopper circuit controls the gate terminals of four pairs of transmission gates via two reverse clock signals, enabling the upper and lower pairs of transmission gates and the left and right pairs of transmission gates alternately. This allows the differential signals to be transmitted sequentially from the input terminals IN_N and IN_P to the output terminals OUT_N and OUT_P, thus reducing noise. Simultaneously, the chopper circuit is controlled by the enable signal EN. When EN is 0, the chopper clock signal circuit stops the clock signal and sends a shutdown signal, setting the NMOS gate terminal to 0 and all PMOS gate terminals to 1, effectively shutting down all four pairs of transmission gates. This results in a high-impedance node when viewed from the output terminal to the input terminal, equivalent to a circuit breaker. When EN is 1, the chopper clock signal circuit transmits the clock signal normally to the gate terminals of the four pairs of transmission gates, and the chopper circuit operates normally, sequentially transmitting the differential signals IN_N and IN_P to OUT_N and OUT_P.

[0010] The chopper clock signal enable processing circuit enables the clock signal according to the state of the enable signal EN, controls the enable state of the chopper circuit to change the clock signal into a shutdown signal, sets the NMOS gate terminal of the chopper circuit to 0, sets all PMOS gate terminals to 1, shuts down all four pairs of transmission gates, and makes the output terminal a high-impedance node when viewed from the input terminal, which is equivalent to a circuit breaker.

[0011] The circuit described herein, when used for four-channel time-division multiplexing, connects the four differential inputs and enable signals to four chopper circuits with enable functions respectively, and connects the differential output terminals. At any given time, only one port is enabled, outputting one signal. The signals are enabled sequentially to achieve multi-channel time-division multiplexing.

[0012] The circuit described is used as an analog front-end circuit for neural signal acquisition.

[0013] Compared with the prior art, the present invention has the following beneficial effects: To address the low-noise requirements of low-noise amplifiers, the circuit combines a chopper circuit with time-division multiplexing technology. By utilizing the gate-end control characteristics of the chopper circuit, the chopper circuit is enabled, enabling it to replace the multiplexer composed of transmission gates for multiplexing, simplifying the circuit complexity of the time-division multiplexing path, and further reducing the noise contribution of the chopper circuit to the overall circuit. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the chopper circuit structure for multiplexing multiplexing in this invention.

[0015] Figure 2 This is a schematic diagram of the single-channel chopper circuit structure in this invention.

[0016] Figure 3 This is a timing diagram of the chopper clock signal enable processing circuit in this invention.

[0017] Figure 4 This is a schematic diagram of the application of time-division multiplexing in traditional implementation circuits.

[0018] Figure 5 This is a schematic diagram illustrating the application of the time-division multiplexing of the present invention. Detailed Implementation

[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0020] like Figure 1 As shown, a chopper circuit for multiplexing time division multiplexing includes: The differential chopper circuit controls the gate terminals of four pairs of transmission gates through two reverse clocks, enabling the upper and lower pairs of transmission gates and the left and right pairs of transmission gates alternately to transmit the differential signal from the input terminals IN_N and IN_P to the output terminals OUT_N and OUT_P in turn, thereby reducing noise.

[0021] The chopper clock signal enable processing circuit enables the clock signal according to the state of the enable signal EN, thereby controlling the enable state of the chopper circuit.

[0022] In the differential chopper circuit, two reverse clock signals control the gate terminals of four pairs of transmission gates, enabling the upper and lower pairs and the left and right pairs of transmission gates alternately. This allows the differential signals to be transmitted sequentially from the input terminals IN_N and IN_P to the output terminals OUT_N and OUT_P, thus reducing noise. Simultaneously, the chopper circuit is controlled by the enable signal EN. When EN is 0, the chopper clock signal circuit stops the clock signal and sends a shutdown signal, setting the NMOS gate to 0 and all PMOS gates to 1, effectively turning off all four pairs of transmission gates. This results in a high-impedance node from the output to the input, equivalent to a circuit breaker. When EN is 1, the chopper clock signal circuit transmits the clock signal normally to the gate terminals of the four pairs of transmission gates, and the chopper circuit operates normally, sequentially transmitting the differential signals IN_N and IN_P to OUT_N and OUT_P.

[0023] In the chopper clock signal enable processing circuit, the clock signal is enabled according to the state of the enable signal EN, controlling the enable state of the chopper circuit. The clock signal is then converted into a shutdown signal, setting the NMOS gate to 0 and all PMOS gates to 1 in the chopper circuit, thus shutting down all four pairs of transmission gates. This results in a high-impedance node when viewed from the output to the input, effectively creating a circuit break.

[0024] The implementation method of the entire chopper circuit is described below: When the chopper circuit starts working, the chopper clock signal enable processing circuit first processes the clock signal, enabling it according to the state of the enable signal EN. When the enable signal EN is 0, the chopper clock signal circuit stops the clock signal and sends a shutdown signal. The NMOS gate is set to 0, and all PMOS gates are set to 1, turning off all four pairs of transmission gates. From the output to the input, this is a high-impedance node, equivalent to an open circuit. When the enable signal EN is 1, the chopper clock signal circuit transmits the clock signal normally to the four pairs of transmission gates. The chopper circuit works normally, alternately transmitting the differential signals IN_N and IN_P to OUT_N and OUT_P.

[0025] like Figure 2 The diagram shows a schematic of a single-channel chopper circuit. When the enable signal EN is 0, the PMOS gate signals p1 and p2 controlling the chopper circuit are set to 1, and the NMOS gate signals n1 and n2 controlling the chopper circuit are set to 0.

[0026] like Figure 3The diagram shows the timing sequence of the chopper clock signal enable processing circuit. At time T0, the enable signal EN1 is 0, p1 and p2 are set to 1 through NAND gates, and n1 and n2 are set to 0 through inverters. At this time, the four pairs of transmission gates in the chopper circuit are turned off. At time T1, the enable signal EN1 is set to 1. The NAND gates do not affect the normal transmission of the clock signal. p1 and n1 are transmitted to 1 and 0 respectively, turning off their left and right pairs of transmission gates. p2 and n2 are set to 0 and 1 respectively, turning on their upper and lower pairs of transmission gates. At this time, the input IN_N is transmitted to the output OUT_N, and the input IN_P is transmitted to the output OUT_P.

[0027] At time T2, p1 and n1 are set to 0 and 1 respectively, opening their left and right pairs of transmission gates. At the same time, p1 and n1 are set to 1 and 0 respectively, closing their left and right pairs of transmission gates. At this point, the input IN_N is transmitted to the output OUT_P, and the input IN_P is transmitted to the output OUT_N. Thus, at times T1 and T2, the alternating transmission from input to output is completed, achieving the goal of shifting the low-frequency signal to a higher frequency to reduce low-frequency flicker noise in the chopper circuit. At times T3, T4, T5, and T6, the clock signal is consistent with that at times T1 and T2. At time T7, the enable signal EN1 is 0, consistent with time T0. p1 and p2 are set to 1 through NAND gates, and n1 and n2 are set to 0 through inverters. At this time, the four pairs of transmission gates in the chopper circuit are closed.

[0028] like Figure 4 As shown, taking four-channel time-division multiplexing as an example, the traditional implementation circuit consists of four differential chopper circuits followed by an analog four-input selector. The output of the four-input selector is connected to the input of the low-noise amplifier module, realizing the traditional low-noise amplifier circuit design for multiplexed time-division multiplexing. In actual use, the four-channel differential chopper circuit operates continuously, and the four-input selector sequentially selects one signal from the four-channel differential chopper circuit to transmit to the input of the low-noise amplifier module. After amplification by the low-noise amplifier, the signal is output. The overall noise level within the simulated bandwidth is 3.78μV.

[0029] like Figure 5 As shown, taking a four-way time-division multiplexing circuit as an example, a low-noise amplifier (LNA) module is added after the present invention to realize the low-noise amplifier circuit design for multiplexed time-division multiplexing. In actual use, the four enable terminals are enabled sequentially, transmitting the input signals sequentially to the input terminals of the low-noise amplifier, which then amplifies the signals before output. Simulation results show that the overall noise level within the bandwidth is 3.48 μV, a reduction of 0.3 μV compared to traditional multiplexed time-division multiplexing circuits. Because the low-noise amplifier in this simulation has relatively high noise, the reduction is not significant; however, in some low-noise applications with extremely high noise requirements, a higher reduction can be achieved.

[0030] The embodiments described above can be further combined or replaced, and these embodiments are merely descriptions of preferred embodiments of the present invention, not limitations on the concept and scope of the present invention. Various changes and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the inventive concept are all within the protection scope of the present invention. The protection scope of the present invention is given by the appended claims and any equivalents.

Claims

1. A chopper circuit for multiplexed time-division multiplexing, characterized in that, Includes one or more parallel channels, each channel including: The differential chopper circuit contains four pairs of complementary transmission gates, each pair consisting of NMOS and PMOS transistors. The gate terminals of the four pairs of transmission gates are controlled by two inverted clock signals CLK_N and CLK_P, so that the upper and lower pairs of transmission gates and the left and right pairs of transmission gates are alternately enabled, and the differential signal is transmitted from the input terminals IN_N and IN_P to the output terminals OUT_N and OUT_P in turn. The input signal is chopped and modulated by the alternating conduction to reduce low-frequency noise. The chopper clock signal enable processing circuit enables the clock signal according to the state of the enable signal EN, controlling the enable state of the chopper circuit: when EN is 0, the output shutdown signal turns off all four pairs of transmission gates; when EN is 1, the clock signal is transmitted normally to the gate terminals, so that the circuit alternately turns on the upper / lower and left / right transmission gates in each cycle.

2. The circuit as described in claim 1, characterized in that, The differential chopper circuit controls the gate terminals of four pairs of transmission gates via two reverse clock signals, enabling the upper and lower pairs of transmission gates and the left and right pairs of transmission gates alternately. This allows the differential signals to be transmitted sequentially from the input terminals IN_N and IN_P to the output terminals OUT_N and OUT_P, thus reducing noise. Simultaneously, the chopper circuit is controlled by the enable signal EN. When EN is 0, the chopper clock signal circuit stops the clock signal and sends a shutdown signal, setting the NMOS gate terminal to 0 and all PMOS gate terminals to 1, effectively shutting down all four pairs of transmission gates. This results in a high-impedance node when viewed from the output terminal to the input terminal, equivalent to a circuit breaker. When EN is 1, the chopper clock signal circuit transmits the clock signal normally to the gate terminals of the four pairs of transmission gates, and the chopper circuit operates normally, sequentially transmitting the differential signals IN_N and IN_P to OUT_N and OUT_P.

3. The circuit as described in claim 1, characterized in that, The chopper clock signal enable processing circuit enables the clock signal according to the state of the enable signal EN, controls the enable state of the chopper circuit to change the clock signal into a shutdown signal, sets the NMOS gate terminal of the chopper circuit to 0, sets all PMOS gate terminals to 1, shuts down all four pairs of transmission gates, and makes the output terminal a high-impedance node when viewed from the input terminal, which is equivalent to a circuit breaker.

4. The circuit as described in claim 1, characterized in that, When performing four-channel time-division multiplexing, the four differential inputs and enable signals are respectively connected to four chopper circuits with enable functions, and the differential output terminals are connected. Only one port is enabled at a time, outputting one signal. The signals are enabled in turn to achieve multi-channel time-division multiplexing.

5. The application of the circuit as described in claim 1, characterized in that, Analog front-end circuitry for neural signal acquisition.

Images