Switch control circuit

Abstract

The invention discloses a switch control circuit. The switch control circuit comprises an operational amplifier, a switch unit, a sampling unit and a first comparator, the first input end of the operational amplifier is used for receiving input signals, the second input end of the operational amplifier is connected with the output end of the operational amplifier, the output end of the operational amplifier is used for outputting driving signals, the switch unit is connected with the output end of the operational amplifier, and the sampling unit samples current on the output tube to obtain sampling signals. The first comparator compares the sampling signal with the reference signal to generate a first characterization signal for characterizing whether the switch unit is over-current or not. According to the switch control circuit, the sampling unit is used for sampling the current on the output tube to obtain the sampling signal, the first comparator is used for comparing the sampling signal with the reference signal to generate the first characterization signal, and therefore whether overcurrent occurs on the switch unit or not is detected.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a switch control circuit. Background Technology

[0002] Switch control circuits are generally used for the transmission of control signals. In switch control circuits, it is necessary to protect the switch and require that the current flowing into / out of the switch is not too large, otherwise the switch may be burned out. Overcurrent detection on the switch is a difficult point in the protection measures.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a switch control circuit that can detect whether there is overcurrent in the switch.

[0005] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution: a switch control circuit, comprising: an operational amplifier, a switch unit, a sampling unit, and a first comparator;

[0006] The first input terminal of the operational amplifier is used to receive an input signal. The second input terminal of the operational amplifier is connected to the output terminal of the operational amplifier. The output terminal of the operational amplifier is used to output a drive signal. The switching unit is connected to the output terminal of the operational amplifier to control the transmission of the drive signal. The sampling unit is connected to the output transistor of the operational amplifier to sample the current on the output transistor to obtain a sampling signal. The first input terminal of the first comparator is connected to the sampling unit to receive the sampling signal. The second input terminal of the first comparator is used to receive a reference signal. The first comparator is used to compare the sampling signal and the reference signal to generate a first characterization signal to characterize whether there is an overcurrent on the switching unit.

[0007] In one or more embodiments of the present invention, the switch control circuit further includes a detection unit connected to a first input terminal of an operational amplifier, a second input terminal of an operational amplifier, and an output terminal of a first comparator. The detection unit is used to detect the input signal and the feedback signal at the second input terminal of the operational amplifier to generate a second characterization signal for characterizing whether there is an overcurrent on the switch unit based on the change between the input signal and the feedback signal combined with a first characterization signal.

[0008] In one or more embodiments of the present invention, the detection unit includes a second comparator, a storage unit, and an AND gate. The first input terminal of the second comparator is connected to the first input terminal of an operational amplifier, and the second input terminal of the second comparator is connected to the second input terminal of the operational amplifier. The input terminal of the storage unit is connected to the output terminal of the second comparator. The first input terminal of the AND gate is connected to the output terminal of the first comparator, and the second input terminal of the AND gate is connected to the output terminal of the storage unit. The output terminal of the AND gate is used to output a second characterization signal; or

[0009] The detection unit includes a second comparator, a storage unit, an inverter, and an AND gate. The first input terminal of the second comparator is connected to the first input terminal of the operational amplifier, and the second input terminal of the second comparator is connected to the second input terminal of the operational amplifier. The input terminal of the storage unit is connected to the output terminal of the second comparator, and the input terminal of the inverter is connected to the output terminal of the storage unit. The first input terminal of the AND gate is connected to the output terminal of the first comparator, and the second input terminal of the AND gate is connected to the output terminal of the inverter. The output terminal of the AND gate is used to output a second characterization signal.

[0010] In one or more embodiments of the present invention, the second comparator includes a cross-coupling unit, a tail current unit, a first input unit, and a second input unit; a first terminal of the first input unit and a first terminal of the second input unit are connected to the tail current unit, and a second terminal of the first input unit and a second terminal of the second input unit are connected to the cross-coupling unit; the first input unit simultaneously receives an input signal, and the second input unit simultaneously receives a feedback signal.

[0011] In one or more embodiments of the present invention, the first input unit includes a plurality of first input tubes and a first control unit;

[0012] The first control unit is connected to at least a portion of the first input transistor between the cross-coupling unit and the tail current unit. The first control unit is used to control the on / off state between the first input transistor and the cross-coupling unit and the tail current unit. The control terminal of the first input transistor is used to receive input signals; or

[0013] The first end of the first input transistor is connected to the tail current unit, the second end of the first input transistor is connected to the cross-coupling unit, the first control unit is connected to the control terminal of at least one first input transistor, the first control unit is simultaneously connected to the ground voltage and the first input terminal signal, and the first control unit is used to control the on / off connection between the control terminal of the first input transistor and the reference voltage or between the control terminal of the first input transistor and the first input terminal signal.

[0014] In one or more embodiments of the present invention, the second input unit includes a plurality of second input transistors and a second control unit. The second control unit is connected to at least a portion of the second input transistors between the cross-coupling unit and the tail current unit. The second control unit is used to control the on / off connection between the second input transistors and the cross-coupling unit and the tail current unit. The control terminal of the second input transistor is used to receive a feedback signal; or

[0015] The first end of the second input transistor is connected to the tail current unit, the second end of the second input transistor is connected to the cross-coupling unit, the second control unit is connected to the control terminal of at least one second input transistor, the second control unit is simultaneously connected to the ground voltage and the first input terminal signal, and the second control unit is used to control the on / off connection between the control terminal of the second input transistor and the reference voltage or between the control terminal of the second input transistor and the second input terminal signal.

[0016] In one or more embodiments of the present invention, the operational amplifier includes an input stage for receiving input signals and feedback signals, an output stage for outputting drive signals, and a bandwidth adjustment unit connected to the input stage and the output stage.

[0017] In one or more embodiments of the present invention, the bandwidth adjustment unit includes capacitors connected to the input stage and the output stage; or

[0018] The bandwidth adjustment unit includes multiple adjustment capacitors and adjustment switch groups connected between the input stage and the output stage. The adjustment switch groups are used to control the on / off connection between one or more adjustment capacitors and the input stage and the output stage.

[0019] In one or more embodiments of the present invention, the output stage includes a second bias unit and an output transistor. The control terminal of the output transistor is connected to the input stage, the first terminal of the bandwidth adjustment unit, and the sampling unit. The second terminal of the output transistor is connected to the second terminal of the bandwidth adjustment unit and the second terminal of the second bias unit to form the output terminal of the operational amplifier. The first terminal of the second bias unit and the first terminal of the output transistor are respectively connected to the reference voltage and the power supply voltage.

[0020] In one or more embodiments of the present invention, the sampling unit includes a sampling tube and a first bias unit. The control terminal of the sampling tube is connected to the control terminal of the output tube, and the second terminal of the sampling tube is connected to the first terminal of the first bias unit. The first terminal of the sampling tube and the second terminal of the first bias unit are respectively connected to a reference voltage and a power supply voltage.

[0021] Compared with the prior art, the switch control circuit of the present invention obtains a sampling signal by sampling the current on the output tube through a sampling unit, and generates a first characterization signal by comparing the sampling signal and a reference signal through a first comparator, thereby realizing the detection of whether there is overcurrent on the switch unit. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a partial circuit diagram of the switch control circuit in Embodiment 1 of the present invention.

[0024] Figure 2 This is a circuit diagram of the detection unit and the first comparator in Embodiment 1 of the present invention.

[0025] Figure 3 This is a circuit diagram of the bandwidth adjustment unit in another embodiment of the present invention.

[0026] Figure 4 This is a circuit diagram of the second comparator in Embodiment 1 of the present invention.

[0027] Figure 5 This is a partial circuit diagram of the switch control circuit in Embodiment 2 of the present invention.

[0028] Figure 6 This is a circuit diagram of the detection unit and the first comparator in Embodiment 2 of the present invention. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0030] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0031] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0032] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0033] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0034] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0035] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0036] Example 1

[0037] like Figure 1 and Figure 2 As shown, a switch control circuit in one embodiment of the present invention includes: an operational amplifier 10, a switch unit 20, a sampling unit 30, and a first comparator CMP1.

[0038] The first input terminal of the operational amplifier 10 is used to receive the input signal INP. The second input terminal of the operational amplifier 10 is connected to the output terminal of the operational amplifier 10 to form negative feedback. The second input terminal of the operational amplifier 10 is used to receive the feedback signal INN. The output terminal A of the operational amplifier 10 is used to output the drive signal. The switching unit 20 is connected to the output terminal A of the operational amplifier 10 to control the transmission of the drive signal.

[0039] The sampling unit 30 is connected to the output transistor MO of the operational amplifier 10 to obtain a sampling signal by sampling the current on the output transistor MO. The first input terminal of the first comparator CMP1 is connected to the sampling unit 30 to receive the sampling signal. The second input terminal of the first comparator CMP1 is used to receive the reference signal REF. The first comparator CMP1 is used to compare the sampling signal and the reference signal REF to generate a first characterization signal P1 to characterize whether there is an overcurrent on the switching unit 20.

[0040] In one embodiment, the first input terminal of the first comparator CMP1 is a negative input terminal, and the second input terminal of the first comparator CMP1 is a positive input terminal. In other embodiments, the first input terminal of the first comparator CMP1 can be a positive input terminal, and the second input terminal of the first comparator CMP1 can be a negative input terminal.

[0041] like Figure 1 As shown, the switching unit 20 includes a first switch S1. The first end of the first switch S1 is connected to the output terminal A of the operational amplifier 10, and the second end of the first switch S1 is connected to the first input terminal of the first comparator CMP1.

[0042] In one embodiment, the switching unit 20 further includes a first capacitor C1 and a second capacitor C2. The first terminal of the first capacitor C1 is connected to the first terminal of the first switch S1, and the second terminal of the first capacitor C1 is connected to ground. The first terminal of the second capacitor C2 is connected to the second terminal of the second switch, and the second terminal of the second capacitor C2 is connected to ground. The first capacitor C1 is used to ensure the stability of the drive signal output from the output terminal A of the operational amplifier 10, and the second capacitor C2 is used to ensure the stability of the signal at the second terminal of the first switch S1. In other embodiments, either the first capacitor C1 or the second capacitor C2 may be omitted, or neither the first capacitor C1 nor the second capacitor C2 may be included.

[0043] like Figure 1 As shown, the sampling unit 30 includes a sampling transistor MK and a first bias unit. The control terminal of the sampling transistor MK is connected to the control terminal of the output transistor MO. The second terminal of the sampling transistor MK is connected to the first terminal of the first bias unit to form node C to generate a sampling signal. The first terminal of the sampling transistor MK is connected to a reference voltage, and the second terminal of the first bias unit is connected to the power supply voltage VDD. The reference voltage is ground voltage GND. In one embodiment, the first bias unit includes a resistor R. The first terminal of the resistor R is connected to the second terminal of the sampling transistor MK to form node C to generate a sampling signal, and the second terminal of the resistor R is connected to the power supply voltage VDD. In other embodiments, the reference voltage may be other voltages.

[0044] like Figure 1As shown, the current on the output transistor MO is mirrored by the sampling transistor MK. The mirrored current flows through the resistor R and generates a sampling signal at node C. The sampling signal is compared with the reference signal REF by the first comparator CMP1 to determine whether there is a large current flowing through the output transistor MO, and thus whether the first switch S1 is overcurrent.

[0045] However, the above method has a drawback: when the input signal INP drops rapidly, the drive signal will also drop rapidly because the capacitor at the output terminal A of the operational amplifier 10 needs to discharge. At this time, the discharge path will go from the output terminal A of the operational amplifier 10 through the output transistor MO to ground. At this time, the sampling transistor MK will also have a large mirror current. The first comparator CMP1 outputs a high-level first characterization signal P1 and triggers the alarm. However, in fact, no overcurrent is generated on the first switch S1, so it is a false alarm.

[0046] Based on the above-mentioned shortcomings, an implementation for example Figure 2 As shown, the switch control circuit also includes a detection unit 40, which is connected to the first input terminal of the operational amplifier 10, the second input terminal of the operational amplifier 10, and the output terminal of the first comparator CMP1. The detection unit 40 is used to detect the input signal INP and the feedback signal INN to generate a second characterization signal for characterizing whether there is an overcurrent on the switch unit based on the change between the input signal INP and the feedback signal INN and the first characterization signal P1.

[0047] Specifically, the detection unit 40 includes a second comparator CMP2, a storage unit, and an AND gate. The first input of the second comparator CMP2 is connected to the first input of the operational amplifier 10 to receive the input signal INP. The second input of the second comparator CMP2 is connected to the second input of the operational amplifier 10 to receive the feedback signal INN. The input of the storage unit is connected to the output OUT of the second comparator CMP2. The first input of the AND gate is connected to the output of the first comparator CMP1, and the second input of the AND gate is connected to the output of the storage unit. The output of the AND gate is used to output the second characterization signal P2. In one embodiment, the first input of the second comparator CMP2 is a positive input, the second input of the second comparator CMP2 is a negative input, and the storage unit is a latch. In other embodiments, the first input of the second comparator CMP2 can be a negative input, the second input of the second comparator CMP2 can be a positive input, and the storage unit can also be other circuit structures, or a delay circuit can be used instead.

[0048] like Figure 1 As shown, the operational amplifier 10 includes an input stage for receiving input signal INP and feedback signal INN, an output stage for output driving signal, and a bandwidth adjustment unit 11 connected to the input stage and the output stage.

[0049] The input stage includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a current source I. The control terminal of the first transistor M1 receives the input signal INP. The control terminal of the second transistor M2 is connected to the output terminal A of the operational amplifier 10 and receives the feedback signal INN. The first terminals of the first transistor M1 and the second transistor M2 are connected to the first terminal of the current source I. The second terminal of the current source I is connected to a reference voltage. The third transistor M3 and the fourth transistor M4 form a current mirror. The control terminals of the third transistor M3 and the fourth transistor M4, the second terminal of the third transistor M3, and the second terminal of the first transistor M1 are connected. The second terminal of the fourth transistor M4 is connected to the second terminal of the second transistor M2, the control terminal of the output transistor MO, and the first terminal of the bandwidth adjustment unit 11. The first terminals of the third transistor M3 and the fourth transistor M4 are connected to the power supply voltage VDD. In other embodiments, the input stage can also have other circuit structures.

[0050] The output stage includes a second bias unit and the aforementioned output transistor MO. The control terminal of the output transistor MO is connected to the second terminal of the fourth transistor M4 and the second terminal of the second transistor M2 in the input stage, the first terminal of the bandwidth adjustment unit 11, and the control terminal of the sampling transistor MK in the sampling unit 30. The second terminal of the output transistor MO is connected to the second terminal of the bandwidth adjustment unit 11 and the second terminal of the second bias unit to form the output terminal A of the operational amplifier 10. The first terminal of the output transistor MO is connected to the reference voltage, and the first terminal of the second bias unit is connected to the power supply voltage VDD. In one embodiment, the second bias unit includes a bias transistor MP. The control terminal of the bias transistor MP is used to receive the bias voltage VP, the first terminal of the bias transistor MP is used to receive the power supply voltage VDD, and the second terminal of the bias transistor MP is connected to the second terminal of the output transistor MO. In other embodiments, the second bias unit can be a resistor or other structure. In addition, the output transistor MO can be a P-channel MOS transistor. In this case, the positions of the output transistor MO and the second bias unit need to be interchanged, and the structure of the corresponding sampling unit 30 is also adapted accordingly.

[0051] like Figure 1 As shown, in one embodiment, the bandwidth adjustment unit 11 includes a capacitor Cp connected to the input stage and the output stage. Specifically, the first end of the capacitor Cp is connected to the second end of the fourth transistor M4, the second end of the second transistor M2 and the control terminal of the output transistor MO, and the second end of the capacitor Cp is connected to the second end of the bias transistor MP and the second end of the output transistor MO.

[0052] In other embodiments, the bandwidth adjustment unit 11 includes a plurality of regulating capacitors and a group of regulating switches connected between the input stage and the output stage. The group of regulating switches controls the switching between one or more regulating capacitors and the input stage and the output stage. The group of regulating switches consists of one or more regulating switches, and the regulating capacitors and regulating switches connected in series form a capacitor branch. Figure 3 Three parallel capacitor branches are shown. These parallel branches form two common terminals. One common terminal is connected to the second terminal of the fourth transistor M4, the second terminal of the second transistor M2, and the control terminal of the output transistor MO. The other common terminal is connected to the second terminal of the bias transistor MP and the second terminal of the output transistor MO. The three capacitor branches are respectively series-connected regulating capacitor Cy1 and regulating switch Sy1, series-connected regulating capacitor Cy2 and regulating switch Sy2, and series-connected regulating capacitor Cy3 and regulating switch Sy3. The number of capacitor branches can be increased or decreased as needed. Additionally, it is possible to select one or some capacitor branches containing only regulating capacitors.

[0053] like Figure 4 As shown, the second comparator CMP2 includes a cross-coupling unit 411, a tail current unit Iw, a first input unit 412, and a second input unit 413. The first terminal of the first input unit 412 and the first terminal of the second input unit 413 are connected to the tail current unit Iw. The second terminal of the first input unit 412 and the second terminal of the second input unit 413 are connected to the cross-coupling unit 411. The first input unit 412 simultaneously receives the input signal INP, and the second input unit 413 simultaneously receives the feedback signal INN.

[0054] The cross-coupling unit 411 includes a fifth transistor M5 and a sixth transistor M6. The first terminals of the fifth transistor M5 and the sixth transistor M6 are connected to the power supply voltage VDD. The control terminal of the sixth transistor M6 is connected to the second terminal of the fifth transistor M5 to form a first connection terminal K1. The control terminal of the fifth transistor M5 is connected to the second terminal of the sixth transistor M6 to form a second connection terminal K2. The second connection terminal K2 serves as the output terminal OUT of the second comparator CMP2.

[0055] The first input unit 412 includes a plurality of first input transistors and a first control unit. The first end of the first input transistor is connected to the tail current unit Iw, and the second end of the first input transistor is connected to the cross-coupling unit 411. The first control unit is connected to the control terminal of at least one first input transistor. The first control unit is simultaneously connected to the ground voltage and the first input terminal signal. The first control unit is used to control the on / off connection between the control terminal of the first input transistor and the reference voltage or between the control terminal of the first input transistor and the first input terminal signal.

[0056] In one embodiment, two first input transistors Ma1 and Ma2 are provided, and the first control unit includes a first switching switch Sa. The second ends of the first input transistors Ma1 and Ma2 are connected to a first connection terminal K1. The first ends of the first input transistors Ma1 and Ma2 are connected to the first end of the tail current unit Iw, and the second end of the tail current unit Iw is connected to a reference voltage. The first end of the first switching switch Sa is connected to the control terminal of the first input transistor Ma1 to form the first input terminal of the second comparator CMP2 to receive the input signal INP. The second end of the first switching switch Sa is connected to the reference voltage, and the common terminal of the first switching switch Sa is connected to the control terminal of the first input transistor Ma2. The first switching switch Sa is used to switch the connection between the control terminal of the first input transistor Ma2 and the first end of the first switching switch Sa, or between the control terminal of the first input transistor Ma2 and the second end of the first switching switch Sa. In other embodiments, the number of first input transistors connected in parallel and the corresponding number of first switching switches can be set as needed.

[0057] The second input unit 413 includes multiple second input transistors and a second control unit. The first end of the second input transistor is connected to the tail current unit Iw, and the second end of the second input transistor is connected to the cross-coupling unit 411. The second control unit is connected to the control terminal of at least one second input transistor. The second control unit is simultaneously connected to the ground voltage and the first input terminal signal. The second control unit is used to control the connection and disconnection between the control terminal of the second input transistor and the reference voltage or between the control terminal of the second input transistor and the second input terminal signal.

[0058] In one embodiment, two second input transistors Mb1 and Mb2 are provided, and the second control unit includes a second switching switch Sb. The second ends of the second input transistors Mb1 and Mb2 are connected to a second connection terminal K2. The first ends of the second input transistors Mb1 and Mb2 are connected to the first end of the tail current unit Iw, and the second end of the tail current unit Iw is connected to a reference voltage. The first end of the second switching switch Sb is connected to the control terminal of the second input transistor Mb1 to form the second input terminal of the second comparator CMP2 to receive the feedback signal INN. The second end of the second switching switch Sb is connected to the reference voltage, and the common terminal of the second switching switch Sb is connected to the control terminal of the second input transistor Mb2. The second switching switch Sb is used to switch between connecting the control terminal of the second input transistor Mb2 to the first end of the second switching switch Sb or between connecting the control terminal of the second input transistor Mb2 to the second end of the second switching switch Sb. In other embodiments, the number of second input transistors and the second switching switch can be set as needed.

[0059] In other embodiments, the first input unit 412 includes a plurality of first input transistors and a first control unit. The first control unit is connected to at least a portion of the first input transistors between the cross-coupling unit 411 and the tail current unit Iw. The first control unit is used to control the on / off connection between the first input transistors and the cross-coupling unit 411 and the tail current unit Iw. The control terminal of the first input transistor is used to receive the input signal INP. Specifically, the first control unit includes a control switch. The control switch and the first input transistor are connected in series between the first connection terminal K1 and the first terminal of the tail current unit Iw. The control terminal of the first input transistor receives the input signal INP. The number of first control switches and the number of first input transistors connected in series with the first control switches can be set as needed.

[0060] In other embodiments, the second input unit 413 includes a plurality of second input transistors and a second control unit. The second control unit is connected to at least a portion of the second input transistors between the cross-coupling unit 411 and the tail current unit Iw. The second control unit is used to control the on / off connection between the second input transistors and the cross-coupling unit 411 and the tail current unit Iw. The control terminal of the second input transistor is used to receive a feedback signal INN. Specifically, the second control unit includes a second control switch. The second control switch and the second input transistor are connected in series between the second connection terminal K2 and the first terminal of the tail current unit Iw. The control terminal of the second input transistor receives the feedback signal INN. The number of second control switches and the number of second input transistors connected in series with the second control switches can be set as needed.

[0061] In one embodiment, the output transistor MO, sampling transistor MK, first transistor M1, second transistor M2, first input transistors Ma1, Ma2, and second input transistors Mb1, Mb2 are N-channel MOSFETs; the third transistor M3, fourth transistor M4, bias transistor MP, fifth transistor M5, and sixth transistor M6 are P-channel MOSFETs. In other embodiments, the output transistor MO, sampling transistor MK, first transistor M1, second transistor M2, first input transistors Ma1, Ma2, and second input transistors Mb1, Mb2 are P-channel MOSFETs; the third transistor M3, fourth transistor M4, bias transistor MP, fifth transistor M5, and sixth transistor M6 are N-channel MOSFETs.

[0062] The first terminals of the output transistor MO, the sampling transistor MK, the first transistor M1, the second transistor M2, the first input transistor Ma1, the first input transistor Ma2, the second input transistor Mb1, the second input transistor Mb2, the third transistor M3, the fourth transistor M4, the bias transistor MP, the fifth transistor M5, and the sixth transistor M6 are the sources; the second terminals of the output transistor MO, the sampling transistor MK, the first transistor M1, the second transistor M2, the first input transistor Ma1, the first input transistor Ma2, and the second input transistor Mb1 are the sources. The second terminal of the transistor, the second terminal of the second input transistor Mb2, the second terminal of the third transistor M3, the second terminal of the fourth transistor M4, the second terminal of the bias transistor MP, the second terminal of the fifth transistor M5, and the second terminal of the sixth transistor M6 are the drains; the control terminals of the output transistor MO, the control terminals of the sampling transistor MK, the control terminals of the first transistor M1, the control terminals of the second transistor M2, the control terminals of the first input transistor Ma1, the control terminals of the first input transistor Ma2, the control terminals of the second input transistor Mb1, the control terminals of the second input transistor Mb2, the control terminals of the third transistor M3, the control terminals of the fourth transistor M4, the control terminals of the bias transistor MP, the control terminals of the fifth transistor M5, and the control terminals of the sixth transistor M6 are the gates.

[0063] In one embodiment, the detection unit 40 can detect whether the input signal INP has decreased. When the input signal INP does not change, the input terminal of the operational amplifier 10 is virtually shorted, so the feedback signal INN is equal to the input signal INP, and the second comparator CMP2 does not flip.

[0064] When it is necessary to detect a downward change in the input signal INP, the second comparator CMP2 is configured to positive threshold voltage mode. At this time, the first switching switch Sa connects the control terminal of the first input transistor Ma2 to the input signal INP, and the second switching switch Sb connects the control terminal of the second input transistor Mb2 to the reference voltage, so that INP+Vth>INN, where Vth is the threshold voltage of the second comparator CMP2, and the second comparator CMP2 will output a high-level signal. If the input signal INP decreases, due to the bandwidth limitation of operational amplifier 10, the feedback signal INN cannot keep up with the change in the input signal INP. At this time, INP + Vth < INN, and the second comparator CMP2 outputs a low-level signal, providing a detection flag signal. The storage unit temporarily stores this low-level signal (setting up the storage unit can prevent the feedback signal INN from following the change in the input signal INP and causing a detection error due to the change in the output of the second comparator CMP2). At this time, even if the first comparator CMP1 outputs a high-level first characterization signal P1, the second characterization signal P2 output after passing through the AND gate will still be low and will not trigger an alarm. That is, when the current on the sampling tube MK increases due to the decreasing input signal INP, false alarms can be avoided.

[0065] The capacitor Cp in the bandwidth adjustment unit 11 can be changed according to the response requirements to changes in the input signal INP. When a response to slowly changing input signal INP is not required, capacitor Cp can be reduced to increase the bandwidth of operational amplifier 10, allowing the feedback signal INN to change synchronously with the input signal INP, and the second comparator CMP2 will not flip. When a response to slowly changing input signal INP is required, capacitor Cp can be increased to reduce the bandwidth of operational amplifier 10, preventing the feedback signal INN from changing synchronously with the input signal INP, and causing the second comparator CMP2 to flip. Figure 4 The threshold voltage Vth of the second comparator CMP2 is configurable, and the detection input signal INP can be controlled by configuring positive and negative threshold voltage modes.

[0066] The time constant of the op-amp settling is GBW is the bandwidth configured by the operational amplifier 10 through the capacitor Cp, and G is the closed-loop gain bandwidth, which is 1 in this application.

[0067] The detection rate of the input signal INP can be determined by the following formula. Assuming that the voltage of the input signal INP changes by V1 at time t1, the threshold voltage Vth of the second comparator CMP2 is configured to be V2, and the current time is t2, then when the feedback signal INN is V2 higher than the input signal INP, the output of the second comparator CMP2 will flip.

[0068]

[0069] The present invention also discloses a chip including the above-described switch control circuit.

[0070] Example 2

[0071] like Figure 5 As shown, the difference between this embodiment and Embodiment 1 is that the input stage of the operational amplifier 10 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a current source I. The control terminal of the first transistor M1 receives the input signal INP. The control terminal of the second transistor M2 is connected to the output terminal A of the operational amplifier 10 and receives the feedback signal INN. The first terminals of the first transistor M1 and the second transistor M2 are connected to the first terminal of the current source I. The second terminal of the current source I is connected to a reference voltage. The third transistor M3 and the fourth transistor M4 form a current mirror. The control terminals of the third transistor M3 and the fourth transistor M4, the second terminal of the fourth transistor M4, and the second terminal of the second transistor M2 are connected. The second terminal of the third transistor M3 is connected to the second terminal of the first transistor M1 and the control terminal of the output transistor MO. The first terminals of the third transistor M3 and the first terminals of the fourth transistor M4 are connected to the power supply voltage VDD. In other embodiments, the input stage can also have other circuit structures.

[0072] The output stage includes a second bias unit and an output transistor MO. The control terminal of the output transistor MO is connected to the second terminal of the third transistor M3 of the input stage, the second terminal of the first transistor M1, the first terminal of the bandwidth adjustment unit 11, and the control terminal of the sampling transistor MK of the sampling unit 30. The second terminal of the output transistor MO is connected to the second terminal of the bandwidth adjustment unit 11 and the second terminal of the second bias unit to form the output terminal A of the operational amplifier 10. The first terminal of the output transistor MO is connected to the power supply voltage VDD, and the first terminal of the second bias unit is connected to the reference voltage. In one embodiment, the second bias unit includes a bias transistor MP. The control terminal of the bias transistor MP is used to receive the bias voltage VP, the first terminal of the bias transistor MP is used to receive the reference voltage, and the second terminal of the bias transistor MP is connected to the second terminal of the output transistor MO. In one embodiment, the reference voltage is ground voltage GND. In other embodiments, the second bias unit can be a resistor or other structure.

[0073] The output transistor MO is a P-channel MOSFET, the bias transistor MP is an N-channel MOSFET, the first terminal of the output transistor MO and the first terminal of the bias transistor MP are the source, the second terminal of the output transistor MO and the second terminal of the bias transistor MP are the drain, and the control terminal of the output transistor MO and the control terminal of the bias transistor MP are the gate.

[0074] like Figure 5As shown, the sampling unit 30 includes a sampling transistor MK and a first bias unit. The control terminal of the sampling transistor MK is connected to the control terminal of the output transistor MO. The second terminal of the sampling transistor MK is connected to the first terminal of the first bias unit to form node C to generate a sampling signal. The first terminal of the sampling transistor MK is connected to the power supply voltage VDD, and the second terminal of the first bias unit is connected to a reference voltage, which is ground voltage GND. In one embodiment, the first bias unit includes a resistor R. The first terminal of the resistor R is connected to the second terminal of the sampling transistor MK to form node C to generate a sampling signal, and the second terminal of the resistor R is connected to the reference voltage. In other embodiments, the reference voltage can be other voltages. The sampling transistor MK is a P-channel MOS transistor. The first terminal of the sampling transistor MK is the source, the second terminal of the sampling transistor MK is the drain, and the control terminal of the sampling transistor MK is the gate.

[0075] like Figure 6 As shown, the second input terminal of the first comparator CMP1 is connected to the second terminal of the sampling tube MK of the sampling unit 30 to receive the sampling signal. The first input terminal of the first comparator CMP1 is used to receive the reference signal REF. The first comparator CMP1 is used to compare the sampling signal and the reference signal REF to generate a first characterization signal P1 to characterize whether there is an overcurrent in the switching unit 20. In one embodiment, the second input terminal of the first comparator CMP1 is a positive input terminal, and the first input terminal of the first comparator CMP1 is a negative input terminal.

[0076] like Figure 6 As shown, the detection unit 40 includes a second comparator CMP2, a storage unit, an inverter N1, and an AND gate. The first input terminal of the second comparator CMP2 is connected to the first input terminal of the operational amplifier 10 to receive the input signal INP. The second input terminal of the second comparator CMP2 is connected to the second input terminal of the operational amplifier 10 to receive the feedback signal INN. The input terminal of the storage unit is connected to the output terminal OUT of the second comparator CMP2. The input terminal of the inverter N1 is connected to the output terminal of the storage unit. The first input terminal of the AND gate is connected to the output terminal of the first comparator CMP1. The second input terminal of the AND gate is connected to the output terminal of the inverter N1. The output terminal of the AND gate is used to output the second characterization signal P2.

[0077] In one embodiment, the detection unit 40 detects whether the input signal INP rises. When the input signal INP does not change, the input terminal of the operational amplifier 10 is virtually shorted, so the feedback signal INN is equal to the input signal INP, and the second comparator CMP2 does not flip.

[0078] When it is necessary to detect an upward change in the input signal INP, Figure 4The second comparator CMP2 is configured in negative threshold voltage mode. In this mode, the first switch Sa connects the control terminal of the first input transistor Ma2 to the reference voltage, and the second switch Sb connects the control terminal of the second input transistor Mb2 to the input signal INP, making INP < INN + Vth, where Vth is the threshold voltage of the second comparator CMP2. The second comparator CMP2 will output a low-level signal. If the input signal INP rises, due to the bandwidth limitation of operational amplifier 10, the feedback signal INN cannot keep up with the change in the input signal INP. At this time, INP > INN + Vth, and the second comparator CMP2 outputs a high-level signal, providing a detection flag signal. The storage unit temporarily stores this high-level signal, and the inverter N1 inverts this high-level signal to output a low-level signal. Even if the first comparator CMP1 outputs a high-level first characterization signal P1, the second characterization signal P2 output after AND gate is still low and will not trigger an alarm. That is, when the current on the sampling transistor MK increases due to the rising input signal INP, false alarms can be avoided.

[0079] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0080] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A switch control circuit, characterized in that, include: Operational amplifier, switching unit, sampling unit, and first comparator; The first input terminal of the operational amplifier is used to receive an input signal. The second input terminal of the operational amplifier is connected to the output terminal of the operational amplifier. The output terminal of the operational amplifier is used to output a drive signal. The switching unit is connected to the output terminal of the operational amplifier to control the transmission of the drive signal. The sampling unit is connected to the output transistor of the operational amplifier to sample the current on the output transistor to obtain a sampling signal. The first input terminal of the first comparator is connected to the sampling unit to receive the sampling signal. The second input terminal of the first comparator is used to receive a reference signal. The first comparator is used to compare the sampling signal and the reference signal to generate a first characterization signal to characterize whether there is an overcurrent on the switching unit.

2. The switch control circuit according to claim 1, characterized in that, The switch control circuit further includes a detection unit, which is connected to the first input terminal of the operational amplifier, the second input terminal of the operational amplifier, and the output terminal of the first comparator. The detection unit is used to detect the input signal and the feedback signal on the second input terminal of the operational amplifier to generate a second characterization signal based on the change between the input signal and the feedback signal and the first characterization signal to characterize whether there is an overcurrent on the switch unit.

3. The switch control circuit according to claim 2, characterized in that, The detection unit includes a second comparator, a storage unit, and an AND gate. The first input of the second comparator is connected to the first input of an operational amplifier, and the second input of the second comparator is also connected to the second input of the operational amplifier. The input of the storage unit is connected to the output of the second comparator. The first input of the AND gate is connected to the output of the first comparator, and the second input of the AND gate is connected to the output of the storage unit. The output of the AND gate is used to output a second characterization signal; or The detection unit includes a second comparator, a storage unit, an inverter, and an AND gate. The first input terminal of the second comparator is connected to the first input terminal of the operational amplifier, and the second input terminal of the second comparator is connected to the second input terminal of the operational amplifier. The input terminal of the storage unit is connected to the output terminal of the second comparator, and the input terminal of the inverter is connected to the output terminal of the storage unit. The first input terminal of the AND gate is connected to the output terminal of the first comparator, and the second input terminal of the AND gate is connected to the output terminal of the inverter. The output terminal of the AND gate is used to output a second characterization signal.

4. The switch control circuit according to claim 3, characterized in that, The second comparator includes a cross-coupling unit, a tail current unit, a first input unit, and a second input unit; the first terminal of the first input unit and the first terminal of the second input unit are connected to the tail current unit, and the second terminal of the first input unit and the second terminal of the second input unit are connected to the cross-coupling unit; the first input unit simultaneously receives the input signal, and the second input unit simultaneously receives the feedback signal.

5. The switch control circuit according to claim 4, characterized in that, The first input unit includes a plurality of first input tubes and a first control unit; The first control unit is connected to at least a portion of the first input transistor between the cross-coupling unit and the tail current unit. The first control unit is used to control the on / off connection between the first input transistor and the cross-coupling unit and the tail current unit. The control terminal of the first input transistor is used to receive input signals. or The first end of the first input transistor is connected to the tail current unit, the second end of the first input transistor is connected to the cross-coupling unit, the first control unit is connected to the control terminal of at least one first input transistor, the first control unit is simultaneously connected to the ground voltage and the first input terminal signal, and the first control unit is used to control the on / off connection between the control terminal of the first input transistor and the reference voltage or between the control terminal of the first input transistor and the first input terminal signal.

6. The switch control circuit according to claim 4, characterized in that, The second input unit includes a plurality of second input transistors and a second control unit. The second control unit is connected to at least a portion of the second input transistors between the cross-coupling unit and the tail current unit. The second control unit is used to control the on / off connection between the second input transistors and the cross-coupling unit and the tail current unit. The control terminal of the second input transistor is used to receive feedback signals. or The first end of the second input transistor is connected to the tail current unit, the second end of the second input transistor is connected to the cross-coupling unit, the second control unit is connected to the control terminal of at least one second input transistor, the second control unit is simultaneously connected to the ground voltage and the first input terminal signal, and the second control unit is used to control the on / off connection between the control terminal of the second input transistor and the reference voltage or between the control terminal of the second input transistor and the second input terminal signal.

7. The switch control circuit according to claim 1, characterized in that, The operational amplifier includes an input stage for receiving input signals and feedback signals, an output stage for outputting drive signals, and a bandwidth adjustment unit connected to the input stage and the output stage.

8. The switch control circuit according to claim 7, characterized in that, The bandwidth adjustment unit includes capacitors connected to the input stage and the output stage; or The bandwidth adjustment unit includes multiple adjustment capacitors and adjustment switch groups connected between the input stage and the output stage. The adjustment switch groups are used to control the on / off connection between one or more adjustment capacitors and the input stage and the output stage.

9. The switch control circuit according to claim 7, characterized in that, The output stage includes a second bias unit and an output transistor. The control terminal of the output transistor is connected to the input stage, the first terminal of the bandwidth adjustment unit, and the sampling unit. The second terminal of the output transistor is connected to the second terminal of the bandwidth adjustment unit and the second terminal of the second bias unit to form the output terminal of the operational amplifier. The first terminal of the second bias unit and the first terminal of the output transistor are respectively connected to the reference voltage and the power supply voltage.

10. The switch control circuit according to claim 1, characterized in that, The sampling unit includes a sampling tube and a first bias unit. The control terminal of the sampling tube is connected to the control terminal of the output tube, and the second terminal of the sampling tube is connected to the first terminal of the first bias unit. The first terminal of the sampling tube and the second terminal of the first bias unit are respectively connected to the reference voltage and the power supply voltage.

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