Distributed brain neuron electrophysiological signal recording and stimulating system

Abstract

The invention relates to the technical field of electrophysiological signal recording and stimulation of cerebral neurons, in particular to a distributed electrophysiological signal recording and stimulation system for cerebral neurons. The system comprises a recording path and a stimulation path, wherein the recording path is composed of an analog switch, a multi-stage cascade amplifier, a plurality of analog-to-digital converters, an FPGA main control board and a computer, and electrophysiological signals are collected and uploaded; the stimulation channel is composed of the computer, the FPGA main control board, a digital-to-analog converter and the analog switch and is used for issuing an electrical stimulation signal; wherein the amplifier, the converter and the power supply module are integrated on an independent PCB (Printed Circuit Board) and are connected with the FPGA main control board through an FMC (Frequency Management Controller) interface. The system configures the oversampling multiplying power of the analog-to-digital converter through the FPGA main control board so as to optimize the actual sampling rate and the signal-to-noise ratio. According to the invention, integration of acquisition and stimulation functions, hardware modularization and dynamic adjustment of signal quality are realized, and the flexibility and signal fidelity of the system are improved.

Description

Technical Field

[0001] This invention relates to the field of electrophysiological signal recording and stimulation technology of brain neurons, and particularly to a distributed electrophysiological signal recording and stimulation system for brain neurons, which is suitable for in vivo electrophysiological brain science research. Background Technology

[0002] In cutting-edge research such as brain-computer interfaces, electrophysiological signal acquisition systems require high-fidelity synchronous acquisition of weak neural signals from multiple channels and the application of precise electrical stimulation. However, the sampling frequency of existing mainstream systems is usually fixed at the hardware level and cannot be dynamically adjusted according to experimental needs, leading to a fundamental dilemma: when capturing high-frequency action potentials, insufficient sampling rate can easily cause signal aliasing and information loss due to the Nyquist sampling theorem; when recording low-frequency field potentials, an excessively high fixed sampling rate generates redundant data, unnecessarily increasing storage, bandwidth, and power consumption burdens. Researchers are unable to optimize the trade-off between signal fidelity and system efficiency.

[0003] Existing technologies, such as the multi-channel acquisition device disclosed in CN120788588A, have their ADC sampling rate determined during the hardware design phase and cannot be adjusted during subsequent use. Such systems also lack integrated acquisition and stimulation design, making channel resources difficult to reuse.

[0004] The technical problem that the existing technology has not yet solved is that there is no integrated electrophysiological recording and stimulation system that can dynamically adjust the sampling rate and signal-to-noise ratio without replacing the hardware, which makes it difficult to meet the needs of modern neuroscience for device flexibility, miniaturization and signal fidelity. Summary of the Invention

[0005] (1) Technical problems to be solved To address the technical problem of existing electrophysiological recording systems being unable to achieve a balance between signal fidelity and system efficiency due to fixed sampling frequencies, this invention provides an electrophysiological signal recording and stimulation system for distributed brain neurons with flexibly configurable sampling rates and a modular design.

[0006] (2) Technical solution A distributed electrophysiological signal recording and stimulation system for brain neurons. The system includes recording and stimulation pathways, and shares an analog switch to simplify front-end design and improve integration.

[0007] The recording path is used to acquire, process, and upload signals, and includes an analog switch, an amplification unit, an analog-to-digital converter, and an FPGA main control board connected in sequence. The stimulation path is used to receive and transmit stimulation signals, and includes the FPGA main control board, the digital-to-analog converter, and the analog switch connected in sequence. The analog switch is shared by the recording path and the stimulation path, and operates in a time-division multiplexing manner under the control of the FPGA main control board.

[0008] Furthermore, the FPGA main control board not only serves as the system's control core but also constitutes a high-speed data interaction platform. This main control board integrates an FPGA chip, DDR3 memory, and an Ethernet communication interface. The DDR3 memory is used for real-time caching of large amounts of acquired electrophysiological signal data; the Ethernet communication interface is used for high-speed, stable bidirectional communication with the host computer, receiving control commands and uploading data.

[0009] To achieve modularity and scalability, the amplification unit, analog-to-digital conversion unit, digital-to-analog conversion unit, and system power module are highly integrated onto a single printed circuit board. This printed circuit board connects to the FPGA main control board via a standardized board-to-board connector, forming a complete acquisition and stimulation node. Preferably, the standardized board-to-board connector is an FPGA mezzanine card interface.

[0010] As the core control unit of the system, the FPGA main control board is configured to perform the following key functions: Sampling control: The oversampling rate of the analog-to-digital conversion unit is dynamically adjusted according to instructions from the computer, thereby optimizing the trade-off between the actual sampling rate and the signal-to-noise ratio of the system.

[0011] Stimulation waveform generation and driving: Receive and parse stimulation parameter instructions from the computer, and drive the digital-to-analog conversion unit to output precise electrical stimulation signals with corresponding waveforms, frequencies, and amplitudes.

[0012] Data stream management: In the recording path, the digitized electrophysiological signals are processed in real time, and they are controlled to pass through the first-in-first-out queue for encapsulation and packaging, cached in DDR3 memory, and then sent to the computer through the Ethernet interface via queue scheduling.

[0013] Pathway switching control: The control system uses the shared analog switch in a time-division multiplexing manner to precisely switch between the electrophysiological signal acquisition mode and the electrical stimulation signal transmission mode, avoiding mutual interference.

[0014] In terms of hardware layout and power supply design, the independent printed circuit board also includes a power module. This module provides stable, multi-channel isolated voltages to the amplification unit, analog-to-digital converter, and digital-to-analog converter on the board. To ensure signal quality, the power supply lines and signal traces of the recording and stimulation paths on the printed circuit board are physically isolated to minimize crosstalk and noise.

[0015] (3) Beneficial effects The beneficial effects of this invention are: by dynamically configuring the oversampling rate of the analog-to-digital converter unit through FPGA, the system can dynamically adjust the oversampling rate of the analog-to-digital converter unit according to instructions from the computer to achieve a trade-off between sampling rate and signal-to-noise ratio. It can adapt to multi-modal recording requirements ranging from high-frequency action potentials to slow-wave field potentials without hardware modifications. Theoretically, the signal-to-noise ratio improvement follows a 10log... 10 (OSR) dB. In one embodiment, the AD7606 ADC is used, and the measured signal-to-noise ratio is improved by 7.9 dB under 64x oversampling, which effectively improves the detection capability of weak signals. At the same time, the recording and stimulation pathways share an analog switch and adopt time-division multiplexing control, which reduces the hardware cost of a single channel and the system size. The front-end circuit adopts a distributed architecture with FMC modular interface, which supports flexible expansion of multiple boards and plug-and-play maintenance, significantly improving the system's integration, flexibility and signal fidelity. Attached Figure Description

[0016] Figure 1 This is a structural diagram of the distributed brain neuron electrophysiological signal recording and stimulation system of the present invention.

[0017] Figure 2 This is a system framework diagram in Embodiment 1 of the present invention.

[0018] Figure 3 This is a circuit diagram of the power supply module in Embodiment 2 of the present invention. Detailed Implementation

[0019] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figure 1 The diagram shown is an overall workflow flowchart of a distributed brain neuron electrophysiological signal recording and stimulation system according to an embodiment of the present invention. See also... Figure 1 The system of the present invention mainly includes: a computer FPGA main control board, an analog-to-digital conversion unit, a cascaded amplifier, a digital-to-analog conversion unit, and an analog switch. The FPGA main control board integrates an FPGA main control chip, a DDR3 memory, and an Ethernet communication interface.

[0020] The system is designed to accommodate brain-computer interface (BCI) electrodes. These electrodes are electrically connected to the analog switch and can input electrophysiological signals or output stimulation signals. The PCB integrates not only the analog-to-digital converter (ADC), cascaded amplifier, digital-to-analog converter (DAC), and analog switch, but also a power supply module to power the PCB modules. Specifically, the cascaded amplifier conditions and amplifies the input electrophysiological signals; the ADC converts the amplified analog signals into digital signals, which are then transmitted to the FPGA via the FMC interface; the DAC receives digital instructions from the FPGA and outputs specific stimulation waveforms to the BCI electrodes.

[0021] The FPGA main control board is connected to the PCB via a standard inter-board interface (such as an FMC interface). When the computer software sends a command for data acquisition, the analog switch electrically activates the recording channel. The FPGA main control board drives the analog-to-digital converter (ADC) to operate and sets the oversampling rate of the chip. It then encapsulates and packages the digital signal output by the ADC, uses a FIFO to buffer the data in DDR3, reads the data from DDR3 using the FIFO, and subsequently encapsulates the data into an Ethernet communication protocol and sends it to the computer via Ethernet. The computer software saves the data from each channel separately, completing the electrophysiological signal recording. In addition, the computer software sets relevant stimulation signals and sends commands to the FPGA main control board via Ethernet. The FPGA main control board recognizes the commands and activates the stimulation pathway with the analog switch, driving the ADC to output a specific command waveform to the brain-computer interface electrodes, completing the neuronal electrophysiological stimulation. Example 1

[0022] In an embodiment of the present invention patent application, Figure 1 This is a structural diagram of a distributed brain neuron electrophysiological signal recording and stimulation system. Its flow, connections, and functional descriptions of each unit are as follows: like Figure 2 As shown, the cascaded amplification unit consists of eight 4-channel LT6238 amplifiers cascaded in two stages; the analog-to-digital conversion unit consists of two 8-channel ADC chips AD7606; the digital-to-analog conversion unit consists of two 8-channel DAC chips LTC2666 and an FPGA main control board (model AX7450B); the workflow of each unit is as follows: Figure 2The left electrode acquires the raw, weak electrophysiological signal. When the recording mode is set in the computer software, an analog switch connects the electrode to the LT6238 amplifier. The raw electrophysiological signal is amplified by two stages of amplification. With a noise density of 1.1 nV / √Hz and a gain-bandwidth product of 215 MHz, the low-noise raw electrophysiological signal can be amplified up to 5000 times. The amplified signal is then sampled synchronously through 16 channels using two AD7606 amplifiers. Each channel outputs a 16-bit digital signal, which is transmitted in parallel to the AX7450B FPGA development board. The FPGA internally constructs a two-stage FIFO data buffer mechanism. The received digital signal is first written to the first-stage FIFO for clock domain synchronization and data width conversion, then transmitted to DDR3 memory for large-capacity buffering to prevent data loss. After being read out by the second-stage FIFO, it is encapsulated using the Ethernet protocol stack and finally packaged into UDP packets, which are then uploaded to the host computer in real time via a gigabit Ethernet interface. The AD7606 has a maximum sampling rate of 200 kHz and a built-in optional digital first-order sinc filter. This filter should be used in recordings with lower throughput or requiring a higher signal-to-noise ratio. The oversampling ratio of the digital filter is controlled by the oversampling pins OS[2:0]. When the computer software sends instructions to the FPGA, and the FPGA sets the oversampling pins to 000, 001, 010, 011, 100, 101, and 110 respectively, the oversampling ratios are no oversampling, 2, 4, 8, 16, 32, and 64, respectively, and the signal-to-noise ratios are 89dB, 91.2dB, 92.6dB, 94.2dB, 95.5dB, 96.4dB, and 96.9dB, respectively.

[0023] The stimulation signal output process is as follows: The host computer software sends UDP protocol command packets to the AX7450B development board via a gigabit Ethernet interface. The command packets include channel selection code, stimulation mode code, waveform parameters, and trigger timing control fields. The AX7450B development board has a command parsing module that performs CRC verification and protocol parsing on the received UDP data packets, extracts the stimulation parameters, and writes them into the stimulation configuration register. The AX7450B development board sends a configuration sequence to the LTC2666 digital-to-analog converter via the SPI bus of the FMC interface, including writing to the control register, channel enable register, and waveform data buffer register. The AX7450B development board generates a corresponding digital waveform sequence according to the stimulation mode code and synchronously loads it into the input FIFO of the LTC2666 through a parallel data interface. After receiving the LDAC trigger signal, the LTC2666 converts the digital waveform into an analog voltage output with a setup time of less than 10μs. The output voltage is applied to the target electrode after being selected by the analog switch, completing the closed-loop stimulation output. Example 2

[0024] This embodiment presents a power supply module for a PCB, such as... Figure 3As shown, the power module provides a stable and reliable multi-channel isolated power supply for the distributed brain neuron electrophysiological signal recording and stimulation system, and its circuit design is illustrated in the figure. This power module employs a multi-stage buck converter architecture, capable of converting the input 12V DC power supply into multiple different voltage levels required by the system, including 3.3V, 5V, -3.3V, and 6V. The core components of the power module include four LT3092EM5E buck converters, each responsible for generating a stable output voltage. The input power supply is first pre-filtered by a filter circuit composed of inductors and capacitors, and then fed into the four buck converters. The output of each buck converter is further smoothed by an LC filter network composed of inductors and capacitors to ensure the stability and low noise characteristics of the output voltage.

[0025] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A distributed brain neuron electrophysiological signal acquisition and stimulation system, characterized in that, This includes recording pathways and stimulation pathways; The recording pathway includes an analog switch, an amplification unit, an analog-to-digital conversion unit, and a field-programmable gate array (FPGA) main control board connected in sequence, used to acquire, process, and upload electrophysiological signals of brain neurons; The stimulation pathway includes the FPGA main control board, the digital-to-analog converter unit and the analog switch connected in sequence, for receiving and sending stimulation signals; The analog switch is shared by the recording pathway and the stimulation pathway.

2. The system according to claim 1, characterized in that, The FPGA main control board integrates an FPGA main control chip, a DDR3 memory, and an Ethernet communication interface; the DDR3 memory is used to cache the electrophysiological signal data to prevent its loss, and the Ethernet communication interface is used to communicate with the computer.

3. The system according to claim 1, characterized in that, The amplification unit, the analog-to-digital conversion unit, the digital-to-analog conversion unit, and the system power module are integrated on a single printed circuit board (PCB); the PCB is connected to the FPGA main control board via a standardized board-to-board connector.

4. The system according to claim 3, characterized in that, The standardized board-to-board connector is an FPGA mezzanine card (FMC) interface.

5. The system according to claim 1, characterized in that, The FPGA main control board is configured to adjust the oversampling rate of the analog-to-digital conversion unit according to the received instructions, thereby changing the actual sampling rate and signal-to-noise ratio of the system.

6. The system according to claim 1 or 5, characterized in that, The FPGA main control board is also configured to receive instructions from the computer and drive the digital-to-analog conversion unit to output corresponding stimulation signals.

7. The system according to claim 1, characterized in that, The amplification unit includes multiple cascaded amplifiers, and both the analog-to-digital conversion unit and the digital-to-analog conversion unit include several parallel multi-channel converter chips.

8. The system according to claim 1, characterized in that, In the recording path, the electrophysiological signal digitized by the analog-to-digital conversion unit is input into the FPGA main control board, then sequentially passes through the first-in-first-out (FIFO) queue for encapsulation and packaging, is cached in the DDR3 memory, output through the FIFO queue, and finally sent to the computer via the Ethernet.

9. The system according to claim 1, characterized in that, Under the control of the FPGA main control board, the system can time-division multiplex the shared analog switch and switch between electrophysiological signal acquisition mode and electrical stimulation signal transmission mode.

10. The system according to claim 3, characterized in that, It also includes a power management module, which is the power module integrated on the PCB, used to provide stable voltage with multiple isolation channels for the amplification unit, analog-to-digital conversion unit and digital-to-analog conversion unit.

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