Single wire transmission circuit and method

Abstract

The invention discloses a single-line transmission circuit and method, and the circuit comprises a double-edge pulse double-pulse-width monostable circuit, a level conversion circuit, and a decoding circuit, and the double-edge pulse double-pulse-width monostable circuit is connected with a first power supply voltage and a first reference voltage of a low-voltage domain. The pulse generator is used for generating a first pulse signal with wide pulse width and narrow pulse width based on an input signal; the level conversion circuit is used for converting the first pulse signal into a second pulse signal with a wide pulse width and a narrow pulse width in a high-voltage domain; and the decoding circuit is used for decoding the second pulse signal to generate an output signal of a high-voltage domain. According to the single-line transmission circuit and the single-line transmission method, the input signal is encoded into the edge pulse signal, then the edge pulse signal is subjected to level conversion and is decoded and restored into the output signal, and the level conversion circuit is only temporarily started at the edge moment of the signal, so that the consumed current is greatly reduced; the purposes of area reduction and low power consumption are achieved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a single-wire transmission circuit and method. Background Technology

[0002] Low-voltage-to-high-voltage transmission circuits typically convert digital signals generated in the low-voltage domain into digital signals that can operate effectively in the high-voltage domain (where the potential can change rapidly). These cross-voltage domain transmission circuits are usually implemented using high-voltage MOS devices to perform the conversion between the low-voltage and high-voltage domains.

[0003] In the gate drive design of high-voltage power switching devices (such as MOSFETs or IGBTs), a bootstrap scheme based on diodes and capacitors is often used to generate the high and low logic levels required for drive. In this scheme, the supply voltage (VOH) for the high-side drive is directly provided by the energy stored in the bootstrap capacitor. Therefore, any quiescent current present in the high-side drive circuit will continuously consume the energy of this capacitor, causing the supply voltage it maintains to drop. Thus, high-voltage MOSFET or IGBT drive circuits are very sensitive to the power consumption of the low-voltage-to-high-voltage transfer circuit and need to minimize their energy loss.

[0004] Figure 1 This is a schematic diagram of an existing low-voltage to high-voltage domain transmission circuit. The circuit directly controls a set of complementary pull-down NMOS transistors M1 and M2 using the input signal, which are then pulled up to the output high-level signal VOH by resistors R1 and R2. The advantages of this circuit are its simple structure and fast switching speed; the disadvantage is that regardless of whether the input signal is high-level (VIH) or low-level (GND), one MOS switch is always on, thus current always flows through the corresponding pull-up resistor, resulting in additional power consumption. Furthermore, the existing low-voltage to high-voltage domain transmission circuit requires the area of ​​two MOS transistors, leading to additional power consumption and cost issues.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a single-wire transmission circuit and method that can reduce power consumption and lower costs.

[0007] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution: a single-wire transmission circuit, comprising: a dual-edge pulse dual-pulse-width monostable circuit, a level conversion circuit, and a decoding circuit.

[0008] The dual-edge pulse dual-pulse-width monostable circuit is connected to the first power supply voltage and the first reference voltage in the low-voltage domain, and is used to generate a first pulse signal with wide pulse width and narrow pulse width based on the input signal in the low-voltage domain.

[0009] The level conversion circuit is used to convert the first pulse signal into a second pulse signal with a wide pulse width and a narrow pulse width in the high voltage domain;

[0010] The decoding circuit is used to decode the second pulse signal to generate a high-voltage output signal.

[0011] In one or more embodiments of the present invention, the level conversion circuit includes a transistor and a pull-up unit. The control terminal of the transistor is connected to the output terminal of a dual-edge pulse dual-pulse-width monostable circuit to receive a first pulse signal. The first terminal of the pull-up unit is connected to the second terminal of the transistor and the input terminal of the decoding circuit. The second terminal of the pull-up unit is connected to the second power supply voltage of the high-voltage domain. The first terminal of the transistor is connected to the second reference voltage of the high-voltage domain.

[0012] In one or more embodiments of the present invention, the level conversion circuit further includes a clamping unit, the first end of which is connected to the second end of the transistor and the input end of the decoding circuit, and the second end of which is connected to the second power supply voltage of the high voltage domain.

[0013] In one or more embodiments of the present invention, the level conversion circuit further includes a current limiting unit, wherein a first terminal of the current limiting unit is connected to a first terminal of the transistor, and a second terminal of the current limiting unit is connected to a second reference voltage of the high voltage domain.

[0014] In one or more embodiments of the present invention, the pull-up unit includes a first resistor, a first end of which is connected to a second end of a transistor and an input end of a decoding circuit, and a second end of which is connected to a second power supply voltage of a high-voltage domain.

[0015] In one or more embodiments of the present invention, the clamping unit includes a diode, the cathode of which is connected to a second power supply voltage of a high-voltage domain, and the anode of which is connected to a second terminal of a transistor.

[0016] In one or more embodiments of the present invention, the current limiting unit includes a second resistor, the first end of which is connected to the first end of the transistor, and the second end of which is connected to a second reference voltage of the high voltage domain.

[0017] In one or more embodiments of the present invention, the decoding circuit includes a monostable circuit, an inverter, and a D flip-flop. The monostable circuit is used to generate a clock signal with a fixed pulse width based on a second pulse signal. The input terminal of the inverter is used to receive the second pulse signal. The D input terminal of the D flip-flop is connected to the output terminal of the inverter. The clock input terminal of the D flip-flop is connected to the output terminal of the monostable circuit to receive the clock signal. The output terminal of the D flip-flop is used to generate an output signal.

[0018] The present invention also discloses a single-wire transmission method, which, based on the aforementioned single-wire transmission circuit, includes:

[0019] A first pulse signal with wide and narrow pulse widths is generated based on the input signal in the low voltage domain using a dual-edge pulse dual-pulse-width monostable circuit.

[0020] The first pulse signal is converted into a second pulse signal with a wide pulse width and a narrow pulse width in the high voltage domain by a level conversion circuit;

[0021] The second pulse signal is decoded by the decoding circuit to generate the high-voltage output signal.

[0022] In one or more embodiments of the present invention, the step of decoding the second pulse signal through the decoding circuit to generate a high-voltage domain output signal includes:

[0023] A clock signal with a fixed pulse width is generated based on the second pulse signal using a monostable circuit;

[0024] The second pulse signal is inverted using an inverter;

[0025] The clock signal is used as the clock signal for the D flip-flop, and the output signal is generated by the D flip-flop based on the inverted signal output by the inverter.

[0026] Compared with the prior art, the single-wire transmission circuit and method of the present invention first encodes the high / low level input signal into an edge pulse signal, and then performs level conversion on the edge pulse signal and decodes it back into a high / low level output signal. Since the level conversion circuit is only briefly turned on at the edge of the signal, the current consumption is greatly reduced, thus achieving the purpose of reducing area and power consumption. The circuit has low power consumption and simple structure, and is particularly suitable for high and low voltage transmission systems. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a circuit diagram of a transmission circuit in the prior art.

[0029] Figure 2 This is a circuit diagram of a single-wire transmission circuit according to an embodiment of the present invention.

[0030] Figure 3 This is a signal waveform diagram of a single-wire transmission circuit in one embodiment of the present invention. Detailed Implementation

[0031] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0032] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0033] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0034] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0035] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0036] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0037] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0038] like Figure 2 As shown, a single-wire transmission circuit in one embodiment of the present invention includes: a dual-edge pulse dual-pulse-width monostable circuit 10, a level conversion circuit 20, and a decoding circuit 30.

[0039] A dual-edge pulse dual-width monostable circuit 10 is connected to the first power supply voltage VIH and the first reference voltage VIL in the low-voltage domain. It is used to generate a first pulse signal Shot with wide and narrow pulse widths based on the input signal Intput (which can be a digital signal) in the low-voltage domain. A level-shifting circuit 20 converts the first pulse signal Shot into a second pulse signal Shotb in the high-voltage domain, also with wide and narrow pulse widths. A decoding circuit 30 decodes the second pulse signal Shotb to generate an output signal Output (which can be a digital signal) in the high-voltage domain. The voltage values ​​of the first power supply voltage VIH and the first reference voltage VIL can be selected as needed; the first reference voltage VIL can be the ground voltage in the low-voltage domain.

[0040] The level conversion circuit 20 includes a transistor MN, a clamping unit, a current limiting unit, and a pull-up unit. In one embodiment, the transistor MN is an N-channel MOSFET, with its first terminal being the source, its second terminal being the drain, and its control terminal being the gate.

[0041] The control terminal of transistor MN is connected to the output terminal of the dual-edge pulse dual-width monostable circuit 10 to receive the first pulse signal Shot. The first terminal of the pull-up unit is connected to the second terminal of transistor MN and the input terminal of the decoding circuit 30; the second terminal of the pull-up unit is connected to the second power supply voltage VOH of the high-voltage domain. The first terminal of the clamping unit is connected to the second terminal of transistor MN and the input terminal of the decoding circuit 30; the second terminal of the clamping unit is connected to the second power supply voltage VOH of the high-voltage domain. The first terminal of transistor MN is connected to the first terminal of the current-limiting unit, and the second terminal of the current-limiting unit is connected to the second reference voltage VOL of the high-voltage domain. In other embodiments, the current-limiting unit may be omitted. The voltage values ​​of the second power supply voltage VOH and the second reference voltage VOL can be selected as needed; the second reference voltage VOL can be the ground voltage of the high-voltage domain.

[0042] In one embodiment, the pull-up unit includes a first resistor Ra, the first end of which is connected to the second end of the transistor MN and the input terminal of the decoding circuit 30, and the second end of the first resistor Ra is connected to the second power supply voltage VOH of the high-voltage domain. In other embodiments, the pull-up unit may be other circuit structures.

[0043] In one embodiment, the clamping unit includes a diode Z, the cathode of which is connected to the second power supply voltage VOH of the high-voltage domain, and the anode of which is connected to the second terminal of the transistor MN. The clamping unit is used to clamp the voltage of the second pulse signal Shotb to VOH-Vz (Vz is the clamping voltage of diode Z) when the transistor MN is turned on. In other embodiments, the clamping unit can be other circuit structures.

[0044] In one embodiment, the current limiting unit includes a second resistor Rb, the first end of which is connected to the first end of the transistor MN, and the second end of which is connected to the second reference voltage VOL of the high-voltage domain. In other embodiments, the current limiting unit may be other circuit structures.

[0045] like Figure 2 As shown, the decoding circuit 30 includes a monostable circuit 31, an inverter 32, and a D flip-flop 33. The monostable circuit 31 generates a fixed-width clock signal CLK based on the second pulse signal Shotb (a fixed-width clock signal CLK means that the duration of each high level of the clock signal CLK is the same, while the duration of a single high level can be adjusted as needed). The input of the inverter 32 receives the second pulse signal Shotb, and the inverter 32 outputs an inverted signal D. The D input of the D flip-flop 33 is connected to the output of the inverter 32 to receive the inverted signal D. The clock input of the D flip-flop 33 is connected to the output of the monostable circuit 31 to receive the clock signal CLK. The output of the D flip-flop 33 generates the output signal Output.

[0046] This embodiment also discloses a single-wire transmission method, based on the above-described single-wire transmission circuit, including:

[0047] The dual-edge pulse dual-pulse-width monostable circuit 10 generates a first pulse signal Shot with wide and narrow pulse widths based on the input signal Intput in the low-voltage domain.

[0048] The first pulse signal Shot is converted into a second pulse signal Shotb with a wide pulse width and a narrow pulse width in the high voltage domain by the level conversion circuit 20.

[0049] The second pulse signal Shotb is decoded by the decoding circuit 30 to generate the high-voltage domain output signal Output.

[0050] Specifically, a clock signal CLK with a fixed pulse width is generated by the monostable circuit 31 based on the second pulse signal Shotb.

[0051] The second pulse signal Shotb is inverted by inverter 32.

[0052] The clock signal CLK is used as the clock signal of the D flip-flop 33, and the D flip-flop 33 generates the output signal Output based on the inverted signal D output by the inverter 32.

[0053] Figure 3 for Figure 2 The waveform diagrams of each node in the single-wire transmission circuit are shown in the figure. Figure 3 and Figure 2 As shown, the input signal Input is input to the dual-edge pulse dual-width monostable circuit 21. The dual-edge pulse dual-width monostable circuit 21 outputs a first pulse signal Shot in the low-voltage domain. The wide pulse width Tw1 of the first pulse signal Shot in the low-voltage domain is generated at the rising and falling edges of the input signal Input, and the narrow pulse width Tw2 of the first pulse signal Shot in the low-voltage domain is generated at the falling edge of the input signal Input. The high-level voltage of the first pulse signal Shot is the same as the high-level voltage of the input signal Input, and the low-level voltage of the first pulse signal Shot is the same as the low-level voltage of the input signal Input. The high-level voltage of the input signal Input is VIH, and the low-level voltage is VIL.

[0054] The first pulse signal Shot in the low-voltage domain is input to the gate of the high-voltage transistor MN. When the high-level voltage VIH of the first pulse signal Shot in the low-voltage domain is greater than the conduction threshold voltage of the high-voltage transistor MN, the transistor MN is turned on. When the first pulse signal Shot in the low-voltage domain is low, the transistor MN is turned off. At this time, due to the pull-up of the first resistor Ra, the second terminal (drain) of the transistor MN outputs a second pulse signal Shotb at a high level (VOH) in the high-voltage domain. When the high level of the first pulse signal Shot in the low-voltage domain arrives, the transistor MN is turned on. Due to the clamping of the diode Z, the second terminal (drain) of the transistor MN outputs a second pulse signal Shotb at a low level (VOH-Vz) in the high-voltage domain. Generally, VOH-Vz is higher than the second reference voltage VOL to ensure the withstand voltage of the subsequent circuit.

[0055] The second pulse signal Shotb is input to the inverter 32. The inverter 32 inverts the second pulse signal Shotb and converts it into an inverted signal D that can be recognized by the D flip-flop 33. The high-level voltage of the inverted signal D is VOH and the low-level voltage is VOL.

[0056] The second pulse signal Shotb is input to the monostable circuit 31. When the falling edge of the wide pulse width TW1 and the narrow pulse width TW2 of the second pulse signal Shotb arrives, the monostable circuit 31 outputs a clock signal CLK with a fixed pulse width Tw3. The clock signal CLK is a clock signal that can be recognized by the D flip-flop 33. The high-level voltage of the clock signal CLK is VOH and the low-level voltage is VOL.

[0057] The inverting signal D and the clock signal CLK are input to the D input and clock input terminals of the D flip-flop 233, respectively. According to the characteristics of the D flip-flop 233, when the inverting signal D is a wide-pulse pulse, a high-level output signal Output with a voltage of VOH is generated when the high-level edge of the clock signal CLK arrives; when the inverting signal D is a narrow-pulse pulse, a low-level output signal Output with a voltage of VOL is generated when the high-level edge of the clock signal CLK arrives. This finally realizes the conversion from the low-voltage domain input signal Intput to the high-voltage domain output signal Output.

[0058] The single-wire transmission circuit for switching between low-voltage and high-voltage domains provided by this invention is also applicable to floating high-voltage digital level conversion. The single-wire transmission circuit first encodes the input high / low-level voltage signal into an edge pulse signal, then performs level conversion on the edge pulse signal and decodes it back to a high / low-level voltage signal for output. Since the single-wire transmission circuit has only one high-voltage transistor MN, and the high-voltage transistor MN is only briefly turned on at the signal edge, and the presence of a current-limiting resistor further reduces current consumption, the current consumption is greatly reduced, achieving the goals of reducing area and power consumption. This circuit has low power consumption and a simple structure, making it particularly suitable for high- and low-voltage transmission systems.

[0059] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0060] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A single-wire transmission circuit, characterized in that, include: A dual-edge pulse dual-pulse-width monostable circuit is connected to a first power supply voltage and a first reference voltage in the low-voltage domain, and is used to generate a first pulse signal with wide pulse width and narrow pulse width based on the input signal in the low-voltage domain. A level conversion circuit is used to convert a first pulse signal into a second pulse signal with a wide pulse width and a narrow pulse width in the high voltage domain; The decoding circuit is used to decode the second pulse signal to generate a high-voltage output signal.

2. The single-wire transmission circuit according to claim 1, characterized in that, The level conversion circuit includes a transistor and a pull-up unit. The control terminal of the transistor is connected to the output terminal of the dual-edge pulse dual-pulse width monostable circuit to receive a first pulse signal. The first terminal of the pull-up unit is connected to the second terminal of the transistor and the input terminal of the decoding circuit. The second terminal of the pull-up unit is connected to the second power supply voltage of the high-voltage domain. The first terminal of the transistor is connected to the second reference voltage of the high-voltage domain.

3. The single-wire transmission circuit according to claim 2, characterized in that, The level conversion circuit also includes a clamping unit. The first end of the clamping unit is connected to the second end of the transistor and the input end of the decoding circuit, and the second end of the clamping unit is connected to the second power supply voltage of the high voltage domain.

4. The single-wire transmission circuit according to claim 2, characterized in that, The level conversion circuit also includes a current limiting unit, the first end of which is connected to the first end of the transistor, and the second end of which is connected to the second reference voltage of the high voltage domain.

5. The single-wire transmission circuit according to claim 2, characterized in that, The pull-up unit includes a first resistor, the first end of which is connected to the second end of the transistor and the input end of the decoding circuit, and the second end of which is connected to the second power supply voltage of the high voltage domain.

6. The single-wire transmission circuit according to claim 3, characterized in that, The clamping unit includes a diode, the cathode of which is connected to a second power supply voltage of the high-voltage domain, and the anode of which is connected to a second terminal of a transistor.

7. The single-wire transmission circuit according to claim 4, characterized in that, The current limiting unit includes a second resistor, the first end of which is connected to the first end of the transistor, and the second end of which is connected to the second reference voltage of the high voltage domain.

8. The single-wire transmission circuit according to claim 1, characterized in that, The decoding circuit includes a monostable circuit, an inverter, and a D flip-flop. The monostable circuit is used to generate a clock signal with a fixed pulse width based on a second pulse signal. The input terminal of the inverter is used to receive the second pulse signal. The D input terminal of the D flip-flop is connected to the output terminal of the inverter. The clock input terminal of the D flip-flop is connected to the output terminal of the monostable circuit to receive the clock signal. The output terminal of the D flip-flop is used to generate an output signal.

9. A single-wire transmission method, characterized in that, Based on the single-wire transmission circuit as described in any one of claims 1 to 7, the single-wire transmission method includes: A first pulse signal with wide and narrow pulse widths is generated based on the input signal in the low voltage domain using a dual-edge pulse dual-pulse-width monostable circuit. The first pulse signal is converted into a second pulse signal with a wide pulse width and a narrow pulse width in the high voltage domain by a level conversion circuit; The second pulse signal is decoded by the decoding circuit to generate the high-voltage output signal.

10. The single-wire transmission method according to claim 9, characterized in that, The step of decoding the second pulse signal through the decoding circuit to generate a high-voltage domain output signal includes: A clock signal with a fixed pulse width is generated based on the second pulse signal using a monostable circuit; The second pulse signal is inverted using an inverter; The clock signal is used as the clock signal for the D flip-flop, and the output signal is generated by the D flip-flop based on the inverted signal output by the inverter.

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