An automatic repairable frequency source and its implementation method

Abstract

The application discloses an automatic repair type frequency source and an implementation method thereof, and belongs to the technical field of radar communication and frequency synthesis. In view of the problem that the maintenance efficiency is low after the traditional frequency source fails, and the system is stopped and a large loss is caused, the application adopts a double-backup hardware architecture of two groups of phase-locked loops and two groups of radio frequency signal conditioning circuits, intelligently manages power supply and signal paths through a radio frequency switch network, and collects the working states of components in real time by using a monitoring module; an FPGA control unit executes automatic repair actions based on the locking detection signals and level signals fed back by the monitoring module, and realizes instant diagnosis and seamless switching of faults. The application shortens the fault repair time from the days level of the traditional technology to the millisecond level, realizes zero downtime operation of the system, effectively avoids the economic loss of hundreds of thousands of yuan with the increase of the hardware cost of several thousand yuan, and significantly improves the availability and maintainability of the high-reliability electronic system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radar communication and frequency synthesis, in particular to an automatic repair type frequency source and an implementation method thereof. BACKGROUND

[0002] As the "heart" of modern electronic systems, frequency sources provide stable and accurate reference clock or carrier signals for the entire system, and their performance directly determines key indicators such as communication quality, radar ranging accuracy, and instrument measurement accuracy. In aerospace, national defense and military industry, industrial control, and high-end communication applications, extreme requirements are placed on the reliability and stability of frequency sources. Once a frequency source fails, it will cause the entire complex electronic system to malfunction or degrade in performance, resulting in significant economic losses or even safety accidents.

[0003] Currently, widely used traditional frequency sources are mostly designed with a single modular structure, i.e., a phase-locked loop (PLL) circuit paired with a radio frequency signal conditioning circuit (usually including amplification, filtering, etc.). Although this architecture is simple in structure and low in cost, its inherent reliability bottleneck lies in the lack of effective redundancy backup and fault response mechanisms. When the phase-locked loop inside the frequency source fails due to loss of lock, device aging, etc., or the radio frequency conditioning circuit fails due to faults in power amplifiers, filters, etc., the entire frequency source fails.

[0004] The main difficulty faced by existing technologies lies in the handling process after a fault occurs. First, the discovery of the fault relies on system-level functional abnormalities or regular maintenance checks, and cannot be realized in real time. Second, fault localization is difficult. When a complex system exhibits functional abnormalities, maintenance personnel need to use special instruments (such as spectrum analyzers, frequency meters, etc.) to perform step-by-step troubleshooting to ultimately determine whether the frequency source module itself is faulty. This process is tedious and highly dependent on personnel's experience, and takes a long time, usually several hours or even several days. Third, the fault repair efficiency is low. After confirming the frequency source failure, the entire module often needs to be removed from the system for repair or replacement. The series of processes of disassembly, repair, reinstallation, and debugging will further cause the system to be down for a long time.

[0005] For large industrial production lines, uninterrupted communication networks, or critical facilities, every second of system downtime means significant economic losses or strategic risks. According to statistics, a single unplanned downtime can result in direct and indirect economic losses of hundreds of thousands or even millions of yuan for large enterprises. Therefore, there has been a long-standing technical contradiction in the industry that needs to be addressed: how to significantly improve the availability of frequency sources without significantly increasing costs and system complexity, and to achieve rapid or even instantaneous repair of faults, thereby ensuring the continuous and stable operation of critical systems.

[0006] The existing high reliability design usually focuses on passive protection measures such as derating use of components, redundant power supply, environmental reinforcement, or adopts the whole machine cold backup scheme at the system level. The former cannot fundamentally avoid random failure, and the latter is high in cost, large in size, and complex in switching logic. At present, there is a lack of an active repair solution for the frequency source module itself, which can be integrated in the module, realize automatic perception, intelligent decision and seamless switching. This is the core technical problem that the present application aims to solve. SUMMARY

[0007] In view of the technical problems of poor reliability of traditional frequency sources, long time-consuming for fault repair and serious loss of system downtime in the prior art, the present application provides an automatic repair type frequency source and an implementation method thereof. Through the built-in double backup hardware architecture and the intelligent control logic based on FPGA, real-time monitoring of the working state of the frequency source is realized. When a fault is detected, the signal path can be automatically, quickly and accurately switched from the faulty component to the standby component, so that the fault repair is completed without user awareness, the system availability and reliability are significantly improved, and the huge economic loss caused by frequency source failure is effectively avoided.

[0008] To achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0009] An automatic repair type frequency source comprises a reference clock source, a one-to-two power divider, a first phase-locked loop, a second phase-locked loop, a first radio frequency signal conditioning circuit, a second radio frequency signal conditioning circuit, a radio frequency switch network, a monitoring module and an FPGA control unit.

[0010] The output end of the reference clock source is connected to the input end of the one-to-two power divider, and the two output ends of the one-to-two power divider are respectively connected to the reference input ends of the first phase-locked loop and the second phase-locked loop.

[0011] The radio frequency switch network is controlled by the FPGA control unit, and is used for selectively conducting the power supply and output signal path of the first phase-locked loop or the second phase-locked loop, and selectively conducting the power supply and output signal path of the first radio frequency signal conditioning circuit or the second radio frequency signal conditioning circuit.

[0012] The monitoring module is used for monitoring the working locked state of the first phase-locked loop and the second phase-locked loop in real time, and monitoring the output signal state of the first radio frequency signal conditioning circuit and the second radio frequency signal conditioning circuit, and feeding back the monitoring signal to the FPGA control unit.

[0013] The FPGA control unit is configured to receive the monitoring signal fed back by the monitoring module, and output a control signal to the radio frequency switch network according to the monitoring signal, so as to automatically switch to the standby phase-locked loop or radio frequency signal conditioning circuit when the current working phase-locked loop or radio frequency signal conditioning circuit is monitored to be faulty.

[0014] Specifically, the radio frequency switch network comprises:

[0015] a first analog switch connected in series in a power supply loop of the first phase-locked loop;

[0016] a second analog switch connected in series in a power supply loop of the second phase-locked loop;

[0017] a third analog switch connected in series in a power supply loop of the first radio frequency signal conditioning circuit;

[0018] a fourth analog switch connected in series in a power supply loop of the second radio frequency signal conditioning circuit;

[0019] a first single-pole double-throw switch, a first input end of which is connected to an output end of the first phase-locked loop, a second input end of which is connected to an output end of the second phase-locked loop, and an output common end of which is connected to a signal node;

[0020] a second single-pole double-throw switch, an input common end of which is connected to the signal node, a first output end of which is connected to an input end of the first radio frequency signal conditioning circuit, and a second output end of which is connected to an input end of the second radio frequency signal conditioning circuit;

[0021] a third single-pole double-throw switch, a first input end of which is connected to an output end of the first radio frequency signal conditioning circuit, a second input end of which is connected to an output end of the second radio frequency signal conditioning circuit, and an output common end of which is used as a radio frequency signal output end of a frequency source.

[0022] Specifically, the monitoring module comprises:

[0023] a first monitoring branch configured to acquire a first lock detection signal LD1 of the first phase-locked loop;

[0024] a second monitoring branch configured to acquire a second lock detection signal LD2 of the second phase-locked loop;

[0025] a third monitoring branch configured to monitor an output signal power of the first radio frequency signal conditioning circuit and output a first level signal LVTTL1;

[0026] a fourth monitoring branch configured to monitor an output signal power of the second radio frequency signal conditioning circuit and output a second level signal LVTTL2.

[0027] Specifically, the third monitoring branch comprises a first coupler, a first detector and a first comparator connected in sequence, the input end of the first coupler is coupled to the output end of the first radio frequency signal conditioning circuit, and the first comparator outputs the first level signal LVTTL1 to the FPGA control unit.

[0028] The fourth monitoring branch comprises a second coupler, a second detector and a second comparator connected in sequence, the input end of the second coupler is coupled to the output end of the second radio frequency signal conditioning circuit, and the second comparator outputs the second level signal LVTTL2 to the FPGA control unit.

[0029] Specifically, the reference voltage threshold of the first comparator and the second comparator is set to be 1dB to 3dB lower than the normal output power of the corresponding radio frequency signal.

[0030] Specifically, the first phase-locked loop and the second phase-locked loop are completely identical in model and configuration parameters; and the first radio frequency signal conditioning circuit and the second radio frequency signal conditioning circuit are completely identical in circuit topology and component parameters.

[0031] Specifically, the response time of the FPGA control unit from fault judgment to completion of path switching is less than 200 milliseconds.

[0032] Based on the above structure, the application further provides an implementation method of the automatic repair type frequency source, which is executed by the FPGA control unit and comprises the following steps:

[0033] S1, system power-on initialization, controlling the radio frequency switch network to select the main path composed of the first phase-locked loop and the first radio frequency signal conditioning circuit;

[0034] S2, real-time monitoring of the state monitoring signal of the main path;

[0035] S3, if the state monitoring signal indicates normal, maintaining the current state and returning to S2;

[0036] S4, if the state monitoring signal indicates fault, judging the fault type;

[0037] S5, according to the fault type, controlling the radio frequency switch network to start and switch to the corresponding standby circuit;

[0038] S6, after confirming that the standby circuit works normally, controlling the radio frequency switch network to isolate the fault circuit.

[0039] Specifically, in the S4, the fault type includes phase-locked loop fault and radio frequency signal conditioning circuit fault.

[0040] In the S5, if it is determined that the phase-locked loop is faulty, the radio frequency switch network is controlled to power on the second phase-locked loop and switch the output signal path thereof to the first radio frequency signal conditioning circuit; if it is determined that the radio frequency signal conditioning circuit is faulty, the radio frequency switch network is controlled to power on the second radio frequency signal conditioning circuit and switch the input and output signal paths to the second radio frequency signal conditioning circuit.

[0041] Specifically, the state monitoring signal includes a first lock detection signal LD1 of the first phase-locked loop and a first level signal LVTTL1 representing the output power of the first radio frequency signal conditioning circuit, and the FPGA control unit determines the fault type by judging the level combination of the first lock detection signal LD1 and the first level signal LVTTL1.

[0042] Compared with the prior art, the present application has the following beneficial effects:

[0043] (1) The present application adopts a dual-backup hardware architecture composed of a first phase-locked loop, a second phase-locked loop, a first radio frequency signal conditioning circuit and a second radio frequency signal conditioning circuit, and uses a radio frequency switch network to realize rapid switching of power supply and signal path, thereby shortening the repair time after frequency source failure from several days (≥2 days) required by the traditional technology to milliseconds (<200 ms), realizing zero downtime operation of the system and completely avoiding significant economic losses caused by interruption of key signals.

[0044] (2) The present application sets a monitoring module containing four independent monitoring branches, real-time collects phase-locked loop lock state signals (LD1, LD2) and radio frequency output power level signals (LVTTL1, LVTTL2), and comprehensively judges the multiple signals by the FPGA control unit, thereby realizing instant and accurate positioning and classification of faults, overcoming the drawbacks of low efficiency and dependence on manual fault troubleshooting in the traditional technology, and significantly improving the maintenance efficiency and automation level.

[0045] (3) The present application uses the FPGA control unit to execute an optimized control algorithm to manage the radio frequency switch network and the monitoring module, and builds a full-automatic closed-loop control link of "monitoring-judgment-execution", so that the entire fault repair process does not require any manual intervention, not only reduces the dependence on professional maintenance personnel, but also fundamentally eliminates the secondary risks caused by subjective misjudgment or operation delay, and ensures the high reliability of the system.

[0046] (4) Although the present application introduces dual-backup components, the additional hardware cost is accurately controlled to the level of several thousand yuan through optimized system design and device selection. Compared with the system downtime loss of tens of thousands of yuan that may be avoided by a single fault, the input-output ratio is extremely high, which provides an excellent solution to the traditional contradiction between high reliability and economy. BRIEF DESCRIPTION OF DRAWINGS

[0047] Fig. 1 This is a schematic diagram of the circuit structure of an embodiment of the present invention.

[0048] Fig. 2 This is a schematic diagram of the control flow of an embodiment of the present invention.

[0049] In the above figures, the component names corresponding to the reference numerals are as follows:

[0050] 1-Reference clock source; 2-1-to-2 power divider; 3-First phase-locked loop; 4-Second phase-locked loop; 5-First analog switch; 6-Second analog switch; 7-First single-pole double-throw switch; 8-First RF signal conditioning circuit; 9-Second RF signal conditioning circuit; 10-Third analog switch; 11-Fourth analog switch; 12-First coupler; 13-First detector; 14-First comparator; 15-Second single-pole double-throw switch; 16-Third single-pole double-throw switch; 17-FPGA control unit; 18-Second coupler; 19-Second detector; 20-Second comparator. Detailed Implementation

[0051] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0052] like Figs. 1-2 As shown, the automatic repair frequency source includes a reference clock source 1, a 1-to-2 power divider 2, a first phase-locked loop (PLL) 3, a second PLL 4, a first radio frequency (RF) signal conditioning circuit 8, a second RF signal conditioning circuit 9, an RF switch network, a monitoring module, and an FPGA control unit 17 as the system control core. The first PLL 3, second PLL 4, first RF signal conditioning circuit 8, and second RF signal conditioning circuit 9 form a dual-backup architecture. The first PLL 3 and second PLL 4 have identical models and configuration parameters, used to generate RF signals with the same frequency and phase. The first RF signal conditioning circuit 8 and second RF signal conditioning circuit 9 have identical circuit topologies and component parameters, used to amplify, filter, and condition the signals output by the PLLs. The RF switch network includes a first analog switch 5, a second analog switch 6, a third analog switch 10, a fourth analog switch 11, a first single-pole double-throw (SPD) switch 7, a second SPD switch 15, and a third SPD switch 16.

[0053] The output end of the reference clock source 1 is connected to the input end of a 1:2 power divider 2, and the two output ends of the 1:2 power divider 2 are respectively connected to the reference input ends of a first phase-locked loop 3 and a second phase-locked loop 4. A first analog switch 5 is connected in series in the power supply circuit of the first phase-locked loop 3, for controlling the on-off of the power supply thereof; a second analog switch 6 is connected in series in the power supply circuit of the second phase-locked loop 4, for controlling the on-off of the power supply thereof. The output end of the first phase-locked loop 3 is connected to the first input end of a first single-pole double-throw switch 7, and the output end of the second phase-locked loop 4 is connected to the second input end of the first single-pole double-throw switch 7. The output common end of the first single-pole double-throw switch 7 is connected to a signal node, and the input common end of a second single-pole double-throw switch 15 is connected through the signal node, the first output end of the second single-pole double-throw switch 15 is connected to the input end of a first radio frequency signal conditioning circuit 8, and the second output end is connected to the input end of a second radio frequency signal conditioning circuit 9. A third analog switch 10 is connected in series in the power supply circuit of the first radio frequency signal conditioning circuit 8, for controlling the on-off of the power supply thereof; a fourth analog switch 11 is connected in series in the power supply circuit of the second radio frequency signal conditioning circuit 9, for controlling the on-off of the power supply thereof. The output end of the first radio frequency signal conditioning circuit 8 is connected to the first input end of a third single-pole double-throw switch 16, and the output end of the second radio frequency signal conditioning circuit 9 is connected to the second input end of the third single-pole double-throw switch 16. The output common end of the third single-pole double-throw switch 16 serves as the radio frequency signal output end of the entire frequency source. The radio frequency switch network is controlled by the FPGA control unit 17, for selectively conducting the power supply and output signal path of the first phase-locked loop 3 or the second phase-locked loop 4, and selectively conducting the power supply and output signal path of the first radio frequency signal conditioning circuit 8 or the second radio frequency signal conditioning circuit 9. Generally, the first phase-locked loop and the first radio frequency signal conditioning circuit are selected to be conducted as the main path by default, for normally outputting the radio frequency signal, and the second phase-locked loop and the second radio frequency signal conditioning circuit are the corresponding standby circuits at this time; when the first phase-locked loop is monitored to have a fault, the second phase-locked loop is selected to be conducted and the first phase-locked loop is closed for switching, so as to ensure the normal output of the radio frequency signal; when the first radio frequency signal conditioning circuit is monitored to have a fault, the second radio frequency signal conditioning circuit is selected to be conducted and the first radio frequency signal conditioning circuit is closed for switching, so as to ensure the normal output of the radio frequency signal.

[0054] The monitoring module is used for monitoring the working locking state of the first and second phase-locked loops and the output signal state of the first and second radio frequency signal conditioning circuits in real time. The monitoring module specifically comprises four monitoring branches. The first monitoring branch is used for directly obtaining the first locking detection signal LD1 of the first phase-locked loop 3 and outputting to the FPGA control unit. The second monitoring branch is used for directly obtaining the second locking detection signal LD2 of the second phase-locked loop 4 and outputting to the FPGA control unit. The third monitoring branch is used for monitoring the output signal power of the first radio frequency signal conditioning circuit 8 and outputting the first level signal LVTTL1 to the FPGA control unit. The fourth monitoring branch is used for monitoring the output signal power of the second radio frequency signal conditioning circuit 9 and outputting the second level signal LVTTL2 to the FPGA control unit. The third monitoring branch is composed of a first coupler 12, a first detector 13 and a first comparator 14 connected in sequence. The input end of the first coupler 12 is coupled to the output end of the first radio frequency signal conditioning circuit 8, used for sampling the output signal thereof, and the first level signal LVTTL1 is generated to the FPGA control unit through the first detector 13 and the first comparator 14. The fourth monitoring branch is composed of a second coupler 18, a second detector 19 and a second comparator 20 connected in sequence. The input end of the second coupler 18 is coupled to the output end of the second radio frequency signal conditioning circuit 9, used for sampling the output signal thereof, and the second level signal LVTTL2 is generated to the FPGA control unit through the second detector 19 and the second comparator 20. The reference voltage threshold of the first comparator 14 and the second comparator 20 is set to be 1 dB to 3 dB lower than the corresponding radio frequency signal normal output power.

[0055] The FPGA control unit 17 receives the monitoring signals fed back by the aforementioned monitoring module, and outputs control signals to the control ends of all analog switches and single-pole double-throw switches of the radio frequency switch network, so as to form a complete "monitoring-judgment-execution" closed loop control system. Specifically, after the FPGA control unit receives the first locking detection signal LD1, the second locking detection signal LD2, the first level signal LVTTL1 and the second level signal LVTTL2, it judges whether a fault occurs and the fault type when a fault occurs according to the built-in intelligent algorithm, and then outputs control signals to the control ends of the corresponding analog switches and single-pole double-throw switches in the radio frequency switch network, so as to realize automatic switching to the corresponding backup circuit to ensure the normal output of the radio frequency signal. The response time of the FPGA control unit 17 from fault judgment to complete path switching is less than 200 milliseconds.

[0056] Based on the structure of the automatic repair type frequency source, the implementation method is executed by the FPGA control unit. The state machine can be written in Verilog HDL language inside the FPGA control unit, and the control flow shown in the figure is realized. Fig. 2 The specific steps include the following steps:

[0057] S1, system power initialization, after the system is powered on, the FPGA control unit first initializes itself. Subsequently, the FPGA control unit controls the first analog switch 5 and the third analog switch 10 to be on, and supplies power to the first phase-locked loop 3 and the first radio frequency signal conditioning circuit 8; At the same time, keep the second analog switch 6 and the fourth analog switch 11 in the off state. The FPGA control unit controls the first single-pole double-throw switch 7, the second single-pole double-throw switch 15 and the third single-pole double-throw switch 16 to select the main path formed by the first phase-locked loop and the first radio frequency signal conditioning circuit. The internal counter of the FPGA control unit starts timing and delays for a set time, such as 500ms, to ensure that the main path is stable.

[0058] S2, real-time monitoring of the state monitoring signal of the main path, the FPGA control unit continuously monitors the first lock detection signal LD1 of the first phase-locked loop and the first level signal LVTTL1 representing the output power of the first radio frequency signal conditioning circuit.

[0059] Judgment condition: IF (LD1 == 1’b1) AND (LVTTL1 == 1’b1) / / That is, both are high level. If the condition is true, it means that the main path is working normally, and jump to S3; If the condition is false, that is, any signal is low, it means that the main path is faulty, then immediately jump to S4.

[0060] S3, when the state monitoring signal indicates normal, it is a normal working state, in which the FPGA control unit maintains all current switch states and control signals unchanged. At the same time, S2 is executed in a loop to continuously monitor the state of the main path, realizing real-time monitoring.

[0061] S4, when the state monitoring signal indicates a fault, the FPGA control unit first judges the fault type, which includes phase-locked loop fault and radio frequency signal conditioning circuit fault. The fault type is determined by judging the level combination of the first lock detection signal LD1 and the first level signal LVTTL1, and the judgment process is:

[0062] IF (LD1 == 1’b0) AND (LVTTL1 == 1’b1), determine as phase-locked loop fault (PLL lock loss);

[0063] IF (LD1 == 1’b1) AND (LVTTL1 == 1’b0), determine as radio frequency signal conditioning circuit fault (power insufficient);

[0064] IF (LD1 == 1’b0) AND (LVTTL1 == 1’b0), it is determined as a serious fault (both may have faults or serious problems in the front end), the processing logic can be equivalent to a phase-locked loop fault or triggering the highest level of alarm.

[0065] S5, according to the fault type, the radio frequency switch network is started and switched to the corresponding backup circuit. Specifically, if it is determined in S4 that the phase-locked loop is faulty, the FPGA control unit controls the second analog switch 6 to be conductive, powers on the second phase-locked loop 4, and at the same time controls the first single-pole double-throw switch 7 to be switched to the second input end, connects the second phase-locked loop, and makes the second phase-locked loop output signal path to the first radio frequency signal conditioning circuit; if it is determined in S4 that the radio frequency signal conditioning circuit is faulty: the FPGA control unit controls the fourth analog switch 11 to be conductive, powers on the second radio frequency signal conditioning circuit 9, and at the same time controls the second single-pole double-throw switch 15 to be switched to the second output end and controls the third single-pole double-throw switch 16 to be switched to the second input end, connects the second radio frequency signal conditioning circuit, and makes the input and output signal path to the second radio frequency signal conditioning circuit.

[0066] S6, confirmation and isolation: the FPGA control unit monitors the backup circuit state signal (LD2 or LVTTL2), confirms normal, and disconnects the power supply of the fault main component (disables the first analog switch 5 or the third analog switch 10), and completes the isolation.

[0067] The output frequency of the frequency source is 2.2GHz, for example, to illustrate the configuration of each component, but the technical solutions described in the present application are not limited to this specific frequency. By selecting corresponding frequency band components, the present application can also be applied to other frequency points, such as 100MHz (as a high-precision clock reference), 1.5GHz (GPS L1), 2.4GHz (ISM), 3.5GHz (5G) or higher frequency bands.

[0068] The FPGA control unit 17 adopts the XC6SLX9 chip of the Xilinx Spartan-6 series, responsible for executing the control algorithm. The reference clock source 1 adopts a 100MHz oven controlled crystal oscillator (OCXO), with a phase noise of -160dBc / Hz@1kHz. The 1:2 power divider 2 adopts the Mini-Circuits SBTC-2-10L+ chip. The first phase-locked loop 3 and the second phase-locked loop 4 both adopt the LMX2594RHAT chip, with the same register value configuration, and output a frequency of 2.2GHz. The first analog switch 5, the second analog switch 6, the third analog switch 10 and the fourth analog switch 11 all adopt the ADG849YKSZ-REEL7 chip, used to control the on-off of the +5V power supply circuit. The first single-pole double-throw switch 7, the second single-pole double-throw switch 15 and the third single-pole double-throw switch 16 all adopt the HMC536MS8GE chip, used for high-frequency signal path switching, with a switching time less than 30ns. The first radio frequency signal conditioning circuit 8 and the second radio frequency signal conditioning circuit 9 both contain a PHA-1+ driver amplifier (Output Power @1dB compression 22dBm) and a LFCN-2500 low-pass filter (cutoff frequency 2.5GHz). The first coupler 12 and the second coupler 18 both adopt the BDCA-10-25+ chip, with a coupling degree of 10dB. The first detector 13 and the second detector 19 both adopt the AD8318ACPZ-REEL7 logarithmic detector. The first comparator 14 and the second comparator 20 both adopt the MAX9010EXT high-speed comparator, with the reference voltage threshold set to be 2dB lower than the normal value (+17dBm) (i.e. +15dBm), and the detection voltage is lower than the reference voltage, then the comparator output is low.

[0069] After testing, the above configuration fully achieves the expected effect of the present application. The test results are as follows:

[0070] 1. Performance index: output frequency 2.2GHz, phase noise -110dBc / Hz@1kHz, output power 17dBm±0.5dB, frequency stability ≤±0.5ppm.

[0071] 2、Fault response performance: simulate the fault of phase-locked loop, manually cut off the power supply of the first phase-locked loop, make the LD1 signal immediately become low, the FPGA detects that the LD1 is low in the next monitoring period (microsecond level), and then triggers the fault processing flow, the system completes switching (including PLL locking time) in 50ms, recovers the output, and the output interruption time is less than 1us. It should be noted that the response time of the FPGA from fault judgment to complete the switching of the path refers to the electrical response time experienced from the start of monitoring the fault signal jump in the FPGA, through logical judgment, to finally issuing all switching instructions to the radio frequency switch network. This time does not include the inherent locking time, preheating and stabilizing time and other physical delays after the standby component is powered on. Using a spectrum analyzer for observation, the output signal only has a short glitch at the switching moment, and the frequency stability and power (≤±0.5ppm, ≤±0.5dB) are the same as before switching. Simulate the fault of the regulating circuit, inject a strong interference signal at the input end of the amplifier of the first radio frequency signal regulating circuit, so that the output power decreases to 14dBm, the LVTTL1 signal immediately becomes low, the FPGA detects that the LVTTL1 is low, triggers the switching flow, and the system completes switching (including power-on stabilizing time) in 50ms, recovers the output, and the output interruption time is less than 100ns.

[0072] 3、Reliability verification: no fault for 96 hours of continuous operation, and the switching success rate is 100%.

[0073] 4、Economic benefits: the hardware cost (second PLL, regulating circuit, switch, etc.) increases less than 2000 yuan, and for a large production line that relies on this frequency source, avoiding a two-day shutdown can prevent about 400,000 yuan of economic losses, and the input-output ratio is very high.

[0074] As can be seen, the present application successfully realizes the automatic and rapid repair of the frequency source fault through the hardware architecture and control method, and significantly improves the reliability and usability of the system.

[0075] The above embodiments are only preferred embodiments of the present application, and are not a limitation on the protection scope of the present application. Any change made on the basis of the design principles of the present application and non-creative labor shall be within the protection scope of the present application.

Claims

1. An auto-healing frequency source, characterized by, The application relates to a frequency synthesizer, which comprises a reference clock source (1), a one-to-two power divider (2), a first phase-locked loop (3), a second phase-locked loop (4), a first radio frequency signal conditioning circuit (8), a second radio frequency signal conditioning circuit (9), a radio frequency switch network, a monitoring module and an FPGA control unit (17). An output end of the reference clock source (1) is connected to an input end of the one-to-two power divider (2), and two output ends of the one-to-two power divider (2) are respectively connected to reference input ends of the first phase-locked loop (3) and the second phase-locked loop (4). The radio frequency switch network is controlled by the FPGA control unit (17) and is used for selectively conducting power supply and output signal paths of the first phase-locked loop (3) or the second phase-locked loop (4) and selectively conducting power supply and output signal paths of the first radio frequency signal conditioning circuit (8) or the second radio frequency signal conditioning circuit (9). The monitoring module is used for monitoring working locking states of the first phase-locked loop (3) and the second phase-locked loop (4) and monitoring output signal states of the first radio frequency signal conditioning circuit (8) and the second radio frequency signal conditioning circuit (9) in real time and feeding back monitoring signals to the FPGA control unit (17). The FPGA control unit (17) is used for receiving the monitoring signals fed back by the monitoring module and outputting control signals to the radio frequency switch network according to the monitoring signals so as to automatically switch to a standby phase-locked loop or radio frequency signal conditioning circuit when a currently working phase-locked loop or radio frequency signal conditioning circuit is monitored to be faulty. The radio frequency switch network comprises:

2. The self-healing frequency source of claim 1, wherein, A first analog switch (5) is connected in series in a power supply loop of the first phase-locked loop (3); A second analog switch (6) is connected in series in a power supply loop of the second phase-locked loop (4); A third analog switch (10) is connected in series in a power supply loop of the first radio frequency signal conditioning circuit (8); A fourth analog switch (11) is connected in series in a power supply loop of the second radio frequency signal conditioning circuit (9); A first single-pole double-throw switch (7) has a first input end connected to an output end of the first phase-locked loop (3), a second input end connected to an output end of the second phase-locked loop (4) and an output common end connected to a signal node; A second single-pole double-throw switch (15) has an input common end connected to the signal node, a first output end connected to an input end of the first radio frequency signal conditioning circuit (8) and a second output end connected to an input end of the second radio frequency signal conditioning circuit (9); A third single-pole double-throw switch (16) has a first input end connected to an output end of the first radio frequency signal conditioning circuit (8), a second input end connected to an output end of the second radio frequency signal conditioning circuit (9) and an output common end as a radio frequency signal output end of a frequency source. The monitoring module comprises:

3. The self-healing frequency source of claim 1, wherein, A first monitoring branch is used for acquiring a first locking detection signal LD1 of the first phase-locked loop (3); A second monitoring branch is used for acquiring a second locking detection signal LD2 of the second phase-locked loop (4); ​ A third monitoring branch is configured to monitor the output signal power of the first RF signal conditioning circuit (8) and output a first level signal LVTTL1. A fourth monitoring branch is configured to monitor the output signal power of the second RF signal conditioning circuit (9) and output a second level signal LVTTL2.

4. The self-healing frequency source of claim 3, wherein, The third monitoring branch comprises a first coupler (12), a first detector (13) and a first comparator (14) connected in sequence, the input end of the first coupler (12) is coupled to the output end of the first RF signal conditioning circuit (8), and the first comparator (14) outputs the first level signal LVTTL1 to the FPGA control unit (17). The fourth monitoring branch comprises a second coupler (18), a second detector (19) and a second comparator (20) connected in sequence, the input end of the second coupler (18) is coupled to the output end of the second RF signal conditioning circuit (9), and the second comparator (20) outputs the second level signal LVTTL2 to the FPGA control unit (17).

5. The self-healing frequency source of claim 4, wherein, The reference voltage threshold of the first comparator (14) and the second comparator (20) is set to be 1dB to 3dB lower than the normal output power of the corresponding RF signal.

6. The self-healing frequency source of claim 1, wherein, The first phase-locked loop (3) and the second phase-locked loop (4) are completely identical in model and configuration parameters; the first RF signal conditioning circuit (8) and the second RF signal conditioning circuit (9) are completely identical in circuit topology and component parameters.

7. The self-healing frequency source of any of claims 1-6, wherein, The response time of the FPGA control unit (17) from fault judgment to completion of path switching is less than 200ms.

8. The method of implementing an automatic healing frequency source as claimed in any one of claims 1 to 7, wherein, The steps performed by the FPGA control unit include: S1, system power-on initialization, control the RF switch network to select the main path composed of the first phase-locked loop and the first RF signal conditioning circuit; S2, real-time monitoring of the state monitoring signal of the main path; S3, if the state monitoring signal indicates normal, maintain the current state and return to S2; S4, if the state monitoring signal indicates a fault, determine the fault type; S5, according to the fault type, control the RF switch network to start and switch to the corresponding standby circuit; S6, after confirming that the standby circuit is working normally, control the RF switch network to isolate the fault circuit.

9. The method of implementing an automatic healing frequency source of claim 8, wherein, In S4, the fault types include phase-locked loop faults and RF signal conditioning circuit faults; In S5, if it is determined that the phase-locked loop is faulty, control the RF switch network to power on the second phase-locked loop and switch its output signal path to the first RF signal conditioning circuit; if it is determined that the RF signal conditioning circuit is faulty, control the RF switch network to power on the second RF signal conditioning circuit and switch the input and output signal paths to the second RF signal conditioning circuit.

10. The method of implementing an automatic healing frequency source of claim 8, wherein, The state monitoring signal includes the first lock detection signal LD1 of the first phase-locked loop and the first level signal LVTTL1 representing the output power of the first RF signal conditioning circuit, and the FPGA control unit determines the fault type by judging the level combination of the first lock detection signal LD1 and the first level signal LVTTL1.

Images