Signal processing method, signal processing circuit, equipment, medium and product

Abstract

The invention relates to the technical field of signal processing, and relates to a signal processing method, a signal processing circuit, equipment, a medium and a product. The method comprises the following steps: receiving a first analog signal to obtain a first clock signal, and modulating and amplifying the first analog signal based on the first clock signal to obtain a second analog signal; acquiring a second clock signal, and performing analog-to-digital conversion processing on the second analog signal based on the second clock signal to obtain a first digital signal; filtering the first digital signal to obtain a second digital signal; wherein the period of the first clock signal is determined based on the period of the second clock signal and the oversampling rate. Thus, by performing filtering processing in the digital domain, flicker noise can be suppressed, meanwhile, the area of the signal processing circuit is reduced, and the power consumption resource of the signal processing circuit is further reduced.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and in particular to a signal processing method, signal processing circuit, device, medium and product. Background Technology

[0002] To suppress the ripple generated by chopping technology, some implementations increase the chopping frequency or use a low-pass filter with a narrower bandwidth than the gainable amplifier to filter out flicker noise. However, significantly increasing the chopping frequency increases the design complexity of the analog front-end. Therefore, some solutions employ a method of appropriately increasing or decreasing the chopping frequency and using a low-pass filter with a very narrow bandwidth to filter out flicker noise.

[0003] For example, some solutions use a first-order RC filter as a low-pass filter. However, due to the poor roll-off performance of a first-order RC filter, its ability to suppress low-frequency flicker noise is relatively weak. Therefore, some solutions use a Salen-key active filter as the low-pass filter. While the Salen-key active filter has good roll-off performance and strong noise suppression capability, its bandwidth is very narrow. Narrower bandwidth means a larger device area and higher power consumption. Therefore, using a Salen-key active filter as a low-pass filter increases the circuit area. It is understandable that since circuit power consumption increases with area, using a Salen-key active filter as a low-pass filter further increases the circuit's power consumption. Summary of the Invention

[0004] To address the issue that existing filtering methods increase the area and power consumption of the analog front-end, embodiments of this application provide a signal processing method, signal processing circuit, device, medium, and product, including:

[0005] In a first aspect, embodiments of this application provide a signal processing method, the signal processing method comprising: receiving a first analog signal, acquiring a first clock signal, and modulating and amplifying the first analog signal based on the first clock signal to obtain a second analog signal; acquiring a second clock signal, and performing analog-to-digital conversion processing on the second analog signal based on the second clock signal to obtain a first digital signal; and filtering the first digital signal to obtain a second digital signal; wherein the period of the first clock signal is determined based on the period of the second clock signal and the oversampling rate.

[0006] Based on the above scheme, by using digital domain filtering, flicker noise can be suppressed without reducing the filter bandwidth, thereby reducing the area of ​​the signal processing circuit. Furthermore, since the power consumption of the signal processing circuit decreases with decreasing area, the power consumption resources of the signal processing circuit can be reduced. Moreover, by determining the first clock signal based on the second clock signal and the oversampling rate, gain stabilization can be completed before sampling, avoiding signal distortion caused by timing misalignment.

[0007] In some implementations of the first aspect, the period of the first clock signal includes a sampling time, which is half the period of the first clock signal.

[0008] In some implementations of the first aspect, the period of the first clock signal includes the time for waiting for the chopper to be established and the sampling time, and the total time for waiting for the chopper to be established and the sampling time is half the period of the first clock signal.

[0009] In some implementations of the first aspect, the second analog signal is obtained by modulating and amplifying the first analog signal based on the first clock signal, including: modulating the noise signal in the first analog signal based on a preset sampling duration to obtain a modulated noise signal; wherein, the smaller the preset sampling duration, the higher the frequency of the modulated noise signal; and amplifying the modulated noise signal based on the first clock signal to obtain the second analog signal.

[0010] In some implementations of the first aspect, the noise signal in the first analog signal is modulated based on a preset sampling duration to obtain a modulated noise signal, including: modulating the noise signal in the first analog signal based on a preset sampling duration to modulate the frequency of the modulated noise signal to the notch point frequency of the digital filter.

[0011] In some implementations of the first aspect, the first analog signal includes a positive input analog signal and a negative input analog signal, and the second analog signal includes a positive output analog signal and a negative output analog signal; the second analog signal is obtained by modulating and amplifying the first analog signal based on the first clock signal, including: modulating and amplifying the positive input analog signal based on the first clock signal to obtain a positive output analog signal; and modulating and amplifying the negative input analog signal based on the first clock signal to obtain a negative output analog signal.

[0012] In some implementations of the first aspect, filtering the first digital signal to obtain the second digital signal includes: filtering the first digital signal based on the cutoff frequency to obtain the second digital signal.

[0013] Secondly, embodiments of this application provide a signal processing circuit, including: a programmable gain amplifier, an analog-to-digital converter (ADC), and a digital filter. The output terminal of the programmable gain amplifier is connected to the input terminal of the ADC, and the output terminal of the ADC is connected to the input terminal of the digital filter. The programmable gain amplifier is used to receive a first analog signal, acquire a first clock signal corresponding to the programmable gain amplifier, amplify the first analog signal based on the first clock signal to obtain a second analog signal, and send the second analog signal to the ADC. The ADC is used to acquire a second clock signal corresponding to the ADC, perform analog-to-digital conversion on the second analog signal based on the second clock signal to obtain a first digital signal, and send the first digital signal to the digital filter. The digital filter is used to filter the first digital signal to obtain the second digital signal. The period of the first clock signal is determined based on the period of the second clock signal and the oversampling rate.

[0014] In some implementations of the second aspect, the digital filter is a cascaded integrator-comb filter in a Σ-Δ modulator; the cutoff frequency of the cascaded integrator-comb filter is half the frequency of the first notch point of the cascaded integrator-comb filter.

[0015] Thirdly, this application provides an electronic device, including: a memory for storing instructions executed by one or more processors of the electronic device, and a processor, which is one of the one or more processors of the electronic device, for executing the signal processing method mentioned in the first aspect or any one of the first aspects of this application.

[0016] Fourthly, this application provides a readable storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the signal processing method mentioned in the first aspect or any one of the first aspects of this application.

[0017] Fifthly, embodiments of this application provide a computer program product, which includes computer instructions. When executed by an electronic device, the electronic device executes the computer program code of the signal processing method mentioned in the first aspect or any one of the first aspects of this application.

[0018] It is understood that the specific implementation methods and beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions of the signal processing methods in the first aspect or any of the various implementation methods provided in the first aspect, and will not be repeated here. Attached Figure Description

[0019] Figure 1 According to some embodiments of this application, a schematic flowchart of a signal processing method is shown;

[0020] Figure 2According to some embodiments of this application, a schematic diagram of a signal processing circuit is shown;

[0021] Figure 3 According to some embodiments of this application, a schematic diagram of another signal processing circuit is shown;

[0022] Figure 4 According to some embodiments of this application, a schematic diagram of another signal processing circuit is shown;

[0023] Figure 5 According to some embodiments of this application, a frequency response characteristic diagram of a cascaded integrator comb filter is shown;

[0024] Figure 6 According to some embodiments of this application, a timing diagram is shown;

[0025] Figure 7 According to some embodiments of this application, a schematic diagram of filtering a flickering signal is shown;

[0026] Figure 8 A schematic diagram of flicker noise is shown according to some embodiments of this application;

[0027] Figure 9 According to some embodiments of this application, another timing diagram is shown;

[0028] Figure 10 According to some embodiments of this application, another schematic diagram of filtering a flickering signal is shown;

[0029] Figure 11 According to some embodiments of this application, a schematic diagram of the hardware structure of an electronic device is shown. Detailed Implementation

[0030] It is understood that the embodiments of this application include, but are not limited to, a signal processing method, a signal processing circuit, an apparatus, a medium, and a product.

[0031] It is understood that the signal processing methods mentioned in the embodiments of this application can be applied to electronic devices. These electronic devices can be referred to as terminals, user equipment (UE), mobile stations (MS), mobile terminals (MT), etc. In some implementations, the electronic device can be a smartphone, a smart wearable device, a tablet computer, a computer with wireless transceiver capabilities, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart home, or any device with an analog front end (AFE).

[0032] For example, the signal processing method mentioned in the embodiments of this application can be applied to electronic devices having a voice coil motor (VCM).

[0033] It is understood that the signal processing methods mentioned in the embodiments of this application can be applied to scenarios such as communication, audio processing, video processing, or automatic control, and the embodiments of this application do not impose specific limitations.

[0034] An analog front-end is a circuit module that converts analog signals into digital signals. In an analog front-end with chopping technology, the front-end can chop and modulate the input signal to convert it from a low frequency to a high frequency, obtaining a modulated signal. Next, the analog front-end can amplify the modulated signal. Then, the analog front-end can demodulate and filter to recover the original input signal. During this process, the analog front-end can modulate DC offset and low-frequency noise signals (such as 1 / f noise, also known as flicker noise) to a higher frequency band for removal through filtering and other methods in subsequent processing, thereby improving signal quality.

[0035] The following is an exemplary description of the analog front-end signal processing process. In some implementations, the analog front-end signal processing process may include a chopper modulation stage, an amplification stage, a demodulation stage, and a low-pass filtering stage.

[0036] (1) Chopper modulation stage

[0037] During the chopper modulation stage, the input signal is multiplied by the high-frequency square wave carrier signal corresponding to the high-frequency chopper switch through the high-frequency chopper switch in the chopper, such as the metal oxide semiconductor field-effect transistor (MOSFET) switch, so as to convert the input signal from low frequency to high frequency and obtain a high-frequency input signal.

[0038] For example, the input signal can be referred to as the original low-frequency signal, denoted as S(t), and the frequency of the high-frequency square wave carrier signal can be denoted as f_chop. Typically, the frequency of the high-frequency square wave carrier signal can be kHz to MHz. Thus, by using the high-frequency square wave carrier signal to chop-modulate the input signal, the spectrum of the input signal can be modulated from the baseband (low frequency) to near the frequency of the high-frequency square wave carrier signal. During this process, low-frequency noise signals (such as flicker noise) are also modulated to a high frequency.

[0039] (2) Magnification stage

[0040] In the amplification stage, the modulated signal obtained by chopping modulation is amplified by an amplifier, such as a programmable gain amplifier (PGA), to obtain an amplified signal. The modulated signal may include a high-frequency square wave carrier signal and a noise signal.

[0041] In some implementations, high-frequency noise signals (such as thermal noise) can be suppressed due to the bandwidth limitation of the amplifier, while low-frequency noise signals can be amplified as the modulation signal is amplified.

[0042] (3) Demodulation phase

[0043] During the demodulation stage, a high-frequency square wave carrier signal with the same frequency and phase as that used in the chopping modulation stage is used to demodulate the amplified signal (e.g., multiply it again) to demodulate the useful signal in the amplified signal from high frequency to baseband, while simultaneously modulating the low-frequency noise signal to a higher frequency. For example, the spectrum of the low-frequency noise signal is modulated to near twice the frequency (2f_chop) of the high-frequency square wave carrier signal.

[0044] (4) Low-pass filtering stage

[0045] In the low-pass filtering stage, a low-pass filter, such as one with a cutoff frequency slightly higher than the bandwidth of the noise signal, is used to filter out high-frequency components in the amplified signal, such as high-frequency noise signals obtained by modulating low-frequency noise signals, thermal noise signals between the bandwidth of the low-pass filter and the bandwidth of the amplifier, while retaining the useful low-frequency signal.

[0046] For example, for signal-chain AC noise, after chopping in the modulation stage, low-frequency signal-chain AC noise can be modulated to a higher frequency band. Then, a first-order RC filter can be used to filter the chopped signal-chain AC noise. The chopped signal-chain AC noise with frequencies lower than the cutoff frequency Fc (-3dB) can generally pass through sequentially, while the chopped signal-chain AC noise with frequencies higher than the cutoff frequency Fc (-3dB) will be suppressed by the first-order RC filter.

[0047] However, when using a first-order RC filter to filter low-frequency flicker noise, the poor roll-off performance of the first-order RC filter results in weak suppression of low-frequency flicker noise. While using a Sallen-key active filter to filter low-frequency flicker noise offers better roll-off performance and stronger noise suppression, it increases power consumption and circuit area.

[0048] Therefore, it is understandable that using a low-pass filter to filter analog signals, i.e., filtering in the analog domain, will increase the area of ​​the analog front-end and increase the power consumption of the analog front-end.

[0049] To address the aforementioned problems, this application provides a signal processing method, which may include: receiving a first analog signal, acquiring a first clock signal, and modulating and amplifying the first analog signal based on the first clock signal to obtain a second analog signal; acquiring a second clock signal, and performing analog-to-digital conversion on the second analog signal based on the second clock signal to obtain a first digital signal; and filtering the first digital signal to obtain a second digital signal, wherein the period of the first clock signal is determined based on the period of the second clock signal and the oversampling rate.

[0050] Thus, by employing digital domain filtering, flicker noise can be suppressed without reducing the filter bandwidth, thereby reducing the area of ​​the signal processing circuit. Furthermore, since the power consumption of the signal processing circuit decreases with decreasing area, the power consumption resources of the signal processing circuit can be reduced. Moreover, by determining the first clock signal based on the second clock signal and the oversampling rate, gain stabilization can be completed before sampling, avoiding signal distortion caused by timing misalignment.

[0051] The signal processing methods mentioned in the embodiments of this application will be described in detail below. For example... Figure 1The diagram illustrates a flowchart of a signal processing method. In some implementations, this signal processing method can be applied to a signal processing circuit. For example, the signal processing method may include:

[0052] S101: Receive the first analog signal, acquire the first clock signal, and modulate and amplify the first analog signal based on the first clock signal to obtain the second analog signal.

[0053] It is understandable that in some implementations, the signal processing circuit can modulate the noise signal in the first analog signal based on a preset sampling duration to obtain a modulated noise signal; wherein, the shorter the preset sampling duration, the higher the frequency of the modulated noise signal. Furthermore, the signal processing circuit can amplify the modulated noise signal based on a first clock signal to obtain a second analog signal. In this way, the signal processing circuit can perform modulation and amplification processing on the first analog signal.

[0054] In some exemplary implementations, the signal processing circuit can modulate the noise signal in the first analog signal based on a preset sampling duration, modulating the frequency of the modulated noise signal to a notch frequency. For example, the signal processing circuit can modulate the noise signal in the first analog signal based on a first preset sampling duration, such that the frequency of the modulated noise signal is a first notch frequency. The signal processing circuit can also modulate the noise signal in the first analog signal based on a second preset sampling duration, such that the frequency of the modulated noise signal is a second notch frequency. It is understood that the signal processing circuit can modulate the noise signal in the first analog signal based on other sampling durations, such that the frequency of the modulated noise signal is other notch frequencies; this application does not specifically limit this.

[0055] It is understood that the first analog signal may include a positive input analog signal and a negative input analog signal, and the second analog signal may include a positive output analog signal and a negative output analog signal. Thus, in some implementations, the signal processing circuit can perform modulation and amplification processing (i.e., modulation and amplification) on the positive input analog signal based on the first clock signal to obtain the positive output analog signal. Furthermore, the signal processing circuit can perform modulation and amplification processing on the negative input analog signal based on the first clock signal to obtain the negative output analog signal.

[0056] The period of the first clock signal is determined based on the period of the second clock signal and the oversampling rate. Furthermore, in some implementations, the period of the first clock signal may include the sampling time, which can be half the period of the first clock signal. In other implementations, the period of the first clock signal may include the time for waiting for the chopper to establish and the sampling time, where the total time for waiting for the chopper to establish and the sampling time can be half the period of the first clock signal. Specific determination methods are detailed below and will not be elaborated upon here.

[0057] S102: Obtain the second clock signal, and perform analog-to-digital conversion on the second analog signal based on the second clock signal to obtain the first digital signal.

[0058] In some implementations, the signal processing circuit can acquire a second clock signal and, based on the second clock signal, perform analog-to-digital conversion on the second analog signal to obtain a first digital signal.

[0059] In other implementations, the signal processing circuit can acquire a second clock signal and, based on the second clock signal, perform analog-to-digital conversion on the differential analog signals of the positive and negative output analog signals to obtain a first digital signal.

[0060] S103: Filter the first digital signal to obtain the second digital signal, wherein the period of the first clock signal is determined based on the period of the second clock signal and the oversampling rate.

[0061] In some implementations, the signal processing circuit can filter the first digital signal based on a cutoff frequency to obtain a second digital signal. The cutoff frequency can be determined based on the sampling frequency, oversampling rate, and a preset coefficient; the larger the preset coefficient, the smaller the cutoff frequency.

[0062] Thus, by filtering the digital signal—that is, filtering in the digital domain—compared to filtering in the analog domain, flicker noise can be suppressed without reducing the filter bandwidth, thereby reducing the area of ​​the signal processing circuit. Furthermore, since the power consumption of the signal processing circuit decreases with decreasing area, the power consumption resources of the signal processing circuit can be reduced. Moreover, by determining the first clock signal based on the second clock signal and the oversampling rate, gain stabilization can be completed before sampling, avoiding signal distortion caused by timing misalignment.

[0063] The signal processing circuit mentioned in the embodiments of this application will be described below.

[0064] like Figure 2The diagram shows a schematic of a signal processing circuit. It can be understood that this signal processing circuit may include a programmable gain amplifier 110, an analog-to-digital converter 120, and a digital filter 130. The output of the programmable gain amplifier 110 is connected to the input of the analog-to-digital converter 120, and the output of the analog-to-digital converter 120 is connected to the input of the digital filter 130.

[0065] It is understandable that signal processing circuits can have single-ended outputs or differential outputs.

[0066] When the signal processing circuit is a single-ended output, the programmable gain amplifier 110 can receive the first analog signal, obtain the first clock signal corresponding to the programmable gain amplifier 110, and perform modulation and amplification processing on the first analog signal based on the first clock signal to obtain the second analog signal, and send the second analog signal to the analog-to-digital converter 120.

[0067] When the signal processing circuit has differential output, continue as follows: Figure 2 As shown, the programmable gain amplifier 110 may include a positive input terminal VIP, a negative input terminal VIN, a first clock input terminal, a positive output terminal VOP, and a negative output terminal VON.

[0068] In some implementations, the programmable gain amplifier 110 can receive a first analog signal, obtain a first clock signal corresponding to the programmable gain amplifier 110, and perform sampling and amplification processing on the positive input analog signal and the negative input analog signal based on the first clock signal to obtain a positive output analog signal and a negative output analog signal, which are then output to the analog-to-digital converter 120 through the positive output terminal and the negative output terminal of the programmable gain amplifier 110, respectively.

[0069] In other implementations, the programmable gain amplifier 110 receives the first analog signal, obtains the first clock signal corresponding to the programmable gain amplifier 110, and can perform modulation and amplification processing on the positive input analog signal and the negative input analog signal based on the first clock signal to obtain the positive output analog signal and the negative output analog signal, and output them to the analog-to-digital converter 120 through the positive output terminal and the negative output terminal of the programmable gain amplifier 110, respectively.

[0070] The analog-to-digital converter 120 may include a positive input terminal, a negative input terminal, a second clock input terminal, and an output terminal.

[0071] In some implementations, the analog-to-digital converter 120 can acquire the second clock signal corresponding to the analog-to-digital converter 120, and based on the second clock signal, perform analog-to-digital conversion processing on the second analog signal to obtain the first digital signal, and output it to the digital filter 130 through the output terminal of the analog-to-digital converter 120.

[0072] In other implementations, the positive input terminal of the analog-to-digital converter 120 can be connected to the positive output terminal of the programmable gain amplifier 110, and the negative input terminal of the analog-to-digital converter 120 can be connected to the negative output terminal of the programmable gain amplifier 110. The analog-to-digital converter 120 can acquire a second clock signal corresponding to itself, and based on the second clock signal, perform analog-to-digital conversion processing on the differential signal of the positive output analog signal and the negative output analog signal to obtain a first digital signal, which is then output to the digital filter 130 through the output terminal of the analog-to-digital converter 120.

[0073] The digital filter 130 may include a first clock output terminal, a second clock output terminal, and a digital signal output terminal.

[0074] In some implementations, the digital filter 130 can filter the first digital signal output by the analog-to-digital converter 120 and output a second digital signal through the digital signal output terminal.

[0075] Continue as Figure 2 As shown, the horizontal axis of the frequency response characteristic graph of the digital filter 130 represents frequency (Freq), in Hertz (Hz), and the vertical axis represents the amplitude of the signal transfer function (STF), i.e., the gain of the cascaded integrator-comb filter, in decibels (dB). The cutoff frequency of this digital filter 130 can be F... C This cutoff frequency can be determined based on the sampling frequency F of the digital filter 130. S And the oversampling rate OSR is determined, for example, F C =F S / 2(OSR).

[0076] It is understandable that the frequency response characteristic diagram of digital filter 130 can also be other frequency response characteristic diagrams, such as those described below. Figure 5 The frequency response characteristic diagram shown is not specifically limited in the embodiments of this application.

[0077] Thus, by setting the filtering process from analog domain to digital domain, flicker noise can be suppressed, while reducing the area of ​​the signal processing circuit and further reducing the power consumption of the signal processing circuit. Furthermore, by determining the first clock signal corresponding to the programmable gain amplifier 110 based on the second clock signal corresponding to the analog-to-digital converter 120 and the oversampling amount, gain stabilization can be completed before the analog-to-digital converter 120 samples, avoiding signal distortion caused by timing misalignment.

[0078] like Figure 3 The diagram shows a schematic of another signal processing circuit. (Compared to...) Figure 2The signal processing circuit shown differs in that the digital filter 130 can input a first clock signal (e.g., CLK_CHOP) to the programmable gain amplifier 110 and the analog-to-digital converter 120, and input a second clock signal (e.g., CLK_ADC) to the analog-to-digital converter 120. This allows the programmable gain amplifier 110 to modulate and amplify the first analog signal based on the first clock signal to obtain a second analog signal, and the analog-to-digital converter 120 to modulate and amplify the flicker noise generated by the analog-to-digital converter 120 based on the first clock signal to filter out flicker noise in subsequent filtering processes. Furthermore, the analog-to-digital converter 120 can perform analog-to-digital conversion on the second analog signal based on the second clock signal.

[0079] Furthermore, by inputting a first clock signal (e.g., CLK_CHOP) to the programmable gain amplifier 110 and the analog-to-digital converter 120 through the digital filter 130, the flicker noise in the programmable gain amplifier 110 and the analog-to-digital converter 120 can be modulated and amplified to the notch frequency of the digital filter 130, thereby improving the filtering performance.

[0080] The following is combined with Figure 4 ,right Figure 2 and Figure 3 The programmable gain amplifier 110 in the example will be described in detail. Figure 4 The diagram shows a schematic of a programmable gain amplifier 110.

[0081] like Figure 4 As shown, the programmable gain amplifier 110 may include an operational amplifier (OP), a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0082] In some implementations, one end of the first resistor R1 is the positive input terminal, and the other end of the first resistor R1 and one end of the second resistor R2 are connected to the positive input terminal of the operational amplifier, while the other end of the second resistor R2 is connected to the positive output terminal of the operational amplifier. One end of the third resistor R3 is the negative input terminal, and the other end of the third resistor R3 and one end of the fourth resistor R4 are connected to the negative output terminal of the operational amplifier. The positive output terminal of the operational amplifier can be connected to the positive output terminal of the programmable gain amplifier 110, and the negative output terminal of the operational amplifier can be connected to the negative output terminal of the programmable gain amplifier 110.

[0083] It can be understood that the programmable gain amplifier 110 can determine the gain for a positive input analog signal based on the first resistor R1 and the second resistor R2, thereby amplifying the positive input analog signal. For example, assuming the first resistor R1 has a resistance of 1 ohm and the second resistor R2 has a resistance of 10 ohms, then the gain of the programmable gain amplifier 110 for a positive input analog signal can be 11dB. Similarly, the programmable gain amplifier 110 can determine the gain for a negative input analog signal based on the third resistor R3 and the fourth resistor R4, thereby amplifying the negative input analog signal.

[0084] Understandable Figure 4 This is an illustration of the programmable gain amplifier 110 mentioned in the embodiments of this application. In actual applications, the programmable gain amplifier 110 can also have other structures, and the embodiments of this application do not make specific limitations.

[0085] The following is combined with Figure 5 ,right Figure 2 and Figure 3 The digital filter 130 in the text will be described in detail.

[0086] It is understandable that in some implementations, the digital filter 130 can be a cascaded integrator comb (CIC) in a Σ-Δ modulator (SDM), and the cutoff frequency of the cascaded integrator comb can be half the frequency of the first notch point of the cascaded integrator comb. For example... Figure 5 The diagram shows the frequency response characteristics of a cascaded integrator-comb filter. This frequency response characteristic diagram can represent the filtering characteristics of the cascaded integrator-comb filter for signals of different frequencies. The horizontal axis of the frequency response characteristic diagram represents the frequency (Freq), in Hertz (Hz), and the vertical axis represents the amplitude of the signal transfer function (STF), i.e., the gain of the cascaded integrator-comb filter, in decibels (dB).

[0087] Furthermore, the frequency response characteristic diagram may include the cutoff frequency F of the cascaded integrator-comb filter. C This cutoff frequency corresponds to the cutoff point (-3dB), meaning signals with frequencies lower than the cutoff frequency can pass smoothly through the cascaded integrator-comb filter, while signals with frequencies higher than the cutoff frequency will be suppressed by the cascaded integrator-comb filter. Furthermore, the frequency response characteristic diagram can also include the first and second notch frequencies of the cascaded integrator-comb filter, where the first notch frequency can be F... CIC =F CLK_ADC / OSR, the frequency of the second notch point can be F CLK_ADC / (OSR / 2). Signals with frequencies equal to or equal to the first or second notch frequency will be significantly suppressed by the cascaded integrator-comb filter. Furthermore, in some implementations, the cutoff frequency F of the cascaded integrator-comb filter is... C It can be half the frequency of the first notch point, i.e., F. C =F CIC / 2=F CLK_ADC / OSR / 2. Thus, by utilizing the notch characteristics of a cascaded integrator comb filter, the noise performance of the signal processing circuit can be improved, as well as its signal-to-noise ratio (SNR).

[0088] It is understandable that the time corresponding to half a cycle in the first clock signal can include the waiting time T1 for the chopper to establish and the sampling time T2. Among them, the waiting time T1 for the chopper to establish ensures that the analog-to-digital converter 120 acquires the signal after it has been stabilized by the chopper. Sampling should only be performed after the chopper has established a stable working state to avoid introducing noise or errors.

[0089] To ensure that the analog-to-digital converter 120 acquires the signal stabilized by the chopper, sampling needs to be performed only after the chopper has established a stable operating state. The second clock signal determines the sampling time; therefore, the waiting time T1 for the chopper to establish a stable state is related to the period T of the second clock signal. CLK_ADC Related. Furthermore, to ensure that the analog-to-digital conversion result accurately reflects the characteristics of the original signal, the analog-to-digital converter 120 needs to sample when the output signal of the programmable gain amplifier 110 is stable. Therefore, the sampling time of the programmable gain amplifier 110 will affect the sampling time of the analog-to-digital converter 120, and the two need to be coordinated. That is, the sampling time T2 is related to the period T of the second clock signal. CLK ADC Also related.

[0090] Thus, in some implementations, the time T1 for waiting for the chopper to set up can be set to N*T. CLK_ADC The sampling time T2 can be set to OSR*T CLK_ADC / 2, where N is a positive integer and OSR is the oversampling rate of the second clock signal. That is, the period of the first clock signal is determined based on the period of the second clock signal and the oversampling rate.

[0091] Wherein, the period T of the second clock signal CLK_ADC The oversampling rate (OSR) of the second clock signal remains constant. For example, N can be 1, 2, or 3, and the OSR of the second clock signal can be 2. nFor example, 64, 128, or 256, that is, after the T1 chopping setup is completed within half of the CLK_CHOP sampling period, a sampling operation of duration T2 will be performed, which is equivalent to distributing the sampling operation of the OSR oversampling rate of the second clock signal within one period of CLK_CHOP.

[0092] Thus, the programmable gain amplifier 110 can modulate the noise signal in the first analog signal based on a preset sampling duration to obtain a modulated noise signal; wherein, the shorter the preset sampling duration, the higher the frequency of the modulated noise signal. Furthermore, the programmable gain amplifier 110 amplifies the modulated noise signal to obtain a second analog signal.

[0093] In some implementations, for Figure 3 The timing sequence of the signal processing circuit shown can be as follows: Figure 6 The timing diagram is shown below. CLK_CHOP represents the first clock signal, VOP-VON represents the differential signal output by the programmable gain amplifier 110, and CLK_ADC represents the second clock signal, the frequency of which can be fixed at F = 6MHz. CIC_DATA represents the first digital signal, and ADO represents the second digital signal.

[0094] based on Figure 6 The timing sequence shown is as follows: Figure 7 As shown, Figure 7 In the graph (a), the spectral density of AC noise in the signal chain varies with frequency. The horizontal axis represents frequency (Freq) in Hertz (Hz), and the vertical axis represents spectral density in nanovolts per square root of Hertz (nV / sqrt(Hz)). Figure 7 (b) is a graph showing the spectral density of AC noise in the signal chain after chopping as a function of frequency. The horizontal axis represents frequency in Hertz (Hz), and the vertical axis represents spectral density in nanovolts per square root of Hertz (nV / sqrt(Hz)). Figure 7 (c) in the figure shows the frequency response characteristics of the cascaded integrator-comb filter. The horizontal axis represents frequency in Hertz (Hz), and the vertical axis represents gain in decibels (dB).

[0095] for Figure 7 The AC noise in the signal chain shown in (a) can be reduced after chopping. Figure 7 In (a) of the diagram, the signal chain AC noise is modulated within the dashed box area. Figure 7 Within the dashed box area in (b) of the diagram, the low-frequency signal chain AC noise is modulated to the high-frequency band. Furthermore, due to... Figure 7 The AC noise in the signal chain within the dashed box area in (a) is "moved" to Figure 7 Within the dashed box area in (b) of the diagram, and since spectral density is noise energy per unit frequency, under the same spectral density metric, the low-frequency band obtained by dispersing the originally concentrated low-frequency noise of the signal chain to the high-frequency band is, i.e., Figure 7 In (b), the area filled with diagonal lines represents the noise energy per unit frequency relative to... Figure 7 The noise energy is reduced within the dashed box area in (a) of the diagram, therefore Figure 7 The spectral density of the diagonally filled region in (b) is relative to Figure 7 The spectral density decreases within the dashed box region in (a) of the image.

[0096] Furthermore, such as Figure 7 As shown in (c), a cascaded integrator-comb filter can be used to filter the AC noise of the chopped signal chain. Since the peak frequency of the AC noise in the chopped signal chain is the same as the notch point frequency of the cascaded integrator-comb filter, i.e., Freq_chop = F CLK_ADC / OSR, where Freq_chop can represent the peak frequency of AC noise in the signal chain, and can be F CLK_ADC / OSR represents the first notch frequency of the cascaded integrator-comb filter. Thus, when the chopped AC noise in the signal chain passes through the cascaded integrator-comb filter, the AC noise at its peak frequency will be suppressed due to the notch characteristics of the filter. Furthermore, AC noise in the chopped signal chain with frequencies lower than the cutoff frequency Fc (-3dB) can generally pass through sequentially, while AC noise with frequencies higher than the cutoff frequency Fc (-3dB) will be suppressed by the cascaded integrator-comb filter.

[0097] Thus, the cascaded integrator comb filter can suppress AC noise in the signal chain after chopping at a frequency adjusted to the high-frequency band, while also significantly suppressing AC noise in the signal chain after chopping at the peak frequency, thereby reducing AC noise in the signal chain.

[0098] like Figure 8 As shown, the fco band is the band most severely affected by flicker noise. The fco band is inversely proportional to the channel width (W) and channel length (L) of the analog front end. Therefore, chopping technology can be used to modulate it to a higher frequency band for digital filtering.

[0099] In some other implementations, for Figure 3 The timing sequence of the signal processing circuit shown can be as follows: Figure 9The timing diagram is shown below. Here, CLK_CHOP represents the first clock signal, VOP-VON represents the differential signal output by the programmable gain amplifier 110, CLK_ADC represents the second clock signal, and the frequency of the second clock signal can be F = 6MHz. CIC_DATA represents the first digital signal, and ADO represents the second digital signal.

[0100] Furthermore, it is understandable that the smaller the sampling time T2, the higher the frequency of the noise signal after chopping. In some implementations, T2 can be set to OSR*TCLK_ADC / 4, in which case the frequency of the first clock signal is FCLK_ADC / (2*OSR), and near FCLK_ADC / (2*OSR), the STF gain is smaller, resulting in stronger suppression of high-frequency noise signals. Moreover, with a fixed FC, the suppression of flicker noise increases with the increase of the chopping frequency. Furthermore, the flick-noise and thermal noise corner frequencies of the programmable gain amplifier 110 can be designed to be larger (not exceeding the chopper frequency), thereby further saving circuit design resources, such as reducing circuit area.

[0101] based on Figure 9 The timing sequence shown is as follows: Figure 10 As shown, Figure 10 In the graph (a), the spectral density of AC noise in the signal chain varies with frequency. The horizontal axis represents frequency (Freq) in Hertz (Hz), and the vertical axis represents spectral density in nanovolts per square root of Hertz (nV / sqrt(Hz)). Figure 10 (b) is a graph showing the spectral density of AC noise in the signal chain after chopping as a function of frequency. The horizontal axis represents frequency in Hertz (Hz), and the vertical axis represents spectral density in nanovolts per square root of Hertz (nV / sqrt(Hz)). Figure 10 (c) in the figure shows the frequency response characteristics of the cascaded integrator-comb filter. The horizontal axis represents frequency in Hertz (Hz), and the vertical axis represents gain in decibels (dB).

[0102] for Figure 10 The AC noise in the signal chain shown in (a) can be reduced after chopping. Figure 9 In (a) of the diagram, the signal chain AC noise is modulated within the dashed box area. Figure 10 Within the dashed box in (b) of the diagram, the low-frequency signal chain AC noise is modulated to the high-frequency band. Furthermore, due to... Figure 10 The AC noise in the signal chain within the dashed box area in (a) is "moved" to Figure 10Within the dashed box area in (b) of the diagram, and since spectral density is noise energy per unit frequency, under the same spectral density metric, the low-frequency band obtained by dispersing the originally concentrated low-frequency noise of the signal chain to the high-frequency band is, i.e., Figure 10 In (b), the area filled with diagonal lines represents the noise energy per unit frequency relative to... Figure 10 The noise energy is reduced within the dashed box area in (a) of the diagram, therefore Figure 10 The spectral density of the diagonally filled region in (b) is relative to Figure 10 The spectral density decreases within the dashed box region in (a) of the image.

[0103] Furthermore, such as Figure 10 As shown in (c), a cascaded integrator-comb filter can be used to filter the AC noise of the chopped signal chain. Since the peak frequency of the AC noise in the chopped signal chain is the same as the notch point frequency of the cascaded integrator-comb filter, i.e., Freq_chop = F CLK_ADC / (OSR / 2), where Freq_chop can represent the peak frequency of the AC noise in the signal chain, and F CLK_ADC / (OSR / 2) represents the second notch frequency of the cascaded integrator-comb filter. Thus, when the chopped AC noise in the signal chain passes through the cascaded integrator-comb filter, the AC noise at its peak frequency will be suppressed due to the notch characteristics of the filter. Furthermore, AC noise in the chopped signal chain with frequencies lower than the cutoff frequency Fc (-3dB) can generally pass through sequentially, while AC noise with frequencies higher than the cutoff frequency Fc (-3dB) will be suppressed by the cascaded integrator-comb filter.

[0104] Thus, the cascaded integrator comb filter can suppress AC noise in the signal chain after chopping at the peak frequency, while simultaneously suppressing AC noise in the signal chain after chopping at the peak frequency, thereby reducing or eliminating AC noise in the signal chain modulated to the high frequency.

[0105] It is understood that the signal processing method provided in this application embodiment can be applied to electronic devices. The hardware structure of the electronic device to which the signal processing method provided in this application embodiment is applicable will be described exemplarily below.

[0106] like Figure 11As shown, the electronic device 1100 may include a processor 1110, an external memory interface 1120, an internal memory 1121, a universal serial bus (USB) interface 1130, a charging management module 1140, a power management module 1141, a battery 1142, an antenna, a wireless communication module 1150, an audio module 1160, a speaker 1160A, a receiver 1160B, a microphone 1160C, a headphone jack 1160D, a camera 1170, a display screen 1180, etc.

[0107] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the electronic device 1100. In other embodiments of this application, the electronic device 1100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0108] Processor 1110 may include one or more processing units, such as: application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0109] The controller can generate operation control signals based on the instruction opcode and timing signals to control instruction fetching and execution. The processor 1110 can control instruction fetching and execution through the controller to implement the signal processing method provided in this embodiment. For example, the processor 1110 can control instruction fetching and execution through the controller to implement the above-described... Figure 1 The steps to be implemented in the process shown are as follows.

[0110] The processor 1110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 1110 is a cache memory. This memory can store instructions or data that the processor 1110 has just used or that are used repeatedly. If the processor 1110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 1110, and thus improves the efficiency of the system.

[0111] The wireless communication function of electronic devices can be realized through antennas, wireless communication modules 1150, modem processors, and baseband processors.

[0112] Antennas are used to transmit and receive electromagnetic wave signals. Each antenna in an electronic device can be used to cover one or more communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antennas can be reused as diversity antennas for a wireless local area network. In some other embodiments, antennas can be used in conjunction with tuning switches.

[0113] The wireless communication module 1150 can provide solutions for wireless communication applications in electronic devices, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The wireless communication module 1150 can be one or more devices integrating at least one communication processing module. The wireless communication module 1150 receives electromagnetic waves via an antenna, performs frequency modulation and filtering of the electromagnetic wave signals, and sends the processed signal to the processor 1110. The wireless communication module 1150 can also receive signals to be transmitted from the processor 1110, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via the antenna.

[0114] Electronic devices implement display functions through GPUs, display screens 1180, and application processors. A GPU is a microprocessor for image processing, connecting the display screen 1180 and the application processor. The GPU performs mathematical and geometric calculations for graphics rendering. Processor 1110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0115] Display screen 1180 is used to display images, videos, etc. Display screen 1180 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), Mini-LED, MicroLED, Micro-OLED, quantum dot light-emitting diodes (QLED), etc. In some embodiments, the electronic device may include one or N displays 1180, where N is a positive integer greater than 1.

[0116] In some cases, the embodiments disclosed in this application may be implemented in hardware, firmware, software, or any combination thereof.

[0117] The embodiments disclosed in this application can also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which can be read and executed by one or more processors. For example, the instructions can be distributed via a network or via other computer-readable media. Therefore, machine-readable media can include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, magnetic disks, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other propagation signals. Therefore, machine-readable media includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0118] Embodiments of this application can be implemented as computer programs or program code that execute on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0119] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0120] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. The mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0121] The above describes the possible hardware structures of electronic devices. It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine certain components, or split certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of both.

[0122] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0123] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0124] Although this application has been illustrated and described with reference to certain embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the scope of this application.

Claims

1. A signal processing method, characterized in that, include: Receive a first analog signal, acquire a first clock signal, and modulate and amplify the first analog signal based on the first clock signal to obtain a second analog signal; Acquire a second clock signal, and perform analog-to-digital conversion on the second analog signal based on the second clock signal to obtain a first digital signal; The first digital signal is filtered to obtain the second digital signal; The period of the first clock signal is determined based on the period of the second clock signal and the oversampling rate.

2. The method according to claim 1, characterized in that, The period of the first clock signal includes a sampling time, which is half the period of the first clock signal.

3. The method according to claim 1, characterized in that, The period of the first clock signal includes the waiting time for the chopper to be established and the sampling time, and the total time of the waiting time for the chopper to be established and the sampling time is half of the period of the first clock signal.

4. The method according to any one of claims 1 to 3, characterized in that, The process of modulating and amplifying the first analog signal based on the first clock signal to obtain the second analog signal includes: The noise signal in the first analog signal is modulated based on a preset sampling duration to obtain a modulated noise signal; wherein, the shorter the preset sampling duration, the higher the frequency of the modulated noise signal. The modulated noise signal is amplified based on the first clock signal to obtain the second analog signal.

5. The method according to claim 4, characterized in that, The modulation processing of the noise signal in the first analog signal based on a preset sampling duration to obtain the modulated noise signal includes: Based on the preset sampling duration, the noise signal in the first analog signal is modulated, and the frequency of the modulated noise signal is modulated into the notch point frequency.

6. The method according to claim 4, characterized in that, The first analog signal includes a positive input analog signal and a negative input analog signal, and the second analog signal includes a positive output analog signal and a negative output analog signal; The process of modulating and amplifying the first analog signal based on the first clock signal to obtain the second analog signal includes: The positive input analog signal is modulated and amplified based on the first clock signal to obtain the positive output analog signal; The negative input analog signal is modulated and amplified based on the first clock signal to obtain the negative output analog signal.

7. The method according to claim 1, characterized in that, The step of filtering the first digital signal to obtain the second digital signal includes: The first digital signal is filtered based on the cutoff frequency to obtain the second digital signal.

8. A signal processing circuit, characterized in that, include: A programmable gain amplifier, an analog-to-digital converter, and a digital filter are provided, wherein the output of the programmable gain amplifier is connected to the input of the analog-to-digital converter, and the output of the analog-to-digital converter is connected to the input of the digital filter. The programmable gain amplifier is used to receive a first analog signal, obtain a first clock signal corresponding to the programmable gain amplifier, amplify the first analog signal based on the first clock signal to obtain a second analog signal, and send the second analog signal to the analog-to-digital converter. The analog-to-digital converter is used to acquire the second clock signal corresponding to the analog-to-digital converter, and to perform analog-to-digital conversion processing on the second analog signal based on the second clock signal to obtain a first digital signal, and to send the first digital signal to the digital filter; The digital filter is used to filter the first digital signal to obtain the second digital signal; The period of the first clock signal is determined based on the period of the second clock signal and the oversampling rate.

9. The signal processing circuit according to claim 8, characterized in that, The digital filter is a cascaded integrator comb filter in a Σ-Δ modulator; The cutoff frequency of the cascaded integrator-comb filter is half the frequency of the first notch point of the cascaded integrator-comb filter.

10. An electronic device, characterized in that, include: A memory for storing instructions executed by one or more processors of the electronic device, and a processor, being one of one or more processors of the electronic device, for performing the signal processing method according to any one of claims 1 to 7.

11. A readable storage medium, characterized in that, The readable storage medium stores instructions that, when executed on an electronic device, cause the electronic device to perform the signal processing method of any one of claims 1 to 7.

12. A computer program product, characterized in that, The computer program product includes computer instructions, which, when executed by an electronic device, enable the electronic device to execute computer program code of the signal processing method as described in any one of claims 1 to 7.

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