BGA (Ball Grid Array) gold plating method for PCB (Printed Circuit Board) and PCB

Abstract

The invention discloses a BGA gold plating method for a PCB and the PCB, and belongs to the technical field of printed circuit boards, and the BGA gold plating method for the PCB comprises the steps: firstly, forming a seed layer on the surface of a first substrate in a copper ion sputtering mode, and enabling only the seed layer in a BGA region to be exposed in a film layer coating and local film layer removing mode, according to the method, the seed layer of the BGA area is plated with gold, and finally, the residual film layer and the seed layer under the film layer are removed in sequence, so that accurate gold plating in the BGA area can be realized without influencing other areas, the condition that conductive wires are always left in a conductive wire pulling gold plating mode is avoided, and the problem that the conductive wire pulling mode is used for plating the BGA at present, so that the cost is low is solved. The processing flow is long; and the conductive wire is left.

Description

Technical Field

[0001] This invention relates to a BGA gold plating method for PCBs and a PCB board, belonging to the field of printed circuit board technology. Background Technology

[0002] BGA (Ball Grid Array) has become an indispensable core component of modern equipment due to its high density and high performance. However, BGA pads face risks such as oxidation and soldering reliability during high-density interconnection and high-speed signal transmission, making gold plating of BGAs crucial.

[0003] Currently, traditional BGA gold plating solutions involve either drawing conductive lines or applying thick gold plating. However, as the BGA pitch (distance between pad centers) becomes smaller, drawing conductive lines can no longer meet the requirements. Furthermore, the process of drawing conductive lines is relatively long, and there will be 3-5mil conductive lines remaining between BGAs, which affects signal integrity. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a BGA gold plating method and PCB board for PCB. It is suitable for BGA gold plating with a short distance from the center of the pad to the center of the pad, avoids the influence of gold plating on the signal, and solves the problems of long processing flow and residual conductive lines when using the current method of drawing conductive lines to plate BGA.

[0005] To solve the above-mentioned technical problems, the present invention is implemented using the following technical solution: This invention provides a BGA gold plating method for PCBs, comprising: Based on the graphic scheme, a BGA pattern is fabricated on the copper-clad board to obtain the first substrate. Copper ions are sputtered onto the surface of the first substrate to form a seed layer that serves as a conductive substrate; A film layer for pattern transfer is coated on the surface of the seed layer; Remove local film layers to expose the seed layer on the BGA pattern surface; Gold is plated onto the seed layer on the surface of the BGA pattern to form a second substrate; Remove the remaining membrane layer and seed layer in sequence.

[0006] Further, the step of fabricating a BGA pattern on a copper-clad laminate according to the pattern scheme to obtain a first substrate includes: Based on the inner layer pattern of the graphic scheme, the inner layer pattern is created on copper-clad boards of multiple preset sizes; Multiple copper-clad laminates with inner layer patterns are stacked on prepreg sheets and then pressed together to form a stacked board. Electroplating is performed on the stacked boards to form an outer copper layer on the surface of the stacked boards; Based on the outer layer pattern of the pattern scheme, a BGA pattern is fabricated on the outer copper layer to obtain the first substrate.

[0007] Furthermore, the step of sputtering copper ions on the surface of the first substrate to form a seed layer as a conductive substrate includes sputtering copper ions using a vacuum sputtering method.

[0008] Furthermore, the method of sputtering copper ions using vacuum sputtering includes: in a vacuum environment, bombarding a copper target with argon ions ionized by argon gas to deposit discrete copper ions onto the surface of a first substrate to form a seed layer.

[0009] Furthermore, the seed layer thickness is 300~500nm.

[0010] Furthermore, the step of covering the seed layer surface with a film layer for pattern transfer includes: coating the seed layer surface with a thermosetting wet film and curing it at high temperature to obtain the film layer.

[0011] Furthermore, the thickness of the film layer is 0.7~0.8 mil.

[0012] Furthermore, the removal of the local film layer to expose the seed layer of the BGA pattern surface includes removing the local film layer using a UV laser.

[0013] Further, the sequential removal of the remaining membrane layer and the seed layer includes: The remaining membrane layer is removed using an organic base; The remaining seed layer was removed using a sodium sulfate solution.

[0014] In another aspect, the present invention provides a PCB board manufactured using the above-described BGA gold plating method for PCBs.

[0015] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: This invention first forms a seed layer on the surface of a first substrate by sputtering copper ions. Then, through a coating layer and a partial film removal process, only the seed layer in the BGA area is exposed, and gold is then plated on the seed layer in the BGA area. Finally, the remaining film layer and the seed layer under the film layer are removed sequentially. This allows for precise gold plating in the BGA area without affecting other areas, avoiding the problem of conductive wire residue that always occurs with the wire-drawing gold plating method. This solves the problems of long processing steps and conductive wire residue in the current method of BGA gold plating. Attached Figure Description

[0016] Figure 1 This is a flowchart of a BGA gold plating method for PCB provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the first substrate structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the seed layer structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the membrane structure provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the gold plating layer structure provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the second substrate structure provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of a PCB board provided in an embodiment of the present invention.

[0017] In the figure: 1. First substrate; 101. Copper clad laminate; 102. BGA pattern; 103. Prepreg; 2. Seed layer; 3. Film layer; 4. Gold plating layer; 5. Second substrate. Detailed Implementation

[0018] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0019] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0020] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances. Example 1

[0021] like Figure 1 As shown, a BGA gold plating method for PCBs includes: like Figure 2 As shown, according to the pattern scheme, a BGA pattern 102 is fabricated on the copper-clad laminate 101 to obtain the first substrate 1. Specifically: According to the inner layer pattern of the pattern scheme, the inner layer pattern is produced on copper-clad laminates 101 of multiple preset sizes by exposure, development and etching. Multiple copper-clad laminates 101 with inner layer patterns are stacked on prepreg 103 and pressed together using a vacuum hot press to form a stacked board. Electroplating is performed on the stacked boards to form an outer copper layer on the surface of the stacked boards; Based on the outer layer pattern of the pattern scheme, the BGA pattern 102 and the corresponding circuit are fabricated on the outer copper layer by exposure, development and etching to obtain the first substrate 1.

[0022] like Figure 3 As shown, copper ions are sputtered onto the surface of the first substrate 1 to form a seed layer 2, which serves as a conductive substrate. Specifically: Copper ions are sputtered using vacuum sputtering. In a vacuum environment, argon ions ionized by argon gas bombard the copper target, depositing discrete copper ions onto the surface of the first substrate 1 to form a seed layer 2. Argon gas is an inert gas and poses no risk of chemical reaction to the target and substrate. Using argon gas can improve sputtering efficiency and film quality. In this embodiment, the thickness of seed layer 2 is 300~500nm.

[0023] like Figure 4 As shown, a film layer 3 for pattern transfer is covered on the surface of seed layer 2, specifically: A thermosetting wet film is coated on the surface of the seed layer 2 by spraying. The first substrate 1 with the film is then placed in a high-temperature oven and heated to cure the thermosetting wet film, forming a film layer 3 on the surface of the seed layer 2. The thickness of the film layer 3 is 0.7~0.8 mil.

[0024] like Figure 5 and Figure 6 As shown, in this embodiment, a UV laser machine is used to burn off only the film layer 3 in the BGA region. By partially removing the film layer 3, only the seed layer 2 in the BGA region is exposed. Then, through oxidation-reduction, the seed layer 2 on the surface of the BGA region is precisely plated with gold. The gold anode loses electrons under the action of current and is oxidized into gold ions. The gold ions gain electrons in the seed layer 2, which serves as the cathode, are reduced to gold, and deposited on the BGA surface to form a gold plating layer 4 and obtain the second substrate 5.

[0025] The second substrate 5 is placed inside the stripping line, and the film 3 is removed using a 5% sodium hydroxide solution; The seed layer 2, which is not protected by a wet film or gold, is removed using a micro-etching solution with sodium persulfate as the core component. The thickness removed is only 300-500 nm, which will not affect the copper thickness in other locations. Example 2

[0026] like Figure 1 As shown, a PCB board is manufactured using the following method: Based on the graphic scheme, a BGA pattern is fabricated on the copper-clad board to obtain the first substrate. Copper ions are sputtered onto the surface of the first substrate to form a seed layer that serves as a conductive substrate; A film layer for pattern transfer is coated on the surface of the seed layer; Remove local film layers to expose the seed layer on the BGA pattern surface; Gold is plated onto the seed layer on the surface of the BGA pattern to form a second substrate; like Figure 7 As shown, the remaining film layer and seed layer are removed sequentially to obtain the target PCB board.

[0027] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for gold plating BGAs for PCBs, characterized in that, include: Based on the graphic scheme, a BGA pattern is fabricated on the copper-clad board to obtain the first substrate. Copper ions are sputtered onto the surface of the first substrate to form a seed layer that serves as a conductive substrate; A film layer for pattern transfer is coated on the surface of the seed layer; Remove local film layers to expose the seed layer on the BGA pattern surface; Gold is plated onto the seed layer on the surface of the BGA pattern to form a second substrate; Remove the remaining membrane layer and seed layer in sequence.

2. As described in claim 1, characterized in that, The process of fabricating a BGA pattern on a copper-clad laminate according to the pattern scheme to obtain a first substrate includes: Based on the inner layer pattern of the graphic scheme, the inner layer pattern is created on copper-clad boards of multiple preset sizes; Multiple copper-clad laminates with inner layer patterns are stacked on prepreg sheets and then pressed together to form a stacked board. Electroplating is performed on the stacked boards to form an outer copper layer on the surface of the stacked boards; Based on the outer layer pattern of the pattern scheme, a BGA pattern is fabricated on the outer copper layer to obtain the first substrate.

3. As described in claim 1, characterized in that, The step of sputtering copper ions on the surface of the first substrate to form a seed layer as a conductive substrate includes sputtering copper ions by vacuum sputtering.

4. As described in claim 3, characterized in that, The method of sputtering copper ions using vacuum sputtering includes: bombarding a copper target material with argon ions ionized by argon gas in a vacuum environment to deposit discrete copper ions onto the surface of a first substrate to form a seed layer.

5. As described in claim 3, characterized in that, The thickness of the seed layer is 300~500nm.

6. As described in claim 1, characterized in that, The step of covering the seed layer surface with a film layer for pattern transfer includes: coating the seed layer surface with a thermosetting wet film and curing it at high temperature to obtain the film layer.

7. As described in claim 6, characterized in that, The thickness of the film layer is 0.7~0.8 mil.

8. As described in claim 1, characterized in that, The removal of local film layers to expose the seed layer of the BGA pattern surface includes removing local film layers using UV laser.

9. As described in claim 1, characterized in that, The sequential removal of the remaining membrane layer and the seed layer includes: The remaining membrane layer is removed using an organic base; The remaining seed layer was removed using a sodium sulfate solution.

10. A PCB board, characterized in that, It is prepared by the BGA gold plating method for PCB as described in any one of claims 1 to 9.

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