Semiconductor device, electronic apparatus, and manufacturing method

Abstract

The invention provides a semiconductor device, electronic equipment and a manufacturing method. The semiconductor device includes: a substrate; the memory cells are distributed on the substrate in an array mode, and each memory cell comprises a first isolation layer, an electrode wire, a write-in word line and a first dielectric layer which are perpendicular to the substrate; the grid electrode surrounds the side wall of the first isolation layer; the second dielectric layer is located on one side, away from the first isolation layer, of the gate; the first channel layer is located on the side, away from the grid electrode, of the second dielectric layer, and the material of the first channel layer comprises a single-crystal semiconductor material; the first electrode and the second electrode are separated by the first dielectric layer, the first electrode and the second electrode are respectively in contact with the first channel layer, and the first electrode is in contact with the electrode wire; the third dielectric layer surrounds the side wall of the write-in word line; the second channel layer is located on the side, away from the write-in word line, of the third dielectric layer, and the part, close to the grid electrode, of the second channel layer makes contact with the grid electrode.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, electronic device, and manufacturing method. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The inventors of this disclosure have discovered that in related technologies, in three-dimensional storage devices containing memory cells, the use of amorphous material channel layers in the read transistors of the memory cells can lead to inaccurate stored data.

[0005] In view of this, the present disclosure provides a semiconductor device to improve the accuracy of data storage.

[0006] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a substrate; and a plurality of memory cells arranged in an array on the substrate, each memory cell comprising: a first isolation layer perpendicular to the substrate, an electrode line, a write word line, and a first dielectric layer; a gate surrounding a sidewall of the first isolation layer; a second dielectric layer located on a side of the gate away from the first isolation layer; a first channel layer located on a side of the second dielectric layer away from the gate, the first channel layer being made of a single-crystal semiconductor material; a first electrode and a second electrode separated by the first dielectric layer, wherein the first electrode and the second electrode are respectively in contact with the first channel layer, and the first electrode is in contact with the electrode line; a third dielectric layer surrounding a sidewall of the write word line; and a second channel layer located on a side of the third dielectric layer away from the write word line, a portion of the second channel layer near the gate contacting the gate.

[0007] In some embodiments, the first channel layer includes: a first channel portion located between the second electrode and the second dielectric layer; and a second channel portion located between the first dielectric layer and the second dielectric layer, wherein the second channel portion is in contact with the first electrode.

[0008] In some embodiments, each memory cell further includes a read bit line located on the side of the second electrode away from the first channel layer.

[0009] In some embodiments, each memory cell further includes a write bit line that contacts a portion of the second channel layer on the side away from the gate.

[0010] In some embodiments, each memory cell further includes: a read word line perpendicular to the substrate and surrounded by the first dielectric layer; wherein the electrode line is a common electrode line.

[0011] In some embodiments, the electrode lines are read word lines.

[0012] In some embodiments, the semiconductor device further includes: a plurality of isolation patterns, each isolation pattern including: a first isolation portion and a second isolation portion, wherein the first isolation portion and the second isolation portion are both perpendicular to the substrate, the first isolation portion extends along a first direction parallel to the substrate and is located between adjacent memory cells arranged along a second direction parallel to the substrate, the second isolation portion extends along the second direction and is connected to the first isolation portion, the second isolation portion is located between the electrode line and the write word line, wherein the second direction intersects the first direction.

[0013] In some embodiments, the semiconductor device further includes: multiple layers of alternately stacked insulating layers and doped semiconductor layers; the insulating layers are located between adjacent memory cells in a third direction perpendicular to the substrate; the doped semiconductor layers serve as the first electrode and the second electrode.

[0014] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a plurality of stacked structural layers on a substrate, each structural layer including a doped semiconductor layer and an insulating layer on the semiconductor layer; forming a first channel layer in the plurality of structural layers, the first channel layer being made of a single-crystal semiconductor material; forming a second dielectric layer covering the first channel layer; forming a gate on a side of the second dielectric layer away from the first channel layer; forming a first isolation layer perpendicular to the substrate in the plurality of structural layers, the first isolation layer being surrounded by the gate; forming a first dielectric layer and an electrode line perpendicular to the substrate in the plurality of structural layers, wherein the semiconductor layer isolated by the first dielectric layer serves as a first electrode and a second electrode, wherein the first electrode and the second electrode are respectively in contact with the first channel layer, and the first electrode is in contact with the electrode line; forming a second channel layer in the plurality of structural layers, a portion of the second channel layer near the gate being in contact with the gate; and forming a write word line perpendicular to the substrate and a third dielectric layer surrounding the sidewalls of the write word line in the plurality of structural layers.

[0015] In some embodiments, forming the first channel layer in the plurality of structural layers includes: patterning the plurality of structural layers to form a first opening that exposes the substrate and the semiconductor layer; performing side etching on the semiconductor layer based on the first opening to retract the semiconductor layer relative to the insulating layer, thereby forming a first notch; and forming the first channel layer in the first notch and on the side surface of the semiconductor layer.

[0016] In some embodiments, forming a plurality of stacked structural layers on a substrate includes: forming a plurality of stacked initial layers on the substrate, each initial layer including the doped semiconductor layer and a sacrificial layer on the semiconductor layer; performing patterning on the plurality of initial layers to form the first opening; removing the sacrificial layer through the first opening to form a first cavity; and forming an insulating layer filling the first cavity.

[0017] In some embodiments, forming a plurality of stacked structural layers on a substrate further includes: forming a plurality of isolation patterns in the initial layers before patterning the plurality of initial layers, each isolation pattern including: a first isolation portion and a second isolation portion, wherein the first isolation portion and the second isolation portion are both perpendicular to the substrate, the first isolation portion extends along a first direction parallel to the substrate, the second isolation portion extends along a second direction parallel to the substrate and is connected to the first isolation portion, the second direction intersects the first direction, wherein the first opening is formed between adjacent isolation patterns in the second direction.

[0018] In some embodiments, forming a first dielectric layer perpendicular to the substrate in the plurality of structural layers includes: patterning the plurality of structural layers to form a second opening that exposes the substrate and the first channel layer; and forming a first dielectric layer covering the bottom and sides of the second opening.

[0019] In some embodiments, the manufacturing method further includes: forming a read word line in the second opening where the first dielectric layer is formed; wherein the electrode line is a common electrode line.

[0020] In some embodiments, the electrode lines are read word lines (RWL).

[0021] In some embodiments, forming an electrode line perpendicular to the substrate in the plurality of structural layers includes: patterning the plurality of structural layers to form a third opening that exposes the substrate, the semiconductor layer, and the insulating layer; and forming an electrode line perpendicular to the substrate in the third opening that contacts the semiconductor layer.

[0022] In some embodiments, the manufacturing method further includes: patterning the plurality of structural layers to form a fourth opening, the fourth opening exposing the substrate, the insulating layer and the semiconductor layer; performing side etching on the semiconductor layer through the fourth opening to retract the semiconductor layer relative to the insulating layer, thereby forming a second notch; and forming a read bit line in the second notch.

[0023] In some embodiments, forming a second channel layer in the plurality of structural layers includes: patterning the plurality of structural layers to form a fifth opening and a sixth opening, the fifth opening and the sixth opening respectively exposing the substrate; removing a portion of the semiconductor layer, a portion of the first channel layer and a portion of the second dielectric layer through the fifth opening and the sixth opening to form a second cavity; forming a second channel layer on a surface inside the second cavity through the fifth opening and the sixth opening; the manufacturing method further includes: forming a write bit line in contact with the second channel layer.

[0024] In some embodiments, forming a write word line perpendicular to the substrate and a third dielectric layer surrounding the sidewalls of the write word line in the plurality of structural layers includes: forming a third dielectric layer covering the substrate, the second channel layer and the write bit line in the fifth opening; and forming a write word line filling the fifth opening after forming the third dielectric layer.

[0025] According to another aspect of this disclosure, an electronic device is provided, comprising: a semiconductor device as described above, or a semiconductor device formed according to a method for manufacturing a semiconductor device as described above.

[0026] In the aforementioned semiconductor device, the semiconductor device includes: a substrate and a plurality of memory cells. Each memory cell includes: a first isolation layer perpendicular to the substrate, an electrode line, a write word line, and a first dielectric layer; a gate surrounding the sidewall of the first isolation layer; a second dielectric layer located on the side of the gate away from the first isolation layer; a first channel layer located on the side of the second dielectric layer away from the gate, the first channel layer being made of a single-crystal semiconductor material; a first electrode and a second electrode separated by the first dielectric layer, wherein the first electrode and the second electrode are respectively in contact with the first channel layer, and the first electrode is in contact with the electrode line; a third dielectric layer surrounding the sidewall of the write word line; and a second channel layer located on the side of the third dielectric layer away from the write word line, the portion of the second channel layer near the gate being in contact with the gate. Because the first channel layer uses a single-crystal semiconductor material, the accuracy of data storage can be improved.

[0027] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0028] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0029] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0030] Figure 1A This is a schematic diagram illustrating the circuit structure of a memory cell according to some embodiments of the present disclosure;

[0031] Figure 1B This is a probability distribution diagram of stored data of a semiconductor device according to some embodiments of the present disclosure with respect to a threshold voltage;

[0032] Figure 2 This is a schematic diagram illustrating the circuit structure of a semiconductor device according to some embodiments of the present disclosure;

[0033] Figure 3A This is a schematic top view of a semiconductor device according to some embodiments of the present disclosure;

[0034] Figure 3B This schematically illustrates a semiconductor device according to some embodiments of the present disclosure along... Figure 3A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0035] Figure 3C This schematically illustrates a semiconductor device according to some embodiments of the present disclosure along... Figure 3A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0036] Figure 3D This schematically illustrates a semiconductor device according to some embodiments of the present disclosure along... Figure 3A A cross-sectional view of the structure intercepted by line C-C' in the diagram;

[0037] Figure 3E This schematically illustrates a semiconductor device according to some embodiments of the present disclosure along... Figure 3A A cross-sectional view of the structure intercepted by line D-D' in the diagram;

[0038] Figure 4 This is a schematic diagram illustrating the circuit structure of a memory cell according to other embodiments of the present disclosure;

[0039] Figure 5A This is a schematic top view of a semiconductor device according to other embodiments of the present disclosure;

[0040] Figure 5B This schematically illustrates a semiconductor device according to other embodiments of the present disclosure along... Figure 5A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0041] Figure 5C This schematically illustrates a semiconductor device according to other embodiments of the present disclosure along... Figure 5A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0042] Figure 5D This schematically illustrates a semiconductor device according to other embodiments of the present disclosure along... Figure 5A A cross-sectional view of the structure intercepted by line C-C' in the diagram;

[0043] Figure 5E This schematically illustrates a semiconductor device according to other embodiments of the present disclosure along... Figure 5A A cross-sectional view of the structure intercepted by line D-D' in the diagram;

[0044] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0045] Figure 7A This is a top view schematically illustrating the structure of a stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0046] Figure 7B This schematically illustrates the structure along a stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 7A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0047] Figure 8A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0048] Figure 8B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 8A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0049] Figure 9A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0050] Figure 9B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 9A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0051] Figure 10A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0052] Figure 10B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 10A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0053] Figure 11A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0054] Figure 11B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 11A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0055] Figure 12A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0056] Figure 12B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 12A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0057] Figure 13A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0058] Figure 13B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 13A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0059] Figure 14A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0060] Figure 14B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 14A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0061] Figure 15A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0062] Figure 15BThis schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 15A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0063] Figure 16A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0064] Figure 16B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 16A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0065] Figure 17A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0066] Figure 17B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 17A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0067] Figure 17C This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 17A A cross-sectional view of the structure intercepted by line C-C' in the diagram;

[0068] Figure 18A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0069] Figure 18B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 18A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0070] Figure 18C This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 18A A cross-sectional view of the structure intercepted by line C-C' in the diagram;

[0071] Figure 19A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0072] Figure 19BThis schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 19A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0073] Figure 20A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0074] Figure 20B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 20A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0075] Figure 21A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0076] Figure 21B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 21A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0077] Figure 22A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0078] Figure 22B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 22A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0079] Figure 23A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0080] Figure 23B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 23A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0081] Figure 24A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0082] Figure 24B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 24AA cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0083] Figure 25A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0084] Figure 25B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 25A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0085] Figure 25C This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 25A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0086] Figure 26A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0087] Figure 26B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 26A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0088] Figure 26C This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 26A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0089] Figure 27A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0090] Figure 27B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 27A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0091] Figure 27C This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 27A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0092] Figure 28A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0093] Figure 28B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 28A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0094] Figure 28C This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 28A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0095] Figure 29A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0096] Figure 29B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 29A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0097] Figure 29C This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 29A A cross-sectional view of the structure intercepted by line B-B' in the diagram;

[0098] Figure 30A This is a top view schematically illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0099] Figure 30B This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 30A A cross-sectional view of the structure intercepted by line A-A' in the diagram;

[0100] Figure 30C This schematically illustrates the structure along another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Figure 30A The cross-sectional view of the structure intercepted by line B-B' in the diagram.

[0101] It should be understood that the dimensions of the various parts shown in the accompanying drawings are not drawn to actual scale. Furthermore, the same or similar reference numerals denote the same or similar components. Detailed Implementation

[0102] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0103] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "contains" mean that the element preceding the word encompasses the element listed after it, and do not exclude the possibility of encompassing other elements as well. Terms such as "above," "below," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, this relative positional relationship may also change accordingly.

[0104] In this disclosure, when a specific device is described as being located between a first device and a second device, an intermediary device may or may not be present between the specific device and the first or second device. When a specific device is described as being connected to other devices, the specific device may be directly connected to the other devices without an intermediary device, or it may be not directly connected to the other devices but have an intermediary device.

[0105] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0106] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0107] One type of memory cell structure in related technologies is a 2T0C (2 transistors and 0 capacitors) memory cell structure.

[0108] Figure 1A This is a schematic diagram illustrating the circuit structure of a memory cell according to some embodiments of the present disclosure.

[0109] like Figure 1AAs shown, the memory cell includes a first transistor T1 and a second transistor T2. For example, the first transistor T1 can be a dual-gate transistor or a single-gate transistor. The first transistor T1 is electrically connected to the read word line RWL and the read bit line RBL, and the second transistor T2 is electrically connected to the first transistor T1 and is also electrically connected to the write word line WWL and the write bit line WBL.

[0110] For example, such as Figure 1A As shown, the first transistor T1 is a dual-gate transistor. In this case, as... Figure 1A As shown, in the memory cell, the first gate G1 of the first transistor T1 is electrically connected to the fourth electrode 134 of the second transistor T2. The second gate G2 of the first transistor T1 is electrically connected to the read word line RWL. The first electrode 131 of the first transistor T1 is electrically connected to the common electrode. The second electrode 132 of the first transistor T1 is electrically connected to the read bit line RBL. The third gate G3 of the second transistor T2 is electrically connected to the write word line WWL. The third electrode 133 of the second transistor T2 is electrically connected to the write bit line WBL.

[0111] When the first transistor T1 is a dual-gate transistor, the principle of writing and reading data in the memory cell includes: When writing data, the write word line WWL receives a first level (e.g., a high level), the second transistor T2 is turned on, and the data is written to the memory node SN through the write bit line WBL; when reading data, the read word line RWL receives a first level (e.g., a high level), and the two gates G1 and G2 of the first transistor T1 may be turned on under the combined effect of the stored data in the memory node SN and the first level. After a voltage is applied to the read bit line RBL, current will be output from the first transistor. If the stored data in the memory node SN is "0" (e.g., a low level (e.g., 0V)), the output current may be relatively small (e.g., the current is 0); if the stored data in the memory node SN is "1" (e.g., a high level), the output current may be relatively large. Therefore, the data stored at point SN can be determined based on the magnitude of the current output by the first transistor.

[0112] The above explanation uses a 1-bit data unit storing either "0" or "1" as an example. Those skilled in the art will understand that the storage unit can store other bits of data, such as 2 bits, for example, 11, 10, 01, 00. Different stored data can be represented by storing different voltage values ​​according to the storage node SN in the storage unit.

[0113] Figure 1B This is a probability distribution diagram of stored data of a semiconductor device according to some embodiments of the present disclosure with respect to a threshold voltage. Figure 1B A schematic diagram is shown showing a storage unit storing four types of data.

[0114] Because when reading data from the memory cell, the current output by the first transistor (i.e., the read current) I R With (V) SN -V th ) correlated (e.g., positively correlated), therefore, the current I is read R With (V) DATA -V th ) related (e.g., positively correlated). Here, V SN The voltage value of the storage node, that is, the voltage value of the stored data, V. DATA V th This is the threshold voltage of the first transistor. The Vt of the first transistor in multiple memory cells... th Differences in these factors can affect the accuracy of data reading.

[0115] like Figure 1B As shown, Figure 1B ΔV is shown th and ΔV bit , where ΔV th ΔV is the difference between the minimum threshold voltage and the maximum threshold voltage of the first transistor in all memory cells of the memory. bit ΔV is the minimum difference in voltage values ​​between adjacent stored data in storage node SN. For example, if the stored data 11,10,01,00 corresponds to stored voltages of 1V, 0.5V, 0.3V, and 0V, then ΔV is the minimum difference in voltage values ​​between adjacent stored data. bit The voltage is 0.5V - 0.3V = 0.2V.

[0116] If we want to ensure the accuracy of the stored data as much as possible, then we should try to make ΔV th Less than ΔV bit The inventors of this disclosure have discovered that in related technologies, the channel layer of the first transistor is made of an amorphous semiconductor material, which leads to ΔV th The large size of the transistor is detrimental to the accuracy of data storage. Therefore, embodiments of this disclosure provide a semiconductor device in which the channel layer of the first transistor in the memory cell of the semiconductor device is made of a single-crystal semiconductor material, which can improve the accuracy of data storage.

[0117] Based on this, embodiments of the present disclosure provide a semiconductor device to improve the accuracy of data storage.

[0118] Figure 2 This is a schematic diagram illustrating the circuit structure of a semiconductor device according to some embodiments of the present disclosure. The following is in conjunction with... Figure 1A and Figure 2 A semiconductor device according to some embodiments of the present disclosure is described in detail. For example, the semiconductor device is a three-dimensional memory device.

[0119] like Figure 1A and Figure 2 As shown, the semiconductor device includes multiple memory cells arranged in an array. For example, the array is a three-dimensional array. Figure 2 The diagram shows multiple read word lines (RWL), multiple read bit lines (RBL), multiple write word lines (WWL), and multiple write bit lines (WBL). For example, Figure 2 The diagram shows multiple read word lines RWL11 and RWL12, multiple read bit lines RBL10, RBL11 and RBL12, multiple write word lines WWL11 and WWL12, and multiple write bit lines WBL10, WBL11 and WBL12.

[0120] like Figure 1A As shown, each memory cell includes a first transistor (which may be referred to as a read transistor) T1 and a second transistor (which may be referred to as a write transistor) T2. The first transistor T1 is electrically connected to one of the plurality of read word lines and one of the plurality of read bit lines. The first transistor includes a first channel layer, the material of which includes a single-crystal semiconductor material. The second transistor T2 is electrically connected to the first transistor T1 and is also electrically connected to one of the plurality of write word lines and one of the plurality of write bit lines.

[0121] For example, single-crystal semiconductor materials include single-crystal silicon materials. Of course, those skilled in the art will understand that single-crystal semiconductor materials can also be other types of single-crystal semiconductor materials. The scope of this disclosure is not limited thereto.

[0122] It should be noted that the “channel layer” described in this disclosure (such as the first channel layer described above and / or the second channel layer described later) refers to a structural layer used to form a channel, including but not limited to: a structural layer that does not currently have a channel but can form a channel during subsequent device operation, or a structural layer that currently has a channel.

[0123] In the aforementioned semiconductor device, the first transistor serves as the read transistor. Since the channel layer of the first transistor is made of a single-crystal semiconductor material, the threshold voltage difference ΔV between the first transistors of each memory cell in the semiconductor device can be reduced. th It is relatively small, therefore, the accuracy of data storage can be improved.

[0124] In addition, the channel layer of the first transistor is made of single-crystal semiconductor material, which can improve the mobility of charge carriers and thus improve the read / write speed (or operation speed) of the semiconductor device.

[0125] Figure 3A This is a schematic top view of a semiconductor device according to some embodiments of the present disclosure. Figure 3B This schematically illustrates a semiconductor device according to some embodiments of the present disclosure along... Figure 3A A cross-sectional view of the structure intercepted by line A-A' in the diagram. Figure 3C This schematically illustrates a semiconductor device according to some embodiments of the present disclosure along... Figure 3A The cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 3D This schematically illustrates a semiconductor device according to some embodiments of the present disclosure along... Figure 3A A cross-sectional view of the structure intercepted by line C-C' in the diagram. Figure 3E This schematically illustrates a semiconductor device according to some embodiments of the present disclosure along... Figure 3A The cross-sectional view of the structure intercepted by line D-D' is shown below. Figures 3A to 3E The structure of a semiconductor device according to some embodiments of the present disclosure is described in detail.

[0126] like Figures 3B to 3E As shown, the semiconductor device includes a substrate 101. For example, substrate 101 includes a semiconductor substrate. For example, the substrate may be a silicon substrate or other types of substrate.

[0127] like Figures 3A to 3E As shown, the semiconductor device also includes a plurality of memory cells 20 arranged in an array on the substrate 101. For example, Figure 3B and Figure 3C Storage cells 21, 22, and 23 are shown in the figure.

[0128] Each memory cell includes: a first isolation layer 121 perpendicular to the substrate 101, an electrode line 110, a write word line WWL, and a first dielectric layer 127.

[0129] For example, the material of the first isolation layer 121 includes insulating materials such as silicon dioxide and / or silicon nitride. This first isolation layer can isolate the gates G1 of different memory cells arranged in a direction perpendicular to the substrate, reducing the possibility of short circuits in the gates G1 of different memory cells.

[0130] For example, Figures 3A to 3E A semiconductor device containing a dual-gate transistor (as the first transistor) is shown, the memory cell of which corresponds to... Figure 1A The circuit structure is shown. In this embodiment, for example, electrode line 110 is a common electrode line. For example, the material of the common electrode line includes silicides and / or metals, etc.

[0131] For example, multiple memory cells are arranged in a direction perpendicular to the substrate, so each memory cell may include a portion of a write word line (WWL) perpendicular to the substrate 101.

[0132] It should be noted that the term "perpendicular to" in this disclosure includes, but is not limited to, absolute perpendicularity, but may have a certain margin of error, just as the description "substantially" is added before "perpendicular to".

[0133] Each memory cell also includes a gate (which may be referred to as the first gate G1) surrounding the sidewall of the first isolation layer 121. Figure 1A , Figures 3A to 3E As shown, the first gate G1 is the first gate of the first transistor T1. The first gate G1 is connected to the fourth electrode 134 of the second transistor T2. The connection between the first gate G1 and the fourth electrode 134 of the second transistor T2 can serve as a storage node SN.

[0134] Each memory cell also includes a second dielectric layer 123 located on the side of the gate G1 away from the first isolation layer 121. For example, the material of the second dielectric layer 123 includes insulating materials such as silicon dioxide and / or silicon nitride.

[0135] Each memory cell further includes a first channel layer 141 located on the side of the second dielectric layer 123 away from the gate G1. The material of the first channel layer 141 includes a single-crystal semiconductor material. For example, the single-crystal semiconductor material includes single-crystal silicon. Of course, those skilled in the art will understand that the single-crystal semiconductor material can also be other types of single-crystal semiconductor materials. The scope of this disclosure is not limited thereto.

[0136] Each memory cell further includes a first electrode 131 and a second electrode 132 separated by a first dielectric layer 127. The first electrode 131 and the second electrode 132 are in contact with a first channel layer 141. The first electrode 131 is in contact with an electrode line 110. At least a portion of the first electrode 131 is located between the first channel layer 141 and the electrode line 110. For example, the first electrode 131 may be either a source or a drain. The second electrode 132 is in contact with both the first channel layer 141 and the read bit line (described later) RBL, and at least a portion of the second electrode 132 is located between the first channel layer 141 and the read bit line RBL. For example, the second electrode 132 may be either a source or a drain. Therefore, the first electrode 131 and the second electrode 132 can serve as the source and drain of a first transistor T1.

[0137] In some embodiments, the doping concentration of the first electrode 131 is greater than the doping concentration of the first channel layer 141, and the doping concentration of the second electrode 132 is greater than the doping concentration of the first channel layer 141. For example, the doping concentration of the first electrode 131 is greater than or equal to 10. 20 atom / cm 3 The doping concentration of the second electrode 132 is greater than or equal to 10. 20 atom / cm 3For example, the doping concentration of the first channel layer is less than or equal to 10. 18 atom / cm 3 Such a doping concentration relationship is beneficial for the transistor's turn-on or turn-off.

[0138] In some embodiments, the doping concentration of the first electrode 131 is equal to the doping concentration of the second electrode 132.

[0139] Each memory cell also includes a third dielectric layer 125 surrounding the sidewalls of the write word line WWL. For example, the material of the third dielectric layer 125 includes insulating materials such as silicon dioxide and / or silicon nitride.

[0140] Each memory cell also includes a second channel layer 143 located on the side of the third dielectric layer 125 away from the write word line WWL. A portion of the second channel layer 143 near the gate G1 is in contact with the gate G1. This second channel layer 143 can serve as the channel layer for the second transistor T2. Figure 3B As shown, the third dielectric layer 125 is located between the third gate G3 and the second channel layer 143.

[0141] In some embodiments, the material of the second channel layer includes a metal oxide, etc. For example, the metal oxide material can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the second transistor T2 is relatively small (leakage current less than or equal to 10). -15 A) This ensures the lowest possible refresh rate for the dynamic memory. It should be noted that the metal oxide material can also be ITO (Indium Tin Oxide), IWO, or ZnO. x InO x In₂O₃, InWO₂, SnO₂, TiO₂ x InSnO x Zn x O y N z Mg x Zn y O z In x Zn y O z In x Ga y Zn z O a Zr x In y Zn z O a Hf x In y Znz O a Sn x In y Zn z O a Al x Sn y In z Zn a O d Si x In y Zn z O a Zn x Sn y O z Al x Zn y Sn z O a Ga x Zn y Sn z O a Zr x Zn y Sn z O a InGaSiO, IGZO (Indium Gallium Zinc Oxide), IGO (Indium Gallium Oxide), IZO (Indium Zinc Oxide), IZO x Materials such as transistors are sufficient as long as the leakage current of the transistor meets the requirements; adjustments can be made based on the actual situation.

[0142] Thus, a semiconductor device according to some embodiments of the present disclosure is provided, comprising: a substrate; and a plurality of memory cells arranged in an array on the substrate, each memory cell comprising: a first isolation layer perpendicular to the substrate, an electrode line, a write word line, and a first dielectric layer; a gate surrounding a sidewall of the first isolation layer; a second dielectric layer located on a side of the gate away from the first isolation layer; a first channel layer located on a side of the second dielectric layer away from the gate, the first channel layer being made of a single-crystal semiconductor material; a first electrode and a second electrode separated by the first dielectric layer, wherein the first electrode and the second electrode are respectively in contact with the first channel layer, and the first electrode is in contact with the electrode line; a third dielectric layer surrounding a sidewall of the write word line; and a second channel layer located on a side of the third dielectric layer away from the write word line, the portion of the second channel layer near the gate contacting the gate. In the above semiconductor device, the first channel layer serves as the channel layer of a first transistor T1, where the first transistor serves as a read transistor. Since the first channel layer is made of a single-crystal semiconductor material, the threshold voltage difference ΔV between the first transistors of each memory cell of the semiconductor device can be made... th It is relatively small, therefore, the accuracy of data storage can be improved.

[0143] In addition, the channel layer of the first transistor is made of single-crystal semiconductor material, which can improve the mobility of charge carriers and thus improve the read / write speed (or operation speed) of the semiconductor device.

[0144] In some embodiments, such as Figures 3A to 3E As shown, the first channel layer (141) includes a first channel portion 1411 and a second channel portion 1412. The first channel portion 1411 is located between the second electrode 132 and the second dielectric layer 123. The second channel portion 1412 is located between the first dielectric layer 127 and the second dielectric layer 123. The second channel portion 1412 is in contact with the first electrode 131.

[0145] like Figures 3A to 3E As shown, each memory cell may further include a read bit line RBL located on the side of the second electrode 132 away from the first channel layer 141.

[0146] like Figures 3A to 3E As shown, each memory cell may further include a write bit line WBL that is in contact with a portion of the second channel layer 143 on the side away from the gate G1.

[0147] like Figures 3A to 3EAs shown, each memory cell may also include a read word line RWL perpendicular to the substrate 101 and surrounded by a first dielectric layer 127. For example, multiple memory cells are arranged in a direction perpendicular to the substrate, so each memory cell may include a portion of a read word line RWL perpendicular to the substrate 101.

[0148] like Figures 3A to 3E As shown, the semiconductor device also includes multiple isolation patterns 122. For example, the material of the isolation patterns 122 includes insulating materials such as silicon dioxide and / or silicon nitride. For example, as... Figure 3A As shown, the isolation pattern is T-shaped. Each isolation pattern 122 includes a first isolation portion 1221 and a second isolation portion 1222. Both the first isolation portion 1221 and the second isolation portion 1222 are perpendicular to the substrate 101. The first isolation portion 1221 extends along a first direction 811 parallel to the substrate and is located between adjacent memory cells arranged along a second direction 812 parallel to the substrate. The second isolation portion 1222 extends along the second direction 812 and is connected to the first isolation portion 1221. The second isolation portion 1222 is located between the electrode line 110 and the write word line WWL. The second direction intersects the first direction. For example, the second direction is perpendicular to the first direction. The above isolation pattern can conveniently isolate the write word line WWL from the electrode line 110.

[0149] For example, the second isolation portion 1222 is connected to the middle portion of the first isolation portion 1221. It should be noted that the "middle portion" described here includes, but is not limited to, the portion located exactly in the middle of the first isolation portion 1221. Rather, it can have errors, that is, it can also include portions that are off-center, as long as they are not at either end of the first isolation portion 1221.

[0150] like Figure 3A As shown, the second isolation portion 1222 of an isolation pattern is not connected to the first isolation portion of another isolation pattern adjacent in the second direction 812.

[0151] like Figures 3B to 3C As shown, the semiconductor device further includes: multiple alternating stacked insulating layers 252 and doped semiconductor layers 130. The insulating layers 252 are located between adjacent memory cells along a third direction 813 perpendicular to the substrate. For example, the insulating layer 252 is located between one memory cell 21 and another memory cell 22. The insulating layers 252 can isolate portions of the structure of different memory cells. For example, the material of the insulating layer 252 includes insulating materials such as silicon dioxide and / or silicon nitride. The doped semiconductor layer 130 serves as a first electrode 131 and a second electrode 132.

[0152] In some embodiments, the semiconductor layer 130 is a single-crystal semiconductor layer. For example, the semiconductor layer 130 comprises heavily doped single-crystal Si (silicon). For example, the doping concentration of the semiconductor layer is greater than or equal to 10. 20 atom / cm 3 Of course, those skilled in the art will understand that the semiconductor layer can also be a single-crystal semiconductor layer made of other materials, therefore, the scope of this disclosure is not limited thereto.

[0153] like Figure 3B As shown, a portion of the read word line RWL can serve as the second gate G2 of the first transistor T1. In other words, the second gate G2 and the read word line RWL can be integrally formed, which ensures good contact between the second gate G2 and the read word line RWL and facilitates manufacturing.

[0154] like Figure 3D As shown, the first dielectric layer 127 is located between the second gate G2 and the first channel layer 141. In this way, the first dielectric layer 127 can function as a gate dielectric layer.

[0155] like Figure 3A and 3B As shown, the read word line RWL is located between the first electrode 131 and the second electrode 132, and a portion of the first dielectric layer 127 is located between the read word line RWL and the first electrode 131, while another portion of the first dielectric layer 127 is located between the read word line RWL and the second electrode 132. This structural design can improve the memory cell density of the memory device.

[0156] like Figure 1A , Figures 3A to 3E As shown, a portion of the write word line WWL can serve as the gate (which can be called the third gate) G3 of the second transistor T2. In other words, the third gate and the write word line can be integrally formed, which ensures good contact between the third gate and the write word line and facilitates manufacturing.

[0157] like Figures 3A to 3E As shown, a portion of the write bit line WBL can serve as the third electrode 133 of the second transistor T2. The third electrode 133 is in contact with the second channel layer 143. For example, a portion of the write bit line in contact with the second channel layer can be used as the third electrode. For example, the third electrode 133 can be either the source or the drain. Therefore, the third electrode 133 and the write bit line WBL can be integrally formed, which ensures good contact between the third electrode and the write bit line and facilitates manufacturing.

[0158] like Figure 1A As shown, the first gate G1 of the first transistor T1 is electrically connected to the fourth electrode 134 of the second transistor T2. Figures 3A to 3EAs shown, a portion of the first gate G1 serves as the fourth electrode 134, or in other words, the fourth electrode 134 is integrally formed with the first gate G1. The fourth electrode 134 is in contact with the second channel layer 143. Alternatively, the first gate G1 can be in contact with the second channel layer 143. For example, the fourth electrode 134 can be either the source or the drain.

[0159] like Figures 3A to 3C As shown, the semiconductor device also includes a second isolation layer 124. The second isolation layer 124 is perpendicular to the substrate 101. Figure 3A As shown, the second isolation layer 124 is located between adjacent memory cells arranged in the first direction 811 and is adjacent to the write bit line WBL. For example, the material of the second isolation layer includes insulating materials such as silicon dioxide and / or silicon nitride. The second isolation layer can isolate adjacent memory cells arranged in the first direction, preventing the adjacent memory cells from short-circuiting.

[0160] For example, such as Figures 3A to 3C As shown, adjacent memory cells arranged in the first direction are symmetrically distributed about the second isolation layer 124. This facilitates the arrangement of each memory cell, thereby increasing the memory cell density of the memory device.

[0161] like Figures 3A to 3C As shown, the semiconductor device may further include a third isolation layer 126. The third isolation layer 126 is adjacent to the read bit line RBL. For example, the material of the third isolation layer 126 includes insulating materials such as silicon dioxide and / or silicon nitride. The third isolation layer 126 can isolate different read bit lines, reducing the possibility of short circuits between different read bit lines.

[0162] like Figures 3A to 3E As shown, the semiconductor device may further include a mask layer 251. This mask layer covers the uppermost insulating layer in the multilayer insulating layers 252. Of course, those skilled in the art will understand that the semiconductor device may also exclude the mask layer 251. Therefore, the scope of this disclosure is not limited thereto.

[0163] This concludes the description of the semiconductor device structure when the first transistor T1 is a dual-gate transistor. This structure can improve the accuracy of data storage and the read / write speed. Such a structure is advantageous for providing high-density three-dimensional memory devices (e.g., DRAM (Dynamic Random Access Memory)).

[0164] Figure 4 This is a schematic diagram illustrating the circuit structure of a memory cell according to other embodiments of the present disclosure.

[0165] like Figure 4As shown, in the memory cell, the gate (i.e., the first gate) G1 of the first transistor T1 is electrically connected to the fourth electrode 134 of the second transistor T2. The first electrode 131 of the first transistor T1 is electrically connected to the read word line RWL. The second electrode 132 of the first transistor T1 is electrically connected to the read bit line RBL. The gate (i.e., the third gate) G3 of the second transistor T2 is electrically connected to the write word line WWL. The third electrode 133 of the second transistor T2 is electrically connected to the write bit line WBL.

[0166] The principle of writing and reading data in this memory cell includes: when writing data, the write word line WWL receives a first level (e.g., a high level), the second transistor T2 is turned on, and the data is written to the memory node SN through the write bit line WBL; when reading data, when the read word line RWL is applied with a high level, the magnitude of the current flowing through the first transistor is checked. For example, if the current flowing through the first transistor is relatively large, the data stored in the memory node SN can be considered as data "1", and if the current flowing through the first transistor is relatively small, the data stored in the memory node SN can be considered as data "0".

[0167] Figure 5A This is a schematic top view of a semiconductor device according to other embodiments of the present disclosure. Figure 5B This schematically illustrates a semiconductor device according to other embodiments of the present disclosure along... Figure 5A A cross-sectional view of the structure intercepted by line A-A' in the diagram. Figure 5C This schematically illustrates a semiconductor device according to other embodiments of the present disclosure along... Figure 5A The cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 5D This schematically illustrates a semiconductor device according to other embodiments of the present disclosure along... Figure 5A A cross-sectional view of the structure intercepted by line C-C' in the diagram. Figure 5E This schematically illustrates a semiconductor device according to other embodiments of the present disclosure along... Figure 5A A cross-sectional view of the structure intercepted by line D-D' in the diagram.

[0168] like Figures 5A to 5E As shown, the semiconductor device includes a substrate 101 and a plurality of memory cells arranged in an array on the substrate.

[0169] Each memory cell includes: a first isolation layer 121 perpendicular to the substrate, an electrode line RWL, a write word line WWL, and a first dielectric layer 127. The electrode line RWL is a read word line. Therefore, in semiconductor devices containing single-gate transistors, the electrode line RWL can be referred to as the read word line RWL.

[0170] Each memory cell further includes: a gate G1 surrounding the sidewalls of the first isolation layer 121, a second dielectric layer 123 located on the side of the gate G1 away from the first isolation layer 121, and a first channel layer 141 located on the side of the second dielectric layer 123 away from the gate. The material of the first channel layer includes a single-crystal semiconductor material. The gate G1 serves as the memory node SN. For example, the material of the second dielectric layer 123 includes insulating materials such as silicon dioxide and / or silicon nitride.

[0171] Each memory cell also includes a first electrode 131 and a second electrode 132 separated by a first dielectric layer 127. The first electrode 131 and the second electrode 132 are in contact with the first channel layer 141, and the first electrode 131 is in contact with the electrode line RWL.

[0172] For example, the first electrode 131 is in contact with the first channel layer 141 and the read word line RWL, and at least a portion of the first electrode 131 is located between the first channel layer 141 and the read word line RWL. For example, the first electrode 131 is either a source or a drain. For example, the second electrode 132 is in contact with the first channel layer 141 and the read bit line RBL, and is located between the first channel layer and the read bit line. For example, the second electrode 132 is either a source or a drain.

[0173] In some embodiments, the doping concentration of the first electrode 131 is greater than the doping concentration of the first channel layer 141, and the doping concentration of the second electrode 132 is greater than the doping concentration of the first channel layer 141. For example, the doping concentration of the first electrode 131 is greater than or equal to 10. 20 atom / cm 3 The doping concentration of the second electrode 132 is greater than or equal to 10. 20 atom / cm 3 For example, the doping concentration of the first channel layer is less than or equal to 10. 18 atom / cm 3 Such a doping concentration relationship is beneficial for the transistor's turn-on or turn-off.

[0174] In some embodiments, the doping concentration of the first electrode 131 is equal to the doping concentration of the second electrode 132.

[0175] Each memory cell also includes a third dielectric layer 125 surrounding the sidewall of the write word line WWL, and a second channel layer 143 located on the side of the third dielectric layer away from the write word line. The portion of the second channel layer 143 near the gate is in contact with the gate G1.

[0176] Thus, a semiconductor device according to further embodiments of the present disclosure is provided. This semiconductor device includes a single-gate transistor (as a read transistor). In this semiconductor device, a first channel layer serves as the channel layer of a first transistor T1, which here functions as a read transistor. Since the first channel layer is made of a single-crystal semiconductor material, the threshold voltage difference ΔV between the first transistors of each memory cell in the semiconductor device can be made... th It is relatively small, therefore, the accuracy of data storage can be improved.

[0177] In addition, the channel layer of the first transistor is made of single-crystal semiconductor material, which can improve the mobility of charge carriers and thus improve the read / write speed (or operation speed) of the semiconductor device.

[0178] Figures 5A to 5E Other structures in the semiconductor device shown (e.g., the structure of the second transistor) and Figures 3A to 3E Other structures in the semiconductor device shown (such as the structure of the second transistor) are the same or similar, and will not be described further here. Therefore, Figures 5A to 5E Other structures in the semiconductor device shown can be referred to in the preceding description.

[0179] In some embodiments, such as Figures 5A to 5E As shown, the semiconductor device also includes a plurality of isolation patterns 122. Each isolation pattern includes a first isolation portion 1221 and a second isolation portion 1222. Figures 3A to 3E Compared to the isolation pattern in the semiconductor device shown, such as Figures 5A to 5E The difference in the isolation patterns in the semiconductor devices shown is that, as Figures 5A to 5E The second isolation section 1222 shown is located between the read word line RWL and the write word line WWL, while as Figures 3A to 3E The second isolation section 1222 shown is located between the common electrode line 110 and the write word line WWL.

[0180] In addition, such as Figures 5A to 5E As shown, the first dielectric layer 127 is located between the first electrode 131 and the second electrode 132. Furthermore, the first dielectric layer 127 is located between the first isolation portion 1221 of the isolation pattern and the first channel layer 141. For example, the material of the first dielectric layer 127 includes insulating materials such as silicon dioxide and / or silicon nitride. This first dielectric layer 127 can isolate the first electrode and the second electrode of the first transistor, preventing a short circuit between the first electrode and the second electrode.

[0181] In some embodiments, such as Figures 5A to 5E As shown, the semiconductor device also includes a second isolation layer 124, a third isolation layer 126, an insulating layer 252, and a mask layer 251. These structures are similar to... Figures 3A to 3EThe second isolation layer 124, the third isolation layer 126, the insulating layer 252, and the mask layer 251 in the semiconductor device shown are the same or similar, and will not be described in detail here. Therefore, Figures 5A to 5E The structures of the semiconductor devices shown can be referred to in the preceding description.

[0182] This concludes the description of semiconductor devices according to further embodiments of the present disclosure. This structure can improve the accuracy and read / write speed of data storage. Such a structure is advantageous for providing high-density three-dimensional memory devices (e.g., DRAM).

[0183] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. For example... Figure 6 As shown, the manufacturing method includes steps S610 to S680.

[0184] In step S610, a plurality of stacked structural layers are formed on the substrate, each structural layer including a doped semiconductor layer and an insulating layer on the semiconductor layer.

[0185] In step S620, a first channel layer is formed among multiple structural layers, and the material of the first channel layer includes a single-crystal semiconductor material.

[0186] In step S630, a second dielectric layer covering the first channel layer is formed.

[0187] In step S640, a gate is formed on the side of the second dielectric layer away from the first channel layer.

[0188] In step S650, a first isolation layer perpendicular to the substrate is formed in a plurality of structural layers, the first isolation layer being surrounded by a gate.

[0189] In step S660, a first dielectric layer and an electrode line perpendicular to the substrate are formed in a plurality of structural layers, wherein a semiconductor layer isolated by the first dielectric layer is used as a first electrode and a second electrode, wherein the first electrode and the second electrode are respectively in contact with the first channel layer, and the first electrode is in contact with the electrode line.

[0190] In step S670, a second channel layer is formed in the plurality of structural layers, and a portion of the second channel layer near the gate side contacts the gate.

[0191] In step S680, a write word line perpendicular to the substrate and a third dielectric layer surrounding the sidewalls of the write word line are formed in the plurality of structural layers.

[0192] Thus, a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is provided. This manufacturing method allows for the convenient formation of a first channel layer using single-crystal semiconductor material during the semiconductor device manufacturing process, thereby improving the accuracy of data storage. Furthermore, it can also improve the read / write speed of the semiconductor device.

[0193] Figures 7A to 30C This is a schematic diagram illustrating the structure of several stages in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. The following is in conjunction with... Figures 7A to 30C as well as Figures 3A to 3E The manufacturing process of a semiconductor device according to some embodiments of the present disclosure is described in detail.

[0194] First, multiple stacked structural layers are formed on a substrate, each structural layer including a doped semiconductor layer and an insulating layer on the semiconductor layer. The process of forming multiple structural layers is described below with reference to the accompanying drawings.

[0195] For example, such as Figure 7A and Figure 7B As shown, multiple initial layers are stacked on a substrate 101, each initial layer including a doped semiconductor layer 130 and a sacrificial layer 420 on the semiconductor layer 130. Here, the semiconductor layer 130 and the sacrificial layer 420 are stacked alternately. This facilitates the subsequent formation of a channel layer of single-crystal semiconductor material.

[0196] In some embodiments, the semiconductor layer 130 is a single-crystal semiconductor layer. For example, the semiconductor layer 130 comprises heavily doped single-crystal Si (silicon). For example, the doping concentration of the semiconductor layer is greater than or equal to 10. 20 atom / cm 3 Of course, those skilled in the art will understand that the semiconductor layer can also be a single-crystal semiconductor layer made of other materials, therefore, the scope of this disclosure is not limited thereto.

[0197] In some embodiments, the sacrificial layer 420 may include SiGe (germanium silicon) or the like. Of course, those skilled in the art will understand that the sacrificial layer may also be made of other materials, and therefore the scope of this disclosure is not limited thereto.

[0198] For example, multiple stacked structural layers can be formed on the substrate 101 by epitaxial processes or deposition processes. For example, a doped semiconductor layer 130 can be formed on the substrate by an epitaxial process, and then a sacrificial layer 420 can be formed on the semiconductor layer 130 by an epitaxial process; then the next semiconductor layer 130 can be formed on the sacrificial layer 420 by an epitaxial process, and then the next sacrificial layer 420 can be formed on the next semiconductor layer 130 by an epitaxial process, and so on.

[0199] For the semiconductor layer, doping can be performed during the epitaxial growth process. This reduces damage to the semiconductor layer caused by doping processes in related technologies, thus facilitating the subsequent epitaxial growth of the first channel layer. Furthermore, the doped semiconductor layer can be used to form the first and second electrodes of the first transistor, eliminating the need for separate doping processes on the transistor's source / drain electrodes. This reduces process complexity and simplifies the fabrication process.

[0200] In some embodiments, a mask layer 251 may also be formed on the plurality of stacked initial layers.

[0201] Next, optionally, such as Figure 8A and Figure 8B As shown, multiple isolation patterns 122 are formed in the multiple initial layers before patterning is performed on the multiple initial layers. For example, as Figure 8A As shown, the isolation pattern is T-shaped. Each isolation pattern includes a first isolation portion 1221 and a second isolation portion 1222. Both the first isolation portion 1221 and the second isolation portion 1222 are perpendicular to the substrate 101. The first isolation portion 1221 extends along a first direction 811 parallel to the substrate 101, and the second isolation portion 1222 extends along a second direction 812 parallel to the substrate 101 and is connected to the first isolation portion 1221. The second direction 812 intersects the first direction 811. For example, the second direction is perpendicular to the first direction.

[0202] For example, an opening for the isolation pattern can be formed by patterning, and then an insulating material layer filling the opening can be formed in the opening by a deposition process, thereby forming the isolation pattern 122.

[0203] Next, as Figure 9A and Figure 9B As shown, patterning is performed on multiple initial layers to form a first opening 501. The first opening 501 exposes the substrate 101. For example, the first opening may be adjacent to a first isolation portion of an isolation pattern 122. The first opening 501 is formed between adjacent isolation patterns in the second direction 812.

[0204] Next, as Figure 10A and Figure 10B As shown, the sacrificial layer 420 is removed via the first opening 501 to form the first cavity 601. For example, SiGe (as the sacrificial layer 420) is selectively removed by an etching process to form the first cavity 601.

[0205] Next, an insulating layer 252 is formed in the first cavity. For example, the material of the insulating layer 252 includes silicon dioxide and / or silicon nitride, etc. For example, it can be combined with... Figures 10A to 11B To describe this step. For example, as Figure 10A and Figure 10B As shown, an insulating layer 252 is formed in the first opening 501 and the first cavity 601 by a deposition process, and the insulating layer 252 fills the first opening 501 and the first cavity 601; then, as... Figure 11A and Figure 11B As shown, for example, by an anisotropic etching process, a portion of the insulating layer 252 in the first opening 501 is removed in a direction perpendicular to the substrate, thereby exposing the first opening 501. In this way, the insulating layer 252 is formed in the first cavity 601.

[0206] In this way, multiple stacked structural layers are formed on the substrate.

[0207] In the above embodiment, multiple initial layers are first formed, then a first opening is formed by a patterning process, and then a sacrificial layer is removed through the first opening to form a first cavity. Next, an insulating layer 252 is formed in the first cavity.

[0208] In other embodiments, multiple stacked structural layers may be formed on substrate 101 first, each structural layer including a doped semiconductor layer 130 and an insulating layer 252 on the semiconductor layer, and then the multiple structural layers may be patterned to form a first opening 501 exposing the substrate and the semiconductor layer.

[0209] Next, the first channel layer is formed among multiple structural layers. The process of forming the first communication layer is described below.

[0210] For example, the plurality of structural layers are patterned to form a first opening 501 that exposes the substrate and semiconductor layer, thereby forming Figure 11A and Figure 11B The structure shown. Alternatively, the process of forming multiple stacked structural layers on a substrate, as described earlier, can also be used (see...). Figures 7A to 11B ), thus forming Figure 11A and Figure 11B The structure shown.

[0211] Next, as Figure 12A and Figure 12B As shown, side etching is performed on the semiconductor layer 130 based on the first opening 501, so that the semiconductor layer 130 retracts relative to the insulating layer 252, thereby forming the first notch 801.

[0212] Next, a first channel layer 141 is formed in the first notch 801 and on the side surface of the semiconductor layer 130. The doping concentration of the first channel layer is less than the doping concentration of the semiconductor layer. For example, the doping concentration of the first channel layer is less than or equal to 10. 18 atom / cm 3 .

[0213] In some embodiments, a first channel layer is formed on the side surface of the semiconductor layer 130 by an epitaxial process. This facilitates the formation of the first channel layer of a single-crystal semiconductor material.

[0214] In some embodiments, it can be combined Figures 13A to 14B The process of forming a first channel layer in a first notch and on the side surface of a semiconductor layer is described. For example, as... Figure 13A and Figure 13B As shown, a first channel material layer 141 can be formed in the first opening 501 and the first notch 801 by an epitaxial process. For example, the first channel material layer can be undoped or lightly doped Si. Next, as... Figure 14A and Figure 14B As shown, a portion of the first channel material layer 141 in the first opening 501 is vertically removed by an etching process, and then a portion of the first channel material layer 141 in the first recess 801 is removed by a side etching process, while retaining another portion of the first channel material layer 141 in the first recess 801, thereby forming the first channel layer 141.

[0215] In the above-described manufacturing process of the first channel layer, a structural layer including a semiconductor layer and a sacrificial layer is formed. In a subsequent process, a first notch is formed, and the first channel layer is formed in the first notch and on the side of the semiconductor layer. This facilitates the formation of the first channel layer. Moreover, compared with the manufacturing methods in related technologies, the above-described manufacturing method of this disclosure embodiment can use a doped semiconductor layer to fabricate the first electrode and the second electrode of the first transistor, without the need to perform source / drain doping separately, thereby simplifying the process difficulty of semiconductor devices.

[0216] Next, as Figure 15A and Figure 15B As shown, for example, a second dielectric layer 123 covering the first channel layer 141 is formed by a deposition process.

[0217] Next, a gate G1, i.e., a first gate G1, is formed on the side of the second dielectric layer 123 away from the first channel layer 141. This first gate G1 fills the first notch 801, which facilitates the differentiation of the first gates of different transistors and also facilitates the control of the semiconductor device to be formed.

[0218] For example, such as Figure 15A and Figure 15B As shown, a first gate material layer 621 filling the first opening 501 and the first recess 801 is formed by a deposition process. Next, as... Figure 16A and Figure 16B As shown, for example, a portion of the first gate material layer 621 in the first opening 501 is removed by an etching process, thereby isolating the different first gates arranged in a direction perpendicular to the substrate.

[0219] Next, a first isolation layer 121 perpendicular to the substrate is formed in a plurality of structural layers, the first isolation layer 121 being surrounded by the gate G1. For example, as Figure 16A and Figure 16B As shown, a first isolation layer 121 is formed to fill the first opening 501 through a deposition process. Thus, the formed first isolation layer 121 is surrounded by the gate G1.

[0220] Next, a first dielectric layer and electrode lines perpendicular to the substrate are formed in multiple structural layers.

[0221] For example, such as Figures 17A to 17C As shown, patterning is performed on the plurality of structural layers to form a second opening 502, which exposes the substrate 101 and the first channel layer 141. Additionally, the second opening also exposes an isolation pattern 122 (e.g., a first isolation portion 1221 of the isolation pattern 122). The second opening 502 is located between the first opening 501 and the isolation pattern 122. For example, the second opening 502 is located between the first opening 501 and the first isolation portion 1221 of the isolation pattern 122. For example, the second opening 502 can be formed by photolithography and etching processes, followed by a side etching process on the semiconductor layer to expose the first channel layer 141, as shown. Figure 17C As shown. Figure 17C As shown, the first channel layer 141 retracts relative to the insulating layer 252, thereby forming a notch (which can be called the fourth notch).

[0222] Next, as Figures 18A to 18C As shown, for example, a first dielectric layer 127 covering the bottom and sides of the second opening is formed by a deposition process. This forms the aforementioned first dielectric layer 127.

[0223] Next, as Figures 18A to 18C As shown, a read word line RWL is formed in a second opening 502 where a first dielectric layer 127 is formed. For example, the read word line RWL is formed in the second opening 502 and on the first dielectric layer 127 by a deposition process. For example, a portion of this read word line RWL serves as a second gate G2. This simplifies the process.

[0224] In some embodiments, such as Figures 18A to 18C As shown, a portion of the first dielectric layer 127 and at least a portion of the second gate G2 are recessed into the aforementioned fourth notch.

[0225] Next, combined Figures 19A to 20B Describe the process of forming electrode lines.

[0226] For example, such as Figure 19A and Figure 19BAs shown, patterning is performed on the plurality of structural layers to form a third opening 503. The third opening 503 exposes the substrate 101, the semiconductor layer 130, and the insulating layer 252. The third opening 503 is located between the read word line RWL and the isolation pattern 122. For example, the third opening 503 is located between the read word line RWL and the second isolation portion 1222 of the isolation pattern 122.

[0227] Next, as Figure 20A and Figure 20B As shown, for example, an electrode line 110 perpendicular to the substrate 101 is formed in the third opening 503 by a deposition process. For example, this electrode line 110 is a common electrode line. The electrode line 110 is in contact with the semiconductor layer 130. The portion of the semiconductor layer 130 between the electrode line 110 and the first dielectric layer 127 serves as the first electrode 131 of the first transistor. This can increase the memory cell density of the semiconductor device to be formed.

[0228] Next, as Figure 21A and Figure 21B As shown, the plurality of structural layers are patterned to form a fourth opening 504. The fourth opening 504 exposes the substrate 101, the insulating layer 252, and the semiconductor layer 130. The fourth opening 504 is located on the side of the read word line RWL away from the electrode line 110. That is, the read word line RWL is located between the fourth opening 504 and the electrode line 110. For example, the fourth opening is a groove.

[0229] Next, as Figure 22A and Figure 22B As shown, side etching is performed on the semiconductor layer 130 through the fourth opening 504 so that the semiconductor layer 130 retracts relative to the insulating layer 252, thereby forming the second notch 802.

[0230] Next, a read bit line RBL is formed in the second notch 802. The portion of the semiconductor layer 130 between the read bit line RBL and the first dielectric layer 127 serves as the second electrode 132. This facilitates the formation of the read bit line, and because different read bit lines are formed in different second notches, short circuits between different read bit lines can be prevented.

[0231] For example, a silicide can be formed in the portion of the semiconductor layer 130 that contacts the read bit line RBL, thereby reducing the contact resistance between the second electrode and the read bit line.

[0232] For example, such as Figure 22A and Figure 22B As shown, a read bit line material layer 541 is formed in the fourth opening and the second notch using a deposition process. Then, as... Figure 23A and Figure 23BAs shown, for example, the portion of the read bit line material layer 541 in the fourth opening is vertically removed by an etching process, leaving the portion of the read bit line material layer 541 in the second recess as the read bit line RBL. Here, as... Figure 23B As shown, the read bit lines of each memory cell, arranged in a direction perpendicular to the substrate, are separated. Next, as... Figure 23A and Figure 23B As shown, for example, a third isolation layer 126 that fills the fourth opening is formed by a deposition process.

[0233] Next, a second channel layer is formed in the plurality of structural layers, and a portion of the second channel layer 143 near the gate G1 contacts the gate G1. (The following is a continuation of the previous sentence.) Figures 24A to 26C Describe the process by which the second channel layer is formed.

[0234] For example, such as Figure 24A and Figure 24B As shown, the plurality of structural layers are patterned to form a fifth opening 505 and a sixth opening 506. The fifth opening 505 and the sixth opening 506 expose the substrate 101, respectively. The fifth opening 505 is located on the side of the isolation pattern 122 (e.g., the second isolation portion 1222 of the isolation pattern 122) away from the read bit line RBL, and the sixth opening 506 is located on the side of the fifth opening 505 away from the read bit line RBL.

[0235] Next, as Figures 25A to 25C As shown, for example, a portion of the semiconductor layer 130, a portion of the first channel layer 141, and a portion of the second dielectric layer 123 are removed via a side etching process through a fifth opening 505 and a sixth opening 506 to form a second cavity 602.

[0236] Next, as Figures 26A to 26C As shown, a second channel layer 143 is formed on the surface inside the second cavity 602 through the fifth opening 505 and the sixth opening 506.

[0237] Thus, a second channel layer 143 is formed in the plurality of structural layers.

[0238] In addition, such as Figures 26A to 26C As shown, after the second channel layer 143 is formed, a first pseudo-dielectric layer 701 is also formed to fill the fifth opening, the sixth opening, and the second cavity. For example, the material of the first pseudo-dielectric layer 701 includes insulating materials such as silicon dioxide and / or silicon nitride.

[0239] Next, as Figures 27A to 27C As shown, the second trench layer 143 and the first pseudo dielectric layer 701 are etched to expose the fifth opening 505 and the sixth opening 506.

[0240] Next, as Figures 27A to 27CAs shown, a second dummy dielectric layer 703 is formed in the exposed fifth and sixth openings. For example, the material of the second dummy dielectric layer 703 includes insulating materials such as silicon dioxide and / or silicon nitride.

[0241] Next, as Figures 28A to 28C As shown, the second pseudo dielectric layer 703 in the sixth opening 506 is removed, and the remaining first pseudo dielectric layer 701 is side-etched through the sixth opening 506 so that the first pseudo dielectric layer retracts relative to the second channel layer, thereby forming the third notch 803.

[0242] Next, a write bit line is formed that contacts the second channel layer 143. For example, a write bit line WBL is formed in the third notch 803. A portion of the write bit line WBL that contacts the second channel layer 143 serves as the third electrode 133.

[0243] Because the write bit line is formed in the third notch, short circuits between different bit lines can be prevented. Furthermore, a portion of the write bit line WBL that contacts the second channel layer easily forms silicide, which acts as the third electrode and reduces contact resistance.

[0244] The following is combined Figures 29A to 30C Describe the process of forming the write bit line.

[0245] For example, such as Figures 29A to 29C As shown, a write bit line material layer 720 is formed in the sixth opening 506 and the third notch 803 using a deposition process. Next, as... Figures 30A to 30C As shown, for example, the portion of the write bit line material layer 720 in the sixth opening 506 is removed by an etching process to expose the sixth opening, while the portion of the bit line material layer 720 in the third notch 803 is retained. This separates the write bit lines of the individual memory cells perpendicular to the substrate. Next, as... Figures 30A to 30C As shown, for example, a second isolation layer 124 is formed in the exposed sixth opening 506 by a deposition process.

[0246] Next, as Figures 3A to 3E As shown, the second pseudo dielectric layer 703 and the first pseudo dielectric layer 701 in the fifth opening 505 are removed to expose the fifth opening 505.

[0247] Next, a write word line WWL perpendicular to the substrate and a third dielectric layer 125 surrounding the sidewalls of the write word line WWL are formed in the plurality of structural layers. For example, as Figures 3A to 3EAs shown, a third dielectric layer 125 covering the substrate 101, the second channel layer 143, and the write bit line WBL is formed in the fifth opening 505 by a deposition process. After forming the third dielectric layer 125, a write word line WWL filling the fifth opening 505 is formed, for example, by a deposition process. A portion of the write word line WWL can serve as the third gate G3.

[0248] Thus, a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is provided. The first transistor in the semiconductor device formed by this manufacturing method is a dual-gate transistor. The semiconductor device manufactured by this method can improve the accuracy of data storage and also increase the read / write speed of the semiconductor device. Furthermore, compared with manufacturing methods in related technologies, in the above-described manufacturing method of the embodiments of the present disclosure, the doped semiconductor layer can be used to form the first and second electrodes of the first transistor, eliminating the need for additional source / drain doping, thereby simplifying the process complexity of semiconductor devices (e.g., 3D DRAM).

[0249] In the preceding description, Figures 5A to 5C The semiconductor device shown includes a single-gate transistor and Figures 3A to 3C The semiconductor devices containing dual-gate transistors shown are largely similar in structure, with only some structural differences. The following describes a method for manufacturing a semiconductor device containing a single-gate transistor, with reference to the accompanying drawings.

[0250] First, multiple structural layers, an isolation pattern, a first opening, a first cavity, an insulating layer, a first notch, a first channel layer, a second dielectric layer, and a first gate are formed on the substrate. For details on the formation process of these structures, please refer to [reference needed]. Figures 7A to 16B The corresponding structure and related descriptions in [the document] will not be elaborated here.

[0251] Next, as Figure 17A and Figure 17B As shown, multiple structural layers are patterned to form a second opening 502. The second opening 502 exposes the substrate 101, the isolation pattern 122 (e.g., the first isolation portion 1221 of the isolation pattern 122), and the first channel layer 141. The second opening 502 is located between the first opening 501 and the isolation pattern 122 (e.g., the first isolation portion 1221 of the isolation pattern 122).

[0252] Next, for example, a first dielectric layer 127 filling the second opening 502 is formed by a deposition process (for example, see reference to...). Figures 5A to 5E (The first dielectric layer 127 shown). Thus, a first dielectric layer perpendicular to the substrate is formed in the plurality of structural layers.

[0253] Next, patterning is performed on multiple structural layers to form the third opening 503 (for example, see...). Figure 19A and 19B The third opening 503 is shown. The third opening 503 exposes the substrate 101, the semiconductor layer 130, and the insulating layer 252. The third opening 503 is located between the first dielectric layer 127 and the isolation pattern 122 (e.g., the second isolation portion 1222 of the isolation pattern 122). Since read word lines are formed in this third opening in a subsequent process, this location of the third opening can increase the memory cell density of the memory device.

[0254] Next, electrode lines perpendicular to the substrate are formed in the plurality of structural layers. For example, an electrode line perpendicular to the substrate is formed in the third opening 503. This electrode line is a read word line (RWL) (for example, see reference...). Figures 5A to 5E The read word line RWL is shown. This makes it relatively easy to form the read word line. The portion of the semiconductor layer 130 between the read word line RWL and the first dielectric layer 127 serves as the first electrode 131 (for example, see reference to...). Figures 5A to 5E The first electrode 131 shown.

[0255] Next, the structural layer is patterned to form the fourth opening 504 (for example, see...). Figure 21A and Figure 21B (The fourth opening 504 is shown). The fourth opening 504 exposes the substrate 101, the insulating layer 252, and the semiconductor layer 130. Of course, with... Figure 21A and Figure 21B The fourth opening 504 shown is different in that the fourth opening 504 formed in this step is located on the side of the first dielectric layer 127 away from the read word line RWL.

[0256] Next, side etching is performed on the semiconductor layer 130 through the fourth opening 504 to retract the semiconductor layer 130 relative to the insulating layer 252, thereby forming the second notch 802 (see reference...). Figure 22A and Figure 22B The second notch 802 shown.

[0257] Next, the read bit line RBL is formed in the second notch 802. This facilitates the formation of the read bit line, and because different read bit lines are formed in different second notches, short circuits between different read bit lines can be prevented.

[0258] The portion of semiconductor layer 130 between the read bit line and the first dielectric layer 127 serves as the second electrode 132 (for example, see reference to...). Figures 5A to 5E The second electrode 132 shown.

[0259] Next, the fifth opening, sixth opening, second cavity, second channel layer, first pseudo-dielectric layer, second pseudo-dielectric layer, third notch, third electrode, third dielectric layer, third gate, and write word line are formed. For details on the formation process of these structures, please refer to [reference needed]. Figures 24A to 30C as well as Figures 3A to 3E The corresponding structure and related descriptions in [the document] will not be elaborated here.

[0260] Thus, a method for manufacturing a semiconductor device according to other embodiments of the present disclosure is provided. The first transistor in the semiconductor device formed by this manufacturing method is a single-gate transistor. The semiconductor device manufactured by this method can improve the accuracy of data storage and also increase the read / write speed of the semiconductor device. Furthermore, compared with manufacturing methods in related technologies, in the above-described manufacturing method of the embodiments of the present disclosure, the doped semiconductor layer can be used to form the first and second electrodes of the first transistor, eliminating the need for additional source / drain doping, thereby simplifying the process complexity of semiconductor devices (e.g., 3D DRAM).

[0261] In some embodiments of this disclosure, an electronic device is also provided, comprising the semiconductor device as described above, or a semiconductor device manufactured according to the method for manufacturing the semiconductor device as described above. This electronic device may include a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal, etc.

[0262] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0263] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; and A plurality of memory cells are arranged in an array on the substrate, each memory cell comprising: A first isolation layer, electrode lines, write word lines, and a first dielectric layer perpendicular to the substrate; A gate surrounding the sidewall of the first isolation layer; A second dielectric layer located on the side of the gate away from the first isolation layer; The first channel layer located on the side of the second dielectric layer away from the gate, The material of the first channel layer includes single-crystal semiconductor materials; The first electrode and the second electrode are separated by the first dielectric layer, wherein, The first electrode and the second electrode are respectively in contact with the first channel layer, and the first electrode is in contact with the electrode line; A third dielectric layer surrounding the sidewalls of the write word line; A second channel layer located on the side of the third dielectric layer away from the write word line, wherein a portion of the second channel layer near the gate is in contact with the gate.

2. The semiconductor device according to claim 1, wherein, The first channel layer includes: The first channel portion is located between the second electrode and the second dielectric layer; and The second channel portion is located between the first dielectric layer and the second dielectric layer, wherein the second channel portion is in contact with the first electrode.

3. The semiconductor device according to claim 1 or 2, wherein, Each memory cell also includes a read bit line located on the side of the second electrode away from the first channel layer.

4. The semiconductor device according to claim 1 or 2, wherein, Each memory cell also includes a write bit line that contacts a portion of the second channel layer on the side furthest from the gate.

5. The semiconductor device according to claim 1 or 2, wherein, Each storage unit also includes: The read word line is perpendicular to the substrate and is surrounded by the first dielectric layer; The electrode lines are common electrode lines.

6. The semiconductor device according to claim 1 or 2, wherein, The electrode lines are read word lines.

7. The semiconductor device according to claim 1 or 2, further comprising: Multiple isolation patterns, each isolation pattern including: a first isolation portion and a second isolation portion, wherein the first isolation portion and the second isolation portion are both perpendicular to the substrate, the first isolation portion extends along a first direction parallel to the substrate and is located between adjacent memory cells arranged along a second direction parallel to the substrate, the second isolation portion extends along the second direction and is connected to the first isolation portion, the second isolation portion is located between the electrode line and the write word line, wherein the second direction intersects the first direction.

8. The semiconductor device according to claim 1, further comprising: Multiple layers of alternating insulating layers and doped semiconductor layers; The insulating layer is located between adjacent memory cells in a third direction perpendicular to the substrate; The doped semiconductor layer serves as both the first and second electrodes.

9. A method for manufacturing a semiconductor device, comprising: Multiple stacked structural layers are formed on a substrate, each structural layer including a doped semiconductor layer and an insulating layer on the semiconductor layer; A first channel layer is formed in the plurality of structural layers, wherein the material of the first channel layer includes a single-crystal semiconductor material; A second dielectric layer is formed covering the first channel layer; A gate is formed on the side of the second dielectric layer away from the first channel layer; A first isolation layer perpendicular to the substrate is formed in the plurality of structural layers, and the first isolation layer is surrounded by the gate; A first dielectric layer and an electrode line perpendicular to the substrate are formed in the plurality of structural layers, wherein the semiconductor layer isolated by the first dielectric layer serves as a first electrode and a second electrode, wherein the first electrode and the second electrode are respectively in contact with the first channel layer, and the first electrode is in contact with the electrode line; A second channel layer is formed in the plurality of structural layers, wherein a portion of the second channel layer near the gate side contacts the gate; and Write word lines perpendicular to the substrate and a third dielectric layer surrounding the sidewalls of the write word lines are formed in the plurality of structural layers.

10. The manufacturing method according to claim 9, wherein: Forming the first channel layer in the plurality of structural layers includes: The plurality of structural layers are patterned to form a first opening that exposes the substrate and the semiconductor layer; Side etching is performed on the semiconductor layer based on the first opening, so that the semiconductor layer retracts relative to the insulating layer, thereby forming a first notch; The first channel layer is formed in the first notch and on the side of the semiconductor layer.

11. The manufacturing method according to claim 10, wherein, Multiple stacked structural layers formed on the substrate include: Multiple initial layers are stacked on a substrate, each initial layer comprising the doped semiconductor layer and a sacrificial layer on the semiconductor layer; Patterning is performed on the plurality of initial layers to form the first opening; The sacrificial layer is removed through the first opening to form a first cavity; An insulating layer is formed in the first cavity.

12. The manufacturing method according to claim 11, wherein, The formation of multiple stacked structural layers on the substrate also includes: Before patterning is performed on the plurality of initial layers, a plurality of isolation patterns are formed in the plurality of initial layers. Each isolation pattern includes: a first isolation portion and a second isolation portion, wherein the first isolation portion and the second isolation portion are both perpendicular to the substrate, the first isolation portion extends along a first direction parallel to the substrate, the second isolation portion extends along a second direction parallel to the substrate and is connected to the first isolation portion, the second direction intersects the first direction, wherein the first opening is formed between adjacent isolation patterns in the second direction.

13. The manufacturing method according to claim 9, wherein, Forming a first dielectric layer perpendicular to the substrate in the plurality of structural layers includes: Patterning is performed on the plurality of structural layers to form a second opening, the second opening exposing the substrate and the first trench layer; and A first dielectric layer is formed covering the bottom and sides of the second opening.

14. The manufacturing method according to claim 13, further comprising: A read word line is formed in the second opening where the first dielectric layer is formed; The electrode lines are common electrode lines.

15. The manufacturing method according to claim 9, wherein, The electrode lines are read word lines.

16. The manufacturing method according to claim 9, wherein, Forming electrode lines perpendicular to the substrate in the plurality of structural layers includes: Patterning is performed on the plurality of structural layers to form a third opening, the third opening exposing the substrate, the semiconductor layer, and the insulating layer; and An electrode line perpendicular to the substrate is formed in the third opening, and the electrode line is in contact with the semiconductor layer.

17. The manufacturing method according to claim 9, further comprising: The plurality of structural layers are patterned to form a fourth opening that exposes the substrate, the insulating layer, and the semiconductor layer; Side etching is performed on the semiconductor layer through the fourth opening to retract the semiconductor layer relative to the insulating layer, thereby forming a second notch; A read bit line is formed in the second notch.

18. The manufacturing method according to claim 9, wherein, Forming a second channel layer in the plurality of structural layers includes: Patterning is performed on the plurality of structural layers to form a fifth opening and a sixth opening, the fifth opening and the sixth opening respectively exposing the substrate; A portion of the semiconductor layer, a portion of the first channel layer, and a portion of the second dielectric layer are removed via the fifth and sixth openings to form a second cavity; A second channel layer is formed on the surface inside the second cavity through the fifth opening and the sixth opening; The manufacturing method further includes: A write bit line is formed that contacts the second channel layer.

19. The manufacturing method according to claim 18, wherein, The formation of a write word line perpendicular to the substrate and a third dielectric layer surrounding the sidewalls of the write word line in the plurality of structural layers includes: A third dielectric layer is formed in the fifth opening, covering the substrate, the second channel layer, and the write bit line; After the third dielectric layer is formed, a write word line is formed to fill the fifth opening.

20. An electronic device, comprising: The semiconductor device as described in any one of claims 1 to 8, or the semiconductor device formed by the manufacturing method of the semiconductor device as described in any one of claims 9 to 19.

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