Memory device

Abstract

The embodiment of the invention provides a memory device, and the memory device comprises a first semiconductor structure which comprises a memory cell array; the second semiconductor structure at least comprises a plurality of first control circuits and at least part of peripheral circuits distributed in gaps of the plurality of first control circuits; the first semiconductor structure and the second semiconductor structure are stacked and connected; the first interconnection layer is located on the side, away from the first semiconductor structure, of the second semiconductor structure; a plurality of connection structures; the connection structure penetrates part of the second semiconductor structure, one end is connected with at least part of the peripheral circuit at the gap, and the other end is connected with the first interconnection layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory device. Background Technology

[0002] Memory devices are storage devices used to preserve information in modern information technology. As people's requirements for storage devices continue to increase, there is still much room for improvement in memory device technology. Summary of the Invention

[0003] In view of this, embodiments of this application provide a memory device.

[0004] In a first aspect, embodiments of this application provide a memory device, the memory device comprising: a first semiconductor structure including a memory cell array; a second semiconductor structure including at least a plurality of first control circuits and at least a portion of peripheral circuits distributed in the gaps between the plurality of first control circuits; the first semiconductor structure and the second semiconductor structure being stacked and connected; a first interconnect layer located on the side of the second semiconductor structure away from the first semiconductor structure; a plurality of connection structures; the connection structures penetrating a portion of the second semiconductor structure, one end being connected to at least a portion of the peripheral circuits in the gaps, and the other end being connected to the first interconnect layer.

[0005] In some embodiments, the memory device further includes a second interconnect layer located between the first semiconductor structure and the second semiconductor structure, the first semiconductor structure and the second semiconductor structure being connected through the second interconnect layer.

[0006] In some embodiments, the memory device further includes a third interconnect layer, a first bonding layer, a second bonding layer, and a fourth interconnect layer that are stacked between the first semiconductor structure and the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure are connected through the third interconnect layer, the first bonding layer, the second bonding layer, and the fourth interconnect layer.

[0007] In some embodiments, the memory cell array includes a plurality of memory cells, each memory cell including a plurality of memory blocks; a first control circuit is connected to a memory block, and peripheral circuits are connected to all memory cells; at least a portion of the peripheral circuits includes a plurality of first portions and a second portion; a first portion is correspondingly connected to a corresponding memory block, the boundary of the first control circuit setting area overlaps with the boundary of the corresponding memory block setting area; the boundary of the second portion setting area overlaps with the boundary of the gap between adjacent memory blocks; the plurality of first portions and / or second portions are connected to a first interconnect layer through a plurality of connection structures.

[0008] In some embodiments, the first control circuit includes a sensing amplifier circuit and a word line driving circuit; the sensing amplifier circuit is connected to the bit lines in the memory block; and the word line driving circuit is connected to the word lines in the memory block.

[0009] In some embodiments, the sensing amplification circuit connected to the memory block is disposed in the first region and the second region; the word line driving circuit connected to the memory block is disposed in the third region and the fourth region; the first region and the second region both extend along the first direction and are offset along the second direction, the third region and the fourth region both extend along the second direction and are offset along the first direction, the first direction is perpendicular to the direction of bit line extension, and the second direction is perpendicular to the direction of word line extension.

[0010] In some embodiments, the boundary of the first region is in contact with the boundary of the third region, and the boundary of the second region is in contact with the boundary of the fourth region; the sum of the dimensions of the boundaries of the first region and the third region along the first direction is the first dimension, and the dimension of the boundary of the storage block setting region along the first direction is the second dimension, wherein the first dimension is smaller than the second dimension.

[0011] In some embodiments, the first semiconductor structure further includes a first contact connected to a word line and a second contact connected to a bit line; both the first and second contacts are disposed on a side close to the second semiconductor structure; the second semiconductor structure further includes a third contact connected to a sensing amplifier circuit and a fourth contact connected to a word line driving circuit; both the third and fourth contacts are disposed on a side close to the first semiconductor structure; the second and third contacts, and the first and fourth contacts are all connected at least through an interconnect layer located between the first and second semiconductor structures.

[0012] In some embodiments, the second semiconductor structure includes a plurality of active regions spaced apart by isolated regions; a connection structure is disposed at the boundary of the active regions and in the isolated regions.

[0013] In some embodiments, the memory device further includes power supply wiring; the power supply wiring is disposed in the first interconnect layer.

[0014] In some embodiments, the second semiconductor structure further includes: a plurality of second control circuits, one of which is connected to a memory bank; the second control circuits are distributed in the gaps between the plurality of first control circuits; the second control circuits include row decoding circuits and column decoding circuits.

[0015] In some embodiments, the boundary of the second control circuit setting area overlaps with the boundary of the gap between adjacent memory cells.

[0016] In some embodiments, the memory device further includes pads; the pads are located on the side of the first interconnect layer away from the second semiconductor structure and are electrically connected to the first interconnect layer.

[0017] In some embodiments, the memory cell array includes: a plurality of word lines extending along a first direction; a plurality of bit lines extending along a second direction; a plurality of semiconductor pillars arranged in an array and a memory structure corresponding to each plurality of semiconductor pillars; the semiconductor pillars and the corresponding memory structures are stacked; wherein the semiconductor pillars extend along a third direction and have a first end and a second end disposed opposite to each other in the third direction, the first end being connected to the bit line and the second end being connected to the memory structure; the word lines are coupled to at least one side of the semiconductor pillars; the third direction is perpendicular to both the first direction and the second direction.

[0018] In some embodiments, the storage structure includes a capacitor; the capacitor includes a cup-shaped capacitor, a cylindrical capacitor, or a pillar-shaped capacitor.

[0019] In some embodiments, the multiple storage structures are arranged in a square or hexagonal pattern.

[0020] In some embodiments, the word line is coupled to one side of the semiconductor pillar; or, the word line is coupled to both sides of the semiconductor pillar that are opposite to each other; or, the word line is coupled to all sides of the semiconductor pillar.

[0021] In some embodiments, the semiconductor pillar is made of indium gallium zinc oxide.

[0022] In some embodiments, the memory device includes dynamic random access memory.

[0023] Secondly, embodiments of this application provide another memory device, which includes: a first semiconductor structure including a memory cell array; a second semiconductor structure including at least a plurality of first control circuits and at least a portion of peripheral circuits distributed in the gaps between the plurality of first control circuits; a first interconnect layer located on the side of the second semiconductor structure away from the first semiconductor structure; a plurality of connection structures; the connection structures penetrate a portion of the second semiconductor structure, one end of which is connected to at least a portion of the peripheral circuits in the gaps, and the other end of which is connected to the first interconnect layer; and a second interconnect layer located between the first semiconductor structure and the second semiconductor structure, which is connected to both the memory cell array and the first control circuits.

[0024] In some embodiments, the memory cell array includes a plurality of memory cells, each memory cell including a plurality of memory blocks; a first control circuit is connected to a memory block, and peripheral circuits are connected to all memory cells; at least a portion of the peripheral circuits includes a plurality of first portions and a second portion; the boundary of the region set by the first control circuit, which is connected to a corresponding memory block, overlaps with the boundary of the region set by the corresponding memory block; the boundary of the region set by the second portion overlaps with the boundary of the gap between adjacent memory blocks; the plurality of first portions and / or the second portion are connected to a first interconnect layer through a plurality of connection structures.

[0025] In some embodiments, the memory device further includes power supply wiring; the power supply wiring is disposed in the first interconnect layer.

[0026] Thirdly, embodiments of this application provide another memory device, the memory device comprising: a first semiconductor structure including a memory cell array; a second semiconductor structure including at least a plurality of first control circuits and at least a portion of peripheral circuits distributed in the gaps between the plurality of first control circuits; a first interconnect layer located on the side of the second semiconductor structure away from the first semiconductor structure; and a third interconnect layer, a first bonding layer, a second bonding layer and a fourth interconnect layer stacked therebetween the first semiconductor structure and connected to both the memory cell array and the first control circuits.

[0027] In some embodiments, the memory cell array includes a plurality of memory cells, each memory cell including a plurality of memory blocks; a first control circuit is connected to a memory block, and peripheral circuits are connected to all memory cells; at least a portion of the peripheral circuits includes a plurality of first portions and a second portion; the boundary of the region set by the first control circuit, which is connected to a corresponding memory block, overlaps with the boundary of the region set by the corresponding memory block; the boundary of the region set by the second portion overlaps with the boundary of the gap between adjacent memory blocks; the plurality of first portions and / or the second portion are connected to a first interconnect layer through a plurality of connection structures.

[0028] In some embodiments, the memory device further includes power supply wiring; the power supply wiring is disposed in the first interconnect layer.

[0029] In various embodiments of this application, a first semiconductor structure including a memory cell array and a second semiconductor structure including a first control circuit and peripheral circuits are stacked. Compared with a scheme in which the two are arranged side by side, the storage density of the memory device can be improved. By using back-side wiring of the second semiconductor structure and connecting it to at least part of the peripheral circuits through the connection structure through the second semiconductor structure, at least part of the peripheral circuits can be distributed in the gaps of the first control circuit. Compared with directly placing the peripheral circuits in a complete area, the additional area brought by the peripheral circuits in the second semiconductor structure is directly reduced. In this way, the size of the memory device can be reduced, and the storage density of the memory device can be further improved. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the composition structure of an exemplary dynamic random access memory according to an embodiment of this application;

[0031] Figure 2 This is one of the top views illustrating the distribution of the memory cell array and peripheral circuitry in an exemplary memory device according to an embodiment of this application;

[0032] Figure 3AThis is a second top view schematic diagram of the distribution of the memory cell array and peripheral circuitry in an exemplary memory device according to an embodiment of this application;

[0033] Figure 3B An exemplary embodiment of this application is based on Figure 3A A specific unfolded diagram;

[0034] Figure 3C An exemplary embodiment of this application is based on Figure 3A A magnified schematic diagram of region PZ;

[0035] Figure 4A This is a third top view schematic diagram of the distribution of the memory cell array and peripheral circuitry in an exemplary memory device according to an embodiment of this application;

[0036] Figure 4B This is a fourth top view schematic diagram of the distribution of the memory cell array and peripheral circuitry in an exemplary memory device according to an embodiment of this application;

[0037] Figure 5A An exemplary embodiment of this application is based on Figure 4A or Figure 4B An enlarged schematic diagram of region QZ;

[0038] Figure 5B An exemplary embodiment of this application is based on Figure 5A A magnified diagram of region RZ;

[0039] Figure 6 One of the cross-sectional schematic diagrams of the memory device provided in the embodiments of this application;

[0040] Figure 7 A second cross-sectional schematic diagram of a memory device provided in an embodiment of this application;

[0041] Figure 8 One of the plan layout diagrams of a first control circuit corresponding to a memory block of a memory device provided in an embodiment of this application;

[0042] Figure 9 A second plan layout diagram of the first control circuit corresponding to a memory block of the memory device provided in the embodiments of this application;

[0043] Figure 10A One of the planar layout diagrams of the memory cell array of the memory device provided in the embodiments of this application;

[0044] Figure 10B for Figure 10A A schematic diagram of the cross-section along section CC;

[0045] Figure 11AA second planar layout diagram of the memory cell array of the memory device provided in the embodiments of this application;

[0046] Figure 11B for Figure 11A A schematic diagram of the cross-section along section CC;

[0047] Figure 12A The third planar layout diagram of the memory cell array of the memory device provided in the embodiments of this application;

[0048] Figure 12B for Figure 12A A schematic diagram of the cross-section along section CC;

[0049] Figure 13A One of the planar layout diagrams of the memory structure of the memory device provided in the embodiments of this application;

[0050] Figure 13B A second planar layout diagram of the memory structure of the memory device provided in the embodiments of this application;

[0051] Figure 14 A schematic flowchart illustrating a method for fabricating a memory device according to an embodiment of this application;

[0052] Figures 15A to 15K A cross-sectional schematic diagram of the process of forming a memory device provided in this application embodiment. Figure 1 ;

[0053] Figures 16A to 16D A cross-sectional schematic diagram of the process of forming a memory device provided in this application embodiment. Figure 2 . Detailed Implementation

[0054] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0055] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0056] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0057] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0058] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0060] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0061] The memory devices involved in the embodiments of this application can be random access memory (RAM), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. The following description uses DRAM as an example only.

[0062] Figure 1 This is a schematic diagram of the composition structure of an exemplary dynamic random access memory according to an embodiment of this application.

[0063] Figure 1 The right side shows a schematic circuit of a memory cell in DRAM. DRAM includes at least one DRAM die, and each DRAM die includes a memory cell array. The memory cell array includes multiple memory cells 10 arranged in an array. Each memory cell 10 includes an array transistor TA and a capacitor C. The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, which can be regarded as a typical mesh structure. The memory cell array uses rows and columns to specify addresses. By specifying the intersection of the rows and columns (by specifying the row address and column address of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and perform read, write, or refresh operations on the data stored therein.

[0064] Figure 1 The left side illustrates the memory cell array, word lines (rows), bit lines (columns), and some control and peripheral circuitry within a DRAM. It's important to note that the row decoding circuit in the control circuit selects a word line to choose the row of the memory cell to access, responding to the address input to it. The row decoding circuit decodes the input address and enables (activates) the word line corresponding to the decoded address. The column decoding circuit in the control circuit selects one or more bit lines to input the user's output data into a portion of the row of the memory cell corresponding to the selected word line.

[0065] Figure 2This is one of the top views illustrating the distribution of the memory cell array and peripheral circuitry in an exemplary memory device according to an embodiment of this application. The following is in conjunction with... Figure 2 A detailed description is given of one layout method for memory devices. (In the introduction...) Figure 2 Before illustrating the memory device, the various directions that may be used in the following description are defined. Two directions parallel to the plane of the substrate (or semiconductor structure) are defined as the first direction (i.e., the X direction) and the second direction (i.e., the Y direction). A third direction (i.e., the Z direction) is defined perpendicular to the plane of the substrate (or semiconductor structure). In some embodiments, the X, Y, and Z directions may be mutually perpendicular.

[0066] For example, such as Figure 2 As shown, the memory cell array 21 and peripheral circuits 22 are arranged side by side. More specifically, the memory cell array 21 includes multiple (e.g., 16) memory banks 21-1 (Bank0-Bank15). Each memory bank 21-1 includes multiple memory blocks 21-2. Each memory block 21-2 has a corresponding sensing amplifier (SA) circuit 26 and a word line driver (WLD) circuit 25 arranged around its perimeter. Each memory bank has a corresponding column decoding circuit 24 and a row decoding circuit 23 arranged on both sides. Multiple (e.g., 4) memory banks form a memory bank row, and peripheral circuits 22 corresponding to all memory banks are arranged between the two middle memory bank rows. It should be noted that... Figure 2 The number of memory cells and the positional relationship of the circuits are for illustrative purposes only and are not intended to limit the number of memory cells and the positional relationship of the circuits in the memory devices of this application.

[0067] Here and below, peripheral circuit 22 is the control circuit for all memory banks; in other words, all memory banks share peripheral circuit 22. Peripheral circuit 22 may include, but is not limited to, command buffers, command decoders, address buffers, data buffers, mode registers, etc. The first control circuit is the control circuit for the corresponding memory block, such as the aforementioned SA and WLD, meaning each memory block corresponds to a set of SA and WLD. Furthermore, considering wiring convenience, each set of SA and WLD for each memory block is placed next to the corresponding memory block. The second control circuit is the control circuit for the corresponding memory bank, such as the aforementioned column decoding circuit and row decoding circuit. In other words, each memory bank corresponds to a set of column decoding circuits and row decoding circuits, and considering wiring convenience, each set of column decoding circuits and row decoding circuits for each memory bank is placed next to the corresponding memory bank.

[0068] Figure 3AThis is a second top view schematic diagram of the distribution of the memory cell array and peripheral circuitry in an exemplary memory device according to an embodiment of this application; Figure 3B An exemplary embodiment of this application is based on Figure 3A A specific unfolded diagram; Figure 3C An exemplary embodiment of this application is based on Figure 3A A magnified schematic diagram of region PZ.

[0069] refer to Figure 3A and Figure 3B The memory device can be a structure consisting of a first semiconductor structure including a memory cell array and a second semiconductor structure including peripheral circuits stacked along the Z direction; wherein, Figure 3B and Figure 2 The difference lies in that SA 26 and WLD 25 of each storage block 21-2 are both located at the bottom of each storage block. Based on this, in Figure 3B In the enlarged view corresponding to each storage block 21-2, the solid line represents the enlarged portion of storage block 21-2, and the dashed line represents the SA 26 and WLD 25 corresponding to storage block 21-2 located directly below it. It should be noted that in some embodiments, the positions of storage block 21-2 and its corresponding SA 26 and WLD 25 can be interchanged. The following explanation uses the example of SA 26 and WLD 25 located below storage block 21-2 as an example.

[0070] exist Figure 3A In the first semiconductor structure, the peripheral circuits 22 corresponding to all memory cells are disposed on the second semiconductor structure. For ease of wiring, the middle area between the two memory cell arrays 21 disposed on the first semiconductor structure can be left empty, that is, without placing any devices, so that the peripheral circuits 22 located on the second semiconductor structure can be directly observed from above.

[0071] Figure 3A The region PZ is marked with a dashed line, indicating... Figure 3C The image shows the corresponding setting areas for SA 26 and WLD 25 located directly below 16 storage blocks 21-2. For example, storage block 0 corresponds to one SA and one WLD located in two areas. Figure 3C In the middle, there are multiple storage blocks 21-2 arranged in an array, corresponding to multiple SA26 and WLD 25 arranged in an array.

[0072] In the above embodiments, the SA and WLD corresponding to each memory block can be directly laid below the corresponding memory block without bringing additional chip area; however, the above peripheral circuit is laid outside the plane (XY plane) where the memory cell array is located, which brings additional area occupation.

[0073] In the above embodiments, considering that the peripheral circuits typically occupy a large area, dispersing them in separate, spaced areas would lead to complex interconnection wiring for these peripheral circuits. Furthermore, this complex wiring might conflict with the wiring of the aforementioned first and second control circuits. Therefore, the control circuits are centrally located on the second semiconductor structure, leaving the area of ​​the first semiconductor structure corresponding to the peripheral circuits essentially unused and wasted. With the increasing integration density of Complementary Metal Oxide Semiconductor (CMOS), the area occupied by the first control circuit decreases. The area occupied by the first control circuit for each memory block is smaller than the area occupied by the memory block itself. Therefore, besides arranging the first control circuit, there is still a relatively large empty area below the memory block. This empty area can be rationally arranged and combined to form a larger area to accommodate at least some of the peripheral circuits.

[0074] Figure 4A This is a third top view schematic diagram of the distribution of the memory cell array and peripheral circuitry in an exemplary memory device according to an embodiment of this application; Figure 4B This is a top view of the distribution of the memory cell array and peripheral circuitry in an exemplary memory device according to an embodiment of this application. Figure 5A An exemplary embodiment of this application is based on Figure 4A or Figure 4B An enlarged schematic diagram of region QZ; Figure 5B An exemplary embodiment of this application is based on Figure 5A A magnified diagram of region RZ.

[0075] In some embodiments, reference Figure 4A Figure 4B and Figure 5A , Figure 5B Compared to Figures 3A to 3CThe memory device shown can utilize the aforementioned free space to rationally place at least part of the peripheral circuits, directly reducing the extra area occupied by the peripheral circuits. At the same time, a second semiconductor structure with peripheral circuits and a first control circuit is formed on the front side. The lines connecting the first control circuit and the memory cell array are arranged on the front side of the second semiconductor structure, and the lines connecting the peripheral circuits scattered in the gaps between the locations of the first control circuit are arranged on the back side of the second semiconductor structure. This can avoid the conflict between the wiring of the two, thereby achieving the purpose of saving area without changing the storage capacity or reducing the performance of the control circuit.

[0076] Figure 3A Memory devices can be used as Figure 4A and Figure 4B The control group of memory devices Figure 4A , 4B Memory devices can be understood as those that directly utilize the storage capacity of the memory device without changing its storage capacity. Figure 3A The empty area below the memory block of the memory device, or the larger empty area below the memory block after the size of the first control circuit is reduced, is used to place at least part of the peripheral circuit. Figure 4A Some peripheral circuits were placed in unused areas. Figure 4A The remaining peripheral circuitry not placed in the empty area, as shown in the figure, has a dimension A2 along the Y direction that is smaller than... Figure 3A The corresponding peripheral circuit's dimension A1 along the Y direction, Figure 4B All peripheral circuits are placed in an unused area, i.e. Figure 4B All peripheral circuits are located below the memory cell array. It should be noted that in some embodiments, the positions of the memory block, its corresponding SA, WLD, and peripheral circuits in the empty spaces can be interchanged. The following explanation uses the example of the SA, WLD, and peripheral circuits in the empty spaces being located below the memory block.

[0077] Figure 5A In, can be with Figure 3C By comparison, it can be understood that there are multiple storage blocks arranged in an array, corresponding to multiple SAs, WLDs, and some peripheral circuits PCs arranged in an array. It should be noted that, compared to... Figure 3C , Figure 5A The size of the first control circuit has been reduced, and there is a larger free area below each memory block array to place at least part of the peripheral circuit PC.

[0078] Figure 5B The back-side wiring of the second semiconductor structure is shown using dashed line perspective (which can be understood as...). Figure 6 and Figure 7 The three metal layers in the middle (302), Figure 5BIt also uses solid dots to demonstrate Through-Silicon Contact (TSC) (which can be understood as...) Figure 6 and Figure 7 (Connection structure 204 in the text). It should be noted that, Figure 5B The location and quantity of back-side wiring and through-silicon contacts are for illustrative purposes only and are not intended to limit the location and quantity of wiring and through-silicon contacts in the memory devices of this application.

[0079] refer to Figure 5B The back-side wiring is connected to at least a portion of the peripheral circuitry via through-silicon contacts. In other words, the back-side wiring and through-silicon contacts are used to connect at least a portion of the peripheral circuitry in the unused areas, and the connection does not conflict with the front-side wiring of the first control circuitry located on the front side of the second semiconductor structure.

[0080] refer to Figure 5B In some embodiments, the metal interconnect traces in the back-side wiring of the second semiconductor structure can be used to lay out a power bus. Since the power bus is close to the wiring of the peripheral circuit, the voltage drop of the power supply is very low, and the utilization rate is very high. At the same time, the metal layer on the back side of the second semiconductor structure used for peripheral circuit interconnection and the metal layer used for power bus layout can share some metal layers, thereby reducing the total number of metal layers on the front and back sides, thus saving process costs.

[0081] In a first aspect, embodiments of this application provide a memory device, with reference to Figure 6 and Figure 7 The memory device includes: a first semiconductor structure including a memory cell array; a second semiconductor structure including at least a plurality of first control circuits and at least a portion of peripheral circuits distributed in the gaps between the plurality of first control circuits; the first semiconductor structure and the second semiconductor structure are stacked and connected; a first interconnect layer located on the side of the second semiconductor structure away from the first semiconductor structure; a plurality of connection structures; the connection structures penetrate a portion of the second semiconductor structure, one end of which is connected to at least a portion of the peripheral circuits in the gaps, and the other end of which is connected to the first interconnect layer.

[0082] Here and below, the first direction can also be understood as the direction in which the word line (WL) extends, represented by the X direction in the attached figure; the second direction can also be understood as the direction in which the bit line (BL) extends, represented by the Y direction in the attached figure; and the third direction can be understood as the stacking direction of the first semiconductor structure and the second semiconductor structure, represented by the Z direction in the attached figure.

[0083] It should be noted that, Figure 6The cross section shown is the cross section formed by the extension direction of the word line of a memory device - the stacking direction of the first semiconductor structure and the second semiconductor structure, denoted as the XZ section in the attached figure; Figure 7 The cross section shown is the cross section formed by the direction of the bit line extension of another memory device - the stacking direction of the first semiconductor structure and the second semiconductor structure, and is represented as the YZ cross section in the attached figure.

[0084] It should be noted that, Figure 6 and Figure 7 Components / circuits / devices with the same label in a circuit can be understood as the same or similar components / circuits / devices.

[0085] The first semiconductor structure 100 may include a memory cell array. Each memory cell in the memory cell array may refer to the foregoing. Figure 1 The description of the memory cell is explained below. The capacitor C can be formed in a planar, stacked, or trench configuration, depending on the manufacturing method. The capacitor C can be coupled to a first doped region (e.g., source region S) of the array transistor TA to be charged or discharged through the first doped region. The word line WL can be coupled to the gate of the array transistor TA to turn the array transistor TA on or off. The bit line BL can be coupled to a second doped region (e.g., drain region D) of the array transistor TA and serves as a path for charging or discharging the capacitor C.

[0086] The second semiconductor structure 200 may include a first control circuit and at least a portion of peripheral circuitry. The first control circuit and peripheral circuitry may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array by applying voltage and / or current signals to each target memory cell via bit lines and word lines, and sensing voltage and / or current signals from each target memory cell. The first control circuit and peripheral circuitry may include various types of circuitry formed using MOS technology. Both the first control circuitry and at least a portion of the peripheral circuitry may each include a plurality of peripheral transistors TC to form control circuitry configured to operate the memory cell array (e.g., write or read memory cells from the memory cell array).

[0087] As mentioned earlier, the peripheral circuitry corresponds to the control circuitry for all memory banks; in other words, all memory banks share the peripheral circuitry. The peripheral circuitry may include, but is not limited to, command buffers, command decoders, address buffers, data buffers, mode registers, etc. The first control circuitry corresponds to the control circuitry for the memory block, such as SA and WLD, meaning that each memory block corresponds to a set of SA and WLD.

[0088] SA is configured to sense a low-power signal from bit line BL representing a data bit (one or zero) stored in a DRAM memory cell and amplify a small voltage swing to a recognizable logic level, enabling the data to be correctly interpreted by logic cells outside the DRAM memory device. WLD can be configured to apply a corresponding drive voltage to the word line of the select / deselect memory block.

[0089] In some embodiments, the second semiconductor structure 200 includes a first substrate 202 and peripheral transistors TC located on the front side of the second substrate. In some embodiments, the first substrate 202 may include silicon (Si), germanium (Ge), silicon germanide (SiGe), etc., or it may be silicon on insulator (SOI) or germanium on insulator (GOI). In some embodiments, the first substrate 202 may be doped with certain impurity ions as needed. The impurity ions may be N-type or P-type impurity ions, and the doping includes well region doping and source / drain region doping. In some embodiments, the peripheral transistors TC may include NMOS transistors formed in P-wells and PMOS transistors formed in N-wells. Multiple peripheral transistors TC are interconnected through a metal interconnect layer to form a first control circuit and at least a portion of the peripheral circuitry.

[0090] In some embodiments, the front-side metal interconnect layer may be a metal interconnect layer on the side of the first substrate 202 with the peripheral transistor TC (i.e., the side close to the first side SUR1 (or front side) of the second semiconductor structure 200), and the metal interconnect layer includes contacts and metal interconnects. In some embodiments, the front-side metal interconnect layer includes multiple layers of metals stacked alternately and interconnected and multiple contacts. In some specific embodiments, the front-side metal interconnect layer has three layers, including a zero-layer contact 210, a zero-layer metal layer 211, a first-layer contact 212, a first-layer metal layer 213, a second-layer contact 214, and a second-layer metal layer 215 stacked sequentially, wherein the multiple layers of metals include the zero-layer metal layer 211, the first-layer metal layer 213, and the second-layer metal layer 215, and the multiple contacts include the zero-layer contact 210, the first-layer contact 212, and the second-layer contact 214. The zero-layer contact 210 extends and couples to the first source / drain S / D1, the second source / drain S / D2 of the peripheral transistor TC or extends to the gate G of the peripheral transistor TC. Here and below, the materials for contacts and metal interconnects include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicides, nitrides, or any combination thereof.

[0091] The first interconnect layer 300 is located on the side of the second semiconductor structure 200 away from the first semiconductor structure 100. Exemplarily, the first interconnect layer 300 can be understood as a back metal interconnect layer, which can be a metal interconnect layer formed on the second surface SUR2 (or back surface) of the second semiconductor structure 200, and the metal interconnect layer includes contacts and metal interconnect lines.

[0092] In some embodiments, the back metal interconnect layer includes alternating and interconnected multilayer metal layers and multiple contacts. In some specific embodiments, the back metal interconnect layer has two layers, including three-layer contacts 301, three-layer metal layers 302, four-layer contacts 303, and four-layer metal layers 304 stacked sequentially, wherein the multilayer metal layers include three-layer metal layers 302 and four-layer metal layers 304, and the multiple contacts include three-layer contacts 301 and four-layer contacts 303. The three-layer contacts 301 (which can be understood as connection structure 204) extend and couple to the front metal interconnect layer, for example, the three-layer contacts 301 extend and couple to the zero-layer metal layer 211. In some embodiments, the material of the three-layer metal layer 302 may be the same as or different from the material of the four-layer metal layer 304. In some specific embodiments, the material of the four-layer metal layer 302 includes aluminum or an aluminum alloy, and the material of the three-layer metal layer 302 includes copper or a copper alloy.

[0093] The connection structure 204 penetrates a portion of the second semiconductor structure 200, with one end connected to at least a portion of the peripheral circuitry at the gap, and the other end connected to the first interconnect layer 300. For example, the connection structure 204 penetrates the first substrate 202, with one end extending to the front metal interconnect layer and connecting to at least a portion of the peripheral circuitry in the second semiconductor structure 200, and the other end extending to the back metal interconnect layer and connecting to the first interconnect layer 300. For instance, the connection structure 204 penetrates the first substrate 202 and extends to the three-layer metal layer 302 and the zero-layer metal layer 211 at both ends, respectively.

[0094] The gap can be understood as a first insulating structure 206 separating multiple active regions in the first substrate 202, or as a second insulating structure 208 separating multiple well regions (P-wells / N-wells) in the first substrate 202. The first insulating structure 206 and the second insulating structure 208 located in the first substrate 202 can be obtained through a shallow trench isolation (STI) process. The materials of the first insulating structure 206 and the second insulating structure 208 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0095] For details regarding the interconnection between the first semiconductor structure 100 and the second semiconductor structure 200 layers, please refer to the description below.

[0096] In this embodiment, the stacked arrangement of the first semiconductor structure and the second semiconductor structure can significantly improve the storage density of the memory device. By utilizing the back-side wiring of the second semiconductor structure and connecting it to at least some peripheral circuits through the connection structure, at least some peripheral circuits can be distributed and arranged below the storage blocks of the memory cell array, directly reducing the area occupied by the peripheral circuits in the second semiconductor structure. The routing of the back-side wiring of the second semiconductor structure can realize the interconnection between the distributed at least some peripheral circuits without conflicting with the connection of the front-side wiring of the second semiconductor structure.

[0097] refer to Figure 6 In some embodiments, the memory device further includes a second interconnect layer located between the first semiconductor structure and the second semiconductor structure, the first semiconductor structure and the second semiconductor structure being connected through the second interconnect layer. The second interconnect layer 400 may be a metal interconnect layer formed on the first surface SUR1 (or front side) of the second semiconductor structure 200 and the third surface SUR3 (the third surface SUR3 can be understood as the surface of the first semiconductor structure 100 adjacent to the first surface SUR1) of the first semiconductor structure 100. The second interconnect layer 400 may include one or more interconnect layers, such as the aforementioned sequentially stacked zero-layer contact 210, zero-layer metal layer 211, first-layer contact 212, first-layer metal layer 213, second-layer contact 214, second-layer metal layer 215, second interconnect layer 400, word line contact 402, bit line contact 404, etc. The materials of the word line contact 402 and bit line contact 404 include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. In some embodiments, the second interconnect layer further includes a capacitor common electrode contact 406. The materials for the capacitor common electrode contact 406 include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polycrystalline silicon, doped silicon, silicide, nitride, or any combination thereof.

[0098] It should be noted that, in Figure 6 In the illustrated embodiment, the first semiconductor structure and the second semiconductor structure are connected only through a second interconnect layer between them. The third substrate 302 is a substrate used for carrying functions, not as a growth substrate, and the third substrate 302 can be selectively removed. That is, Figure 6 In the illustrated embodiment, both the first semiconductor structure and the second semiconductor are grown on the basis of the first substrate 202, which reduces the use of the growth substrate and saves costs.

[0099] refer to Figure 7In some embodiments, the memory device further includes a third interconnect layer, a first bonding layer, a second bonding layer, and a fourth interconnect layer that are stacked between the first semiconductor structure and the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure are connected through the third interconnect layer, the first bonding layer, the second bonding layer, and the fourth interconnect layer.

[0100] Here and below, the third interconnect layer, the first bonding layer, the second bonding layer, and the fourth interconnect layer can be referred to as the bonding interconnect structure 500. The bonding interconnect structure 500 includes contacts and metal interconnects.

[0101] The third interconnect layer and the first bonding layer can be metal interconnect layers (including contacts and metal interconnects) formed on the first surface SUR1 (or front side) of the second semiconductor structure 200. The third interconnect layer can include one or more interconnect layers, such as the aforementioned sequentially stacked zero-layer contact 210, zero-layer metal layer 211, first-layer contact 212, first-layer metal layer 213, second-layer contact 214, and second-layer metal layer 215. The first bonding layer can include a first bonding contact 502. The fourth interconnect layer and the second bonding layer can be metal interconnect layers (including contacts and metal interconnects) formed on the third surface SUR3 of the first semiconductor structure 100. The fourth interconnect layer can include one or more interconnect layers, such as five metal layers 506. The second bonding layer can include a second bonding contact 504. The second semiconductor structure 200 having the first bonding contact 502 and the first semiconductor structure 100 having the second bonding contact 504 can be used to obtain a bonding interconnect structure 500 with a bonding interface 508 through a hybrid bonding process, etc., and the first bonding contact 502 and the second bonding contact 504 are in contact with each other and electrically connected.

[0102] It should be noted that, in Figure 7 In the illustrated embodiment, the first semiconductor structure and the second semiconductor structure are connected by bonding. The first substrate 202 serves as the growth substrate for the second semiconductor structure 200, and the second substrate 102 serves as the growth substrate for the first semiconductor structure 100. That is, Figure 7 In the illustrated embodiment, the first semiconductor structure and the second semiconductor are grown on different substrates, which can solve the problem of mutual constraints between the process of the memory cell array and the process of the peripheral circuit, thereby shortening the development cycle of the memory device.

[0103] refer to Figure 5BIn some embodiments, the memory cell array includes multiple memory banks, and each memory bank includes multiple memory blocks; a first control circuit is connected to a memory block, and peripheral circuits are connected to all memory banks; at least a portion of the peripheral circuits includes multiple first portions and a second portion; the boundary of the first control circuit setting area corresponding to a corresponding memory block overlaps with the boundary of the corresponding memory block setting area; the boundary of the second portion setting area overlaps with the boundary of the gap between adjacent memory blocks; the multiple first portions and / or the second portions are connected to a first interconnect layer through multiple connection structures.

[0104] In some embodiments, the storage cell array may include multiple storage banks, such as 16 storage banks, and the number of storage banks may be less than 16 or more than 16. Each storage bank may include multiple blocks, such as 16 storage blocks, and the number of storage blocks may be less than 16 or more than 16.

[0105] In some embodiments, the spare area SZ may include a first spare area SZ1 located in the projection area below the memory block, excluding the first control circuit, and a second spare area SZ2 located in the projection area below the gap between adjacent memory blocks. The number of first spare areas SZ1 is the same as the number of memory blocks included in the memory cell array.

[0106] For example, at least a portion of the peripheral circuit PC includes a plurality of first portions PC1 located in the first vacant region SZ1. Figure 5B The image shows two first parts (PC1) and a second part (PC2) located in the second empty region SZ2. Figure 5B The diagram shows two first portions PC1 located below and spaced apart from the memory blocks, and a second portion PC2 located below as a whole between adjacent memory blocks. Both first portions PC1 and one second portion PC2 are connected to the three-layer metal layer 302 of the first interconnect layer via multiple connection structures 204.

[0107] refer to Figure 6 and Figure 7 In some embodiments, the first control circuit includes a sensing amplifier circuit and a word line driving circuit; the sensing amplifier circuit is connected to the bit lines in the memory block; and the word line driving circuit is connected to the word lines in the memory block.

[0108] refer to Figure 6In some embodiments, the first semiconductor structure 100 may include a memory cell array, and the first control circuit of the second semiconductor structure 200 may include a word line driving circuit and a sensing amplification circuit. The word lines WL of the memory cell array can be connected to the word line driving circuit via word line contacts 402, and the bit lines BL of the memory cell array can be connected to the sensing amplification circuit via bit line contacts 404. In some embodiments, the word lines WL can be connected to the word line contacts 402 via word line connection structure 108 and word line landing pads 104. Additionally, the capacitor C can be connected to the capacitor common electrode contact 406 via capacitor connection structure 110 and capacitor landing pads 106.

[0109] refer to Figure 7 In some embodiments, the first semiconductor structure 100 may include a memory cell array, and the first control circuit of the second semiconductor structure 200 may include a word line driving circuit and a sensing amplification circuit. The word line WL of the memory cell array can be connected to the word line driving circuit via a bonding interconnect structure 500, and the bit line BL of the memory cell array can be connected to the sensing amplification circuit via the bonding interconnect structure 500. In some embodiments, the word line WL, bit line BL, and capacitor C of the memory cell array in the first semiconductor structure 100 can be connected to the five-layer metal layer 506 of the bonding interconnect structure 500 via the word line connection structure 108, the bit line connection structure 112, and the capacitor connection structure 110, respectively. They are also connected to a plurality of second bonding contacts 504 and a plurality of first bonding contacts 502 of the bonding interconnect structure 500 via the five-layer metal layer 506, and then connected to the word line driving circuit and the sensing amplification circuit in the second semiconductor structure 200 via the plurality of first bonding contacts 502.

[0110] In some embodiments, word line connection structure 108 and / or bit line connection structure 112 may be located directly below the memory block.

[0111] refer to Figure 5A In some embodiments, the sensing amplification circuit connected to the memory block is disposed in the first region and the second region; the word line driving circuit connected to the memory block is disposed in the third region and the fourth region; the first region and the second region both extend along the first direction and are offset along the second direction, the third region and the fourth region both extend along the second direction and are offset along the first direction, the first direction is perpendicular to the direction of bit line extension, and the second direction is perpendicular to the direction of word line extension.

[0112] Here, the first and second regions are used to house the sensing amplifier circuit. Considering that the sensing amplifier circuit is connected to the bit lines, and the bit lines extend along two directions and are arranged along the first direction, to facilitate the wiring of the bit lines and the sensing amplifier circuit, such as the connection structure between the bit lines and the sensing amplifier circuit extending along the Z direction, both the first and second regions extend along the first direction. The third and fourth regions are used to house the word line driver circuit. Considering that the word line driver circuit is connected to the word lines, and the word lines extend along one direction and are arranged along the second direction, to facilitate the wiring of the word lines and the word line driver circuit, both the third and fourth regions extend along the second direction. It should be noted that the SA and WLD in the corresponding region (projected region) under the memory block can be adjusted according to actual needs. Their positional layout mainly considers the convenience of connecting with the word lines and bit lines in the memory block, while avoiding dividing the corresponding region under the memory block into too many fragments.

[0113] It is understandable that setting the corresponding SA and WLD of the memory block in the area directly below the memory block (the projected area) can reduce the total length of the bit line to the sensing amplifier circuit wiring, reduce the coupling effect, and increase the sensing window.

[0114] In other embodiments, within a storage block 4, a first region and a second region are diagonally arranged and adjacent to each other, while a third region and a fourth region are diagonally arranged and isolated from each other. The sensing amplification circuit, also referred to as sensing amplification circuit SA, comprises a first sensing portion SA1 and a second sensing portion SA2 respectively located in the first and second regions. The word line driving circuit, also referred to as word line driving circuit WLD, comprises a first driving portion WLD1 and a second driving portion WLD2 respectively located in the third and fourth regions. In some embodiments, the sum of the dimensions of the regions where the first sensing portion SA1 and the second sensing portion SA2 are located along a first direction is less than or equal to the dimension of the region boundary of a storage block 4 along the first direction. Figure 5A The diagram shows the case where the sum of the dimensions of the regions defined by the first driving section WLD1 and the second driving section WLD2 along the second direction is less than or equal to the dimension of the region boundary defined by a storage block 4 along the second direction. Figure 5A The example shown is the case where they are equal.

[0115] In some embodiments, the boundary of the first region is in contact with the boundary of the third region, and the boundary of the second region is in contact with the boundary of the fourth region; the sum of the dimensions of the boundaries of the first region and the third region along the first direction is the first dimension, and the dimension of the boundary of the storage block setting region along the first direction is the second dimension, wherein the first dimension is smaller than the second dimension.

[0116] Here, the first dimension is smaller than the second dimension, which allows for more free space to be used for external circuitry.

[0117] refer to Figure 8 In other embodiments, in the corresponding regions under a memory block 4, the first region and the second region are diagonally arranged and adjacent to each other, and the third region and the fourth region are diagonally arranged and isolated from each other. The sensing amplification circuit, also called the sensing amplification circuit SA, consists of a first sensing portion SA1 and a second sensing portion SA2 respectively arranged in the first region and the second region. The sum of the dimensions of the first sensing portion SA1 and the second sensing portion SA2 along the first direction is less than the dimension of a memory block 4 along the first direction. The word line driving circuit, also called the word line driving circuit WLD, consists of a first driving portion WLD1 and a second driving portion WLD2 respectively arranged in the third region and the fourth region. The sum of the dimensions of the first driving portion WLD1 and the second driving portion WLD2 along the second direction is less than the dimension of a memory block 4 along the second direction.

[0118] refer to Figure 9 In some embodiments, in the region corresponding to a memory block 4, both the sensing amplifier circuit SA and the word line driving circuit WLD extend along a first direction. The sensing amplifier circuit SA consists of two parts (a first sensing part SA1 and a second sensing part SA2) arranged at intervals along a second direction, and the word line driving circuit WLD is a single unit located between the first sensing part SA1 and the second sensing part SA2. The boundary of the region where the first sensing part SA1 and the second sensing part SA2 are located is smaller along the first direction than the boundary of the region where a memory block 4 is located along the first direction. The boundary of the region where the word line driving circuit WLD is located is smaller along the second direction than the boundary of the region where a memory block 4 is located along the second direction. Furthermore, the boundary of the region where the word line driving circuit WLD is located is smaller along the first direction than the boundary of the region where a memory block 4 is located along the first direction.

[0119] refer to Figure 6 and Figure 7 In some embodiments, the first semiconductor structure 100 further includes a first contact connected to a word line WL and a second contact connected to a bit line BL; both the first and second contacts are disposed on a side close to the second semiconductor structure; the second semiconductor structure 200 further includes a third contact connected to a sensing amplifier circuit and a fourth contact connected to a word line driving circuit; both the third and fourth contacts are disposed on a side close to the first semiconductor structure; the second and third contacts, and the first and fourth contacts are all connected at least through an interconnect layer located between the first and second semiconductor structures.

[0120] Here, the first contact can be understood as Figure 6 The word line connection structure 108 and the word line landing pad 104, the second contact can be understood as Figure 6The bit line contact 404, the third contact can be understood as Figure 6 The portion of the front-side metal interconnect layer connected to the sensing amplification circuit; the fourth contact can be understood as... Figure 6 The portion of the front-side metal interconnect layer connected to the word line driving circuit. The second and third contacts, and the first and fourth contacts are all connected at least through the second interconnect layer 400 located between the first and second semiconductor structures.

[0121] Here, the first contact can be understood as Figure 7 The word line connection structure 108, the second contact can be understood as Figure 7 The bit line connection structure 112, the third contact can be understood as Figure 7 The portion of the front-side metal interconnect layer connected to the sensing amplification circuit; the fourth contact can be understood as... Figure 7 The portion of the front-side metal interconnect layer is connected to the word line driving circuit. The second and third contacts, and the first and fourth contacts, are all connected via a bonding interconnect structure 500 located between the first and second semiconductor structures. In some embodiments, the first and / or second contacts may be located at the edge of the memory cell array or directly below the memory cell array.

[0122] In some embodiments, the first semiconductor structure 100 further includes a fifth contact connected to a capacitor C; the fifth contact is disposed on a side close to the second semiconductor structure; the second semiconductor structure 200 further includes a sixth contact connected to a common electrode; the sixth contact is disposed on a side close to the first semiconductor structure; the fifth and sixth contacts are connected through an interconnect layer located between the first and second semiconductor structures. In some embodiments, the fifth contact may be located at the edge of the memory cell array.

[0123] refer to Figure 6 and Figure 7 and in conjunction with references Figure 5B In some embodiments, the second semiconductor structure includes a plurality of active regions spaced apart by isolated regions; a connection structure is disposed at the boundaries of the active regions and in the isolated regions.

[0124] In some embodiments, the first substrate 202 of the second semiconductor structure 200 includes a first insulating structure 206 that separates multiple active regions, and the connection structure 204 may be disposed in the first insulating structure 206; and / or, the first substrate 202 of the second semiconductor structure 200 further includes a second insulating structure 208 that separates multiple well regions (P-wells / N-wells), and the connection structure 204 may be disposed in the second insulating structure 208. The materials and locations of the first insulating structure 206 and the second insulating structure 208 have been described previously and will not be repeated here.

[0125] Here, the connection structure 204 is arranged from the boundary of the active region and the isolation region to prevent the connection structure penetrating the first substrate from damaging the first control circuit or at least part of the peripheral circuit located in the first substrate.

[0126] refer to Figure 6 and Figure 7 In some embodiments, the memory device further includes power supply wiring; the power supply wiring is disposed in the first interconnect layer.

[0127] In some specific embodiments, a portion of the metal interconnects of the first interconnect layer 300 (e.g.) Figure 6 and Figure 7 The four metal layers 304 shown are used as power supply wiring, and the power supply wiring is connected to contacts (e.g. Figure 6 and Figure 7 The four-layer contact 303 shown is connected to the wiring layer corresponding to at least a portion of the peripheral circuitry. A portion of the metal interconnects of the first interconnect layer 300 (e.g., ...) Figure 6 and Figure 7 The three-layer metal layer 302 shown serves as the wiring layer for the peripheral circuit, and the wiring of the peripheral circuit is achieved through contacts (e.g. Figure 6 and Figure 7 The connection structure 204 shown is connected to at least a portion of the peripheral circuit PC.

[0128] It should be noted that in some other embodiments, the positions of the power supply wiring and peripheral circuit wiring layers can be interchanged. In other embodiments, the power supply wiring and peripheral circuit wiring layers can also be distributed in different locations on the same metal layer. In summary, the embodiments of this application do not limit the positional relationship between them.

[0129] It is understandable that supplying power from the back of the second semiconductor structure allows the power supply to be closer to the peripheral circuits and the first circuit, resulting in a smaller trace voltage drop and thus higher power utilization. Simultaneously, the metal layers on the back of the second semiconductor structure used for peripheral circuit interconnection and power bus layout reduce the total number of metal layers on the front and back sides, thereby saving on manufacturing costs and reducing the size occupied by the metal layers.

[0130] In some embodiments, the second semiconductor structure further includes: a plurality of second control circuits, one of which is connected to a memory bank; the second control circuits are distributed in the gaps between the plurality of first control circuits; the second control circuits include row decoding circuits and column decoding circuits.

[0131] Here, the second control circuit is the control circuit for the corresponding memory cell, such as the aforementioned column decoding circuit and row decoding circuit. Each memory cell corresponds to a set of column decoding circuits and row decoding circuits. In addition to placing the peripheral circuits in the aforementioned empty area, the column decoding circuits and row decoding circuits are also placed in the corresponding lower positions of the memory cell.

[0132] In some specific embodiments, the boundary of the second control circuit setting area overlaps with the boundary of the gap between adjacent memory cells.

[0133] Here, considering the convenience of wiring, each memory cell will have a set of column decoding circuits and row decoding circuits placed next to the corresponding position below the memory cell. For example, the second control circuit is placed in the position below the gap between adjacent memory cells, so that the boundary of the area where the second control circuit is placed overlaps with the boundary of the gap between adjacent memory cells.

[0134] This reduces the additional area required by the second control circuit, thereby further increasing the storage density of the memory device.

[0135] refer to Figure 6 and Figure 7 In some embodiments, the memory device further includes pads; the pads are located on the side of the first interconnect layer away from the second semiconductor structure and are electrically connected to the first interconnect layer.

[0136] Here, pad 306 can be located on the first interconnect layer and electrically connected to it. Exemplarily, pad 306 can be used as a lead-out pad for a memory device, thereby enabling electrical connection between the memory device and external devices. The material of pad 306 can be understood with reference to the materials of the aforementioned four metal layers 304. For example, the material of pad 306 may include metals that are easily patterned directly by photolithography, such as aluminum or aluminum alloys, or metals with good conductivity, such as copper or copper alloys.

[0137] refer to Figure 6 and Figure 7 In some embodiments, the memory cell array includes: multiple word lines WL extending along a first direction; multiple bit lines BL extending along a second direction; multiple semiconductor pillars arranged in an array and a memory structure corresponding to each of the multiple semiconductor pillars; the semiconductor pillars and the corresponding memory structures are stacked; wherein, the semiconductor pillars extend along a third direction and have a first end and a second end disposed opposite to each other in the third direction, the first end being connected to the bit line and the second end being connected to the memory structure; the word lines are coupled to at least one side of the semiconductor pillars; the third direction is perpendicular to both the first direction and the second direction.

[0138] Here, the semiconductor pillar can be understood as... Figure 6 or Figure 7The channel structure of the array transistor TA. The memory structure can be understood as... Figure 6 or Figure 7 The capacitor C.

[0139] In this embodiment, the semiconductor pillars extend along a third direction, meaning the channel structure of the array transistors extends along a third direction. As vertical transistors, the array transistors are advantageous for reducing their size. The array transistors and the memory structure are stacked along a third direction, and the area of ​​a single memory cell in the memory cell array can be four times the area of ​​the array (i.e., 4F). 2 This can improve the integration of memory devices.

[0140] refer to Figure 6 and Figure 7 In some embodiments, the storage structure includes a capacitor; the capacitor C includes a cup-shaped capacitor, a cylindrical capacitor, or a pillar-shaped capacitor. Exemplarily, the cup-shaped capacitor, cylindrical capacitor, and pillar-shaped capacitor all include a bottom electrode, a top electrode, and a dielectric layer located between the bottom electrode and the top electrode. It should be noted that the bottom electrode of a capacitor is connected to the source of an array of transistors, and the top electrode of each capacitor is connected to a common electrode for grounding; the capacitor is used to store written data.

[0141] It should be noted that, when the bottom electrode areas of cup-shaped capacitors, cylindrical capacitors, and pillar-shaped capacitors are equal, the top electrode area of ​​the cylindrical capacitor is the largest, followed by the cup-shaped and pillar-shaped capacitors. Therefore, in some specific embodiments, cylindrical capacitors can be used as memory cells, which is beneficial for improving the integration density of memory devices.

[0142] In some embodiments, the multiple storage structures are arranged in a square or hexagonal pattern. For example, refer to... Figure 13A In the XY top view plane, the array layout of multiple memory structures can be arranged in a square, and the gap between the four memory structures arranged in a square is the first gap MESH1. For example, refer to... Figure 13B In the XY top-view plane, the array layout of multiple memory structures can be hexagonal, with the gap between four memory structures arranged in a hexagonal pattern being the second gap MESH2. In practical applications, multiple memory structures can also be arranged in other array layouts besides square and hexagonal arrangements. Compared to a square arrangement of multiple memory structures, a hexagonal arrangement offers higher density; for example, the second gap MESH2 is smaller than the first gap MESH1, which is beneficial for improving the integration of memory devices.

[0143] In some embodiments, reference Figure 10A and Figure 10BThe word line WL is coupled to one side of the semiconductor pillar CH, forming a single-side gate structure; or, refer to Figure 11A and Figure 11B The word line WL is coupled to both sides of the semiconductor pillar CH, forming a double-side gate structure; or, refer to Figure 12A and Figure 12B The word line WL is coupled to each side of the semiconductor pillar CH, forming a gate-all-around structure.

[0144] In some embodiments, the material of the semiconductor pillar CH may include at least one of indium gallium zinc oxide, indium zinc oxide, gallium zinc oxide, indium gallium oxide, zinc oxide, indium oxide, and gallium oxide. In some embodiments, the material of the semiconductor pillar CH includes indium gallium zinc oxide.

[0145] Understandably, indium gallium zinc oxide (IGZO) possesses characteristics such as high mobility, good uniformity, low power consumption, and low noise. Transistor channels formed using semiconductor pillars (CH) including IGZO exhibit both high field-effect mobility and high threshold voltage, resulting in superior performance. Furthermore, IGZO can be directly fabricated through processes such as deposition and is easy to process.

[0146] Secondly, embodiments of this application provide another memory device, referencing Figure 6 The memory device includes: a first semiconductor structure 100, including a memory cell array; a second semiconductor structure 200, including at least a plurality of first control circuits and at least a portion of peripheral circuits distributed in the gaps between the plurality of first control circuits; a first interconnect layer 300, located on the side of the second semiconductor structure away from the first semiconductor structure; a plurality of connection structures 204; each connection structure 204 penetrates a portion of the second semiconductor structure, with one end connected to at least a portion of the peripheral circuits in the gaps and the other end connected to the first interconnect layer; and a second interconnect layer 400, located between the first semiconductor structure 100 and the second semiconductor structure 200, and connected to both the memory cell array and the first control circuits.

[0147] Figure 6 For detailed information on the planar layout of the memory devices shown, please refer to [reference needed]. Figure 4A , Figure 4B , Figure 5A and 5BTo understand, in some embodiments, the memory cell array includes multiple memory banks, and each memory bank includes multiple memory blocks; a first control circuit is connected to a memory block, and peripheral circuits are connected to all memory banks; at least some of the peripheral circuits include multiple first portions PC1 and a second portion PC2; the boundary of the region set by the first control circuit connected to a corresponding memory block of a first portion PC1 overlaps with the boundary of the region set by the corresponding memory block; the boundary of the region set by the second portion PC2 overlaps with the boundary of the gap between adjacent memory blocks; the multiple first portions and / or second portions are connected to a first interconnect layer through multiple connection structures.

[0148] In some embodiments, the memory device further includes power supply wiring; the power supply wiring is disposed in the first interconnect layer 300.

[0149] In this embodiment, the stacked arrangement of the first semiconductor structure and the second semiconductor structure can significantly improve the storage density of the memory device. By utilizing the back-side wiring of the second semiconductor structure and connecting it to at least some peripheral circuits through the connection structure, at least some peripheral circuits can be distributed and arranged below the memory blocks of the memory cell array, directly reducing the area occupied by the peripheral circuits in the second semiconductor structure. The routing of the back-side wiring of the second semiconductor structure can realize the interconnection between the distributed peripheral circuits without interfering with the connection of the front-side wiring of the second semiconductor structure. At the same time, both the first semiconductor structure and the second semiconductor are grown on the same substrate, which can reduce the use of the growth substrate and save costs.

[0150] Thirdly, embodiments of this application provide yet another memory device, as referenced Figure 7 The memory device includes: a first semiconductor structure 100, including a memory cell array; a second semiconductor structure 200, including at least a plurality of first control circuits and at least a portion of peripheral circuits distributed in the gaps between the plurality of first control circuits; a first interconnect layer 300, located on the side of the second semiconductor structure away from the first semiconductor structure; and a third interconnect layer, a first bonding layer, a second bonding layer and a fourth interconnect layer (the third interconnect layer, the first bonding layer, the second bonding layer and the fourth interconnect layer can be referred to as the bonding interconnect structure 500) stacked together, located between the first semiconductor structure and the second semiconductor structure, and connected to both the memory cell array and the first control circuits.

[0151] Figure 7 For detailed information on the planar layout of the memory devices shown, please refer to [link / reference]. Figure 4A , Figure 4B , Figure 5A and 5BTo understand, in some embodiments, the memory cell array includes multiple memory banks, and each memory bank includes multiple memory blocks; a first control circuit is connected to a memory block, and peripheral circuits are connected to all memory banks; at least some of the peripheral circuits include multiple first portions PC1 and a second portion PC2; the boundary of the region set by the first control circuit connected to a corresponding memory block of a first portion PC1 overlaps with the boundary of the region set by the corresponding memory block; the boundary of the region set by the second portion PC2 overlaps with the boundary of the gap between adjacent memory blocks; the multiple first portions and / or second portions are connected to a first interconnect layer through multiple connection structures.

[0152] In some embodiments, the memory device further includes power supply wiring; the power supply wiring is disposed in the first interconnect layer.

[0153] In various embodiments of this application, the first semiconductor structure and the second semiconductor structure are stacked, which can significantly improve the storage density of the memory device. By utilizing the back-side wiring of the second semiconductor structure and connecting it to at least some peripheral circuits through the connection structure, at least some peripheral circuits can be distributed and arranged below the memory blocks of the memory cell array, directly reducing the area occupied by the peripheral circuits in the second semiconductor structure. The routing of the back-side wiring of the second semiconductor structure can realize the interconnection between the distributed peripheral circuits without interfering with the connection of the front-side wiring of the second semiconductor structure. At the same time, the first semiconductor structure and the second semiconductor are grown and fabricated using different substrates, which can solve the problem of mutual constraints between the process of the memory cell array and the process of the peripheral circuit, thereby shortening the development cycle of the memory device.

[0154] Fourthly, embodiments of this application provide a method for manufacturing a memory device, referring to... Figure 14 , Figure 14 This application provides a flowchart illustrating a method for fabricating a memory device; the method includes:

[0155] Step S1401: Form a first semiconductor structure; the first semiconductor structure includes a memory cell array;

[0156] Step S1402: Form a second semiconductor structure, the second semiconductor structure including at least a plurality of first control circuits and at least a portion of peripheral circuits distributed in the gaps between the plurality of first control circuits; the first semiconductor structure and the second semiconductor structure are stacked and connected;

[0157] Step S1403: Form a first interconnect layer on the side of the second semiconductor structure away from the first semiconductor structure;

[0158] Step S1404: Form a plurality of connection structures; the connection structures penetrate the second semiconductor structure, one end of which is connected to at least a portion of the peripheral circuit at the gap, and the other end is connected to the first interconnect layer.

[0159] It should be understood that Figure 14 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 14 The steps shown can be adjusted in order according to actual needs. As mentioned earlier, there can be various different relative positions between the gate (word line) and the semiconductor pillar in a memory device, and different relative positions correspond to different specific fabrication methods. In this embodiment, the two gates corresponding to two adjacent semiconductor bodies are respectively arranged back-to-back. Figure 10A , Figure 10B The example shown is a back-to-back setup.

[0160] There are various methods for forming the first semiconductor structure, the second semiconductor structure, the first interconnect layer, and the connection structure. Several methods are illustrated in the embodiments of this application. The formation process of the first semiconductor structure, the second semiconductor structure, the first interconnect layer, and the connection structure will be described in detail below with reference to the accompanying drawings.

[0161] In some implementations of steps S1401 to S1404, forming the first semiconductor structure, the second semiconductor structure, and the first interconnect layer includes: forming the second semiconductor structure on the first surface of the first substrate; forming the second interconnect layer on the second semiconductor structure; forming the first semiconductor structure on the second interconnect layer; connecting the first semiconductor structure and the second semiconductor structure through the second interconnect layer; forming the first interconnect layer on the second surface of the first substrate; the first surface and the second surface are two surfaces disposed opposite to each other along the thickness direction of the first substrate.

[0162] In some specific implementations, forming a first semiconductor structure includes: forming a plurality of bit lines extending along a second direction; forming a plurality of semiconductor pillars on the surface of the bit lines; the semiconductor pillars extending along the thickness direction of a first substrate; forming a plurality of word lines extending along a first direction; the word lines being located on at least one side of the semiconductor pillars; both the first and second directions being perpendicular to the thickness direction of the first substrate; and forming a memory structure on the surface of each semiconductor pillar away from the bit lines.

[0163] In some specific implementations, the method further includes: providing a third substrate; bonding the third substrate to the memory structure to form a bonding structure; flipping the bonding structure to expose a second surface of the first substrate; and removing the third substrate after forming a first interconnect layer on the second surface of the first substrate.

[0164] Figures 15A to 15KA cross-sectional schematic diagram of the process of forming a memory device provided in this application embodiment. Figure 1 It should be noted that, Figure 15C for Figure 15B The diagram below shows a top view of the corresponding stage; the formation process of the memory device is described in detail below with reference to the accompanying drawings.

[0165] refer to Figure 15A A first substrate 202 is provided, and a second semiconductor structure 200 is formed on a first surface of the first substrate 202. In some embodiments, the first substrate 202 may include a substrate made of semiconductor materials such as silicon, germanium, or silicon germanide; in other embodiments, the first substrate 202 may also be silicon-on-insulator or germanium-on-insulator. In some embodiments, the first substrate 202 has two surfaces disposed opposite to each other along the Z direction; the first surface may be the front side of the first substrate 202, and the second surface may be the back side of the first substrate 202.

[0166] The second semiconductor structure 200 includes at least a plurality of first control circuits and at least a portion of peripheral circuits distributed in the gaps between the plurality of first control circuits. In some embodiments, the second semiconductor structure 200 further includes a plurality of second control circuits. The peripheral circuits, first control circuits, and second control circuits can all be understood with reference to the foregoing description of these circuits. The specific composition and formation location of the second semiconductor structure 200 are described below.

[0167] In some embodiments, the memory cell array includes a plurality of memory cells, each memory cell including a plurality of memory blocks; a first control circuit is connected to a memory block, and peripheral circuits are connected to all memory cells; at least a portion of the peripheral circuits includes a plurality of first portions and a second portion; forming at least a portion of the peripheral circuits includes: forming a first portion and a first control circuit at locations in the second semiconductor structure that overlap with the setting region of each memory block; forming a second portion at locations in the second semiconductor structure that overlap with the gap between adjacent memory blocks; the first portions and / or the second portions are connected to a first interconnect layer through a plurality of connection structures.

[0168] In some specific embodiments, the first control circuit includes a sensing amplifier circuit and a word line driving circuit; the sensing amplifier circuit is connected to the bit lines in the memory block; and the word line driving circuit is connected to the word lines in the memory block.

[0169] In some specific embodiments, forming a second semiconductor structure includes: forming a sensing amplification circuit in a first region and a second region; forming a word line driving circuit in a third region and a fourth region; the first region and the second region both extend along a first direction and are offset along a second direction, the third region and the fourth region both extend along a second direction and are offset along a first direction, the first direction is perpendicular to the direction of bit line extension, and the second direction is perpendicular to the direction of word line extension.

[0170] In some specific embodiments, the boundary of the first region is in contact with the boundary of the third region, and the boundary of the second region is in contact with the boundary of the fourth region; the sum of the dimensions of the boundaries of the first region and the third region along the first direction is the first dimension, and the dimension of the boundary of the storage block setting region along the first direction is the second dimension, and the first dimension is smaller than the second dimension.

[0171] In some embodiments, the second semiconductor structure further includes a plurality of second control circuits, one of which is connected to a memory cell; forming the second semiconductor structure further includes forming at least a portion of peripheral circuitry and the plurality of second control circuits in the gaps between the plurality of first control circuits; the second control circuits include row decoding circuits and column decoding circuits. In some specific embodiments, forming the second control circuits includes forming the second control circuits at locations in the second semiconductor structure that overlap with the gaps between adjacent memory cells.

[0172] In some specific embodiments, the specific process of forming the second semiconductor structure 200 may include: first forming a P-type well region (PWell) and an N-type well region (NWell) on the first substrate 202, performing n-doping on the PWell and p-doping on the NWell respectively to form the desired semiconductor doped region; then forming a gate on the substrate surface to obtain a peripheral circuit including a peripheral transistor, a first control circuit and a second control circuit.

[0173] Continue to refer to Figure 15A A portion 400-1 of a second interconnect layer is formed on the second semiconductor structure 200. In some specific embodiments, the portion 400-1 of the second interconnect layer may include one or more metal layers and contacts of the corresponding metal layers. Figure 15A The diagram shows three metal layers and three contact layers. A portion 400-1 of the second interconnect layer is used at least for connecting transistors in the first control circuit and for bringing out the source, drain, and gate of transistors included in the first control circuit and peripheral circuitry. The portion 400-1 of the second interconnect layer includes a third contact connected to the sensing amplifier circuit and a fourth contact connected to the word line driving circuit.

[0174] refer to Figure 15BFurther, another portion 400-2 of the second interconnect layer and the bit line BL of the first semiconductor structure are formed on the second semiconductor structure 200. The bit line BL extends along the second direction, i.e., the Y direction. A portion 400-1 and another portion 400-2 of the second interconnect layer together form the second interconnect layer 400.

[0175] In some specific embodiments, another portion 400-2 of the second interconnect layer may include word line contacts, i.e., first contacts, and bit line contacts, i.e., second contacts. Figure 15B Only the bit line contact and the capacitor common electrode contact can be seen in the middle.

[0176] In some specific embodiments, the methods for forming the second interconnect layer and bit lines include, but are not limited to, first forming trenches using an etching process, and then forming a metal layer and various contacts using a deposition process.

[0177] refer to Figure 15C Multiple bit lines (BLs) extend along the second direction (Y direction) and are spaced apart along the first direction. Word line contacts (WLCTs) are located on one side of the bit line and do not interfere with it. Other contacts (QTCTs) can be located on other sides of the bit line and do not interfere with the bit line or word line. It should be noted that... Figure 15C It is not with Figure 15B The corresponding view along the Z direction is only the view along the Z direction of the manufacturing stage corresponding to 15B. Figure 15C The positional relationships between bit lines, word line contacts, and other contacts shown are for illustrative purposes only and are not intended to limit the positional relationships between bit lines, word line contacts, and other contacts in the embodiments of this application.

[0178] refer to Figure 15D A first dielectric layer is formed on the surface of the bit line BL, and a first groove 151 is formed in the first dielectric layer. The first groove 151 is arranged in an array along a first direction and a second direction. In some specific embodiments, the material of the first dielectric layer includes, but is not limited to, silicon oxide, and the method of forming the dielectric layer includes, but is not limited to, deposition processes, more specifically, physical vapor deposition, chemical vapor deposition, etc. In some specific embodiments, the method of forming the groove 151 includes, but is not limited to, dry etching processes.

[0179] refer to Figure 15E A semiconductor material layer is formed on the sidewalls and bottom of the first groove 151. At least a portion of the semiconductor material layer at the bottom is removed to expose the surface of the bit line. The remaining semiconductor material layer forms a semiconductor pillar 152. The semiconductor pillar 152 may include a semiconductor body 152-1 extending along the Z direction and optionally a semiconductor attachment 152-2 extending along the Y direction. A second groove 153 is formed on the first groove 151 where the semiconductor pillar 152 is formed. The second groove 153 extends along the X direction.

[0180] In some specific embodiments, the material of the semiconductor material layer may include at least one of indium gallium zinc oxide, indium zinc oxide, gallium zinc oxide, indium gallium oxide, zinc oxide, indium oxide, and gallium oxide. The method of forming the semiconductor material layer includes, but is not limited to, a deposition process. The method of removing at least a portion of the bottom semiconductor material layer and forming the second trench includes, but is not limited to, a dry etching process.

[0181] refer to Figure 15F A dielectric material layer is formed in the second groove 153, and the dielectric material layer is etched back to form a second dielectric layer 154. The top surface of the second dielectric layer 154 is lower than the top surface of the semiconductor pillar 152. A gate dielectric material layer 155, a gate material layer 156, and a dielectric material layer are sequentially formed on the top surface of the second dielectric layer 154 and the sidewall of the second groove 153.

[0182] In some specific embodiments, the dielectric material layer is made of materials including, but not limited to, silicon oxide; the gate dielectric material layer 155 is made of materials including, but not limited to, high-dielectric materials; and the gate material layer 156 is made of materials including, but not limited to, tungsten. The methods for forming the dielectric material layer, the gate dielectric layer 155, and the gate material layer 156 include, but are not limited to, deposition processes.

[0183] refer to Figure 15G A portion of the gate dielectric material layer 155 and gate material layer 156 on the top surface of the second dielectric layer 154 is removed, and a portion of the gate dielectric material layer 155 and gate material layer 156 covering the sidewalls of the second recess is etched back to form the gate dielectric layer 157 and gate 158, i.e., word lines WL. Multiple word lines extend along a first direction and are spaced apart along a second direction. The top surface of the gate dielectric layer 157 and the top surface of the gate 158 are lower than the top surface of the semiconductor pillar 152. In some specific embodiments, the methods for removing the top surface of the second dielectric layer 154 and etching back the portion of the gate dielectric material layer 155 and gate material layer 156 on the sidewalls of the second recess include, but are not limited to, dry etching.

[0184] It should be noted that some other essential processes, such as doping the two ends of the semiconductor pillar 152 extending along the Z direction after its formation to form the source and drain, are omitted here. Based on this, the semiconductor pillar 152 is used to form the transistor TA.

[0185] refer to Figure 15H , Figure 15H Is with Figure 15G The corresponding sectional view along section ZX. Figure 15H The text line can be seen contacting WLCT. (See reference.) Figure 15IA memory structure 159 is formed on the surface of each semiconductor pillar 152 away from the bit line. In some embodiments, the memory structure 159 may be a capacitor. In some implementations, the capacitor includes a cup-shaped capacitor, a cylindrical capacitor, or a pillar-shaped capacitor. In some implementations, multiple capacitors are arranged in a square or hexagonal pattern. The specific shape of the capacitor can be understood by referring to the aforementioned capacitor shapes. The methods for forming capacitors are relatively mature and will not be elaborated here.

[0186] It should be noted that, Figure 15H and 15H The number of semiconductor pillars 152 is for illustrative purposes only, intended to show the general appearance of each process, and the number of semiconductor pillars 152 may not be shown equidistantly. Reference Figure 15J A dielectric material layer is filled, and a third substrate 302 is bonded to the dielectric material layer to form a bonding structure. It should be noted that the third substrate 302 serves as a carrier substrate. The third substrate only needs to be firmly bonded to the dielectric material layer; electrical connection is not required.

[0187] refer to Figure 15K The bonding structure is flipped to expose the second surface of the first substrate 202, i.e., the back side of the first substrate. The front side of the first substrate includes multiple active regions spaced apart by isolated regions. Starting from the back side of the first substrate, a connection structure 204 is formed along the Z direction at the boundaries of the active regions (which can be understood as the edges of the active regions) and in the isolated regions, penetrating the first substrate. Next, a first interconnect layer 300 is formed on the back side of the first substrate 202, and wiring layers and power supply wiring for connecting at least a portion of the peripheral circuitry are formed in the first interconnect layer 300. A pad 306 electrically connected to the first interconnect layer is formed on the side of the first interconnect layer away from the second semiconductor structure. In some specific embodiments, the connection structure 204 can be implemented using through-silicon via (TSV) technology.

[0188] In some embodiments, the third substrate 302 may be selectively removed in subsequent processes.

[0189] Here, a method of fabricating a memory device is completed, in which the first semiconductor structure and the second semiconductor are both grown on the same substrate, namely the first substrate 202, which reduces the use of growth substrate and saves costs.

[0190] In some implementations of steps S1401 to S1404, forming the first semiconductor structure, the second semiconductor structure, and the first interconnect layer includes: forming the second semiconductor structure on the first surface of the first substrate; sequentially forming a third interconnect layer and a first bonding layer on the second semiconductor structure; forming the first semiconductor structure on the second substrate; sequentially forming a fourth interconnect layer and a second bonding layer on the first semiconductor structure; bonding the first bonding layer and the second bonding layer; connecting the first semiconductor structure and the second semiconductor structure through the third interconnect layer, the first bonding layer, the second bonding layer, and the fourth interconnect layer; forming the first interconnect layer on the second surface of the first substrate; the first surface and the second surface are two surfaces disposed opposite each other along the thickness of the first substrate.

[0191] In some specific embodiments, forming a first semiconductor structure includes: forming a plurality of memory structures on a second substrate; forming a semiconductor pillar on a surface of each memory structure away from the second substrate; the semiconductor pillar extending along the thickness direction of the second substrate; forming a plurality of word lines extending along a first direction; the word lines being located on at least one side of the semiconductor pillar; forming bit lines on the surface of the semiconductor pillar away from the memory structure; the bit lines extending along a second direction; both the first and second directions being perpendicular to the thickness direction of the second substrate.

[0192] Figures 16A to 16D A cross-sectional schematic diagram of the process of forming a memory device provided in this application embodiment. Figure 2 The formation process of the memory device will be described in detail below with reference to the accompanying drawings.

[0193] refer to Figure 16A A first substrate 202 is provided, and a second semiconductor structure 200 is formed on a first surface of the first substrate 202. The first substrate 202 may refer to the aforementioned... Figure 15A The description in the previous text is for reference only and will not be repeated here. The composition of the second semiconductor 200, the location of each component, and the specific formation method can be found in the preceding text. Figure 15A The descriptions in the text are for reference only and will not be repeated here.

[0194] Continue to refer to Figure 16A A third interconnect layer and a first bonding layer are sequentially formed on the second semiconductor structure 200. In some embodiments, the third interconnect layer 161 may include one or more metal layers and contacts of the corresponding metal layers. Figure 16A The diagram shows three metal layers and three contact layers. The first bonding layer may include a first bonding contact 502.

[0195] In some specific embodiments, the methods for forming the third interconnect layer and the first bonding layer include, but are not limited to, first forming trenches using an etching process, and then forming a metal layer and various contacts or bonding contacts using a deposition process.

[0196] Continue to refer to Figure 16B A second substrate 102 is provided, and a first semiconductor structure 100 is formed on the second substrate 102. Forming the first semiconductor structure 100 may specifically include: forming a plurality of memory structures 159 on the second substrate 102; forming a semiconductor pillar 152 on the surface of each memory structure away from the second substrate; the semiconductor pillars extending in the direction of the thickness of the second substrate and in the Z-direction; forming a plurality of word lines WL extending in a first direction, i.e., the X direction, on at least one side of the semiconductor pillar 152; and forming a bit line BL extending in a second direction, i.e., the Y direction, on the surface of the semiconductor pillar away from the memory structure.

[0197] In some specific embodiments, the storage structure 159 may be a capacitor. In some specific embodiments, the capacitor includes a cup-shaped capacitor, a cylindrical capacitor, or a pillar-shaped capacitor. In some specific embodiments, multiple capacitors are arranged in a square or hexagonal pattern. The specific shape of the capacitor can be understood by referring to the aforementioned capacitor shapes. The methods for forming capacitors are relatively mature and will not be elaborated here.

[0198] In some specific embodiments, the specific method of forming the semiconductor pillar 152 and the word line WL can be described in the parameters described above. Figures 15D to 15F The description in the text is for reference only and will not be repeated here. It should be noted that the bit lines here are formed on the surface of the semiconductor pillar 152 after the semiconductor pillar 152 is formed.

[0199] It should be noted that some other essential processes, such as doping the two ends of the semiconductor pillar 152 extending along the Z direction after its formation to form the source and drain, are omitted here. Based on this, the semiconductor pillar 152 is used to form the transistor TA.

[0200] Continue to refer to Figure 16B A fourth interconnect layer 164 and a second bonding layer are sequentially formed on the first semiconductor structure. In some embodiments, the fourth interconnect layer may include one or more interconnect layers. Figure 16B The diagram shows one metal layer and one contact layer. The second bonding layer may include a second bonding contact 504.

[0201] In some specific embodiments, the methods for forming the fourth interconnect layer and the second bonding layer include, but are not limited to, first forming trenches using an etching process, and then forming a metal layer and various contacts or bonding contacts using a deposition process.

[0202] It should be noted that, Figure 16A The illustrated process and Figure 16B The illustrated processes can be performed one after another or together, and the implementation of this application does not restrict their manufacturing order.

[0203] refer to Figure 16C The first bonding layer and the second bonding layer are bonded together, and the specific bonding method includes, but is not limited to, hybrid bonding. The first semiconductor structure and the second semiconductor structure are electrically connected through the third interconnect layer, the first bonding layer, the second bonding layer, and the fourth interconnect layer.

[0204] refer to Figure 16D The front side of the first substrate 202 includes multiple active regions spaced apart by isolated regions. Starting from the back side of the first substrate 202, a connection structure 204 is formed along the Z direction at the boundaries of the active regions (which can be understood as the edges of the active regions) and in the isolated regions, penetrating the first substrate. Next, a first interconnect layer 300 is formed on the back side of the first substrate 202, and wiring layers and power supply wiring for connecting at least a portion of the peripheral circuitry are formed in the first interconnect layer 300. A pad 306 electrically connected to the first interconnect layer is formed on the side of the first interconnect layer away from the second semiconductor structure. In some specific embodiments, the connection structure 204 may be implemented using through-silicon via (TSV) technology.

[0205] Here, another method of manufacturing memory devices has been completed, in which the first semiconductor structure and the second semiconductor are grown on different substrates. This can solve the problem of mutual constraints between the process of the memory cell array and the process of the peripheral circuit, thereby shortening the development cycle of memory devices.

[0206] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0207] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A memory device, characterized in that, include: A first semiconductor structure, including a memory cell array; The second semiconductor structure includes at least a plurality of first control circuits and at least a portion of peripheral circuits distributed in the gaps between the plurality of first control circuits; The first semiconductor structure and the second semiconductor structure are stacked and connected; The first interconnect layer is located on the side of the second semiconductor structure that is away from the first semiconductor structure; Multiple connection structures; the connection structure penetrates a portion of the second semiconductor structure, one end of which is connected to at least a portion of the peripheral circuit at the gap, and the other end is connected to the first interconnect layer.

2. The memory device according to claim 1, characterized in that, The memory device further includes a second interconnect layer located between the first semiconductor structure and the second semiconductor structure, the first semiconductor structure and the second semiconductor structure being connected through the second interconnect layer.

3. The memory device according to claim 1, characterized in that, The memory device further includes a third interconnect layer, a first bonding layer, a second bonding layer, and a fourth interconnect layer, which are stacked between the first semiconductor structure and the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure are connected through the third interconnect layer, the first bonding layer, the second bonding layer, and the fourth interconnect layer.

4. The memory device according to any one of claims 1 to 3, characterized in that, The storage cell array includes multiple storage cells, and each storage cell includes multiple storage blocks; a first control circuit is connected to one of the storage blocks, and the peripheral circuit is connected to all storage cells; the at least part of the peripheral circuit includes multiple first parts and one second part. The boundary of the first control circuit setting area, which is connected to a corresponding memory block, overlaps with the boundary of the corresponding memory block setting area; the boundary of the second part setting area overlaps with the boundary of the gap between adjacent memory blocks; and multiple first parts and / or second parts are connected to the first interconnect layer through the multiple connection structures.

5. The memory device according to claim 4, characterized in that, The first control circuit includes a sensing amplifier circuit and a word line driving circuit; The sensing amplification circuit is connected to the bit lines in the memory block; the word line driving circuit is connected to the word lines in the memory block.

6. The memory device according to claim 5, characterized in that, The sensing amplification circuit connected to the memory block is located in the first and second regions; the word line driving circuit connected to the memory block is located in the third and fourth regions. The first region and the second region both extend along a first direction and are staggered along a second direction. The third region and the fourth region both extend along the second direction and are staggered along the first direction. The first direction is perpendicular to the direction in which the bit line extends, and the second direction is perpendicular to the direction in which the word line extends.

7. The memory device according to claim 6, characterized in that, The boundary of the first region is in contact with the boundary of the third region, and the boundary of the second region is in contact with the boundary of the fourth region; The sum of the dimensions of the boundary of the first region and the boundary of the third region along the first direction is the first dimension, and the dimension of the boundary of the storage block setting region along the first direction is the second dimension, wherein the first dimension is smaller than the second dimension.

8. The memory device according to claim 5, characterized in that, The first semiconductor structure further includes a first contact connected to the word line and a second contact connected to the bit line; both the first contact and the second contact are disposed on a side close to the second semiconductor structure. The second semiconductor structure further includes a third contact connected to the sensing amplification circuit and a fourth contact connected to the word line driving circuit; both the third contact and the fourth contact are disposed on a side close to the first semiconductor structure. The second contact and the third contact, as well as the first contact and the fourth contact, are all connected at least through an interconnect layer located between the first semiconductor structure and the second semiconductor structure.

9. The memory device according to any one of claims 1 to 3, characterized in that, The second semiconductor structure includes a plurality of active regions spaced apart by isolated regions; the connection structure is disposed at the boundaries of the active regions and in the isolated regions.

10. The memory device according to any one of claims 1 to 3, characterized in that, The memory device also includes power supply wiring; the power supply wiring is disposed in the first interconnect layer.

11. The memory device according to claim 5, characterized in that, The second semiconductor structure further includes: a plurality of second control circuits, one of which is connected to one of the memory cells; the second control circuits are distributed in the gaps between the plurality of first control circuits; The second control circuit includes a row decoding circuit and a column decoding circuit.

12. The memory device according to claim 11, characterized in that, The boundary of the second control circuit setting area overlaps with the boundary of the gap between adjacent storage cells.

13. The memory device according to any one of claims 1 to 3, characterized in that, The memory device also includes pads; The pad is located on the side of the first interconnect layer away from the second semiconductor structure and is electrically connected to the first interconnect layer.

14. The memory device according to any one of claims 1 to 3, characterized in that, The storage cell array includes: Multiple letter lines extending along the first direction; Multiple bit lines extending along the second direction; A plurality of semiconductor pillars arranged in an array and a memory structure corresponding to each of the plurality of semiconductor pillars; the semiconductor pillars and the corresponding memory structures are stacked on top of each other; The semiconductor pillar extends along a third direction and has a first end and a second end disposed opposite to each other in the third direction. The first end is connected to the bit line and the second end is connected to the memory structure. The word line is coupled to at least one side of the semiconductor pillar. The third direction is perpendicular to both the first direction and the second direction.

15. The memory device according to claim 14, characterized in that, The storage structure includes a capacitor; the capacitor includes a cup-shaped capacitor, a cylindrical capacitor, or a pillar-shaped capacitor.

16. The memory device according to claim 14, characterized in that, The multiple storage structures are arranged in a square or hexagonal pattern.

17. The memory device according to claim 14, characterized in that, The word line is coupled to one side of the semiconductor pillar; Alternatively, the word line is coupled to both sides of the semiconductor pillar that are opposite to it; Alternatively, the word line is coupled to each side of the semiconductor pillar.

18. The memory device according to claim 14, characterized in that, The semiconductor pillar is made of indium gallium zinc oxide.

19. The memory device according to any one of claims 1 to 3, characterized in that, The memory device includes dynamic random access memory.

20. A memory device, characterized in that, include: A first semiconductor structure, including a memory cell array; The second semiconductor structure includes at least a plurality of first control circuits and at least a portion of peripheral circuits distributed in the gaps between the plurality of first control circuits; The first interconnect layer is located on the side of the second semiconductor structure that is away from the first semiconductor structure; Multiple connection structures; each connection structure penetrates a portion of the second semiconductor structure, with one end connected to at least a portion of the peripheral circuitry at the gap, and the other end connected to the first interconnect layer; The second interconnect layer is located between the first semiconductor structure and the second semiconductor structure, and is connected to both the memory cell array and the first control circuit.

21. The memory device according to claim 20, characterized in that, The storage cell array includes multiple storage cells, and each storage cell includes multiple storage blocks; a first control circuit is connected to one of the storage blocks, and the peripheral circuit is connected to all storage cells; the at least part of the peripheral circuit includes multiple first parts and one second part. The boundary of the region set by the first control circuit, which is connected to a corresponding memory block, overlaps with the boundary of the region set by the corresponding memory block; the boundary of the region set by the second part overlaps with the boundary of the gap between adjacent memory blocks; and multiple first parts and / or second parts are connected to the first interconnect layer through the multiple connection structures.

22. The memory device according to claim 20, characterized in that, The memory device also includes power supply wiring; the power supply wiring is disposed in the first interconnect layer.

23. A memory device, characterized in that, include: A first semiconductor structure, including a memory cell array; The second semiconductor structure includes at least a plurality of first control circuits and at least a portion of peripheral circuits distributed in the gaps between the plurality of first control circuits; The first interconnect layer is located on the side of the second semiconductor structure that is away from the first semiconductor structure; The third interconnect layer, the first bonding layer, the second bonding layer, and the fourth interconnect layer, which are stacked together, are located between the first semiconductor structure and the second semiconductor structure, and are connected to both the memory cell array and the first control circuit.

24. The memory device according to claim 23, characterized in that, The storage cell array includes multiple storage cells, and each storage cell includes multiple storage blocks; a first control circuit is connected to one of the storage blocks, and the peripheral circuit is connected to all storage cells; the at least part of the peripheral circuit includes multiple first parts and one second part. The boundary of the region set by the first control circuit, which is connected to a corresponding memory block, overlaps with the boundary of the region set by the corresponding memory block; the boundary of the region set by the second part overlaps with the boundary of the gap between adjacent memory blocks; and multiple first parts and / or second parts are connected to the first interconnect layer through the multiple connection structures.

25. The memory device according to claim 23, characterized in that, The memory device also includes power supply wiring; the power supply wiring is disposed in the first interconnect layer.

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