Radiation-enhanced bipolar transistor
By introducing a lightly doped second emitter region and a multilayer doped structure into the bipolar transistor, the gain attenuation problem caused by radiation is solved, and the gain stability and current efficiency are improved in high-radiation environments.
Patent Information
- Application Number
- CN202511008055.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2016-06-25
- Filing Date
- 2017-06-16
- Publication Date
- 2025-10-31
AI Technical Summary
Radiation-induced gain degradation and enhanced low-dose-rate radiation (ELDRS) problems in bipolar transistors, especially in high-radiation environments, have made it difficult for existing technologies to effectively improve the radiation hardening performance of transistors.
A bipolar transistor structure was designed, including a lightly doped second emitter region and a multilayer doped structure, which enhances the robustness to radiation by reducing the formation of interface traps and inversion regions, and combines TEOS or nitrogen passivation technology to reduce the hydrogen injection effect.
It improves the gain stability of transistors under high-dose and low-dose radiation, reduces current demand, enhances resistance to ionizing radiation, and improves heavy ion collision tolerance under reverse bias conditions.
Smart Images
Figure CN120882016A_ABST
Abstract
Description
[0001] This application is a divisional application of Chinese patent application 201710458049.5 entitled "Radiation-Enhanced Bipolar Transistor", filed on June 16, 2017. Background Technology
[0002] Radiation-hardened electronic circuits are required for various applications where systems and circuits are exposed to radiation. Example applications include satellites and other spacecraft, aircraft, medical devices (such as X-ray devices), and nuclear power plants. In such applications, radiation can reduce the gain of bipolar transistors. Radiation hardening of electronic circuits is quantified using the “total ionizing dose” or “total radiation dose” (TID), a measure of the number of protons or heavy ions applied to a circuit or system. Ionizing radiation induces electron-hole pairs in silicon dioxide (SiO2). Protons (heavy ions) are released in the oxide, and protons or holes are transported toward the silicon-oxygen interface in the presence of a bias field, resulting in interface traps at the interface. At high dose rates, there is a high production of electron-hole pairs (charge production). A positive voltage pushes holes toward the interface while flushing away electrons. The accumulation of holes at the interface forms a positive charge barrier and repels generated protons. This keeps protons away from the interface and slows the formation of interface states, while promoting recombination in the oxide. Low dose rates correspond to reduced electron-hole pair generation. In this scenario, the positive voltage pushes holes toward the interface and flushes away electrons in the same manner as at high dose rates, but the accumulation of trapped holes is very low. The repulsive force of the trapped holes is low enough to allow the generated protons to move to the interface and form an interface state. Interface traps can adversely affect the operation of bipolar transistors by reducing the gain β or Hfe. Furthermore, some circuits, such as bipolar transistors, suffer from enhanced low-dose-rate radiation (ELDRS) effects. Specifically, the transistor gain reduction effect can be lower at high radiation dose rates than at more moderate radiation levels. Total dose radiation causes charge production in SiO2 and allows for the formation of interface traps under low dose rate conditions. It also creates hole traps in the oxide covering the base-emitter junction, leading to additional base-emitter leakage. Both effects contribute to the decrease in transistor gain, and therefore require more base current for the same collector current.
[0003] Furthermore, the gain improvement in transistors can be increased with the amount of hydrogen used in the manufacturing process. For example, nitride passivation of the top metallization layer in integrated circuit (IC) manufacturing uses ammonia (NH3) + silane (SiH4), where 11 hydrogen atoms are released to form a single molecule of Si3NH4. Tetraethyl orthosilicate (TEOS) can be used instead of passivating the top metallization layer because TEOS does not use ammonia and does not generate hydrogen during the formation of SiO2. However, TEOS passivation is not as good as nitride passivation. Therefore, improved integrated circuits and bipolar transistors are desired for applications involving radiation exposure without requiring low-hydrogen manufacturing techniques. Summary of the Invention
[0004] The disclosed examples include integrated circuits and vertically or laterally mounted bipolar transistors having a first region of a first conductivity type in a substrate, a collector region of a second conductivity type disposed in the substrate, and a base region of the first conductivity type extending into the first region. A first emitter region of the second conductivity type extends into the first region, and the first emitter region includes a side portion spaced apart from and facing the base region. A second emitter region of the second conductivity type extends downward into the first region and is adjacent to the top surface of the first emitter region and the upper portion of the first side portion. The second emitter region is lightly doped than the first emitter region to mitigate surface effects and gain degradation caused by hydrogen injection from radiation in the most sensitive region near the emitter-base junction region.
[0005] Further disclosed examples include a method of fabricating a bipolar transistor, the method comprising implanting a dopant of a first conductivity type into a semiconductor substrate to form a first region extending downward from a top surface of the substrate; implanting a dopant of the first conductivity type to form a base region extending downward from the top surface into the first region and adjacent to the top surface; and implanting a dopant of a second conductivity type to form a first emitter region including a first side portion spaced apart from and facing the base region. The method further comprises implanting a dopant of the second conductivity type to form a second emitter region extending downward into the first region, the second emitter region being adjacent to the top surface and adjacent to the upper portion of the first side portion of the first emitter region, the second emitter region having a fourth doping concentration less than a third doping concentration. Attached Figure Description
[0006] Figure 1 This is a partial cross-sectional side view of an integrated circuit with a radiation-hardened lateral NPN bipolar transistor, wherein the bipolar transistor has a first base region and a second base region, a first emitter region and a second emitter region, and a top-side collector.
[0007] Figure 2 This is a flowchart illustrating a method for manufacturing a bipolar transistor, including forming a first emitter region and a second emitter region.
[0008] Figures 3-8 It is based on Figure 2 A partial cross-sectional side view of a radiation-hardened NPN bipolar transistor manufactured using the method.
[0009] Figure 9 This is a flowchart illustrating alternative steps for forming the first and second emitter regions of a bipolar transistor.
[0010] Figures 10-13 It is based on Figure 9 A partial cross-sectional side view of a radiation-hardened NPN bipolar transistor subjected to manufacturing processes to form a first emitter region and a second emitter region.
[0011] Figure 14 This is a flowchart illustrating an alternative scheme for forming the first and second emitter regions of a bipolar transistor.
[0012] Figures 15-18 It is based on Figure 14 A partial cross-sectional side view of a radiation-hardened NPN bipolar transistor subjected to manufacturing processes to form a first emitter region and a second emitter region.
[0013] Figure 19 This is a partial cross-sectional side view of another example integrated circuit with a radiation-hardened NPN bipolar transistor, wherein the bipolar transistor has a single base region.
[0014] Figure 20 This is a partial cross-sectional side view of another example integrated circuit with a radiation-hardened NPN bipolar transistor, wherein the bipolar transistor has a first base region, a second base region, and a bottom-side collector.
[0015] Figure 21 This is a partial cross-sectional side view of another example integrated circuit with a radiation-hardened NPN bipolar transistor, wherein the bipolar transistor has a single base region and a bottom-side collector.
[0016] Figure 22 This is a partial cross-sectional side view of another example integrated circuit with a radiation-hardened PNP bipolar transistor, wherein the bipolar transistor includes a first base region and a second base region, a first emitter region and a second emitter region, and a top-side collector. Detailed Implementation
[0017] In the accompanying drawings, similar reference numerals denote similar elements throughout, and various features are not necessarily drawn to scale. In the following discussion and in the claims, the terms "comprising," "including," "containing," "having," "with," or variations thereof are intended to encompass in a manner similar to the term "comprising," and are therefore to be interpreted as meaning "including, but not limited to...". Furthermore, the terms "coupled" or "coupled" mean to include indirect or direct electrical connections or combinations thereof. For example, if a first device is coupled to or coupled to a second device, the connection may be a direct electrical connection or an indirect electrical connection via one or more intermediate devices or connectors.
[0018] Figure 1 The diagram illustrates a radiation-hardened NPN bipolar transistor 100 laterally fabricated in substrates 102 and 104 of an integrated circuit (IC). In one example, the substrate is constructed from an N+ silicon wafer on which an epitaxial silicon layer 104 has a low (N-) doping concentration and has an upper surface or top surface 101. In another example, the substrate may include a lower silicon wafer with an upper portion having a P-conductivity type, in which, for example, an N-well is formed to fabricate the bipolar transistor 100 in an isolation region of an integrated circuit having various circuit types, such as bipolar circuits and CMOS circuits. A P-base region or first region 106 is formed in the epitaxial portion 104 of the substrate, for example, by implanting a P-type dopant (e.g., boron) to form a P-well 106 extending downward from the top surface 101 into the substrate 104. The first region 106 has a first doping concentration and is labeled "P-" in the figures. Figure 1 In the example of an NPN bipolar transistor, a first base portion and a second base portion, or base regions 108a and 108b, are formed in region 106. Base region 108 has a second doping concentration (e.g., P+) greater than the doping concentration of the first region 106. Base regions 108a and 108b extend downward from the top surface 101 into the first region 106 and are near the top surface 101.
[0019] N-type emitter structures 110 and 112 are formed in the first region 106. These emitter structures 110 and 112 include an N+ first emitter region 110 extending downwards into the first region 106 and a shallower, lighter-doped second emitter region 112. The first emitter region 110 has a third doping concentration (N+). The lightly doped second emitter region 112 has a fourth doping concentration (N-) less than the third doping concentration of the first emitter region 110. The first emitter region 110 is adjacent to the top surface 101 and extends downwards into the first region 106 to a depth 110D. Figure 1 In the example, the first emitter region 110 includes a first side face that is spaced apart from and faces the first base region 108a (in Figure 1The left side of the first base region 108b, and the opposite second side of the second base region 108b, which is separated from and faces the second base region 108b. Figure 1 (Right side of the image). In some examples, the second emitter region 112 is formed as a ring around the upper side of the first emitter region 110, and this region 112 is adjacent to the top surface 101 of the epitaxial layer 104 of the substrate. The second emitter region 112 is adjacent to the top surface 101 and extends downward into the first region 106 to a second depth 112D, the second depth 112D being less than the first depth 110D of the first emitter region 110. In this example, emitter regions 110 and 112 are located at... Figure 1 In the view, the first base region 108a and the second base region 108b extend inward and outward along the two sides of the emitter regions 110 and 112. In some examples, the first base region 108a or the second base region 108b may be omitted, for example, as shown below. Figure 19 and Figure 21 As shown, the NPN transistor includes a single base structure. In other examples, the single base structure 108 may be formed to surround the emitter regions 110, 112. In these examples, the second emitter region 112 may (but does not necessarily) extend integrally along one or more sides of the first emitter region 110 facing the base region 108.
[0020] Transistor 100 further includes an N-type collector region 114 (in Figure 1 (Indicated by "N+"). The collector region 114 extends downward in the top surface 101 into the substrate 104. Furthermore, in Figure 1 In this lateral NPN transistor 100, the collector region 114 is laterally separated from the first region 106. This lateral NPN transistor design allows for a top-side collector contact. In other examples, such as those below... Figure 20 and Figure 21 As shown, the collector region consists of an N-epipolar region 104 below the first region 106 and / or an N+ semiconductor portion 102 of the substrate.
[0021] Emitter structures 110 and 112 enhance the robustness of NPN transistor 100 against radiation effects. In particular, compared to conventional bipolar transistor designs, transistor 100 has improved immunity to gain degradation in the presence of TID radiation, including mitigation and avoidance of ELDRS effects. For example, a conventional lateral NPN bipolar transistor without a lightly doped second emitter region is subject to an inversion region along the upper emitter-base junction due to charge trapping and interface trapping at and near the interface above the base region. This leads to gain degradation and increased leakage. In particular, under ionizing radiation, the inversion region can appear at or near the interface with the base oxide, above the emitter-base junction. Typically, emitter diffusion is not a sharp rectangle, but rather rounded or gradually varying, due to implantation and doping concentration. This can behave as if multiple parallel NPN transistors with different characteristics were present. In this regard, rounded implanted or diffused emitters result in different transistor gains and other performance characteristics at different base and collector current levels. In particular, the thickness of the base region is a major driver of the transistor's gain and breakdown voltage performance.
[0022] The disclosed emitter structures 110, 112 mitigate the effects of surface inversion regions to provide a radiation-hardened robust bipolar transistor 100. A lightly doped emitter region 112 (LDE) is provided in the transistor 100 to mitigate or avoid the formation of undesirable emitter-base depletion regions, and the transistor performance characteristics can be tuned by the properties of the first emitter region 110. Adding one or more lightly doped second emitter regions 112 improves surface effects caused by hydrogen ion injection from ionizing radiation and thus minimizes service inversion. Therefore, the first emitter region 110 and the second emitter region 112 together provide improved gains, including low current Hfe or β in the presence of high or low dose radiation, and improved tolerance to heavy ion impacts (e.g., base-emitter shock ionization) under reverse bias conditions. Furthermore, as shown, the transistor 100 can be fabricated in an integrated circuit where other techniques for radiation hardening can be incorporated, including the use of TEOS or other non-hydrogen top passivation techniques. In other examples, nitrogen passivation can be used to passivate the upper metallization layer in the presence of one or more second emitter regions 112 for canceling or reducing the adverse effects of radiation exposure.
[0023] Transistor 100 also includes one or more conductive contacts 122, 124, 126 and a metallization structure with interconnecting features to provide conductivity to the base and emitter (and optionally to the collector). The contacts and metallization structure can be formed using any suitable semiconductor device fabrication technique or material. For example, contacts 122, 124, and 126 can be copper or other conductive materials formed directly or indirectly on the upper surfaces of the respective base region 108, first emitter region 110, and collector region 114, using known silicide contact formation techniques and materials. Transistor 100 can be formed within an IC as part of a larger overall circuit, in which case external conductivity of the individual base, emitter, and / or collector of transistor 100 is not required. For example, the base, emitter, and / or collector of transistor 100 can be interconnected with other devices or components of the integrated circuit via suitable vias and contacts that provide electrical connections through one or more metallization layers 130, 140, 150. In other examples, transistor 100 is formed in an integrated circuit package that provides external connections (IC pins or pads, conductive terminals, etc.) to allow the various terminals of transistor 100 to interconnect with external circuitry. For example, transistor 100 may be formed in a device such as commercially available 2N2222, 2N3700, or 2N2484 products.
[0024] like Figure 1 As shown in the example, a conductive first base contact 122a is formed above the top surface 101 immediately adjacent to (e.g., directly and / or indirectly electrically connected to) the base region 108a, and a second contact 122b is formed above the second base region 108b. Similarly, a conductive emitter contact 124 is formed above a portion of the upper surface of the first emitter region 110. A conductive collector contact 126 is formed above the top surface 101 immediately adjacent to the collector region 114 when connection from above is desired to the collector region 114. It is known that silicon dioxide or other oxide material 120 is formed between contacts 122, 124, and 126. Figure 1 The example provides three layers, including metallization layers 130, 140, and 150 progressively disposed on the top surface 101 of substrates 102 and 104. In this example, the first metallization layer, or metallization layer 130, includes a non-conductive interlayer dielectric (ILD) material 130 (such as TEOS) and conductive via structures 128 providing connections to contacts 122, 124, and 126. The second layer includes ILD material 140 and conductive contacts and VS structures 142 and 144, and the third (e.g., upper) layer includes ILD material 150 and conductive structures 152 and 154. Figure 1In some examples, the final or uppermost metallization layer or layer provides top-side connections for the base, emitter, and collector of transistor 100, although this is not necessary in all embodiments. Furthermore, the IC includes a passivation layer 160 disposed above the top layer 150. As described above, a lightly doped second emitter region 112 is used to promote immunity to gain decay through hydrogen migration to the interface between oxide 120 and the first emitter region 110 near the emitter-base junction. Therefore, the passivation layer 160 at the top of the IC can be formed using a nitrogen passivation technique comprising ammonia and silane to form a Si3NH4 material layer 160. In other examples, the passivation layer 160 comprises tetraethyl orthosilicate (TEOS) material to further promote radiation hardening of transistor 100.
[0025] Same reference Figures 2-8 , Figure 1 The integrated circuits and transistors 100 can be manufactured according to any suitable semiconductor processing technology. Figure 2 This describes an example manufacturing process or method 200 for manufacturing a bipolar transistor 100. Figures 3-8 This describes an NPN transistor 100 manufactured according to method 200. Process 200 includes providing an N+ substrate (e.g., substrate 102) at 202. At 204, using... Figure 3 The epitaxial process 300 illustrated in the diagram grows or otherwise forms an N-epitaxial layer 104 on a substrate 102. Figure 2 At position 206, a field oxide is formed and patterned to expose a first portion or first region of the upper surface 101 of the epitaxial layer 104 (e.g., ...). Figure 4 Patterned field oxide 402).
[0026] exist Figure 2 At position 208, a P-base layer or first region 106 is implanted or otherwise formed in the N-epipolar layer 104. For example, Figure 4 An implantation process 400 is illustrated for implanting a P-type dopant or impurity (e.g., boron in one example) into an exposed first region 106 of an epitaxial layer 104 on an N-substrate. This forms a first region 106 extending downward from a top surface 101, wherein the first region 106 has a first doping concentration. At 210, a thermal diffusion process can be used to diffuse the P-base layer dopant. It will be appreciated that the implantation region illustrated and described herein does not necessarily have a uniform doping concentration as a function of longitudinal depth, and that this concentration can vary along both the longitudinal and lateral directions. Furthermore, the diffusion process at 210 can result in the growth of a certain amount of oxide over the exposed upper region (not shown) of the structure.
[0027] At 220a, a first emitter region 110 and a second emitter region 112 are formed. In this example, the emitter structure is formed by implanting an N-type dopant (e.g., phosphorus) to form the first emitter region 110, which extends downward into the first region 106 and is immediately adjacent to the top surface 101. Figure 5 In this example, implantation process 500 and implantation mask 502 are used to form the first emitter region 110. Furthermore, at 223, mask 502 exposes the simultaneously implanted first region 110 and collector region 114. In other examples, collector region 114 can be formed separately. At 224, a process such as... Figure 6 The implantation process 600 and the second mask 602 shown are used to implant one or more second emitter regions 112. The implanted one or more second regions 112 extend downward into the first region 106 along one or more side edges of the first emitter region 110. In this example, a first emitter implantation mask 502 and a second emitter implantation mask 602 are used, wherein the second emitter implantation mask 602 provides a larger window than the first mask 502 to provide second emitter regions 112 extending laterally outward from the center of the implanted first emitter region 110. In one example, the implantation energy of the implantation process 500 for forming the first emitter region 110 is higher than the implantation energy of the second emitter implantation process 600. Figure 6 As shown, this provides a greater depth for the initial first emitter region than the depth of one or more second emitter regions 112. Furthermore, the implantation dose provided by the first emitter implantation process 500 is one to two orders of magnitude greater than the implantation dose of the second emitter implantation process 600. For example, in one example, the dose of the first process 500 is 10... 13 The dosage is on the order of magnitude, and the dosage of the second process 600 is 10. 11 Up to 10 12 The order of magnitude, so as to form an N-lightly doped region 112 in one example. Then, in Figure 2 226 locations in the middle, using Figure 7 The diffusion process 700 in the IC is used to diffuse the first emitter dopant and the second emitter dopant. In one example, assuming no further significant thermal processing of the IC, the diffusion process at 226 sets the depths 110D and 112D of the respective first emitter portion 110 and the second emitter portion 112, as shown. Figure 7 As shown.
[0028] Continue in Figure 2 At position 228, a P-type dopant is implanted to form base regions 108a and 108b extending downward from the top surface 101 into the first region 106 and adjacent to the top surface 101. In one example, the doping concentration of the base region 108 (P+) is greater than the doping concentration of the first region 106 (P-). Figure 8This process is illustrated by using a mask 802 with openings to form corresponding first base regions 108a and second base regions 108b via an implantation process 800. Then, at 230, annealing or other diffusion processes are performed to diffuse the base dopant into these regions 108. At 232, a base oxide (e.g., Figure 1 The oxide 120 in the middle), and at 234, it forms a contact as the emitter, base, and optionally the collector (e.g., Figure 1 Contacts 122, 124, and 126 in the middle. Figure 2 At point 236, metallization or other back-end processing is performed to provide, for example... Figure 1 The metallized structures 130, 140 and 150 shown include a passivation layer 160.
[0029] Now for reference Figures 9-13 In another example, the first emitter injection and the second emitter injection are diffused separately. Figure 9 Showing the formation Figure 1 Alternative steps 220b for the first and second emitter regions of transistor 100, and Figures 10-13 Shown in accordance with Figure 9 The method involves processing transistors 100 at various stages of the process. Figure 9 The 220b processor can replace the above. Figure 2 Process 200, treatment 220a. In Figure 9 At position 902, the first emitter region 110 is formed by implanting an N-type dopant (e.g., phosphorus) into the first layer 106. Figure 10 This process illustrates the use of a mask 1002 and an implantation process 1000 to form a first emitter region 110, and simultaneously to form a collector region 114. Figure 9 (904 in the middle). Continue at 906, using... Figure 11 The diffusion process 1100 shown diffuses the emitter dopant (e.g., and the collector dopant). At 908, an N-type dopant (e.g., ...) is implanted in the first region 106. Figure 12 The illustration shows an implantation process 1200 using a second implantation mask 1202 to form one or more second emitter regions 112. Then, at 910, using... Figure 13 The diffusion process 1300 shown diffuses the emitter dopant and the lightly doped second emitter dopant at 910.
[0030] Figures 14-18 Instructions for using process 220c ( Figure 5 ) replacement Figure 2 Another example of process 220a in process 200 forming the first emitter region and the second emitter region. In this example, Figure 14The process 220c begins with the implantation of an N-type dopant to form a first emitter region 110 in the P-layer (first region) 106. Figure 15 This process illustrates the use of a first mask 1502 with openings to form a first emitter region 110 and an implanted collector region 114 by employing an implantation process 1500 (e.g., boron dopant in one example). Figure 4 (at position 1404 in the example). Furthermore, in this example, at position 1404... Figure 14 At point 1406, use Figure 16 and Figure 17 The quad or angled implantation processes 1600a and 1600b shown form one or more second emitter regions 112. In one example, the angled implantation process 1600 is performed using the same mask 1502 used when forming the first emitter region 110. This provides one or more second implanted emitter regions 112 along the upper side of the first emitter region 110. Furthermore, as... Figure 17 As shown, in the case of using a single mask 1502, implantation processes 1600a and 1600b in one example also provide a lightly doped region 1600 along the upper side of the implanted collector region 1400. In other examples using a single region 108, the angled implantation process 1600 does not need to form lightly doped emitter regions 1200 on both sides of the first emitter region 110, and can provide a lightly doped region 1200 only along the upper side of the first emitter region 110 facing the single base region 108, or can provide a lightly doped region 1200 along both sides of the first emitter region 110 (e.g., Figure 19 and Figure 21 ).exist Figure 14 At point 1408, use Figure 18 The diffusion process 1800 shown diffuses the first emitter dopant and the second emitter dopant (emitter and LDE dopant).
[0031] Figure 19 Another example integrated circuit with a radiation-hardened NPN bipolar transistor 100 is shown, which has a single P+ base region 108 laterally disposed between emitter regions 110, 112 and a implanted collector region 114. In this case, lightly doped (e.g., N-) second emitter regions 112 are formed on both sides of the first emitter region 110. In an alternative embodiment, the single second emitter region 112 may be formed on the upper right side of the first emitter region 110 facing the single base region 108.
[0032] Figure 20Another example integrated circuit with a radiation-hardened NPN bipolar transistor 100 is shown, the bipolar transistor 100 including a first P+ base region and a second P+ base region on opposite sides of a first emitter region 110 and a second emitter region 112. In this case, as Figure 20 As schematically shown, the collector is not injected into the top side of the substrate structures 102, 104; instead, the lower N+ regions 102 and N- regions 104 provide the transistor collector. In this case, where the transistor 100 is formed in an integrated circuit with other circuit systems, the collector can be connected to other circuits (not shown) via the substrates 102, 104. If the transistor collector requires external connection, bottom-side contacts (not shown) can be formed.
[0033] Figure 21 Another example of a radiation-hardened NPN bipolar transistor 100 is illustrated. In this case, transistor 100 includes a single base region 108 and a bottom-side collector provided by an N+ substrate structure 102 and an N- substrate structure 104.
[0034] Figure 22 This illustrates a radiation-hardened lateral PNP transistor 100, wherein the conductivity types (N and P) are relative to those above. Figure 1 The NPN transistor 100 is the opposite.
[0035] In yet another non-restrictive example, in Figure 2 After the intrinsic base is formed at position 288, a second emitter region (LDE) can be formed. For example, after the intrinsic base is formed at position 228, an LDE mask is formed, and N-implantation is performed to form the second emitter region. Then, annealing is performed at position 230 to diffuse P+ non-intrinsic base dopant and N-LDE dopant.
[0036] The examples above are merely illustrative of several possible embodiments of various aspects of this disclosure, and equivalent variations and / or modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.
Claims
1. A bipolar transistor comprising: A semiconductor substrate, including a top surface; A first region of a first conductivity type extends downward from the top surface into the substrate, and the first region has a first doping concentration; A collector region of the second conductivity type is disposed in the substrate; The base region of the first conductivity type extends downward from the top surface into the first region and is adjacent to the top surface, and the base region has a second doping concentration that is greater than the first doping concentration; The first emitter region of the second conductivity type extends downward into the first region and is adjacent to the top surface. The first emitter region has a third doping concentration and includes a first side that is spaced apart from the base region and faces the base region. as well as The second emitter region of the second conductivity type extends downward into the first region, the second emitter region is adjacent to the top surface and the upper part of the first side of the first emitter region, and the second emitter region has a fourth doping concentration that is less than the third doping concentration.
2. The bipolar transistor of claim 1, further comprising: A second base region of the first conductivity type extends downward from the top surface into the first region and is adjacent to the top surface, and the second base region has the second doping concentration; The first emitter region includes a second side surface that is separated from the second base region and faces the second base region; and The second emitter region is located adjacent to the upper part of the second side of the first emitter region.
3. The bipolar transistor according to claim 2, The current collector region extends downward from the top surface into the substrate, and the current collector region is laterally spaced from the first region; and The bipolar transistor further includes: A conductive first base contact is located immediately above the top surface, adjacent to the base region. A conductive second base contact is located immediately above the top surface, adjacent to the second base region. A conductive emitter contact, which is located immediately above the top surface adjacent to the first emitter region, and A conductive collector contact is located above the top surface and immediately adjacent to the collector region.
4. The bipolar transistor of claim 2, wherein the first emitter region extends downward from the top surface into the first region to a first depth, wherein the second emitter region extends downward from the top surface into the first region to a second depth, and wherein the second depth is less than the first depth.
5. The bipolar transistor of claim 2, wherein the first conductivity type is P-type and the second conductivity type is N-type, and wherein the bipolar transistor is an NPN transistor.
6. The bipolar transistor of claim 1, wherein the first emitter region extends downward from the top surface into the first region to a first depth, wherein the second emitter region extends downward from the top surface into the first region to a second depth, and wherein the second depth is less than the first depth.
7. The bipolar transistor of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type, and wherein the bipolar transistor is an NPN transistor.
8. The bipolar transistor of claim 1, further comprising: A conductive base contact, which is located immediately above the top surface adjacent to the base region, and A conductive emitter contact is located above the top surface, immediately adjacent to the first emitter region.
9. An integrated circuit, or IC, comprising: A semiconductor substrate, including a top surface; A first region of a first conductivity type extends downward from the top surface into the substrate, and the first region has a first doping concentration; A collector region of the second conductivity type is disposed in the substrate; The base region of the first conductivity type extends downward from the top surface into the first region and is adjacent to the top surface, and the base region has a second doping concentration greater than the first doping concentration; A conductive base contact is located immediately above the top surface and adjacent to the base region. The first emitter region of the second conductivity type extends downward into the first region and is adjacent to the top surface. The first emitter region has a third doping concentration. The first emitter region includes a first side surface that is spaced apart from the base region and faces the base region. A conductive emitter contact is located immediately above the top surface, adjacent to the first emitter region. as well as The second emitter region of the second conductivity type extends downward into the first region, the second emitter region is adjacent to the top surface and the upper part of the first side of the first emitter region, and the second emitter region has a fourth doping concentration that is less than the third doping concentration.
10. The IC of claim 9, further comprising a metallization structure disposed above the top surface of the substrate, the metallization structure including a conductive structure that allows external connection to the base contact and the emitter contact.