Method for improving channel carrier mobility and semiconductor structure

Abstract

The invention discloses a method for improving channel carrier mobility and a semiconductor structure, and belongs to the field of semiconductors, and the method comprises the steps: firstly, etching a first groove in an active region of a semiconductor substrate, and then filling the first groove with a piezoelectric material to form a piezoelectric material layer; etching a second groove in the piezoelectric material layer; epitaxially extending a semiconductor material with the same type as a well region of the active region in the second groove to form a compensation semiconductor layer; preparing a gate oxide layer on the compensation semiconductor layer; and preparing a gate on the gate oxide layer. According to the semiconductor structure prepared by the method, the piezoelectric material is inserted into the two ends of the channel region, and unexpectedly, the carrier mobility of the channel region can be improved through the inverse piezoelectric effect of the piezoelectric material by utilizing a high-voltage electric field existing in the drain electrode without additionally applying voltage; and the piezoelectric material also has an insulation and isolation effect, so that the insulativity between the grid electrode and the drain electrode is further improved, and the thermal effect of carriers at the drain electrode is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors and relates to a complementary metal-oxide-semiconductor device manufacturing process technology, specifically to a method and semiconductor structure for improving channel carrier mobility. Background Technology

[0002] As the process dimensions of complementary metal-oxide-semiconductor (CMOS) devices are scaled down to deep submicron levels, the supply voltage does not decrease proportionally with the reduction in device channel length, junction depth, and gate oxide thickness, as well as the increase in substrate doping concentration. This leads to a significant increase in the transverse and longitudinal electric fields of the channel. The high electric field accelerates the movement of charge carriers, transforming them into high-energy hot carriers, which in turn causes device performance degradation. This phenomenon is generally referred to as the channel hot carrier effect (CHC).

[0003] The channel hot carrier effect occurs for the following reasons: Near the drain of a MOSFET, when the device operates at a high drain voltage (V... DS In the saturation region and the channel pinch-off region, an extremely strong transverse electric field (up to 10) is generated. 6 (On the order of V / cm). This electric field accelerates the carriers in the channel (such as electrons in an NMOS transistor), giving them high kinetic energy and turning them into hot carriers. These high-energy carriers may: Impact ionization occurs when high-energy electrons collide with lattice atoms, generating additional electron-hole pairs (secondary charge carriers); these holes are absorbed by the substrate (forming substrate current I). SUB (I) Electrons may be collected by the drain electrode.

[0004] Gate oxide injection allows some hot carriers to gain sufficient energy to overcome the Si-SiO2 barrier (~3.2 eV electrons, ~4.5 eV holes) and inject into the gate oxide layer; these trapped charges lead to a threshold voltage (V... th ) Drift, transconductance (g m (Degradation, etc.)

[0005] Interface traps generate high-energy charge carriers that disrupt the Si-SiO2 interface, creating defect traps that further affect device characteristics.

[0006] One important approach to improving the hot carrier effect in the channel is to utilize strained silicon technology. By applying stress to the channel region, the carrier mobility in the channel region can be increased, the operating voltage can be reduced, and high-energy carriers can be indirectly reduced, thereby achieving the goal of improving the hot carrier effect in the channel.

[0007] Piezoelectric materials can generate an electric field due to mechanical deformation (piezoelectric effect), and can also generate mechanical deformation due to an electric field (inverse piezoelectric effect). This inherent electromechanical coupling effect has led to the widespread application of piezoelectric materials in engineering. Since there is an electric field in complementary metal-oxide-semiconductor devices, and strained silicon technology can improve carrier mobility, the use of piezoelectric materials in complementary metal-oxide-semiconductor devices can theoretically improve channel carrier mobility, thereby improving the channel hot carrier effect.

[0008] Prior art CN116247087A discloses a trench power device with enhanced charge carrier mobility. An insulating structure is provided between the transistor gate and the sidewalls of the gate trench. This insulating structure is configured to electrically insulate the transistor gate from a channel region extending along the sidewalls of the gate trench. The insulating structure includes a piezoelectric material layer or a combination of a piezoelectric material layer and other insulating materials. Essentially, it replaces the original gate oxide layer with a piezoelectric material layer or a combination of a piezoelectric material layer and other insulating materials. It utilizes the gate electric field to generate an inverse piezoelectric effect, improving the channel carrier mobility; this has a certain effect. However, as a basic fact, the insulating properties of piezoelectric materials are generally weaker than those of traditional gate oxide dielectrics. Therefore, replacing the gate oxide layer with a piezoelectric material layer will inevitably reduce the insulating performance, even when using a highly insulating material. According to the technical specifications, a gate oxide thickness of approximately 2.5 times is required to achieve the same voltage blocking effect. This indicates that while employing strained silicon technology, this weakens the insulation function of the gate oxide layer, or necessitates increasing its thickness to meet basic requirements. Insufficient insulation of the gate oxide layer leads to gate leakage, which accelerates gate oxide aging. Localized electric field concentration causes micro-defect accumulation, ultimately resulting in dielectric breakdown (shortened lifetime). Leakage may enhance the injection of high-energy carriers into the gate oxide layer, further triggering the formation of Si-SiO2 interface traps. This negates the carrier mobility enhancement effect achieved through the inverse piezoelectric effect. Therefore, while this technology utilizes silicon straining technology for advancement, it also leaves behind technical risks. Until a piezoelectric material with excellent insulation is found, the application scenarios for this technology are very limited.

[0009] The prior art CN115020427A discloses a semiconductor structure containing transistors on an insulator-coated semiconductor wafer and its formation and operation method. Specifically, a piezoelectric material layer is set under the channel, and two electrodes are additionally set at both ends of the piezoelectric material. By applying a voltage to the two electrodes, the piezoelectric material layer is deformed. The deformed piezoelectric material layer generates stress on the channel to improve the carrier mobility of the channel. This technology is not only complex in manufacturing process, but also adds a lot of extra structures, resulting in very high manufacturing cost. Furthermore, additional voltage needs to be applied during use, resulting in high device power consumption and low reliability.

[0010] The prior art CN119497564A discloses a power device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Specifically, a first piezoelectric material is disposed above the gate to cover it, and a first electrode and a second piezoelectric material layer are disposed below the channel to replace the substrate. This technology uses the second piezoelectric material layer and the first electrode to replace the substrate, which eliminates the substrate resistance and reduces the on-resistance. On the other hand, when a voltage is applied to the first and second piezoelectric material layers, the first and second piezoelectric material layers will deform, generating an additional electric field on the gate structure, thereby improving the mobility and conductivity of charge carriers in the semiconductor structure, thus improving the switching speed and conductivity of the device. Although this technology utilizes the piezoelectric effect of piezoelectric materials to improve the carrier mobility in the channel region, it also requires additional electrodes and electric fields, which is not only structurally complex but also has high energy consumption.

[0011] It is evident that although piezoelectric materials have some applications in improving channel carrier mobility, various problems still exist. Therefore, a great deal of research is still needed on how to set up appropriate piezoelectric material layers to improve channel carrier mobility. Summary of the Invention

[0012] One objective of this invention is to provide a method for improving channel carrier mobility. This method involves inserting piezoelectric materials at specific locations in the channel using a specific process sequence. The high electric field at the drain electrode exerts stress on the channel region due to the inverse piezoelectric effect of the piezoelectric materials, thereby increasing the channel carrier mobility. Simultaneously, the piezoelectric materials also enhance the insulation of the gate oxide layer, preventing electron migration between the gate and the channel. This significantly improves the channel hot carrier effect.

[0013] Another objective of this invention is to prepare a semiconductor structure using the above-mentioned method for improving channel carrier mobility, thereby increasing the limiting operating voltage of the prepared semiconductor structure and improving its electrical performance and durability.

[0014] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: On the one hand, the present invention provides a method for improving channel carrier mobility, comprising the following steps: A semiconductor substrate is provided, on which several active regions are isolated by an isolation structure; The first groove is etched on the surface of the active region; A piezoelectric material is filled into the first groove to form a piezoelectric material layer; A second groove is etched in the piezoelectric material layer; A compensation semiconductor layer is formed by epitaxially extending a semiconductor material of the same type as the well region of the active region inside and outside the second groove. A gate oxide layer is fabricated on the compensation semiconductor layer; A gate is fabricated on the gate oxide layer.

[0015] Furthermore, the piezoelectric material includes any one or a combination of several of MoS2, AlN, AlScN, and ZnO.

[0016] Furthermore, a first groove is formed on the surface of the active region using dry etching or wet etching.

[0017] Furthermore, the process of filling the first groove with piezoelectric material includes chemical vapor deposition (CVD), physical vapor deposition (PVD), and solution methods.

[0018] Furthermore, the depth of the first groove is 10 angstroms to 2000 angstroms.

[0019] Furthermore, a second groove is formed in the piezoelectric material layer by dry etching.

[0020] Furthermore, after etching the second groove, the minimum width between the sidewall of the second groove and the sidewall of the first groove is 10 angstroms to 1500 angstroms.

[0021] Furthermore, a gate oxide layer is prepared on the compensation semiconductor layer using the furnace tube gate oxidation method, and the thickness of the prepared gate oxide layer is 10 angstroms to 1000 angstroms.

[0022] On the other hand, the present invention provides a semiconductor structure including a substrate, a well region formed in the substrate, a gate oxide layer and a gate located above the well region, a source and a drain formed in the well regions on both sides of the gate, the well region between the source and the drain being a channel region, and a piezoelectric material layer disposed between the gate oxide layer and / or the gate and the drain, the piezoelectric material layer forming stress on the channel region to improve the carrier mobility through the high electric field of the drain.

[0023] Furthermore, piezoelectric material layers are provided at both ends of the channel region.

[0024] On the other hand, the present invention provides a method for preparing a semiconductor structure, comprising the following steps: A semiconductor substrate is provided, on which several active regions are isolated by an isolation structure; The first groove is etched on the surface of the active region; A piezoelectric material is filled into the first groove to form a piezoelectric material layer; A second groove is etched in the piezoelectric material layer; A compensation semiconductor layer is formed by epitaxially extending a semiconductor material of the same type as the well region of the active region inside and outside the second groove. A gate oxide layer is fabricated on the compensation semiconductor layer; A gate is fabricated on the gate oxide layer; The source and drain electrodes are prepared to obtain a semiconductor structure.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention, by altering the process sequence, creatively inserts piezoelectric materials into one or both ends of the drain in the channel region. The unexpected technical effects are as follows: This invention not only utilizes the inverse piezoelectric effect of the piezoelectric material to improve channel carrier mobility, but also, without applying additional voltage, leverages the high-voltage electric field inherent in the drain itself to generate stress in the channel region through the inverse piezoelectric effect of the piezoelectric material, thereby improving channel carrier mobility. As the drain electric field increases, the inverse piezoelectric effect intensifies, further increasing the stress in the channel region and further enhancing the improvement in carrier mobility. Within a certain range of drain electric field, it exhibits a self-regulating effect, increasing the upper limit of the drain electric field under the same conditions, or improving device reliability. Furthermore, the piezoelectric material of this invention also provides insulation, further improving the insulation between the gate and drain, reducing the possibility of leakage, and also reducing the thermal effect on carriers at the drain. Attached Figure Description

[0026] Figure 1 This is a flowchart of the method for improving channel carrier mobility in Embodiment 1 of the present invention.

[0027] Figure 2 This is a schematic diagram of the semiconductor substrate provided in Embodiment 1 of the present invention.

[0028] Figure 3 This is a schematic diagram of a single NMOS with a first groove etched in step S200 of Embodiment 1 of the present invention.

[0029] Figure 4 This is a schematic diagram of filling the first groove with piezoelectric material in step S300 of embodiment 1 of the present invention.

[0030] Figure 5 This is a schematic diagram of the planarization of piezoelectric material before fabricating the second groove in step S400 of Embodiment 1 of the present invention.

[0031] Figure 6AThis is a schematic diagram of step S400 of Embodiment 1 of the present invention, in which the second groove is etched.

[0032] Figure 6B This is a schematic diagram of step S400 of Embodiment 1 of the present invention, which is a second embodiment of directly etching a second groove in the piezoelectric material layer.

[0033] Figure 7A This is a schematic diagram of the epitaxial semiconductor material in the second groove produced in the first embodiment of step S400 of embodiment 1 of the present invention.

[0034] Figure 7B This is a schematic diagram of the epitaxial semiconductor material in the second groove produced in the second embodiment of step S400 of embodiment 1 of the present invention.

[0035] Figure 8 This is a schematic diagram of step S500 in embodiment 1 of the present invention, in which the epitaxial semiconductor material is planarized to obtain a compensation semiconductor layer.

[0036] Figure 9 This is a schematic diagram of step S600 in embodiment 1 of the present invention, which involves preparing a gate oxide layer in the compensation semiconductor layer.

[0037] Figure 10 This is a schematic diagram of step S710 in embodiment 1 of the present invention, which involves fabricating a pseudo-gate structure on the gate oxide layer.

[0038] Figure 11 This is a schematic diagram of step S720 of embodiment 1 of the present invention, in which a dielectric layer is deposited on the gate oxide layer.

[0039] Figure 12 This is a schematic diagram of step S730 in embodiment 1 of the present invention, in which excess dielectric layer is removed by anisotropic etching process to form a gate with sidewalls.

[0040] Figure 13 To further prepare the source and drain in Embodiment 2 of the present invention, a schematic diagram of the semiconductor structure is obtained.

[0041] 100 - Semiconductor substrate; 110 - Active region; 120 - Shallow trench isolation structure; 130 - First trench; 200 - Piezoelectric material layer, 201 - Piezoelectric material, 210 - Second groove; 300 - Compensation semiconductor layer, 310 - Semiconductor material; 400-Gate oxide layer; 500 - Gate, 510 - Pseudo-gate structure, 520 - Sidewall, 521 - Dielectric layer; 610 - Source, 620 - Drain. Detailed Implementation

[0042] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention.

[0043] In the description of this invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0044] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0045] Example 1: As Figure 1 As shown, the present invention provides a method for improving channel carrier mobility, comprising the following steps: S100, A semiconductor substrate is provided, on which a plurality of active regions are isolated by an isolation structure; S200, Etch the first groove on the surface of the active region; S300: Fill the first groove with piezoelectric material to form a piezoelectric material layer; S400, Etch a second groove in the piezoelectric material layer; S500, a semiconductor material of the same type as the well region of the active region is epitaxially grown inside and outside the second groove to form a compensation semiconductor layer; S600. Prepare a gate oxide layer on the compensation semiconductor layer; S700: The gate is fabricated on the gate oxide layer.

[0046] This invention, by setting a compensating semiconductor layer, creatively inserts piezoelectric material into the end of the channel region (without completely covering the channel region in depth to meet the requirements of carrier migration in the channel region). An unexpected technical effect is that this invention does not require an additional electric field; it utilizes the high-voltage electric field of the drain to generate stress in the channel region through the inverse piezoelectric effect of the piezoelectric material, improving the carrier mobility in the channel region. When the drain electric field increases, the inverse piezoelectric effect increases, further increasing the stress generated in the channel region and further improving the carrier mobility. Within a certain range of the drain electric field, it has a self-regulating effect, and under the same conditions, it can increase the upper limit of the drain electric field or improve device reliability. In addition, the piezoelectric material of this invention also has an insulating effect, further improving the insulation between the gate and the drain, reducing the possibility of leakage, and also reducing the carrier thermal effect at the drain.

[0047] In step S100, the material of the semiconductor substrate 100 may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. The semiconductor substrate 100 may also be a multilayer structure composed of these semiconductors, or may be silicon on insulator (SOI), silicon on insulator stacked on insulator (SSOI), silicon on insulator stacked on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), etc.

[0048] The processes for forming the well region differ depending on the semiconductor material used, but this does not affect the technical problem solved by this invention. For example, when Si semiconductor material is used as the semiconductor substrate 100, such as... Figure 2 As shown, a shallow trench isolation structure 120 (STI) can be used to isolate and form the active region 110; generally, the active region 110 includes the active region of the P-type well region and the active region of the N-type well region, corresponding to NMOS (N-type field-effect transistor) and PMOS (P-type field-effect transistor), respectively, as shown. Figure 2 As shown, Figure 2 The example shows a semiconductor structure with one NMOS and one PMOS. In reality, the number of NMOS and PMOS depends on the needs of the device. Figure 2 This is for illustrative purposes only.

[0049] S200, see also Figure 3 As shown, Figure 3A schematic diagram of a single NMOS is shown. The method for etching the first groove 130 on the surface of the active region 110 can employ dry etching or wet etching. Before etching, photoresist is coated on the semiconductor substrate 100, and then the area to be etched is exposed in the active region 110 through exposure and development. Afterwards, dry etching or wet etching can be used. The etched first groove 130 is shown as... Figure 3 As shown; common dry etching methods include reactive ion etching (RIE) and deep reactive ion etching (DRIE). The depth of the first groove 130 basically determines the thickness of the subsequent piezoelectric material filling. If the piezoelectric material thickness is too small, the generated stress is insufficient, and the effect of improving the channel carrier mobility is limited. In addition, the insulation performance is also limited, resulting in a limited effect of improving the carrier thermal effect at the drain. If the depth of the first groove 130 is too large, it will affect the channel setting and squeeze the channel space. Therefore, a suitable depth of the first groove 130 can set a suitable piezoelectric material layer, thereby maximizing the function of the piezoelectric material. Therefore, the depth of the first groove 130 is selected in the range of 10 angstroms to 2000 angstroms. The depth is different for different types of devices. For example, for low-voltage devices (LV), the depth should be 10-100 angstroms; for medium-voltage devices (MV), it is generally around 100-1000 angstroms; and for high-voltage devices (HV), the depth is generally around 1000-2000 angstroms. The width or cross-sectional dimensions of the first groove 130 are not required. Generally, it should be approximately equal to the cross-sectional area of ​​the gate. That is, the orthogonal projection of the gate on the semiconductor substrate 100 is the starting region and shape of the first groove 130. Of course, whether the first groove 130 is slightly larger or smaller than the orthogonal projection of the gate does not affect the technical problem solved by the present invention, that is, it does not affect the role of the piezoelectric material in adaptively increasing the carrier migration rate in the present invention.

[0050] S300, see also Figure 4 As shown, before filling the first groove 130 with piezoelectric material 201, the photoresist etching the first groove 130 should be removed, and then the piezoelectric material layer 200 should be formed (e.g., ...). Figure 5 As shown), common piezoelectric materials 201 include MoS2 (molybdenum disulfide), AlN (aluminum nitride), AlScN (scandium-doped aluminum nitride), and ZnO (zinc oxide). Different materials may have the same or different processes. One of them or a combination of several can be used. Generally speaking, when filling, the first groove 130 needs to be completely filled, that is, the height is higher than the two sides of the first groove 130.

[0051] For example, taking MoS2 filling as an example, a chemical vapor deposition (CVD) process can be used to introduce a molybdenum precursor, such as MoO3, and a sulfur source, such as S powder, into a reaction chamber and react them at a high temperature (650℃-850℃) to generate a MoS2 material layer. The specific steps are as follows: Step 1, Precursor Placement: Place the MoO3 powder (or Mo film) in the high-temperature zone (center position). Sulfur powder is placed in the upstream low-temperature zone (about 15-20 cm away from the Mo source). The semiconductor substrate with the first groove is placed upside down in the reaction chamber of the CVD equipment, directly above the Mo source (or at the edge of the downstream high-temperature zone).

[0052] Step 2, Vacuuming: The reaction chamber was evacuated to a low vacuum (~10). -2 Torr), flush with Ar / N2 three times.

[0053] Step 3, Heating Stage: Heat to 150-200°C in the sulfur source region at a rate of 10-20°C / min (sulfur sublimation); The molybdenum source region is heated to 650-850°C (MoO3 is reduced to MoO). x (x<3); Step 4, Growth Stage: Maintain the temperature for 10-30 minutes, and the sulfur vapor reacts with MoO. x The reaction produces MoS2; Carrier gas flow rate: 50-100 sccm (low-pressure growth can reduce nucleation density); Step 5, Cooling Stage: After the semiconductor substrate filled with piezoelectric material is allowed to cool naturally to below 200°C, it can be removed.

[0054] It should be noted that after the molybdenum disulfide deposition is completed, annealing can be performed to improve the deposition quality of the piezoelectric material. Specifically, annealing is carried out at 300-400°C for 1 hour in an Ar / H2 (5%) atmosphere to reduce sulfur vacancies and improve the deposition quality of the piezoelectric material.

[0055] For example, taking AlN as a piezoelectric material, a physical vapor deposition (PVD) process can be used to generate an aluminum nitride film by sputtering or evaporating aluminum in a nitrogen environment to fill the first groove 130. Taking reactive magnetron sputtering as an example, the specific steps are as follows: Step 1: Vacuuming and Pre-sputtering The semiconductor substrate with the first groove is placed into the cavity of the PVD equipment and fixed on the heating stage (the substrate temperature is adjustable, usually 300-500°C).

[0056] Vacuumed to base pressure ≤ 5 × 10 -6 Torr (ensuring no oxygen or water vapor interference).

[0057] Pre-sputtering: Introduce Ar (20-30 sccm), pressure 2-5 mTorr.

[0058] Turn on the DC / RF power supply (100-200 W) and pre-sputter the aluminum target for 10-15 minutes (to remove oxides from the target surface).

[0059] Step 2: Reactive sputtering deposition Gas introduction: Introduce N2 (the ratio of flow rate to Ar needs to be optimized, typically N2:Ar = 1:1 to 1:4).

[0060] Maintain a working gas pressure of 2-10 mTorr (low pressure is beneficial for dense films, while high pressure increases the deposition rate).

[0061] Sputtering parameters: Sputtering power: DC 150-300 W or RF 100-200 W (to avoid target poisoning).

[0062] Substrate temperature: 300-500°C (high temperature improves crystal quality, but AlN decomposition must be avoided).

[0063] Deposition time: 1-2 hours (film thickness ~100-500 nm, deposition rate ~0.5-2 nm / min).

[0064] Step 3: Cooling and Removing the Film After deposition, the power and gas are turned off, and the mixture is allowed to cool naturally to below 150°C under vacuum.

[0065] High-purity N2 or Ar is introduced to restore normal pressure, and the sample is then removed.

[0066] In S400, there are two process paths for etching the second groove. The first implementation involves planarizing the piezoelectric filling material using CMP (chemical mechanical polishing) before etching the second groove. After planarization, as shown... Figure 5 As shown, the second groove 210 obtained by etching is as follows Figure 6A As shown; the second embodiment is a non-planarized piezoelectric material 201 on which the second groove 210 is directly etched, as shown. Figure 6BAs shown, the semiconductor material 310 is subsequently deposited and then planarized together. The etching processes for the second groove 210 using both methods are similar to those for the first groove 130. Both require coating a photoresist layer on the semiconductor substrate 100, then exposing the area to be etched (the second groove 210) through exposure and development. Dry etching or wet etching is then employed. After etching, the photoresist is cleaned off to obtain the second groove 210. The depth of the second groove 210 is generally the same as that of the first groove 130, meaning it needs to penetrate the piezoelectric material layer 200. The width or cross-sectional area of ​​the second groove 210 directly affects the amount of remaining piezoelectric material, which is the width of the piezoelectric material layer 200 inserted into the channel region. It should be noted that since this invention primarily utilizes the high electric field of the drain 620, at least one end of the channel region near the drain 620 needs to be inserted, with a width of 5 angstroms to 1000 angstroms, to meet the requirements for generating sufficient stress and insulation. Of course, for ease of manufacturing and control, piezoelectric material layers 200 can be inserted at both ends of the channel region, that is, the second groove 210 is set approximately centered relative to the first groove 130, such as... Figure 6A and Figure 6B As shown in the figure, the left and right directions represent the width. The width of the piezoelectric material on both sides determines the amount of remaining piezoelectric material, which in turn affects the inverse piezoelectric effect and the increased insulation performance of the piezoelectric material. Generally speaking, the width of the remaining piezoelectric material on one side should be 5 angstroms to 1000 angstroms. The specific value needs to be selected according to the voltage type of the device. Generally speaking, the width ratio of the second groove 210 to the first groove 130 should be selected between 4 and 8:10.

[0067] In step S500, a semiconductor material 310 of the same type as the well region of the active region 110 is epitaxially stretched inside and outside the second groove 210 to form a compensation semiconductor layer 300. Taking NMOS as an example, the well region is a P-type semiconductor material. In this embodiment, a P-type semiconductor material should be epitaxially stretched. For the first process path after planarization of the piezoelectric material 201, the epitaxial layer is as follows: Figure 7A As shown, for the second process path without planarization of piezoelectric materials, the epitaxial growth is as follows: Figure 7B As shown; the two process paths have basically the same epitaxial process. P-type semiconductor materials can be epitaxially grown by chemical vapor deposition (CVD), with silicon source being silane (SiH4) or dichlorosilane (SiH2Cl2), and doping source being trimethylborane (B(CH3)3, TMB) or diborane (B2H6). For N-type semiconductor materials, the corresponding doping source can be replaced.

[0068] After epitaxial semiconductor material 310, planarization is required (using CMP process to planarize P-type semiconductor material, or planarizing P-type semiconductor material and piezoelectric material together). After planarization, as... Figure 8 As shown, a special structure is formed with a compensation semiconductor layer 300 in the middle and piezoelectric material layers 200 at both ends. In fact, it is equivalent to inserting piezoelectric materials into the two ends of the channel region at special positions. The piezoelectric material layer 200 formed by the process of this invention can not only make full use of the high electric field of the drain 620 to generate the inverse piezoelectric effect to induce strain in the channel region and improve the mobility of channel carriers, but also improve the insulation between the gate 500 and the drain 620. Under the dual-action mechanism, it avoids the thermal effect of carriers at the drain 620 and can significantly improve the drain 620 limit voltage during device use. It has unexpected functions and effects. In addition, it also has an adaptive adjustment function. As the electric field of the drain 620 increases, the inverse piezoelectric effect will also increase, and the stress on the channel region will increase. Within a certain range, it has an adaptive adjustment function to improve the mobility of channel carriers. The technical advantages are very obvious.

[0069] It should be noted that the inverse piezoelectric effect of different piezoelectric materials has different directions. That is, under an electric field in a certain direction, some materials are under tensile strain and some materials are under compressive strain. For this invention, the strain direction required for the channel of PMOS and NMOS is also different. However, since the drain electric field direction of PMOS and NMOS is different, only one piezoelectric material needs to be selected to be applicable to both PMOS and NMOS.

[0070] In S600, the present invention uses a furnace tube gate oxidation method to prepare a gate oxide layer 400 on the compensation semiconductor layer 300, and the resulting gate oxide layer 400 is as follows: Figure 9 As shown, furnace tube gate oxidation is a common method for preparing gate oxide layers. When applied to this invention, the gate oxide layer 400 can be prepared in the region surrounded by the piezoelectric material layer, which can further improve the insulation performance of the gate oxide layer 400, increase the breakdown voltage (BV), and avoid tunneling current (Fowler-Nordheim) or direct tunneling during device use.

[0071] In S700, the gate 500 is fabricated on the gate oxide layer 400. Existing technologies can be used, for example, the present invention provides a sidewall process for fabricating the gate 500; the specific steps are as follows: S710. Using an epitaxial process, a pseudo-gate structure 510 is fabricated on the gate oxide layer 400, such as... Figure 10 As shown, the material of the pseudo-gate structure 510 can be polysilicon, high-k material, or a combination of multiple materials; For example, polycrystalline silicon is deposited on a semiconductor substrate on which a gate oxide layer 400 is prepared using a low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) process; Photoresist is coated and patterned using exposure and development techniques, while retaining the photoresist above the pseudo-gate structure 510. Excess polysilicon is removed by etching; After cleaning away the photoresist pattern, a polysilicon layer is obtained as the pseudo-gate structure 510, as shown below. Figure 10 As shown; of course, other high-K materials or combinations of high-K materials and polysilicon can also be used as pseudo-gate structures 510.

[0072] S720, an epitaxial dielectric layer 521 is formed on the polysilicon layer and the semiconductor substrate 100, such as Figure 11 As shown, the epitaxial material can be silicon nitride (Si3N4), silicon oxide (SiO2), or a combination of both; the deposition process is chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0073] S730, the dielectric layer 521 on top of the polysilicon layer and in other areas is removed by anisotropic etching, leaving the dielectric layer 521 on the sidewalls of the polysilicon layer to form sidewalls 520, thus obtaining a complete gate 500. Figure 12 As shown.

[0074] Example 2: This example provides a method for fabricating a semiconductor structure. Based on Example 1, a source 610 and a drain 620 are fabricated in the well regions on both sides of the gate 500 to obtain a semiconductor structure, as shown below. Figure 13 As shown.

[0075] Example 3: This invention also protects a semiconductor structure, such as Figure 13 As shown, the device includes a substrate, a well region formed within the substrate, a gate oxide layer 400 and a gate 500 located above the well region, a source 610 and a drain 620 formed in the well regions on both sides of the gate 500, and the well region between the source 610 and the drain 620 is a channel region. A piezoelectric material layer 200 is disposed between the gate oxide layer 400 and / or the gate 500 and the drain 620. The piezoelectric material layer 200 forms stress on the channel region to improve the carrier mobility through the high electric field of the drain 620.

[0076] The above embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Although the invention has been described in detail with reference to the embodiments, those skilled in the art should understand that various combinations, modifications, or equivalent substitutions of the technical solutions of the invention do not depart from the spirit and scope of the invention and should be covered within the scope of the claims of the invention.

Claims

1. A method for improving channel carrier mobility, characterized in that, Includes the following steps: A semiconductor substrate is provided, on which a plurality of active regions are isolated by an isolation structure; The first groove is etched on the surface of the active region; A piezoelectric material is filled into the first groove to form a piezoelectric material layer; A second groove is etched in the piezoelectric material layer; A compensation semiconductor layer is formed by epitaxially extending a semiconductor material of the same type as the well region of the active region inside and outside the second groove. A gate oxide layer is fabricated on the compensation semiconductor layer; The gate is fabricated on the gate oxide layer.

2. The method for improving channel carrier mobility according to claim 1, characterized in that, The piezoelectric material includes any one or a combination of several of MoS2, AlN, AlScN, and ZnO.

3. The method for improving channel carrier mobility according to claim 1, characterized in that, The first groove is formed on the surface of the active region by dry etching or wet etching.

4. The method for improving channel carrier mobility according to claim 1, characterized in that, The process of filling the first groove with piezoelectric material includes chemical vapor deposition, physical vapor deposition, and solution method.

5. The method for improving channel carrier mobility according to claim 1, characterized in that, A second groove is formed in the piezoelectric material layer by dry etching.

6. The method for improving channel carrier mobility according to claim 1, characterized in that, After etching the second groove, the minimum width between the sidewall of the second groove and the sidewall of the first groove is 10 angstroms to 1500 angstroms.

7. The method for improving channel carrier mobility according to claim 1, characterized in that, A gate oxide layer was prepared on the compensation semiconductor layer using the furnace tube gate oxidation method, and the thickness of the prepared gate oxide layer was 10 angstroms to 1000 angstroms.

8. A semiconductor structure comprising a substrate, a well region formed within the substrate, a gate oxide layer and a gate located above the well region, wherein a source and a drain are formed in the well regions on both sides of the gate, and the well region between the source and the drain is a channel region, characterized in that, The channel region is provided with a piezoelectric material layer at least near the drain end, and the piezoelectric material layer forms stress on the channel region to improve the carrier mobility through the high electric field of the drain.

9. A semiconductor structure according to claim 8, characterized in that, Both ends of the channel area are provided with piezoelectric material layers.

10. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A semiconductor substrate is provided, on which a plurality of active regions are isolated by an isolation structure; The first groove is etched on the surface of the active region; A piezoelectric material is filled into the first groove to form a piezoelectric material layer; A second groove is etched in the piezoelectric material layer; A compensation semiconductor layer is formed by epitaxially extending a semiconductor material of the same type as the well region of the active region inside and outside the second groove. A gate oxide layer is fabricated on the compensation semiconductor layer; A gate is fabricated on the gate oxide layer; The source and drain electrodes are prepared to obtain a semiconductor structure.

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