Semiconductor device, power module, power conversion circuit, vehicle, and method for manufacturing semiconductor device

Abstract

The invention discloses a semiconductor device, a power module, a power conversion circuit, a vehicle and a preparation method of the semiconductor device, and the semiconductor device comprises a semiconductor body which further comprises a gate trench, a source trench, a first region, a second region and a well region; the grid electrode groove is located on at least one side of the source electrode groove, the grid electrode groove is communicated with the source electrode groove, and the depth of the source electrode groove is larger than that of the grid electrode groove in the first direction; the second region is located on the bottom wall of the source trench, and a preset interval is formed between the second region and the well region in the first direction and the second direction; the grid electrode is positioned in the grid electrode groove; the insulating layer surrounds the grid electrode and comprises at least one part located on the side wall of the source electrode groove; the source electrode is located on the first surface, and at least part of the source electrode is located in the source electrode groove and makes contact with the second area; the drain electrode is located on the second surface. According to the technical scheme, the influence of the JFET effect is reduced, and the reliability of the insulating layer in the gate trench is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, a power module, a power conversion circuit, a vehicle, and a method for fabricating the semiconductor device. Background Technology

[0002] Silicon carbide (SiC) possesses excellent physical and electrical properties. Currently, semiconductor devices fabricated using SiC materials have advantages such as high current density and small cell pitch, and are widely used.

[0003] Currently, in trench-type SiC semiconductor devices, a shielding layer needs to be placed at the bottom of the trench to ensure the reliability of the gate oxide. However, the introduction of the shielding layer will introduce the JFET effect, thereby affecting the performance of the semiconductor device. Summary of the Invention

[0004] This application provides a method for fabricating semiconductor devices, power modules, power conversion circuits, vehicles, and semiconductor devices, which reduces the impact of the JFET effect and improves the reliability of the insulating layer in the gate trench.

[0005] In a first aspect, embodiments of this application provide a semiconductor device, including:

[0006] A semiconductor body includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a first region, a second region, and a well region. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The first conductivity type is different from the second conductivity type. The first surface is provided with a gate trench and a source trench. The gate trench is located on at least one side of the source trench and communicates with the source trench. The well region and the first region are located on the side of the gate trench away from the source trench. Along a first direction, the depth of the source trench is greater than the depth of the gate trench. The second region is located on the bottom wall of the source trench and is configured with a second conductivity type. The second region has a predetermined distance from the well region in both a first direction and a second direction. The first direction is perpendicular to the second direction, and the first direction is the direction from the first surface to the second surface.

[0007] The gate is located within the gate trench;

[0008] An insulating layer surrounds the gate and includes at least a portion located on the sidewall of the source trench;

[0009] The source electrode is located on the first surface, and at least a portion of the source electrode is located within the source electrode trench and in contact with the second region;

[0010] The drain electrode is located on the second surface.

[0011] Optionally, the surface of the insulating layer on the side away from the second region is flush with the first surface.

[0012] Optionally, the gate includes a first gate and a second gate, wherein the first gate and the second gate are respectively located in the gate trench on both sides of the source trench.

[0013] Optionally, the vertical projections of the first gate and the second gate on their respective gate trench sidewalls at least cover the vertical projections of the adjacent well region on the sidewalls of the gate trench.

[0014] Optionally, the bottom wall of the gate trench intersects the side wall of the source trench along the second direction, and the gate trench and the source trench form a stepped trench.

[0015] Alternatively, the bottom wall of the gate trench intersects the side wall of the source trench along a third direction, and the gate trench and the source trench form a stepped trench; the third direction intersects the second direction and the first direction respectively.

[0016] Optionally, the semiconductor body further includes a third region configured with a second conductivity type and located on a first surface of the first region away from the gate trench; wherein the ion concentration of the third region is greater than or equal to the ion concentration of the well region.

[0017] Secondly, embodiments of this application provide a power module, including a substrate and a semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device.

[0018] Thirdly, embodiments of this application provide a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction;

[0019] The power conversion circuit includes a circuit board and the semiconductor device described in any embodiment of this application, wherein the semiconductor device is electrically connected to the circuit board.

[0020] Fourthly, embodiments of this application provide a vehicle including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0021] Fifthly, embodiments of this application provide a method for fabricating a semiconductor device, comprising:

[0022] A semiconductor body is provided, comprising a first surface and a second surface disposed opposite to each other. The semiconductor body further comprises a first region, a second region, and a well region. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The first conductivity type is different from the second conductivity type. The first surface is provided with a gate trench and a source trench. The gate trench is located on at least one side of the source trench and communicates with the source trench. The well region and the first region are located on the side of the gate trench away from the source trench. Along a first direction, the depth of the source trench is greater than the depth of the gate trench. The second region is located on the bottom wall of the source trench and is configured with a second conductivity type. The second region has a predetermined distance from the well region in a first direction and a second direction. The first direction is perpendicular to the second direction, and the first direction is the direction from the first surface to the second surface.

[0023] A gate is formed within the gate trench;

[0024] An insulating layer is formed within the gate trench and at least a portion of the source trench, the insulating layer surrounding the gate;

[0025] A source electrode is formed on the first surface, and at least a portion of the source electrode is located within the source electrode trench and in contact with the second region;

[0026] Optionally, the semiconductor body includes:

[0027] An epitaxial layer is grown on one side of the substrate;

[0028] The first surface is defined as the side of the epitaxial layer away from the substrate; a well region and a first region are formed on the first surface, the first region being located on the first surface; the well region is located on the side of the first region away from the first surface; the first region is of a first conductivity type, and the well region is of a second conductivity type; the first conductivity type and the second conductivity type are different.

[0029] A first trench is formed on the first surface, and a gate structure is formed within the first trench;

[0030] A source trench is formed on the side surface of the gate structure away from the second surface. Along the first direction, the depth of the source trench is greater than the depth of the first trench. The portions of the first trench located on both sides of the source trench serve as gate trenches, and the gate structures located within the gate trenches serve as the first gate and the second gate, respectively. The vertical projections of the first gate and the second gate on their respective gate trench sidewalls at least cover the vertical projections of the adjacent well regions on the sidewalls of the gate trenches.

[0031] A second region is formed on the bottom wall of the source trench, and the second region is configured as a second conductivity type.

[0032] Optionally, an insulating layer is formed within the gate trench and at least a portion of the source trench, the insulating layer surrounding the gate, comprising:

[0033] Before forming the gate structure in the first trench, a first sub-insulating layer is formed on the sidewall and bottom wall of the first trench;

[0034] After forming a source trench on the side of the gate structure away from the second surface, a second sub-insulating layer is formed in the gate trench and the source trench. The first sub-insulating layer and the second sub-insulating layer constitute the insulating layer, and the insulating layer covers the surfaces of the first gate and the second gate.

[0035] A second trench is formed on the side of the insulating layer away from the second surface. The second trench is located between the first gate and the second gate. The bottom wall of the second trench is on the same plane as the bottom wall of the source trench. The thickness of the insulating layer between the first gate and the second trench is greater than the thickness of the insulating layer between the first gate and the sidewall of the gate trench, and the thickness of the insulating layer between the second gate and the second trench is greater than the thickness of the insulating layer between the second gate and the sidewall of the gate trench.

[0036] Optionally, after forming the first sub-insulating layer on the sidewall and bottom wall of the first trench, the process includes:

[0037] The thickness of the first sub-insulating layer is increased such that the thickness of the first sub-insulating layer not adjacent to the well region is greater than the thickness of the first sub-insulating layer adjacent to the well region.

[0038] While increasing the thickness of the first sub-insulating layer, a high-k material is deposited to form a composite first sub-insulating layer.

[0039] The semiconductor device provided in this application provides a gate trench and a source trench in the semiconductor body. The gate trench is located on at least one side of the source trench and is connected to the source trench. A second region is formed on the bottom wall of the source trench, and the reliability of the insulating layer at the bottom of the source trench is improved by utilizing the second region. Furthermore, by setting a preset spacing between the second region and the well region in the first and second directions, the distance between the second region and the well region can be increased, thereby increasing the JFET region width between the second region and the well region, improving the JFET effect, and utilizing the second region on the bottom wall of the gate trench to provide electric field shielding protection for the insulating layer, thereby improving the reliability of the insulating layer. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0041] Figure 2 This is a schematic cross-sectional profile of a gate trench provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0043] Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0044] Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application;

[0045] Figure 6 A flowchart illustrating a method for fabricating a semiconductor device as provided in this application embodiment;

[0046] Figure 7 This is a flowchart of a method for fabricating a semiconductor body according to an embodiment of this application;

[0047] Figures 8-13 This is a schematic diagram of an intermediate structure of a semiconductor device provided in an embodiment of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] Figure 1This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. See also... Figure 1 ,include:

[0050] The semiconductor body 100 includes a first surface and a second surface disposed opposite to each other. The semiconductor body 100 also includes a first region 10, a second region 20, and a well region 30. The first region 10 is configured with a first conductivity type and is located on the first surface. The well region 30 is configured with a second conductivity type and is located on the side of the first region 10 away from the first surface. The first conductivity type and the second conductivity type are different. The first surface is provided with a gate trench 40 and a source trench 90. The gate trench 40 is located on at least one side of the source trench 90 and communicates with the source trench 90. The well region 30 and the first region 10 are located on the side of the gate trench 40 away from the source trench 90. Along the first direction Y, the depth of the source trench 90 is greater than the depth of the gate trench 40. The second region 20 is located on the bottom wall of the source trench 90 and is configured with a second conductivity type. The second region has a predetermined distance from the well region 30 in the first direction Y and the second direction X. The first direction Y is perpendicular to the second direction X, and the first direction Y is the direction from the first surface to the second surface.

[0051] Gate 110 is located within gate trench 40;

[0052] An insulating layer 120 surrounds the gate 110 and includes at least a portion of the sidewall of the source trench 90;

[0053] Source 130 is located on the first surface, and at least a portion of source 130 is located within source trench 90 and in contact with the second region 20;

[0054] Drain 140 is located on the second surface.

[0055] Specifically, the semiconductor body 100 may include a substrate 50, an epitaxial layer 60, a first region 10, a second region 20, and a well region 30. The epitaxial layer 60 is located on one side of the substrate 50, and the materials of the substrate 50 and the epitaxial layer 60 may be silicon or silicon carbide. Exemplarily, the epitaxial layer 60 can be formed on the surface of the substrate 50 by epitaxial growth. In this embodiment, the epitaxial layer 60 may further include a drift region 61 and a current diffusion region 62. The drift region 61 is adjacent to the substrate 50, and the current diffusion region 62 is located on the side of the drift region 61 away from the substrate 50.

[0056] The well region 30 is disposed on the side of the epitaxial layer 60 away from the substrate 50, and the first region 10 is disposed on the side of the well region 30 away from the epitaxial layer 60. The well region 30 and the first region 10 can be formed by epitaxial growth, ion implantation, or vapor deposition. For example, in this embodiment, taking ion implantation as an example, the surface of the epitaxial layer 60 away from the substrate 50 is used as the first surface of the semiconductor body 100, and the well region 30 and the first region 10 can be formed on the first surface by ion implantation. For example, the well region 30 is first formed on the first surface by ion implantation, extending from the first surface into the epitaxial layer 60, and then the first region 10 is formed on the first surface by ion implantation, extending from the first surface into the well region 30. It should be noted that when the well region 30 and the first region 10 are formed by ion implantation, depending on the structure of the semiconductor device, full-surface implantation or region implantation in a predetermined area can be selected; no limitation is made here. The well region 30 and the first region 10 can be used to form a conductive channel for a semiconductor device, wherein the first region 10 is of a first conductivity type and the well region 30 is of a second conductivity type.

[0057] It should be noted that in the embodiments of this application, the first conductivity type can be N-type conductivity, and the second conductivity type can be P-type conductivity, or the first conductivity type can be P-type conductivity and the second conductivity type can be N-type conductivity. In the accompanying drawings, P+ and N+ indicate high doping ion concentration in the region, while P- and N- indicate low doping ion concentration in the region. Specifically, N-type conductivity can be obtained by doping with P (phosphorus) or N (nitrogen) ions, and P-type conductivity can be obtained by doping with Al (aluminum) or B (boron) ions. For example, in the embodiments of this application, taking N-type conductivity as the first conductivity type and P-type conductivity as the second conductivity type, when the semiconductor device is an N-type device, the substrate 50 can be an N+ doped silicon carbide substrate 50; the epitaxial layer 60 is an N- doped silicon carbide epitaxial layer 60. When the semiconductor device is a P-type device, the substrate 50 is a P+ doped silicon carbide substrate 50, and the epitaxial layer 60 is a P- doped silicon carbide epitaxial layer 60.

[0058] Gate trench 40 and source trench 90 are formed on the first surface by etching. Gate trench 40 and source trench 90 are adjacent and connected. Positionally, gate trench 40 is adjacent to well region 30 in the second direction X. Gate trench 40 can be located on one side or both sides of source trench 90. In this embodiment, for example, gate trench 40 is provided on both sides of source trench 90, and gate trench 40 is adjacent to well region 30. During the fabrication process, gate trench 40 and source trench 90 can be etched separately to make gate trench 40 and source trench 90 connected. Alternatively, a first trench with a larger opening size can be etched first, and then the source trench 90 can be etched in the first trench. The opening size of the first trench in the second direction X is larger than the opening size of the source trench 90 in the second direction X, thereby forming a connected gate trench 40 and source trench 90.

[0059] A second region 20 is formed on the bottom wall of the source trench 90. The second region 20 is configured with a second conductivity type. The orthographic projection of the second region 20 on the second surface and the orthographic projection of the well region 30 on the second surface have a preset distance in the second direction X. That is, the second region 20 and the well region 30 have a preset distance in the second direction X. Furthermore, since the depth of the source trench in the first direction Y is greater than the depth of the gate trench in the first direction Y, the second region 20 and the well regions 30 on both sides are provided with preset distances in the first direction Y and the second direction X. By adjusting the size of the preset distance, the distance between the second region 20 and the well region 30 in the first direction Y and the second direction X can be increased, thereby increasing the JFET region width between the second region 20 and the well region 30 and improving the JFET effect. In addition, the second region 20 on the bottom wall of the gate trench 40 can also provide electric field shielding for the insulating layer 120, which provides good protection.

[0060] The gate 110 is located within the gate trench 40. The gate 110 can be positioned on one side of the sidewall of the gate trench 40 near the well region 30, wherein the vertical projection of the gate 110 onto the sidewall of the gate trench 40 at least covers the vertical projection of the well region 30 onto the sidewall of the gate trench 40, thereby improving the channel control capability of the gate 110 over the well region 30. For example, the gate 110 can employ a separate first gate 111 and a second gate 112, respectively positioned on one side of the sidewall of the gate trench 40 adjacent to the well region 30. The well regions 30 adjacent to the first gate 111 and the second gate 112 can each form vertical conductive channels, thereby increasing the number of conductive channels, improving the overall channel density of the device, and thus reducing the specific on-resistance of the semiconductor device. The gate 110 can be made of polysilicon, which has a low work function and can effectively regulate the threshold voltage of the device. An insulating layer 120 covers the surface of the gate 110. For example, before forming the gate 110, a first sub-insulating layer can be formed within the gate trench 40 using a dry oxidation process, followed by the formation of the gate 110 through deposition, etching, and other processes. A second sub-insulating layer is then deposited on the surface of the gate 110, ultimately forming the insulating layer 120 covering the gate 110. At least the insulating layer 120 is located within the source trench 90, covering a portion of the bottom wall of the source trench 90. The uncovered area can expose a second region 20, which is a portion of the bottom wall of the source trench 90. At least a portion of the source electrode 130 fills the source trench 90, forming an ohmic contact with the second region 20. For example, the surface of the insulating layer 120 away from the second region 20 is flush with the first surface to improve the overall flatness of the first surface. When the semiconductor device is reverse biased, the reverse current flows from the drain through the drift region 61 and the second region 20 to the source 130, thereby shortening the current path and reducing the reverse conduction voltage drop. When the semiconductor device is forward biased, the source 130 can replenish the lost majority carriers to the second region 20, thus ensuring the performance stability of the second region 20. When the semiconductor device is forward biased, the second region 20 can also protect the corner of the bottom wall of the gate trench 40, thereby improving the reliability of the insulating layer 120 at the bottom corner of the gate trench 40.

[0061] The semiconductor device provided in this application embodiment, by forming a gate trench 40 and a source trench 90 in the semiconductor body 100, wherein the gate trench 40 is located on at least one side of the source trench 90 and is connected to the source trench 90, and a second region 20 is formed on the bottom wall of the source trench 40, the reliability of the bottom insulating layer of the source trench 90 is improved by using the second region 20. Furthermore, by setting a preset interval between the second region 20 and the well region 30 in the first direction Y and the second direction X, the distance between the second region 20 and the well region 30 can be increased, thereby increasing the JFET region width between the second region 20 and the well region 30, improving the JFET effect, and using the second region 20 on the bottom wall of the gate trench 40 to provide electric field shielding protection for the insulating layer 120, improving the reliability of the insulating layer 120.

[0062] See also Figure 1 Optionally, the gate 110 includes a first gate 111 and a second gate 112, with the first gate 111 and the second gate 112 located in the gate trenches 40 on both sides of the source trench 90, respectively.

[0063] Specifically, the sidewall of the gate trench 40 includes a first sidewall 41 extending along the first direction Y. The first sidewall 41 is adjacent to the well region 30. The gate 110 can be a separate first gate 111 and a second gate 112. The first gate 111 and the second gate 112 are respectively disposed on one side of the first sidewall 41 of their respective gate trenches 40. The well region 30 on the side adjacent to the first gate 111 can form a vertical conductive channel, and the well region 30 on the side adjacent to the second gate 112 can form a vertical conductive channel, thereby increasing the number of conductive channels, improving the overall channel density of the device, and thus reducing the specific on-resistance of the semiconductor device.

[0064] Optionally, the orthographic projection of the first gate 111 onto the first sidewall 41 of the gate trench 40 at least partially covers the orthographic projection of the adjacent well region 30 onto the first sidewall 41, and the orthographic projection of the second gate 112 onto the first sidewall 41 of the gate trench 40 at least partially covers the orthographic projection of the adjacent well region 30 onto the first sidewall 41. This improves the control capability of the first gate 111 and the second gate 112 over their respective channels. An insulating layer 120 is coated on the surfaces of the first gate 111 and the second gate 112. A second trench 121 is formed on the surface of the insulating layer 120, exposing a second region 20 of the bottom wall of the source trench 90. By designing the width of the second trench 121 in the second direction X, the side of the first gate 111 away from the first sidewall 41 can have a thicker insulating layer 120, and the side of the second gate 112 away from the first sidewall 41 can also have a thicker insulating layer 120. By retaining a thicker insulating layer 120, the reliability of the insulating layer of the gate trench 40 can be further ensured. Furthermore, by employing separate first gate 111 and second gate 112, the collective effect of adjacent well regions 30 can be utilized to suppress voltage coupling between the first gate 111 and drain 140, as well as voltage coupling between the second gate 112 and drain 140. This reduces the feedback capacitance Crss and the charge Qgd at the gate 110 and drain 140, which is beneficial for improving the quality factor of the semiconductor device and enhancing its dynamic characteristics.

[0065] Based on the above embodiments, optionally, in the second direction X, by adjusting the opening size of the gate trench 40, the distance between the second region 20 and the well region 30 in the second direction X can be increased. In the first direction Y, by adjusting the depth of the source trench 90, the distance between the second region 20 and the well region 30 in the first direction Y can be increased, thereby increasing the JFET region width between the second region 20 and the well region 30. Therefore, by adjusting the morphology of the gate trench 40 and the source trench 90, the second region 20 and the well region 30 can have a natural preset interval in the first direction Y and the second direction X. For example, the gate trench 40 and the source trench 90 can form multi-level stepped trenches or trapezoidal trenches.

[0066] Figure 2 This is a schematic cross-sectional profile of a gate trench provided in an embodiment of this application, combined with... Figure 1 See Figure 2 In this embodiment of the application, the gate trench 40 and the source trench 90 constitute a stepped trench. The sidewall of the gate trench 40 includes a first sidewall 41 extending along the first direction Y, and the sidewall of the source trench 90 includes a second sidewall 42 extending along the first direction Y.

[0067] Specifically, in this embodiment, well regions 30 are provided on both sides of the gate trench 40, and the first sidewall 41 of the gate trench 40 and the second sidewall 42 of the source trench 90 are stepped. The second sidewall 42 is further away from the well region 30 adjacent to the first sidewall 41 in the second direction X. Therefore, the gate trench 40 and the source trench 90 can be stepped trenches in opposite directions. Due to the shape of the stepped trench, the second region 20 and the well region 30 can have a natural preset interval in the first direction Y and the second direction X, thereby increasing the distance between the second region 20 and the well region 30 in the first direction Y and the second direction X, increasing the JFET region width between the second region 20 and the well region 30, and weakening the JFET effect. Furthermore, the second region 20 is located on the bottom wall of the source trench 90, which can shield the electric field of the corner region formed by the second sidewall 42 and the bottom wall of the source trench 90, improving the reliability of the insulating layer 120. Furthermore, the well region 30 can also provide good electric field shielding protection for the insulating layer 120 at the corner between the first sidewall 41 and the bottom wall of the gate trench 40. In this application, the gate trench 40 and the source trench 90 are exemplary in that they form a two-stage stepped shape; in other embodiments, the gate trench 40 and the source trench 90 can be multi-stage stepped. Figure 3 For a schematic diagram of another semiconductor device provided in the embodiments of this application, see [link to schematic diagram]. Figure 3 ,and Figure 1 In contrast, in the embodiments of this application, the gate trench 40 and the source trench 90 adopt a three-step shape, which can also increase the distance between the second region 20 and the well region 30 in the second direction X, thereby weakening the JFET effect.

[0068] Figure 4 For a schematic diagram of another semiconductor device provided in the embodiments of this application, see [link to schematic diagram]. Figure 4 The semiconductor body 100 also includes a fourth region 70 configured as a second conductivity type, located on the side of the bottom wall of the gate trench 40 away from the first surface.

[0069] Specifically, the embodiments of this application and Figure 1 The difference in the embodiment is that a fourth region 70 is provided at the corner of the bottom wall of the gate trench 40. For example, the fourth region 70 is of the second conductivity type, thereby using the fourth region 70 to provide electric field shielding protection for the insulating layer 120 at the corner of the step.

[0070] Optionally, the orthographic projection of the fourth region 70 on the second surface does not overlap with the orthographic projection of the well region 30 on the second surface; that is, the fourth region 70 extends the bottom wall of the gate trench 40 in the second direction X, thereby avoiding the influence of the fourth region 70 on the current path of the adjacent channel.

[0071] Figure 5For a schematic diagram of another semiconductor device provided in the embodiments of this application, see [link to schematic diagram]. Figure 5 The bottom wall of the gate trench 40 intersects the side wall of the source trench 90 along the third direction, and the gate trench 40 and the source trench 90 form a trapezoidal trench; the third direction intersects the second direction X and the first direction Y respectively.

[0072] Specifically, the bottom wall of the gate trench 40 is an inclined sidewall 47; the inclined sidewall 47 intersects with the sidewall of the source trench 90. In this embodiment, the inclined sidewall 47 is connected to the end point of the sidewall of the source trench 90, i.e., the bottom wall of the source trench 90. The gate trench 40 and the source trench 90 form a trench with a shape similar to an inverted trapezoid. Due to the shape of the trapezoidal trench, the second region 20 and the well region 30 can have a natural preset interval in the first direction Y and the second direction X, thereby increasing the distance between the second region 20 and the well region 30 in the first direction Y and the second direction X, thereby increasing the JFET region width between the second region 20 and the well region 30 and weakening the JFET effect. Figure 5 In the exemplary embodiment, the inclined sidewall 47 is a straight sidewall. In other embodiments, the inclined sidewall 47 may also be a curved arc sidewall. The inclined sidewall 47 can also reduce the angle of the connection position with the bottom wall of the source trench 90, so as to reduce the electric field strength at the corner of the insulating layer 120 and prevent electric field concentration.

[0073] Based on the above embodiments, optionally, the semiconductor body 100 further includes a third region 80, which is configured as a second conductivity type and is located on the first surface of the first region 10 away from the gate trench 40; wherein the ion concentration of the third region 80 is greater than or equal to the ion concentration of the well region 30.

[0074] Specifically, the third region 80 is adjacent to the first region 10. The third region 80 can have the same ion concentration as the well region 30, or the ion concentration of the third region 80 can be greater than that of the well region 30. For example, when multiple adjacent regions extend in the second direction X... Figure 1 When the cross-sectional structure shown is used, the third region 80 can serve as an isolation structure to isolate the conductive channels of the well region 30 in the adjacent gate trench 40.

[0075] This application provides a power module based on the above embodiments, including a substrate and a semiconductor device according to any embodiment of this application, wherein the substrate is used to support the semiconductor device.

[0076] The power module provided by the technical solution of this application has the same beneficial effects as the semiconductor device in any embodiment of this application.

[0077] Based on the above embodiments, this application provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, and the semiconductor device is electrically connected to the circuit board.

[0078] The power conversion circuit provided in the embodiments of this application has the same beneficial effects as the semiconductor device in any embodiment of this application.

[0079] Based on the above embodiments, this application provides a vehicle including a load and a power conversion circuit as described in any embodiment of this application. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0080] This application provides a method for fabricating a semiconductor device based on the above embodiments. Figure 6 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application, combined with... Figure 1 , Figure 3 , Figure 4 and Figure 5 ,refer to Figure 6 The preparation methods include:

[0081] S110. A semiconductor body 100 is provided. The semiconductor body 100 includes a first surface and a second surface disposed opposite to each other. The semiconductor body 100 also includes a first region 10, a second region 20, and a well region 30. The first region 10 is configured with a first conductivity type and is located on the first surface. The well region 30 is configured with a second conductivity type and is located on the side of the first region 10 away from the first surface. The first conductivity type is different from the second conductivity type. The first surface is provided with a gate trench 40 and a source trench 90. The gate trench 40 is located on at least one side of the source trench 90 and is connected to the source trench 90. The well region 30 and the first region 10 are located on the side of the gate trench 40 away from the source trench 90. Along the first direction Y, the depth of the source trench 90 is greater than the depth of the gate trench 40. The second region 20 is located on the bottom wall of the source trench 90 and is configured with a second conductivity type. The second region 20 has a preset distance from the well region 30 in the first direction Y and the second direction X. The first direction Y is perpendicular to the second direction X, and the first direction Y is the direction from the first surface to the second surface.

[0082] Specifically, the semiconductor body 100 may include a substrate 50, an epitaxial layer 60, a first region 10, a second region 20, and a well region 30. The epitaxial layer 60 is located on one side of the substrate 50, and the materials of the substrate 50 and the epitaxial layer 60 may be silicon or silicon carbide. Exemplarily, the epitaxial layer 60 can be formed on the surface of the substrate 50 by epitaxial growth. In this embodiment, the epitaxial layer 60 may further include a drift region 61 and a current diffusion region 62. The drift region 61 is adjacent to the substrate 50, and the current diffusion region 62 is located on the side of the drift region 61 away from the substrate 50.

[0083] The well region 30 is disposed on the side of the epitaxial layer 60 away from the substrate 50, and the first region 10 is disposed on the side of the well region 30 away from the epitaxial layer 60. The well region 30 and the first region 10 can be formed by epitaxial growth, ion implantation, or vapor deposition. For example, in this embodiment, the surface of the epitaxial layer 60 away from the substrate 50 is used as the first surface of the semiconductor body 100. The well region 30 and the first region 10 can be formed on the first surface by ion implantation. For instance, the well region 30 is first formed on the first surface by ion implantation, extending from the first surface into the epitaxial layer 60, and then the first region 10 is formed on the first surface by ion implantation, extending from the first surface into the well region 30. It should be noted that when the well region 30 and the first region 10 are formed by ion implantation, depending on the structure of the semiconductor device, full-surface implantation or region implantation in a predetermined area can be selected; no limitation is imposed here. The well region 30 and the first region 10 can be used to form a conductive channel for a semiconductor device, wherein the first region 10 is of a first conductivity type and the well region 30 is of a second conductivity type.

[0084] It should be noted that in the embodiments of this application, the first conductivity type can be N-type conductivity, and the second conductivity type can be P-type conductivity, or the first conductivity type can be P-type conductivity and the second conductivity type can be N-type conductivity. In the accompanying drawings, P+ and N+ indicate high doping ion concentration in the region, while P- and N- indicate low doping ion concentration in the region. Specifically, N-type conductivity can be obtained by doping with P (phosphorus) or N (nitrogen) ions, and P-type conductivity can be obtained by doping with Al (aluminum) or B (boron) ions. For example, in the embodiments of this application, taking N-type conductivity as the first conductivity type and P-type conductivity as the second conductivity type, when the semiconductor device is an N-type device, the substrate 50 can be an N+ doped silicon carbide substrate 50; the epitaxial layer 60 is an N- doped silicon carbide epitaxial layer 60. When the semiconductor device is a P-type device, the substrate 50 is a P+ doped silicon carbide substrate 50, and the epitaxial layer 60 is a P- doped silicon carbide epitaxial layer 60.

[0085] Gate trench 40 and source trench 90 are formed on the first surface by etching. Gate trench 40 and source trench 90 are adjacent and connected. Positionally, gate trench 40 is adjacent to well region 30 in the second direction X. Gate trench 40 can be located on one side or both sides of source trench 90. In this embodiment, for example, gate trench 40 is provided on both sides of source trench 90, and gate trench 40 is adjacent to well region 30. During the fabrication process, gate trench 40 and source trench 90 can be etched separately to make gate trench 40 and source trench 90 connected. Alternatively, a first trench can be etched first, and then source trench 90 can be etched in the first trench. The opening size of the first trench in the second direction is larger than the opening size of the source trench 90 in the second direction, thereby forming a connected gate trench 40 and source trench 90.

[0086] A second region 20 is formed on the bottom wall of the source trench 90. The second region 20 is configured with a second conductivity type. The orthographic projection of the second region 20 on the second surface and the orthographic projection of the well region 30 on the second surface are separated by a preset distance in the second direction X. That is, the second region 20 and the well region 30 are separated by a preset distance in the second direction X. Furthermore, since the depth of the source trench 90 in the first direction Y is greater than the depth of the gate trench 40 in the first direction Y, the second region 20 and the well regions 30 on both sides are separated by a preset distance in both the first direction Y and the second direction X. By adjusting the size of the preset distance, the distance between the second region 20 and the well region 30 in the first direction Y and the second direction X can be increased, thereby increasing the JFET region width between the second region 20 and the well region 30 and improving the JFET effect. In addition, the second region 20 on the bottom wall of the gate trench 40 can also provide electric field shielding for the insulating layer 120, which provides good protection.

[0087] S120, A gate 110 is formed in the gate trench 40;

[0088] Specifically, the gate 110 is located within the gate trench 40. The gate 110 can be positioned on one side of the sidewall of the gate trench 40 near the well region 30, wherein the vertical projection of the gate 110 onto the sidewall of the gate trench 40 at least covers the vertical projection of the well region 30 onto the sidewall of the gate trench 40, thereby improving the channel control capability of the gate 110 over the well region 30. For example, the gate 110 can employ a separate first gate 111 and a second gate 112, respectively positioned on one side of the sidewall of the gate trench 40 adjacent to the well region 30. The well regions 30 adjacent to the first gate 111 and the second gate 112 can each form vertical conductive channels, thereby increasing the number of conductive channels, improving the overall channel density of the device, and thus reducing the specific on-resistance of the semiconductor device. The gate 110 can be made of polysilicon, which has a low work function and can effectively regulate the threshold voltage of the device.

[0089] S130. An insulating layer 120 is formed in the gate trench 40 and at least part of the source trench 90, the insulating layer 120 surrounding the gate 110.

[0090] Specifically, the insulating layer 120 covers the surface of the gate 110. For example, before forming the gate 110, a first sub-insulating layer 123 can be formed in the gate trench 40 by a dry oxidation process, and then the gate 110 can be formed by deposition, etching and other processes. Then, a second sub-insulating layer 124 is deposited on the surface of the gate 110, and finally the insulating layer 120 covering the gate 110 is formed. Among them, the insulating layer 120 is partially located in the source trench, covering part of the bottom wall of the source trench, and the uncovered area can expose part of the second region 20 of the bottom wall of the source trench.

[0091] S140, a source electrode 130 is formed on the first surface, and at least a portion of the source electrode 130 is located within the source trench 90 and in contact with the second region 20;

[0092] Specifically, the source 130 can be formed on the first surface by sputtering or other methods. For example, the material of the source 130 can be titanium (Ti), nickel (Ni), or silver (Ag). At least a portion of the source 130 fills the source trench to form an ohmic contact with the second region 20. For example, the surface of the insulating layer 120 away from the second region 20 is flush with the first surface, which can improve the overall flatness of the first surface. When the semiconductor device is reverse biased, the reverse current flows from the drain through the drift region 61 and the second region 20 to the source 130, thereby shortening the current path and reducing the reverse conduction voltage drop. When the semiconductor device is forward biased, the source 130 can replenish the lost majority carriers in the second region 20, thereby ensuring the performance stability of the second region 20. When the semiconductor device is forward biased, the second region 20 can also protect the corner of the bottom wall of the gate trench 40, thereby improving the reliability of the insulating layer 120 at the bottom corner of the gate trench 40.

[0093] S150, Drain 140 is formed on the second surface.

[0094] Specifically, the surface of the substrate 50 away from the epitaxial layer 60 is first thinned, and then the drain 140 is formed by sputtering or other methods. For example, the material of the drain 140 can be titanium (Ti), nickel (Ni), or silver (Ag).

[0095] The semiconductor device fabrication method provided in this application embodiment involves forming a gate trench 40 and a source trench 90 in a semiconductor body 100. The gate trench 40 is located on at least one side of the source trench 90 and is connected to the source trench 90. A second region 20 is formed on the bottom wall of the source trench 40, thereby improving the reliability of the bottom insulating layer of the source trench 90. Furthermore, by setting a predetermined interval between the second region 20 and the well region 30 in the first direction Y and the second direction X, the distance between the second region 20 and the well region 30 can be increased, thereby increasing the JFET region width between the second region 20 and the well region 30, improving the JFET effect, and using the second region 20 on the bottom wall of the gate trench 40 to provide electric field shielding protection for the insulating layer 120, thus improving the reliability of the insulating layer 120.

[0096] As an optional embodiment, with Figure 1 Taking the structure of semiconductor devices as an example, Figure 7 A flowchart illustrating another method for fabricating a semiconductor device provided in this application embodiment. Figures 8-13 This is a schematic diagram of an intermediate structure of a semiconductor device provided in an embodiment of this application, with reference to... Figures 7-13 The preparation methods include:

[0097] S210, An epitaxial layer 60 is grown on one side of the substrate 50;

[0098] Specifically, the epitaxial layer 60 is located on one side of the substrate 50, and the materials of the substrate 50 and the epitaxial layer 60 can be silicon or silicon carbide. Exemplarily, the epitaxial layer 60 can be formed on the surface of the substrate 50 by epitaxial growth. In this embodiment, the epitaxial layer 60 may further include a drift region 61 and a current diffusion region 62, with the drift region 61 adjacent to the substrate 50 and the current diffusion region 62 located on the side of the drift region 61 away from the substrate 50.

[0099] S220, the side of the epitaxial layer 60 away from the substrate 50 is taken as the first surface; a well region 30 and a first region 10 are formed on the first surface, the first region 10 is located on the first surface; the well region 30 is located on the side of the first region 10 away from the first surface; the first region 10 is of a first conductivity type, and the well region 30 is of a second conductivity type; the first conductivity type and the second conductivity type are different.

[0100] Specifically, the surface of the epitaxial layer 60 away from the substrate 50 is used as the first surface of the semiconductor body 100. The well region 30 and the first region 10 can be formed on the first surface by ion implantation. First, the well region 30 is formed on the first surface by ion implantation, extending from the first surface into the epitaxial layer 60. Then, the first region 10 is formed on the first surface by ion implantation, extending from the first surface into the well region 30. It should be noted that when the well region 30 and the first region 10 are formed by ion implantation, depending on the structure of the semiconductor device, full-surface implantation or region implantation in a preset area can be selected, without limitation. In this embodiment, region implantation is performed in a preset area. In some embodiments, a third region 80 can also be formed on the first surface. The third region 80 is located on the side of the first region 10 away from the gate trench 40, wherein the ion concentration of the third region 80 is greater than or equal to the ion concentration of the well region 30. Its structure is as follows. Figure 8 As shown.

[0101] S230, A first groove 91 is formed on the first surface;

[0102] Specifically, a first trench 91 is formed on the first surface by an etching process, wherein the sidewall of the first trench 91 is adjacent to the trap region 30.

[0103] S240, a first sub-insulating layer 123 is formed on the sidewall and bottom wall of the first trench 91; wherein, the first sub-insulating layer 123 can be formed within the gate trench 40 by a dry oxidation process. Its structure is as follows: Figure 9 As shown.

[0104] S250, A gate structure 113 is formed in the first trench 91; the gate structure 113 can be made of polysilicon, and the gate structure 113 fills the first trench 91, its structure as follows: Figure 10 As shown.

[0105] S260, a source trench 90 is formed on the side surface of the gate structure 113 away from the second surface. Along the first direction, the depth of the source trench 90 is greater than the depth of the first trench 91. The portion of the first trench 91 located on both sides of the source trench 90 serves as a gate trench 40. The gate structure 113 located within the gate trench 40 serves as a first gate 111 and a second gate 112, respectively. The vertical projections of the first gate 111 and the second gate 112 on the sidewalls of their respective gate trenches 40 at least cover the vertical projections of the adjacent well region 30 on the sidewalls of the gate trench 40.

[0106] Specifically, a source trench 90 is formed again within the surface of the gate structure 113 through an etching process. The opening size of the source trench 90 is smaller than that of the first trench 91. The gate structures 113 on both sides of the source trench 90 constitute the first gate 111 and the second gate 112, respectively. The orthographic projection of the first gate 111 onto the first sidewall 41 of the gate trench 40 at least partially covers the orthographic projection of the adjacent well region 30 onto the first sidewall 41. Similarly, the orthographic projection of the second gate 112 onto the first sidewall 41 of the gate trench 40 at least partially covers the orthographic projection of the adjacent well region 30 onto the first sidewall 41. This improves the control capability of the first gate 111 and the second gate 112 over their respective channels. By employing separate first gate 111 and second gate 112, the collective effect of adjacent well regions 30 can be utilized to suppress voltage coupling between the first gate 111 and drain 140, as well as voltage coupling between the second gate 112 and drain 140. This reduces the feedback capacitance Crss and the charge Qgd at the gate 110 and drain 140, which is beneficial for improving the quality factor and dynamic characteristics of the semiconductor device. Its structure is as follows: Figure 11 As shown.

[0107] S270, A second region 20 is formed on the bottom wall of the source trench 90, and the second region 20 is configured as a second conductivity type.

[0108] S280, A second sub-insulating layer 124 is formed in the gate trench 40 and the source trench 90. The first sub-insulating layer 123 and the second sub-insulating layer 124 constitute an insulating layer 120. The insulating layer 120 covers the surfaces of the first gate 111 and the second gate 112.

[0109] Specifically, a second sub-insulating layer 124 is deposited within the gate trench 40 and the source trench 90 to form an insulating layer 120 covering the gate 110. Its structure is as follows: Figure 12 As shown.

[0110] S290, a second trench 121 is formed on the side surface of the insulating layer 120 away from the second surface. The second trench 121 is located between the first gate 111 and the second gate 112. The bottom wall of the second trench 121 is located in the same plane as the bottom wall of the source trench 90. The thickness of the insulating layer 120 between the first gate 111 and the second trench 121 is greater than the thickness of the insulating layer 120 between the first gate 111 and the sidewall of the gate trench 40. The thickness of the insulating layer 120 between the second gate 112 and the second trench 121 is greater than the thickness of the insulating layer 120 between the second gate 112 and the sidewall of the gate trench 40.

[0111] Specifically, after depositing the second sub-insulating layer 124 within the gate trench 40 and source trench 90, a thicker insulating layer 120 is formed between the first gate 111 and the second gate 112. A second trench 121 is formed by etching on the insulating layer 120 between the first gate 111 and the second gate 112. The second trench 121 can penetrate the insulating layer 120, thereby exposing a portion of the second region 20 of the bottom wall of the source trench 90. By designing the width dimension of the second trench 121 in the second direction X, a thicker insulating layer 120 can be formed on the side of the first gate 111 away from the well region, and a thicker insulating layer 120 can be formed on the side of the second gate 112 away from the well region. By retaining a thicker insulating layer 120, the reliability of the gate oxide in the gate trench 40 can be further ensured. Its structure is as follows... Figure 13 As shown.

[0112] S300, a source electrode 130 is formed on the first surface, and at least a portion of the source electrode 130 is located within the source trench 90 and forms an ohmic contact with the second region 20; its structure is as follows. Figure 1 As shown.

[0113] S310, Drain 140 is formed on the second surface.

[0114] Based on the above embodiments, optionally, after forming the first sub-insulating layer 123 on the sidewall and bottom wall of the first trench 91, the process includes:

[0115] The thickness of the thickened portion of the first sub-insulating layer 123 is increased such that the thickness of the first sub-insulating layer 123 not adjacent to the well region 30 is greater than the thickness of the first sub-insulating layer 123 adjacent to the well region 30.

[0116] While increasing the thickness of the first sub-insulating layer 123, a high-k material is deposited to form a composite first sub-insulating layer 123.

[0117] Specifically, by increasing the thickness of the first sub-insulating layer 123, which is not adjacent to the well region 30, the electric field at the corner can be reduced, thereby improving the stability of the insulating layer 120. Optionally, a high-k material can be deposited simultaneously with the increase in the thickness of the first sub-insulating layer 123 to form a composite first sub-insulating layer 123. Utilizing the composite first sub-insulating layer 123 with high-k material, the electron mobility at the interface between the first gate 111 and the second gate 112 is improved, reducing the on-resistance of the device. The thickness of the first sub-insulating layer 123 is less than the thickness of the second sub-insulating layer 124, thereby ensuring the control capability of the first gate 111 and the second gate 112 over the adjacent well region 30. Furthermore, by increasing the thickness of the second sub-insulating layer 124, the electric field at the corner is reduced, thereby improving the stability of the insulating layer 120.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a first region, a second region, and a well region. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The first conductivity type is different from the second conductivity type; The first surface is provided with a gate trench and a source trench. The gate trench is located on at least one side of the source trench and is connected to the source trench. The well region and the first region are located on the side of the gate trench away from the source trench. Along the first direction, the depth of the source trench is greater than the depth of the gate trench. The second region is located on the bottom wall of the source trench and is configured as a second conductivity type. The second region has a predetermined distance from the well region in the first direction and the second direction. The first direction is perpendicular to the second direction, and the first direction is the direction from the first surface to the second surface. The gate is located within the gate trench; An insulating layer surrounds the gate and includes at least a portion located on the sidewall of the source trench; The source electrode is located on the first surface, and at least a portion of the source electrode is located within the source electrode trench and in contact with the second region; The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The surface of the insulating layer on the side away from the second region is flush with the first surface.

3. The semiconductor device according to claim 1, characterized in that, The gate includes a first gate and a second gate, which are located in the gate trenches on both sides of the source trench.

4. The semiconductor device according to claim 3, characterized in that, The vertical projections of the first gate and the second gate on their respective gate trench sidewalls at least cover the vertical projections of the adjacent well region on the sidewalls of the gate trench.

5. The semiconductor device according to claim 4, characterized in that, The bottom wall of the gate trench intersects the side wall of the source trench along the second direction, and the gate trench and the source trench form a stepped trench. Alternatively, the bottom wall of the gate trench intersects the side wall of the source trench along a third direction, and the gate trench and the source trench form a trapezoidal trench. The third direction intersects with the second direction and the first direction, respectively.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a third region configured with a second conductivity type and located on a first surface of the first region away from the gate trench; wherein the ion concentration of the third region is greater than or equal to the ion concentration of the well region.

7. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1-6, wherein the substrate is used to support the semiconductor device.

8. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-6, wherein the semiconductor device is electrically connected to the circuit board.

9. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 8, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

10. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other, the semiconductor body further including a first region, a second region and a well region; the first region is configured with a first conductivity type and is located on the first surface; the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface; The first conductivity type is different from the second conductivity type; The first surface is provided with a gate trench and a source trench. The gate trench is located on at least one side of the source trench and is connected to the source trench. The well region and the first region are located on the side of the gate trench away from the source trench. Along the first direction, the depth of the source trench is greater than the depth of the gate trench. The second region is located on the bottom wall of the source trench and is configured as a second conductivity type. The second region has a predetermined distance from the well region in the first direction and the second direction. The first direction is perpendicular to the second direction, and the first direction is the direction from the first surface to the second surface. A gate is formed within the gate trench; An insulating layer is formed within the gate trench and at least a portion of the source trench, the insulating layer surrounding the gate; A source electrode is formed on the first surface, and at least a portion of the source electrode is located within the source electrode trench and in contact with the second region.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The semiconductor body includes: An epitaxial layer is grown on one side of the substrate; The first surface is defined as the side of the epitaxial layer away from the substrate; a well region and a first region are formed on the first surface, the first region being located on the first surface; the well region is located on the side of the first region away from the first surface; the first region is of a first conductivity type, and the well region is of a second conductivity type; the first conductivity type and the second conductivity type are different. A first trench is formed on the first surface, and a gate structure is formed within the first trench; A source trench is formed on the side surface of the gate structure away from the second surface. Along the first direction, the depth of the source trench is greater than the depth of the first trench. The portions of the first trench located on both sides of the source trench serve as gate trenches, and the gate structures located within the gate trenches serve as the first gate and the second gate, respectively. The vertical projections of the first gate and the second gate on their respective gate trench sidewalls at least cover the vertical projections of the adjacent well regions on the sidewalls of the gate trenches. A second region is formed on the bottom wall of the source trench, and the second region is configured as a second conductivity type.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, An insulating layer is formed within the gate trench and at least a portion of the source trench, the insulating layer surrounding the gate, comprising: Before forming the gate structure in the first trench, a first sub-insulating layer is formed on the sidewall and bottom wall of the first trench; After forming a source trench on the side of the gate structure away from the second surface, a second sub-insulating layer is formed in the gate trench and the source trench. The first sub-insulating layer and the second sub-insulating layer constitute the insulating layer, and the insulating layer covers the surfaces of the first gate and the second gate. A second trench is formed on the side of the insulating layer away from the second surface. The second trench is located between the first gate and the second gate. The bottom wall of the second trench is on the same plane as the bottom wall of the source trench. The thickness of the insulating layer between the first gate and the second trench is greater than the thickness of the insulating layer between the first gate and the sidewall of the gate trench, and the thickness of the insulating layer between the second gate and the second trench is greater than the thickness of the insulating layer between the second gate and the sidewall of the gate trench.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, After forming the first sub-insulating layer on the sidewall and bottom wall of the first trench, the process includes: The thickness of the first sub-insulating layer is increased such that the thickness of the first sub-insulating layer not adjacent to the well region is greater than the thickness of the first sub-insulating layer adjacent to the well region. While increasing the thickness of the first sub-insulating layer, a high-k material is deposited to form a composite first sub-insulating layer.

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