A deep trench filled 950V superjunction MOS termination structure and its fabrication method

Abstract

This invention discloses a 950V superjunction MOS termination structure with a deep trench-filled structure and its fabrication method. The device additionally includes a floating P-pillar connection layer implantation, a polysilicon field plate in the termination region, and a metal field plate in the termination region. The entire device is epitaxially grown on an N-type substrate, expanding multiple functional layers under optimal conditions. This invention utilizes a deep trench-filled process to effectively reduce on-resistance, improve breakdown voltage level and stability through optimized structural design and manufacturing process, while optimizing switching losses in the termination section and improving overall performance. Two N-type epitaxial layers are grown on the substrate to optimize the charge imbalance caused by the etching angle in the deep trench etching. Due to the different resistivities of the two epitaxial layers, the entire N-pillar and P-pillar achieve maximum charge balance. Furthermore, by lightly implanting a P-type layer onto the surface of the termination region, the floating P-pillars in the termination region are connected, and the surface electric field distribution is optimized to achieve more stable breakdown characteristics.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and more specifically, to a deep trench filled 950V superjunction MOS termination structure and its fabrication method. Background Technology

[0002] Traditional power MOSFET devices face an inherent contradiction between on-resistance RDS(on) and breakdown voltage BV in high-voltage applications above 600V, known as the silicon limit. Power systems demand higher energy efficiency and miniaturization, and planar gate structures are increasingly unable to meet this trend.

[0003] Superjunction technology, by introducing alternating P / N pillar structures, creates a charge compensation effect in the drift region, breaking through the performance bottleneck of traditional devices and significantly reducing conduction losses while maintaining high breakdown voltage. Although superjunctions can achieve a better relationship between breakdown voltage and on-resistance using the principle of charge balance, they still cannot avoid the problem of unstable breakdown at the device termination. This is mainly because in the actual production of power devices, the P / N junction interface is not an ideal parallel planar junction, but rather forms cylindrical and spherical junctions at the edges due to diffusion. These curved junctions lead to electric field concentration, thereby reducing the breakdown voltage of the device. Therefore, for power devices with high breakdown voltage, the design requirements for the termination structure are more stringent.

[0004] For ease of understanding, please refer to the accompanying drawings in the instruction manual. Figure 2 To explain, Figure 2This is a schematic cross-sectional view of the transition and termination regions of an existing deep-trench-filled high-voltage superjunction MOS device, including an N+ substrate 201, an N-type epitaxial layer 202, a JFET implantation region 203, a deep-trench-filled P-pillar region 204, a P-body implantation region 205, a gate oxide layer 206, a cell-region gate polysilicon 207, an N+ source implantation region 208, an ILD dielectric layer 209, a front-side source metal electrode 210, a stop-ring metal 211, and a back-side metal electrode 212. Termination structure types mainly include equipotential rings, floating field plates, termination extension, and lateral doping techniques. The manufacturing processes for superjunction structures are mainly divided into multiple epitaxial processes and deep-trench filling. Multiple epitaxial processes have various types of termination structures and are relatively mature. However, deep-trench etching terminations have always suffered from breakdown instability at high voltage levels. For superjunction MOS termination structures with a breakdown voltage of 950V, optimization can be achieved by adjusting the number of P-pillars in the termination region, the arrangement of P-pillars, and the connection of P-type implantation to the P-pillars. However, as the voltage increases, the number of P pillars increases, resulting in an excessively large terminal area. The P-type injection method of connecting P pillars will also increase the concentration of P pillars due to P-type injection, resulting in an excessively high P-type concentration on the surface that cannot be exhausted. Some terminal structures use a truncated method of adding deep oxide trenches to optimize the terminal area, but this method is difficult to implement in actual manufacturing processes.

[0005] For deep-trench-filled superjunction MOSFETs with voltage levels above 950V, improvements in materials, processes, and structures are necessary to ensure stable breakdown voltage. Due to the high voltage level of 950V, the epitaxial wafer thickness is typically around 75μm, and the depth of the P-pillars formed by deep trench etching reaches 65μm. Therefore, the P-pillar trench etching will inevitably create a significant width difference between the trench surface and the trench bottom due to the etching angle, resulting in an inability to achieve charge balance. Summary of the Invention

[0006] In view of the shortcomings of the existing technology, the purpose of this invention is to provide a 950V superjunction MOS termination structure with deep trench filling and its fabrication method, thereby solving one or more of the above-mentioned problems.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A deep trench filled 950V superjunction MOS termination structure includes an N+ substrate, a back metal electrode on the back side of the N+ substrate, and a continuous primary N-type epitaxial layer and a secondary N-type epitaxial layer arranged sequentially on the front side of the N+ substrate.

[0009] The primary N-type epitaxial layer and the secondary N-type epitaxial layer are filled with recessed, equally spaced deep grooves to create P-pillar regions.

[0010] One end of the secondary N-type epitaxial layer is provided with a front-side source metal electrode. An ILD dielectric layer is provided inside the front-side source metal electrode. A cell region gate polysilicon is provided inside the ILD dielectric layer. A gate oxide layer is provided at the bottom of the ILD dielectric layer. A recessed JFET implantation region is provided at the top of the secondary N-type epitaxial layer at this end. A Pbody body region implantation is provided at the top of the two outermost adjacent deep trench-filled P pillar regions at this end. A recessed N+ source implantation region is provided at the top of the outermost deep trench-filled P pillar regions at this end. The gate oxide layer is in contact with the ILD dielectric layer, the cell region gate polysilicon, the N+ source implantation region, the Pbody body region implantation, the JFET implantation region, and the secondary N-type epitaxial surface.

[0011] The secondary N-type epitaxial layer has a recessed Ptop floating P-pillar connection layer implanted at the top of its central region. A separate ILD dielectric layer is located on the top surface of the central region of the secondary N-type epitaxial layer, extending to the other end of the secondary N-type epitaxial layer. Several equally spaced terminal polysilicon field plates are located within the ILD dielectric layer, and several equally spaced terminal metal field plates are located on the top of the ILD dielectric layer. The ILD dielectric layer is in contact with the Ptop floating P-pillar connection layer implanted, the secondary N-type epitaxial layer, and the front source metal electrode surface.

[0012] The other end of the secondary N-type epitaxial layer is provided with a stop ring metal. The two sides of the stop ring metal are in contact with the ILD dielectric layer in the central region. There is no Ptop floating P-pillar connecting layer injected at the top of the secondary N-type epitaxial layer at this end.

[0013] Furthermore, the number of polysilicon field plates in the terminal region of the ILD dielectric layer is greater than the number of metal field plates in the terminal region.

[0014] Furthermore, the ILD dielectric layer thickness in the central region of the secondary N-type epitaxial layer is greater than the ILD dielectric layer thickness on both sides of the secondary N-type epitaxial layer.

[0015] Furthermore, the primary N-type epitaxy and the secondary N-type epitaxy have an overall structure that is wider at the top and narrower at the bottom, while the deep groove-filled P-pillar region has an overall structure that is narrower at the top and wider at the bottom.

[0016] A method for fabricating a 950V superjunction MOS termination structure with a deep trench filled structure, comprising the following steps.

[0017] S1. Prepare an N+ substrate, and grow a first N-type epitaxial growth and a second N-type epitaxial growth on the N+ substrate in sequence;

[0018] S2. A thin pre-oxidant layer is grown on the secondary N-type epitaxy, and JFET implantation is performed to form the JFET implantation region. The thin pre-oxidant layer on the device surface is then removed.

[0019] S3. Deep trench etching and P-type epitaxial filling are performed on the primary N-type epitaxial layer and the secondary N-type epitaxial layer to form a deep trench filled P-pillar region. A sacrificial oxide layer is grown on the surface and CMP mechanical planarization is performed to maintain the surface flatness.

[0020] S4. A thin pre-oxidized layer is grown on the surface as an injection barrier layer, and high-dose, low-energy P-type body region injection in the active region and low-dose, low-energy P-type connecting layer injection in the primary terminal region are performed. High-temperature push-bonding is used to form the Pbody injection region in the active region and the Ptop floating P-pillar connecting layer injection in the terminal region.

[0021] S5. Thermally deposit field oxygen on the surface and perform active region etching to grow a gate oxide layer in the active region, deposit polysilicon and perform etching to form cell region gate polysilicon and terminal region polysilicon field plate.

[0022] S6. Etch the oxide layer, implant to form the N+ source implantation region and activate it, deposit and reflow the ILD to form a layered ILD dielectric layer, open the hole to complete the metal deposition and etching, and form the front source metal electrode, the cut-off ring metal and the terminal region metal field plate. Metallize the back side of the N+ substrate to form the back metal electrode.

[0023] Furthermore, the resistivity of the primary and secondary N-type epitaxy in step S1 is different, the thickness of the thin pre-oxidation layer in step S2 is 200 Å, and the implantation condition of the N-type JFET implantation region is 2e12cm. -2 / 60keV.

[0024] Furthermore, in step S3, the deep trench etching is performed using wet etching, with a trench depth of 65 μm, a trench width of 5 μm, an etching angle of 88.8°, and a P-type epitaxial fill concentration of 4.2e15cm. -2 .

[0025] Furthermore, in step S4, the thickness of the thin pre-oxidized layer is 200 Å, and the injection conditions for the Pbody region injection are 6e13 cm. -2 The annealing conditions were 60 keV, 1100℃, and 180 min.

[0026] Furthermore, in step S5, the ambient temperature for surface thermal deposition is 980°C, and the thickness of the field oxide layer is 8000 Å; the growth temperature of the gate oxide layer is 1050°C, the growth thickness is 1000 Å, and the growth time is 90 min; the self-doping concentration of the deposited polysilicon is 4.3e20cm. -3 The thickness is 4000 angstroms; the width of the gate polysilicon in the cell region is 7 μm, and the width of the polysilicon field plate in the terminal region is 15 μm.

[0027] Furthermore, in step S6, the remaining thickness of the oxide layer after etching is 200 Å; the implantation activation condition for the N+ source implantation region is 5e15cm of arsenic ions. -2 / 50keV, annealing temperature is 950℃, annealing time is 30min;

[0028] The interlayer dielectric thickness of the ILD is 11200 angstroms, the dense reflow temperature is 900℃, and the dense reflow time is 30 min;

[0029] The aperture size before metal deposition and etching is 3 μm, and the hole filling conditions are boron difluoride at 1.25e15cm. -2 / 40keV, boron 3.5e15cm -2 / 80keV, and perform rapid annealing for 15s;

[0030] The width of the metal field plate in the terminal area is 10μm, and 4μm aluminum-copper alloy front and back metal electrodes are deposited.

[0031] In summary, the present invention has the following beneficial effects: by utilizing deep trench filling technology and optimizing structural design and manufacturing process, the on-resistance is effectively reduced, the breakdown voltage level and its stability are improved, and the terminal area can be reduced to optimize the switching loss of the terminal part and improve the overall performance; by growing two N-type epitaxy layers on the substrate, the charge imbalance caused by the etching angle problem of deep trench etching is optimized. Due to the different resistivity of the two epitaxy layers, the entire N-pillar and P-pillar achieve the maximum charge balance. By performing P-type light implantation on the surface of the terminal area, the floating P-pillars in the terminal area are connected. Then, by combining polysilicon field plates and metal field plates, the surface electric field distribution is optimized to achieve more stable breakdown characteristics. Attached Figure Description

[0032] Figure 1 A cross-sectional view of the transition region and termination region of a deep trench-filled high-voltage superjunction MOS device according to one embodiment of the present invention;

[0033] Figure 2 A schematic cross-sectional view of the transition region and termination region structure of an existing deep trench filled high voltage superjunction MOS device provided by the present invention;

[0034] Figure 3 This is a comparison chart of IV curves between the present invention and existing solutions;

[0035] Figure 4 This is a comparison diagram of the surface electric field curves of the present invention and existing solutions;

[0036] Figure 5 A schematic diagram of the electric field distribution of the terminal structure of a deep trench-filled high-voltage superjunction MOS device according to one embodiment of the present invention;

[0037] Figure 6 A schematic diagram of the collision ionization rate distribution of the terminal structure of a deep trench-filled high-voltage superjunction MOS device according to one embodiment of the present invention;

[0038] Figure 7A schematic diagram of the structure after step S1 of the fabrication method of the deep trench filled 950V superjunction MOS termination structure provided by the present invention.

[0039] Figure 8 A schematic diagram of the structure after step S2 of the fabrication method of the deep trench filled 950V superjunction MOS termination structure provided by the present invention.

[0040] Figure 9 A schematic diagram of the structure after step S3 of the fabrication method of the deep trench filled 950V superjunction MOS termination structure provided by the present invention.

[0041] Figure 10 A schematic diagram of the structure after step S4 of the fabrication method of the deep trench filled 950V superjunction MOS termination structure provided by the present invention.

[0042] Figure 11 A schematic diagram of the structure after step S5 of the fabrication method of the deep trench filled 950V superjunction MOS termination structure provided by the present invention.

[0043] Figure 12 This is a schematic diagram of the structure after step S6 of the fabrication method for the deep trench filled 950V superjunction MOS termination structure provided by the present invention.

[0044] In the diagram: 101, N+ substrate; 102, primary N-type epitaxy; 103, secondary N-type epitaxy; 104, JFET implantation region; 105, deep trench filled P-pillar region; 106, Ptop floating P-pillar interconnect layer implantation; 107, Pbody body region implantation; 108, gate oxide layer; 109, cell region gate polysilicon; 110, termination region polysilicon field plate; 111, N+ source implantation region; 112, ILD dielectric layer; 113, front source metal electrode; 114, termination region metal field plate; 115, cutoff ring metal; 116, back metal electrode;

[0045] 201, N+ substrate; 202, N-type epitaxy; 203, JFET implantation region; 204, deep trench filled P-pillar region; 205, Pbody implantation region; 206, gate oxide layer; 207, cell region gate polysilicon; 208, N+ source implantation region; 209, ILD dielectric layer; 210, front source metal electrode; 211, cutoff ring metal; 212, back metal electrode. Detailed Implementation

[0046] Example:

[0047] The following is in conjunction with the appendix Figure 1-12 The present invention will be described in further detail below.

[0048] A method for fabricating a 950V superjunction MOS termination structure with a deep trench filled structure mainly includes six steps:

[0049] S1, such as Figure 7 As shown, an arsenic-doped N+ substrate 101 with a resistivity of 0.002~0.003 Ω·cm is prepared. A primary N-type epitaxial layer 102 with a thickness of 42 μm is grown on the N+ substrate 101 with a resistivity of 3.4 Ω·cm and phosphorus impurity is incorporated, and the layer is grown at a temperature of 1000℃. A secondary N-type epitaxial layer 103 with a thickness of 33 μm is grown on the N+ substrate 101 with a resistivity of 2.0 Ω·cm and phosphorus impurity is incorporated, and the layer is grown at a temperature of 1000℃.

[0050] Among them, the resistivity of the primary N-type epitaxial layer 102 and the secondary N-type epitaxial layer 103 are different. Due to the angle of the deep trench etching, the width difference between the tops of the trenches can reach 1.3μm. Therefore, the total charge of the P-pillars is lower at deeper positions. The resistivity of the primary N-type epitaxial layer 102 at the bottom is higher than that of the secondary N-type epitaxial layer 103 at the top. In this way, the primary N-type epitaxial layer 102 and the narrower P-pillars can also achieve charge balance. Similarly, the lower resistivity of the secondary N-type epitaxial layer 103 can satisfy the requirement that the total charge of the N-pillars and P-pillars in the upper half of the region is basically equal.

[0051] S2, such as Figure 8 As shown, a thin pre-oxide layer is grown on the secondary N-type epitaxial layer 103, and N-type JFET implantation is performed. The N-type JFET implantation region 104 is defined by photolithography, and then the thin pre-oxide layer on the device surface is completely removed.

[0052] The thickness of the thin pre-oxidized layer is 200 angstroms, and the implantation conditions of the N-type JFET implantation region 104 are 2e12cm. -2 / 60keV, the injected impurity is phosphorus, and the injection angle is 7°.

[0053] S3, such as Figure 9 As shown, deep trench etching and P-type epitaxial filling are performed on the primary N-type epitaxial layer 102 and the secondary N-type epitaxial layer 103. Specifically, after the N-type JFET implantation region 104 is formed, the oxide layer on the surface is completely removed, and deep trench etching of the P-pillar is performed. After the deep trench etching is completed, P-pillar epitaxial filling is performed to form the deep trench filled P-pillar region 105. Then, a sacrificial oxide layer of 1265 angstroms is grown on the surface at a furnace tube temperature of 900°C. Afterward, the oxide layer is completely removed using CMP process to ensure surface flatness.

[0054] The deep trench etching was performed using wet etching, with a trench depth of 65 μm, a trench width of 5 μm, an etching angle of 88.8°, and a P-type epitaxial fill concentration of 4.2e15cm. -2 The thickness is 65 μm, and the P-pillar doping concentration is 4.2e15 / cm. 3The depth, width, and P-pillar concentration of the superjunction MOSFET directly affect its voltage withstand performance.

[0055] S4, such as Figure 10 As shown, a thin pre-oxidized layer is grown on the surface to act as an ion implantation barrier layer at a temperature of 950°C and a thickness of 200 Å. A high-dose, low-energy P-body region implantation in the active region and a low-dose, low-energy P-type connector layer implantation in the terminal region are performed. Then, they are combined and subjected to high-temperature push-bonding to form the Pbody implantation region in the active region and the Ptop floating P-pillar connector layer implantation in the terminal region 106.

[0056] The thickness of the thin pre-oxidized layer is 200 angstroms, and the injection conditions for the Ptop floating P-pillar connecting layer injection of 106 are 2e12cm. -2 / 80keV, the injection condition for injecting 107 into the Pbody region is 6e13cm. -2 / 60keV, injection angle 7°, annealing conditions 1100℃, annealing time 180min.

[0057] S5, such as Figure 11 As shown, after P-type ion implantation, field oxygen is thermally deposited on the surface, and active region etching is performed to grow a gate oxide layer 108 in the active region. Then, polysilicon is deposited, and the deposited polysilicon is etched to form the cell region gate polysilicon 109 of the active region and the terminal region polysilicon field plate 110 of the terminal region. The etching of polysilicon is to form the polysilicon field plate of the gate and the terminal region. The gate is mainly connected to the gate PAD electrode through metal. The polysilicon field plate mainly optimizes the electric field distribution between the P-type connection layer and the P-pillar to prevent electric field spikes caused by the connection between the P-type connection layer and the P-pillar.

[0058] The surface thermal deposition environment temperature was 980℃, and the field oxide layer thickness was 8000 Å. The gate oxide layer 108 used existing mature processes to control its thickness, with a growth temperature of 1050℃, a growth thickness of 1000 Å, and a growth time of 90 min. The self-doping concentration of the deposited polysilicon was 4.3e20cm. -3 The thickness is 4000 angstroms; the width of the gate polysilicon 109 in the cell region is 7 μm, and the width of the terminal polysilicon field plate 110 is 15 μm.

[0059] S6, such as Figure 12As shown, an oxide layer of a certain thickness is etched, an N+ source implantation region 111 is formed and activated, an ILD is deposited and reflowed to form a layered ILD dielectric layer 112, and metal deposition and etching are completed by opening holes to form the front source metal electrode 113, the stop ring metal 115, and the terminal region metal field plate 114. Surface dielectrics and organic materials are deposited and etched, and after depositing a passivation layer, the lead region is photolithographically etched again. The back side of the N+ substrate 101 is metallized to form the back metal electrode 116; the metal etching is to form the floating metal field plate of the source and terminal regions. The metal field plate is mainly arranged according to the polysilicon field plate to optimize the electric field peaks of some P pillars and the polysilicon field plate. The drain motor is formed below the N+ substrate 101.

[0060] The remaining thickness of the oxide layer after etching is 200 Å; the implantation activation condition of the N+ source implantation region 111 is 5e15cm of arsenic ions. -2 / 50keV, annealing temperature is 950℃, annealing time is 30min;

[0061] Plasma-enhanced chemical vapor deposition was used on the surface to ensure that the interlayer dielectric thickness of the ILD was 11200 angstroms, the dense reflow temperature was 900℃, and the dense reflow time was 30 min;

[0062] The aperture size before metal deposition and etching is 3 μm, and the hole filling conditions are boron difluoride at 1.25e15cm. -2 / 40keV, boron 3.5e15cm -2 / 80keV, and perform rapid annealing for 15s;

[0063] A 4μm aluminum-copper alloy was then deposited and etched. The width of the terminal metal field plate 114 was 10μm, and the surface dielectric layer formed the front metal electrode and the back metal electrode 116.

[0064] The 950V superjunction MOS termination structure with deep trench filling obtained based on the above fabrication method, such as Figure 1As shown, it includes an N+ substrate 101 doped with arsenic. A back metal electrode 116 is provided on the back side of the N+ substrate 101. A primary N-type epitaxial layer 102 and a secondary N-type epitaxial layer 103 are grown sequentially with the front side of the N+ substrate 101 facing upwards. Deep trench etching and P-type epitaxial filling are used to form recessed, equally spaced deep trench-filled P-pillar regions 105 in the primary N-type epitaxial layer 102 and the secondary N-type epitaxial layer 103. After hole etching and hole injection, metal is deposited at one end of the secondary N-type epitaxial layer 103, and the front source metal electrode 113 is etched out. An ILD dielectric layer 112 is provided inside the front source metal electrode 113. A cell region gate polysilicon 109 is provided inside the ILD dielectric layer 112. Field oxide is deposited at the bottom of the ILD dielectric layer 112, and the active region is etched. A gate oxide layer 108 is grown on the surface. The top of the secondary N-type epitaxial layer 103 at this end is implanted to form a sunken JFET implantation region 104. The tops of the two outermost adjacent deep trench-filled P-pillar regions 105 at this end are treated with sacrificial oxidation and CMP to flatten the device surface. The Pbody body region implantation 107 is injected and activated, and the top of the outermost deep trench-filled P-pillar region 105 is etched with oxide layer before the N+ source implantation region 111 is injected and recessed; the gate oxide layer 108 simultaneously contacts the ILD dielectric layer 112, the cell gate polysilicon 109, the N+ source implantation region 111, the Pbody body region implantation 107, the JFET implantation region 104, and the secondary N-type epitaxial layer 103; the top of the central region of the secondary N-type epitaxial layer 103 is treated with sacrificial oxidation and CMP before the recessed floating P-pillar interconnection layer implantation 106 is injected and activated on the flat device surface, and the secondary N-type... A separate ILD dielectric layer 112 is provided on the top surface of the central region of the epitaxial layer 103. The ILD dielectric layer 112 extends to the other end of the secondary N-type epitaxial layer 103. Several equally spaced terminal polysilicon field plates 110 are provided within the ILD dielectric layer 112. After hole etching and hole injection, metal is deposited on the top of the ILD dielectric layer 112, and several equally spaced terminal metal field plates 114 are etched out. The ILD dielectric layer 112 is in contact with the Ptop floating P-pillar connection layer implantation 106, the secondary N-type epitaxial layer 103, and the front source metal electrode 113. A stop ring metal 1 is provided on the top of the other end of the secondary N-type epitaxial layer 103. 15. The two sides of the stop ring metal 115 are in contact with the surface of the ILD dielectric layer 112 in the central region. The top of the secondary N-type epitaxial layer 103 at this end is not injected with a floating P-pillar connection layer 106. The number of polysilicon field plates 110 in the terminal region of the ILD dielectric layer 112 is greater than the number of metal field plates 114 in the terminal region. The thickness of the ILD dielectric layer 112 in the central region of the secondary N-type epitaxial layer 103 is greater than the thickness of the ILD dielectric layers 112 on both sides of the secondary N-type epitaxial layer 103. The primary N-type epitaxial layer 102 and the secondary N-type epitaxial layer 103 are generally of a structure that is wider at the top and narrower at the bottom. The deep trench filled P-pillar region 105 is generally of a structure that is narrower at the top and wider at the bottom.

[0065] The total positive and negative charges of the first N-type epitaxial layer 102 and the lower half of the deep trench-filled P-pillar region 105 are approximately equal. Similarly, the total positive and negative charges of the second N-type epitaxial layer 103 and the upper half of the deep trench-filled P-pillar region 105 are also approximately equal. The purpose of these two N-type epitaxies is to alleviate the charge imbalance caused by the P-pillar trench etching angle. By adjusting the resistivity of the two epitaxies and the P-pillar epitaxial concentration, the breakdown voltage performance of the superjunction MOSFET can be adjusted. The implantation dose and implantation energy of the Pbody implantation 107 can adjust the threshold voltage of the superjunction MOSFET. The number of P-pillar connections in the Ptop floating P-pillar connection layer implantation 106 in the termination region can adjust the electric field distribution on the termination surface and optimize the electric field peak value in the termination region. Increasing the number of P-pillars optimizes the electric field distribution in the termination region; more P-pillars result in a more stable breakdown voltage and fewer electric field spikes.

[0066] The N-type substrate, used in two epitaxy layers, compensates for the charge imbalance between the upper and lower P-pillars and N-pillars caused by deep trench etching, similar to two superjunctions. This achieves charge balance between the upper and lower P-pillars and N-pillars respectively. Since the depth of the P-pillars gradually increases with the breakdown voltage, the trench etching will have a certain tilt angle. Single epitaxy is difficult to guarantee the breakdown voltage parameters, while double epitaxy greatly alleviates this situation. A P-type interconnect layer is used to condense the floating P-pillars in the termination region, optimizing the electric field peaks between P-pillars caused by a single floating P-pillar, thereby optimizing the collisional ionization rate of the termination region. An alternating design of polysilicon field plates and metal field plates is used to solve the problem of high electric field regions after the connection of the floating P-pillars in the termination region with the P-type interconnect layer, further optimizing the electric field distribution in the termination region, so that the breakdown region is concentrated near the cell rather than in the termination region. The P-type interconnect layer, polysilicon field plate, and metal field plate effectively reduce the termination region area at the 950V level.

[0067] Figure 3 Comparing the IV characteristics of existing structures and the structure of this application, the breakdown voltage of the structure of this application is higher than that of conventional superjunction MOS devices. From Figure 3 As can be seen, the two structures differ significantly in voltage magnitude. The curves represent the line current in a two-dimensional simulation. The conventional superjunction MOS device can only achieve a breakdown voltage of around 974V, failing to reach the required 1100V voltage level. This is because in a single-epitaxy superjunction MOS device, the presence of a deep trench etching angle leads to charge imbalance, preventing the device from achieving charge balance as with 90° etching. The termination region is entirely composed of floating P-pillars, failing to optimize the surface electric field, and the breakdown region is mainly concentrated near the gate electrode in the termination region. However, by connecting floating P-pillars with Ptops and combining them with polysilicon and metal field plates to optimize the surface electric field, the breakdown region is brought closer to the cell.

[0068] Figure 4 To compare the electric field distribution of the existing structure and the structure of this application, from Figure 4As can be seen, the terminal structure of this application significantly optimizes the surface electric field. The high electric field near the gate electrode in the terminal region is optimized, making the overall electric field of the terminal region more uniform. This also concentrates areas with high collisional ionization rates near the cell and transition regions, allowing the cell and transition regions to break down preferentially.

[0069] Figure 5 This is a schematic diagram of the electric field distribution of the scheme in this application. Figure 5 As can be seen, the electric field is highest near the cell region. As the P pillars in the terminal region are gradually depleted, the electric field gradually decreases. Furthermore, the electric field near the gate metal gradually becomes more uniform due to the presence of the Ptop interconnect layer, the floating polysilicon field plate, and the floating metal field plate.

[0070] Figure 6 This is a schematic diagram of the collision ionization rate of the scheme in this application. Figure 6 As can be seen, the collisional ionization rate is highest in the cell region and the transition region, and breakdown occurs preferentially.

[0071] Compared to existing solutions, this application addresses the shortcomings of unstable breakdown voltage and inability to further increase withstand voltage in high-voltage applications. It utilizes Ptop light ion implantation to connect the floating P-pillars in the termination region, and combines this with polysilicon and metal field plates to optimize the local electric field, achieving a more stable termination withstand voltage. This ensures higher withstand voltage while ensuring breakdown occurs near the cell and transition regions. More stable termination breakdown characteristics can be achieved simply by adjusting the number of floating P-pillars connected by the Ptop or by adjusting the relative positions of the polysilicon and metal field plates. As the breakdown voltage increases further, the number of floating P-pillars in the termination region can be adjusted, and the corresponding withstand voltage can be obtained by adjusting the number of P-pillars connected by the Ptop and the position of the field plates.

[0072] It should be noted that this specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. Those skilled in the art, after reading this specification, can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they fall within the scope of the claims of the present invention. Other principles based on the present invention, such as using double epitaxy to improve the withstand voltage of deep trench etched superjunctions, and using Ptop interconnect layers, polysilicon floating field plates, and metal floating field plates to optimize the surface electric field, are also within the scope of protection of the present invention.

Claims

1. A 950V superjunction MOS termination structure with a deep trench filled structure, characterized in that: It includes an N+ substrate, with a back metal electrode on the back side of the N+ substrate, and a series of primary N-type epitaxial layers and secondary N-type epitaxial layers arranged sequentially on the front side of the N+ substrate. The primary N-type epitaxial layer and the secondary N-type epitaxial layer are filled with recessed, equally spaced deep grooves to create P-pillar regions. One end of the secondary N-type epitaxial layer is provided with a front-side source metal electrode. Inside the front-side source metal electrode is an ILD dielectric layer. Inside the ILD dielectric layer is a cell region gate polysilicon. At the bottom of the ILD dielectric layer is a gate oxide layer. At the top of the secondary N-type epitaxial layer at this end is a sunken JFET implantation region. At the top of the two adjacent deep trench-filled P-pillar regions at the outermost end is a Pbody body region implantation region. At the top of the outermost deep trench-filled P-pillar region at this end is a recessed N+ source implantation region. The gate oxide layer is simultaneously in contact with the ILD dielectric layer, the cell region gate polysilicon, the N+ source implantation region, the Pbody body implantation region, the JFET implantation region, and the secondary N-type epitaxial surface. The secondary N-type epitaxial layer has a recessed Ptop floating P-pillar connection layer implanted at the top of its central region. A separate ILD dielectric layer is located on the top surface of the central region of the secondary N-type epitaxial layer, extending to the other end of the secondary N-type epitaxial layer. Several equally spaced terminal polysilicon field plates are located within the ILD dielectric layer, and several equally spaced terminal metal field plates are located on the top of the ILD dielectric layer. The ILD dielectric layer is in contact with the Ptop floating P-pillar connection layer implanted, the secondary N-type epitaxial layer, and the front source metal electrode surface. The other end of the secondary N-type epitaxial layer is provided with a stop ring metal. The two sides of the stop ring metal are in contact with the ILD dielectric layer in the central region. There is no Ptop floating P-pillar connecting layer injected at the top of the secondary N-type epitaxial layer at this end.

2. The 950V superjunction MOS termination structure with deep trench filling according to claim 1, characterized in that: The number of polysilicon field plates in the terminal region of the ILD dielectric layer is greater than the number of metal field plates in the terminal region.

3. The 950V superjunction MOS termination structure with deep trench filling according to claim 1, characterized in that: The thickness of the ILD dielectric layer in the central region of the secondary N-type epitaxial layer is greater than the thickness of the ILD dielectric layers on both sides of the secondary N-type epitaxial layer.

4. The 950V superjunction MOS termination structure with deep trench filling according to claim 1, characterized in that: The primary and secondary N-type epitaxy have an overall structure that is wider at the top and narrower at the bottom, while the deep groove-filled P-pillar region has an overall structure that is narrower at the top and wider at the bottom.

5. A method for fabricating a 950V superjunction MOS termination structure with a deep trench filled structure, characterized in that: The steps are as follows: S1. Prepare an N+ substrate, and grow a first N-type epitaxial growth and a second N-type epitaxial growth on the N+ substrate in sequence; S2. A thin pre-oxidant layer is grown on the secondary N-type epitaxy, and JFET implantation is performed to form the JFET implantation region. The thin pre-oxidant layer on the device surface is then removed. S3. Deep trench etching and P-type epitaxial filling are performed on the primary N-type epitaxial layer and the secondary N-type epitaxial layer to form a deep trench filled P-pillar region. A sacrificial oxide layer is grown on the surface and CMP mechanical planarization is performed to maintain the surface flatness. S4. A thin pre-oxidized layer is grown on the surface as an injection barrier layer, and high-dose, low-energy P-type body region injection in the active region and low-dose, low-energy P-type connecting layer injection in the primary terminal region are performed. High-temperature push-bonding is used to form the Pbody injection region in the active region and the Ptop floating P-pillar connecting layer injection in the terminal region. S5. Thermally deposit field oxygen on the surface and perform active region etching to grow a gate oxide layer in the active region, deposit polysilicon and perform etching to form cell region gate polysilicon and terminal region polysilicon field plate. S6. Etch the oxide layer, implant to form the N+ source implantation region and activate it, deposit and reflow the ILD to form a layered ILD dielectric layer, open the hole to complete the metal deposition and etching, and form the front source metal electrode, the cut-off ring metal and the terminal region metal field plate. Metallize the back side of the N+ substrate to form the back metal electrode.

6. The method for fabricating a 950V superjunction MOS termination structure with a deep trench filling structure according to claim 5, characterized in that: In step S1, the resistivity of the primary and secondary N-type epitaxy is different. In step S2, the thickness of the thin pre-oxidation layer is 200 Å, and the implantation condition of the N-type JFET implantation region is 2e12cm. -2 / 60keV.

7. The method for fabricating a 950V superjunction MOS termination structure with a deep trench filling structure according to claim 5, characterized in that: In step S3, the deep trench etching is performed using wet etching. The etched area has a trench depth of 65 μm, a trench width of 5 μm, an etching angle of 88.8°, and a P-type epitaxial fill concentration of 4.2e15cm. -2 .

8. The method for fabricating a 950V superjunction MOS termination structure with a deep trench filling structure according to claim 5, characterized in that: In step S4, the thickness of the thin pre-oxidized layer is 200 Å, and the injection conditions for the Pbody region are 6e13 cm. -2 The annealing conditions were 60 keV, 1100℃, and 180 min.

9. The method for fabricating a 950V superjunction MOS termination structure with a deep trench filling structure according to claim 5, characterized in that: In step S5, the ambient temperature for surface thermal deposition is 980℃, and the thickness of the field oxide layer is 8000 Å; the growth temperature of the gate oxide layer is 1050℃, the growth thickness is 1000 Å, and the growth time is 90 min; the self-doping concentration of the deposited polysilicon is 4.3e20cm. -3 The thickness is 4000 angstroms; the width of the gate polysilicon in the cell region is 7 μm, and the width of the polysilicon field plate in the terminal region is 15 μm.

10. The method for fabricating a 950V superjunction MOS termination structure with a deep trench filling structure according to claim 5, characterized in that: The remaining thickness of the oxide layer after etching in step S6 is 200 Å; the implantation activation condition for the N+ source implantation region is 5e15cm of arsenic ions. -2 / 50keV, annealing temperature is 950℃, annealing time is 30min; The interlayer dielectric thickness of the ILD is 11200 angstroms, the dense reflow temperature is 900℃, and the dense reflow time is 30 min; The aperture size before metal deposition and etching is 3 μm, and the hole filling conditions are boron difluoride at 1.25e15cm. -2 / 40keV, boron 3.5e15cm -2 / 80keV, and perform rapid annealing for 15s; The width of the metal field plate in the terminal area is 10μm, and 4μm aluminum-copper alloy front and back metal electrodes are deposited.

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