BC battery preparation process
By combining inkjet printing of hot-melt materials with chemical etching, the problems of complex BC battery manufacturing processes, high costs, and low yield rates have been solved, enabling efficient and low-cost BC battery production.
Patent Information
- Application Number
- CN202510981395.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-16
- Publication Date
- 2025-10-31
AI Technical Summary
Existing BC battery manufacturing processes are complex, have high production costs, low yield rates, and low mass production efficiency.
The mask area is formed by inkjet printing of hot melt material, and P/N type interdigitated structure is prepared by chemical etching. Appropriate cleaning and etching solutions are selected to ensure the adjustability of the processing window and the integrity of the material, and to avoid damage.
It improved the yield rate of BC batteries, reduced production costs, shortened processing time, and increased production efficiency.
Smart Images
Figure CN120882151A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of photovoltaic cell manufacturing technology, specifically to a BC cell manufacturing process with higher yield and lower manufacturing cost. Background Technology
[0002] Back-contact solar cells (hereinafter referred to as BC cells) are a type of photovoltaic cell in which the positive and negative electrodes are arranged on the back side. In traditional solar cells, the front side has grid lines to collect current, which can block some sunlight and cause energy loss. However, by adjusting the positive and negative electrodes to the back side, BC cells achieve a grid-free design on the front side, thus reducing light energy loss and achieving higher conversion efficiency.
[0003] However, the fabrication process of BC cells is correspondingly more complex than that of traditional solar cells. In conventional processing, selectively forming staggered P-type and N-type doped regions on the back of the BC cell using precision techniques such as masking or laser doping is a complex step. The conventional masking and chemical etching process mainly includes steps such as photoresist coating, exposure, development, chemical etching, and mask removal. This overall process is complex and costly; the development window is narrow, making it easy for mask material residue to occur, which makes it difficult to control the product yield. The laser etching process mainly includes steps such as mask preparation, exposure, laser ablation, cleaning, and passivation. The high temperature of the laser during this process can cause thermal damage such as microcracks in the silicon substrate, amorphization, or diffusion of doped regions. Furthermore, this process has a slower production cycle, resulting in lower mass production efficiency for BC cells.
[0004] Therefore, there is an urgent need for a BC battery manufacturing process that can overcome the shortcomings of the traditional BC battery processing technology. Summary of the Invention
[0005] The purpose of this invention is to provide a BC battery manufacturing process with high production yield, low production cost and fast production speed.
[0006] This invention is achieved through the following technical solution: A BC battery fabrication process includes the following steps: S1. Processing the back side of an N-type silicon wafer to sequentially form a SiO2 layer, a p-type polycrystalline silicon layer, and a borosilicate glass layer from the inside out on the back side of the N-type silicon wafer; S2. Inkjet printing a hot-melt material onto the surface of a p-shaped poly region defined on the back side of the N-type silicon wafer to form a mask region, etching the borosilicate glass layer in the non-mask region; removing the hot-melt material in the mask region, and then etching the p-type polycrystalline silicon layer in the borosilicate glass removal region; S3. Processing the back side of the N-type silicon wafer to sequentially form a SiO2 layer, a p-type polycrystalline silicon layer, and a borosilicate glass layer on the back side of the N-type silicon wafer from the inside out; S4. A SiO2 layer, an n-type polycrystalline silicon layer, and a phosphosilicate glass layer are sequentially formed on the back side of the N-type silicon wafer from the inside out; S5. A hot-melt material is inkjet printed on the surface of the n-shaped poly area defined on the back side of the N-type silicon wafer to form a mask area, and the phosphosilicate glass layer in the non-mask area is etched; the hot-melt material in the mask area is removed, and the n-type polycrystalline silicon layer in the phosphosilicate glass removal area is etched again while texturing the front side of the N-type silicon wafer; S6. The front and back surfaces of the N-type silicon wafer are passivated; S7. Screen printing and sintering are performed on the back side of the N-type silicon wafer to prepare a metal electrode.
[0007] In S1 and S3, conventional existing techniques can be used to process the corresponding structure on the back side of the N-type silicon wafer. For example, in S1 and S3, any one of the following deposition methods can be used to deposit a SiO2 layer and a polycrystalline silicon layer on the back side of the N-type silicon wafer: low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD). Subsequently, the subsequent processing steps can be adjusted according to processing factors such as the deposition method. For example, after completing the deposition using LPCVD in S1, boron diffusion is required in a diffusion furnace to obtain the p-type polycrystalline silicon layer and borosilicate glass layer. When using PECVD or PVD, boron can be incorporated during the deposition process, and only high-temperature annealing is needed to obtain the required p-type polycrystalline silicon layer and borosilicate glass layer. In S3, when using LPCVD, phosphorus diffusion is performed after deposition. When using PECVD or PVD, phosphorus is incorporated during the deposition process, followed by high-temperature annealing.
[0008] In this invention, the ease of shaping inkjet thermal fusion materials is utilized during the fabrication of BC batteries to create mask areas of different shapes on the back of N-type silicon wafers, facilitating chemical etching. Simultaneously, the highly adjustable processing window of inkjet processing ensures proper connection between its processing windows and those of etching and cleaning steps. This results in a suitable overall processing rhythm for the BC battery fabrication process, preventing disruptions to the overall processing rhythm caused by excessively short processing windows for certain steps.
[0009] As a further improvement of the present invention, the hot melt material is selected from at least one of acrylate, rosin resin, C11-C22 alkyl acid, polypropylene wax, microcrystalline wax, polyethylene wax, and ethylene-vinyl acetate copolymer wax. The selection of the above-mentioned hot melt material is based on its strong shaping ability; the hot melt material can accurately form a mask area with the required shape and size parameters on the back side of an N-type silicon wafer using inkjet printing. Furthermore, the physicochemical properties of the hot melt material meet the requirements of the BC battery fabrication process. Specifically, the hot melt material will not be removed during the etching step, thus preventing damage to the mask area, and the hot melt material can be completely removed from the N-type silicon wafer using cleaning solutions or similar means without affecting subsequent etching and other processing steps.
[0010] As a further improvement of the present invention, a cleaning solution is used in S2 and S4 to remove the hot-melt material in the mask area. The cleaning solution contains 1-10 wt% diethylene glycol butyl ether and 1-10 wt% NaOH; the cleaning time of the cleaning solution in S2 and S4 is 60-400 s. Hereinafter, diethylene glycol butyl ether is abbreviated as BDG. With the selection of the above-mentioned hot-melt material and cleaning solution, on the one hand, it is ensured that the hot-melt material can be thoroughly removed from the N-type silicon wafer after the masking process is completed; on the other hand, the cleaning solution will not damage other material layers on the BC battery, thus ensuring that the step of manufacturing the mask area using inkjet hot-melt material does not conflict with other steps in the BC battery fabrication process.
[0011] As a further improvement of the present invention, in S2 and S4, the thickness of the mask layer formed by the hot melt material is 2~30µm. If the mask layer is too thin, it is difficult to achieve the desired masking effect, which may cause the etching solution to corrode the material within the mask area, resulting in defective batteries and thus reducing the battery yield. Conversely, if the mask layer is too thick, it wastes hot melt material and may increase the difficulty of cleaning the hot melt material, increasing the probability of residual hot melt material, which affects subsequent battery processing steps and also easily reduces the overall battery yield.
[0012] As a further improvement of the present invention, between S4 and S5, the following step is also included: removing the borosilicate glass layer and phosphosilicate glass layer remaining on the back side of the N-type silicon wafer.
[0013] As a further improvement of the present invention, in S2 and S4, and between S4 and S5, when removing the residual borosilicate glass layer and phosphosilicate glass layer, the borosilicate glass layer and / or the phosphosilicate glass layer are etched with an etching solution, wherein the etching solution is an acid solution.
[0014] As a further improvement of the present invention, in S2, the volume concentration of the etching solution is 50-80%, and the reaction time is 20-180 s; in S4, the volume concentration of the etching solution is 5-50%, and the reaction time is 15-150 s; in S5, the volume concentration of the etching solution is 20-70%, and the reaction time is 20-180 s. In S2 and S4, when the etching solution is performing the etching operation, the hot-melt material is still attached to the back side of the N-type silicon wafer. Therefore, the limitation of the etching solution concentration and the etching reaction time in this step ensures both the smooth progress of the etching operation in the non-mask area and prevents the etching solution from eroding and damaging the hot-melt material in the mask area.
[0015] As a further improvement of the present invention, in S2, a first reaction solution is used to remove the p-type polycrystalline silicon layer in the borosilicate glass removal zone. The first reaction solution contains at least an alkaline solution, which is selected from at least one of NaOH solution and KOH solution, and the volume concentration of the alkaline solution is 0.5~10%.
[0016] As a further improvement of the present invention, the first reaction solution further includes an etching additive, wherein the etching additive is selected from at least one of wetting agents, corrosion inhibitors, stabilizers, and complexing agents.
[0017] As a further improvement of the present invention, in S2, when etching the p-type polycrystalline silicon layer in the borosilicate glass removal zone, the reaction temperature is 40~80 ℃ and the reaction time is 100~300 s.
[0018] As a further improvement of the present invention, in S4, a second reaction solution is used to etch the n-type polycrystalline silicon layer in the phosphorosilicate glass removal zone and simultaneously texturing is performed. The second reaction solution contains at least an alkaline solution and a texturing additive. The alkaline solution is selected from at least one of NaOH solution and KOH solution, and its volume concentration is 0.5-10%.
[0019] As a further improvement of the present invention, in S4, when etching the n-type polycrystalline silicon layer in the phosphorus glass removal zone, the reaction temperature is 50~85 ℃ and the reaction time is 100~300 s.
[0020] The beneficial effect of this invention is that, in the fabrication process of BC batteries, a processing step is introduced to form a mask area by inkjet printing hot melt material, and at the same time, a P / N type cross-finger structure is prepared by chemical etching.
[0021] On the one hand, compared to the conventional process route combining masking and chemical etching, the process in this invention has lower requirements for the timing of transitions between steps. For example, the processing window of each step is more adjustable, unlike the strict limitations on the processing window in existing technologies such as development. In this invention, the adjustment of the processing window of each step can achieve coordination between multiple processing steps, thereby optimizing the overall processing speed of the fabrication process. At the same time, the process of this invention, through the selection of hot melt materials, cleaning solutions, and other reaction agents, ensures that the removal of mask materials is relatively convenient. This reduces the probability of hot melt materials remaining in the original mask area after the mask removal step, thus reducing the probability of obtaining defective products and improving the yield of BC cells. In addition, the selection of reaction agents is also compatible with the BC cell fabrication process. For example, it ensures that the mask material is not eliminated by the etching solution and other reaction agents, and that the cleaning solution and other materials do not damage the structure on the N-type silicon wafer, such as the BSG layer. This ensures the smooth integration of the inkjet printing hot melt material to form the mask area into the BC cell fabrication process.
[0022] On the other hand, compared with the laser etching process, the process in this invention ensures that the N-type silicon wafer and its surface structure are not damaged during processing through the selection of reaction reagents, thereby improving the production yield of BC cells. At the same time, the inkjet equipment used in the fabrication process of this invention has relatively lower procurement and maintenance costs than the precision laser equipment used in the laser etching process, which is conducive to the promotion and use of the fabrication process of this invention. In addition, the reaction time of each step in this invention is shorter, making the overall processing cycle of the fabrication process faster than that of the laser etching process, thus improving the fabrication efficiency of BC cells. Attached Figure Description
[0023] The accompanying drawings are provided below to illustrate the preferred embodiments of the invention and to aid in understanding the objectives and advantages of the invention, wherein: Figure 1 The flowchart of the processing steps shown in Example 1 is as follows. Detailed Implementation
[0024] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.
[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Example
[0026] This embodiment provides a BC battery fabrication process, see attached document. Figure 1 As shown, it includes the following steps: S1. Polish the back side of the N-type silicon wafer, wash it with water, and then dry it. The polishing process of the silicon substrate can use mature existing technology. In this embodiment, for example, the N-type silicon wafer is reacted for 350 s in a mixture of 4% volume concentration NaOH solution and polishing additive at a reaction temperature of 60 ℃. The polishing additive used is a common commercially available product, such as those produced by companies like Shichuang, Sanfeng, and Topband. After polishing, the back side of the N-type silicon wafer is processed to sequentially prepare a SiO2 layer, a p-type polycrystalline silicon layer (hereinafter referred to as the P-poly layer), and a borosilicate glass layer (hereinafter referred to as the BSG layer) from the inside out on the back side of the N-type silicon wafer. In this embodiment, for example, firstly, a SiO2 layer and a polycrystalline silicon layer are deposited on the back side of an N-type silicon wafer using LPCVD, wherein the thickness of the SiO2 layer is controlled at 1.2 nm and the thickness of the polycrystalline silicon layer is controlled at 60 nm; subsequently, the N-type silicon wafer is subjected to boron diffusion using a diffusion furnace to process the polycrystalline silicon layer into a P-poly layer, and a BSG layer is formed on its surface.
[0027] S2. A hot-melt material is inkjet-printed onto the surface of the p-shaped poly region defined on the back of the N-type silicon wafer to form a mask area. In this embodiment, the hot-melt material used is polypropylene wax, and the thickness of the hot-melt material on the N-type silicon wafer is 25 μm.
[0028] After the masked area is formed, the BSG layer in the non-masked area is etched using an etching solution. In this embodiment, for example, the etching solution used is a 65% volume concentration HF solution, and the etching reaction lasts for 130 seconds.
[0029] After the BSG layer is etched, a cleaning solution is used to remove the hot-melt material in the mask area. In this embodiment, for example, the cleaning solution used is a mixed solution containing 5 wt% BDG and 7 wt% NaOH, and the cleaning time is 360 s.
[0030] After removing the hot-melt material, the P-poly layer in the BSG removal area is etched using a first reaction solution. In this embodiment, for example, the first reaction solution contains a NaOH solution and an etching additive, wherein the NaOH solution has a volume concentration of 7.5%; the etching additive is a common commercially available product that can maintain the stability of the chemical composition of the first reaction solution and control the reaction rate, and can be an etching additive produced by manufacturers such as Shichuang, Sanfeng, and Topband; the etching reaction is carried out at 45 °C for 180 s.
[0031] S3. The back side of the N-type silicon wafer is processed to sequentially form a SiO2 layer, an n-type polycrystalline silicon layer (hereinafter referred to as the N-poly layer), and a phosphosilicate glass layer (hereinafter referred to as the PSG layer) from the inside out on the back side of the N-type silicon wafer. In this embodiment, for example, the SiO2 layer and the polycrystalline silicon layer are deposited on the back side of the N-type silicon wafer by LPCVD, wherein the thickness of the SiO2 layer is controlled at 1.2 nm and the thickness of the polycrystalline silicon layer is controlled at 60 nm; subsequently, phosphorus diffusion is performed on the N-type silicon wafer using a diffusion furnace to process the polycrystalline silicon layer into an N-poly layer, and a PSG layer is formed on its surface.
[0032] S4. A hot-melt material is inkjet-printed onto the surface of the n-shaped poly area defined on the back of the N-type silicon wafer to form a mask area. The hot-melt material used is still polypropylene wax; the thickness of the hot-melt material on the N-type silicon wafer is 25 μm.
[0033] After the mask region is formed, the PSG layer in the non-mask region is etched using the etching solution. The etching solution used is a 45% volume concentration HF solution, and the etching reaction lasts for 130 seconds.
[0034] After the PSG layer etching is completed, the hot-melt material in the mask area is removed using the cleaning solution. The cleaning solution used is a mixed solution containing 5 wt% BDG and 7 wt% NaOH, and the cleaning time is 360 s.
[0035] After removing the hot-melt material, a second reaction solution is used to etch the N-poly layer in the PSG removal area and simultaneously texturize the front side of the N-type silicon wafer. In this embodiment, for example, the second reaction solution contains a NaOH solution and a texturing additive, wherein the NaOH solution has a volume concentration of 7.5%; the texturing additive is a common commercially available product that can form a uniform, dense, low-reflectivity textured surface on the silicon wafer to enhance the light absorption capacity of the BC cell; etching additives produced by manufacturers such as CECI, Sanfeng, and Topband can be used; the etching reaction is carried out at 55 °C for 200 s.
[0036] After texturing, an etching solution is used to further remove the residual BSG and PSG layers on the back side of the N-type silicon wafer. The etching solution used is a 65% volume concentration HF solution, and the etching reaction lasts for 120 seconds.
[0037] In S1 of this embodiment, when processing the back structure of the N-type silicon wafer, some p-type polysilicon components are deposited around the front edge of the N-type silicon wafer. However, when the p-type polysilicon layer in the non-mask area is removed using an etchant in S2, the p-type polysilicon deposited around the front edge will be removed simultaneously by etching. Correspondingly, in S3 and S4, the n-type polysilicon deposited around the front edge can also be removed during the preparation process. Overall, the preparation process of this embodiment ensures that the plating phenomenon will not affect the subsequent processing of the BC battery, ensuring that a BC battery that meets the usage requirements can be prepared, and thus not affecting the production yield of the BC battery.
[0038] S5. Passivate the front and back surfaces of the N-type silicon wafer to generate a passivation layer. The passivation step can employ mature existing technology. In this embodiment, for example, an atomic layer deposition device is used to deposit passivation layers on the front and back surfaces of the N-type silicon wafer. The formed passivation layer includes an aluminum oxide layer with a deposition thickness of 30 nm.
[0039] S6. Screen printing and sintering are performed on the back side of the N-type silicon wafer to prepare a metal electrode. The metal electrode preparation step can use mature existing technology. In this embodiment, for example, silver paste is deposited on the P / N junction by screen printing, and then sintering is performed to prepare the metal electrode.
[0040] The preparation process in this embodiment improves the yield by 0.4% compared to the laser etching process using the same raw materials. Example
[0041] This embodiment provides a BC battery manufacturing process, which includes the following steps: S1. Polish the back side of the N-type silicon wafer, wash it with water, and then dry it. The polishing process of the silicon substrate can use mature existing technology. In this embodiment, for example, the N-type silicon wafer is reacted for 250 s in a mixture of 6% volume concentration NaOH solution and polishing additive at a reaction temperature of 65 ℃. The polishing additive used is a common commercially available product, such as those produced by companies like Shichuang, Sanfeng, and Topband. After polishing, the back side of the N-type silicon wafer is processed to sequentially prepare a SiO2 layer, a p-type polycrystalline silicon layer (hereinafter referred to as the P-poly layer), and a borosilicate glass layer (hereinafter referred to as the BSG layer) from the inside out on the back side of the N-type silicon wafer. In this embodiment, for example, a SiO2 layer and a boron-doped polysilicon layer are deposited on the back side of an N-type silicon wafer by PVD, wherein the thickness of the SiO2 layer is controlled at 1.1 nm and the thickness of the boron-doped polysilicon layer is controlled at 110 nm. Subsequently, the boron-doped polysilicon layer is activated by annealing at 950 °C for 40 min to form a P-poly layer, and a BSG protective layer is formed on its surface.
[0042] S2. A hot-melt material is inkjet printed onto the p-shaped poly area on the back side of the N-type silicon wafer to form a mask area. In this embodiment, the hot-melt material used is rosin ester resin; the thickness of the hot-melt material on the N-type silicon wafer is 14 μm.
[0043] After the mask area is formed, the BSG layer in the non-mask area is etched using an etching solution. In this embodiment, for example, the etching solution used is a 75% volume concentration HF solution, and the etching reaction lasts for 170 s.
[0044] After the BSG layer is etched, a cleaning solution is used to remove the hot-melt material in the mask area. In this embodiment, for example, the cleaning solution used is a mixed solution containing 6 wt% BDG and 5 wt% NaOH, and the cleaning time is 280 s.
[0045] After removing the hot-melt material, the P-poly layer in the BSG removal area is etched using a first reaction solution. In this embodiment, for example, the first reaction solution contains a NaOH solution and an etching additive, wherein the NaOH solution has a volume concentration of 10%; the etching additive is a common commercially available product that can maintain the stability of the chemical composition of the first reaction solution and control the reaction rate, and can be an etching additive produced by manufacturers such as Shichuang, Sanfeng, and Topband; the etching reaction is carried out at 75°C for 200 seconds.
[0046] S3. The back side of the N-type silicon wafer is processed to sequentially form a SiO2 layer, an n-type polycrystalline silicon layer (hereinafter referred to as the N-poly layer), and a phosphorus silicate glass layer (hereinafter referred to as the PSG layer) from the inside out on the back side of the N-type silicon wafer. In this embodiment, for example, the SiO2 layer and the phosphorus-doped polycrystalline silicon layer are deposited on the back side of the N-type silicon wafer by PVD, wherein the thickness of the SiO2 layer is controlled at 1.1 nm and the thickness of the phosphorus-doped polycrystalline silicon layer is controlled at 110 nm. Subsequently, the phosphorus-doped polycrystalline silicon layer is annealed at 950 °C for 40 min to activate and form the N-poly layer, and a PSG protective layer is formed on its surface.
[0047] S4. A hot-melt material is inkjet-printed onto the surface of the n-shaped poly area defined on the back of the N-type silicon wafer to form a mask area. The hot-melt material used is still rosin ester resin; the thickness of the hot-melt material on the N-type silicon wafer is 14 μm.
[0048] After the mask area is formed, the PSG layer in the non-mask area is etched using the etching solution. The etching solution used is a 35% volume concentration HF solution, and the etching reaction lasts for 120 seconds.
[0049] After the PSG layer etching is completed, the hot-melt material in the mask area is removed using the cleaning solution. The cleaning solution used is a mixed solution containing 6 wt% BDG and 5 wt% NaOH, and the cleaning time is 280 s.
[0050] After removing the hot-melt material, a second reaction solution is used to etch the N-poly layer in the PSG removal area and simultaneously texturize the front side of the N-type silicon wafer. In this embodiment, for example, the second reaction solution contains a NaOH solution and a texturing additive, wherein the NaOH solution has a volume concentration of 9.5%; the texturing additive is a common commercially available product that can form a uniform, dense, low-reflectivity textured surface on the silicon wafer to enhance the light absorption capacity of the BC cell; etching additives produced by manufacturers such as CECI, Sanfeng, and Topband can be used; the etching reaction is carried out at 60 °C for 240 s.
[0051] After texturing, an etching solution is used to further remove the residual BSG and PSG layers on the back side of the N-type silicon wafer. The etching solution used is a 50% volume concentration HF solution, and the etching reaction lasts for 90 seconds.
[0052] S5. Passivate the front and back surfaces of the N-type silicon wafer to generate a passivation layer. The passivation step can employ mature existing technology. In this embodiment, for example, plasma chemical vapor deposition equipment is used to deposit passivation layers on the front and back surfaces of the N-type silicon wafer. The formed passivation layer contains a silicon nitride thin film with a thickness of 80 nm and a refractive index of 2.1.
[0053] S6. Screen printing and sintering are performed on the back side of the N-type silicon wafer to prepare a metal electrode. The metal electrode preparation step can use mature existing technology. In this embodiment, for example, silver paste is deposited on the P / N junction by screen printing, and then sintering is performed to prepare the metal electrode.
[0054] The preparation process in this embodiment improves the yield by 0.3% compared to the laser etching process using the same raw materials. Example
[0055] This embodiment provides a BC battery manufacturing process, which includes the following steps: S1. Polish the back side of the N-type silicon wafer, wash with water, and then dry. The polishing process of the silicon substrate can employ mature existing technologies. In this embodiment, for example, the N-type silicon wafer is reacted for 300 seconds at a reaction temperature of 70 °C in a mixture of 8% (v / v) NaOH solution and polishing additives. The polishing additives used are common commercially available products, such as those produced by companies like Shichuang, Sanfeng, and Topband. After polishing, the back side of the N-type silicon wafer is processed to sequentially prepare a SiO2 layer, a p-type polycrystalline silicon layer (hereinafter referred to as the P-poly layer), and a borosilicate glass layer (hereinafter referred to as the BSG layer) from the inside out on the back side of the N-type silicon wafer. In this embodiment, for example, a SiO2 layer and a boron-doped polysilicon layer are deposited on the back side of an N-type silicon wafer by PECVD, wherein the thickness of the SiO2 layer is controlled at 1.4 nm and the thickness of the boron-doped polysilicon layer is controlled at 90 nm. Subsequently, the boron-doped polysilicon layer is activated by annealing at 900 °C for 60 min to form a P-poly layer, and a BSG protective layer is formed on its surface.
[0056] S2. A hot-melt material is inkjet-printed onto the p-shaped poly area on the back side of the N-type silicon wafer to form a mask area. In this embodiment, the hot-melt material used is ethylene-vinyl acetate copolymer wax; the thickness of the hot-melt material on the N-type silicon wafer is 8 μm.
[0057] After the masked area is formed, the BSG layer in the non-masked area is etched using an etching solution. In this embodiment, for example, the etching solution used is a 55% volume concentration HF solution, and the etching reaction lasts for 180 s.
[0058] After the BSG layer is etched, a cleaning solution is used to remove the hot-melt material in the mask area. In this embodiment, for example, the cleaning solution used is a mixed solution containing 10 wt% BDG and 5 wt% NaOH, and the cleaning time is 200 s.
[0059] After removing the hot-melt material, the P-poly layer in the BSG removal area is etched using a first reaction solution. In this embodiment, for example, the first reaction solution contains a NaOH solution and an etching additive, wherein the NaOH solution has a volume concentration of 4%; the etching additive is a common commercially available product that can maintain the stability of the chemical composition of the first reaction solution and control the reaction rate, and can be an etching additive produced by manufacturers such as Shichuang, Sanfeng, and Topband; the etching reaction is carried out at 65°C for 150 seconds.
[0060] S3. The back side of the N-type silicon wafer is processed to sequentially form a SiO2 layer, an n-type polycrystalline silicon layer (hereinafter referred to as the N-poly layer), and a phosphorus silicate glass layer (hereinafter referred to as the PSG layer) from the inside out on the back side of the N-type silicon wafer. In this embodiment, for example, the SiO2 layer and the phosphorus-doped polycrystalline silicon layer are deposited on the back side of the N-type silicon wafer by PECVD, wherein the thickness of the SiO2 layer is controlled at 1.4 nm and the thickness of the phosphorus-doped polycrystalline silicon layer is controlled at 90 nm. Subsequently, the phosphorus-doped polycrystalline silicon layer is annealed at 750 °C for 60 min to activate it to form the N-poly layer, and a PSG protective layer is formed on its surface.
[0061] S4. A hot-melt material is inkjet printed onto the surface of the n-shaped poly region on the back of the N-type silicon wafer to form a mask area. The hot-melt material used is still ethylene-vinyl acetate copolymer wax; the thickness of the hot-melt material on the N-type silicon wafer is 8 μm.
[0062] After the mask region is formed, the PSG layer in the non-mask region is etched using the etching solution. The etching solution used is a 20% volume concentration HF solution, and the etching reaction lasts for 150 seconds.
[0063] After the PSG layer etching is completed, the hot-melt material in the mask area is removed using the cleaning solution. The cleaning solution used is a mixed solution containing 10 wt% BDG and 5 wt% NaOH, and the cleaning time is 200 s.
[0064] After removing the hot-melt material, a second reaction solution is used to etch the N-poly layer in the PSG removal area and simultaneously texturize the front side of the N-type silicon wafer. In this embodiment, for example, the second reaction solution contains a NaOH solution and a texturing additive, wherein the NaOH solution has a volume concentration of 8%; the texturing additive is a common commercially available product that can form a uniform, dense, low-reflectivity textured surface on the silicon wafer to enhance the light absorption capacity of the BC cell; etching additives produced by manufacturers such as CECI, Sanfeng, and Topband can be used; the etching reaction is carried out at 85 °C for 280 s.
[0065] After texturing is completed, the remaining BSG and PSG layers on the back side of the N-type silicon wafer are further removed using the etching solution. The etching solution used is a 25% volume concentration HF solution, and the etching reaction lasts for 175 seconds.
[0066] S5. Passivate the front and back surfaces of the N-type silicon wafer to generate a passivation layer. The passivation step can employ mature existing technology. In this embodiment, for example, a plasma chemical vapor deposition (PCVDC) device is used to deposit passivation layers on the front and back surfaces of the N-type silicon wafer. The formed passivation layer contains a silicon nitride thin film with a thickness of 75 nm and a refractive index of 1.95.
[0067] S6. Screen printing and sintering are performed on the back side of the N-type silicon wafer to prepare a metal electrode. The metal electrode preparation step can use mature existing technology. In this embodiment, for example, silver paste is deposited on the P / N junction by screen printing, and then sintering is performed to prepare the metal electrode.
[0068] The preparation process in this embodiment improves the yield by 0.3% compared to the laser etching process using the same raw materials.
[0069] Performance testing: In this embodiment, the BC battery prepared by the process described in Example 1 and the BC battery prepared by the conventional laser etching process were selected as experimental examples and comparative examples, respectively, to test the performance of the BC battery.
[0070] For experimental methods that do not specify conditions, the determination is usually carried out according to national standards. If there is no corresponding national standard, then the generally accepted international standards, standard conditions, or conditions recommended by the manufacturer shall be followed.
[0071] In this embodiment, the main performance testing items for the BC battery include open-circuit voltage, short-circuit current, fill factor, and efficiency. Open-circuit voltage refers to the voltage across the BC battery when no load is connected. Short-circuit current refers to the current flowing through the battery when it is short-circuited. The fill factor is the ratio of the BC battery's maximum power to the product of its open-circuit voltage and short-circuit current; it is an important indicator of internal battery losses. Efficiency is the ratio of the BC battery's output power to its input power; it is a comprehensive indicator reflecting the BC battery's performance, including its conversion rate.
[0072] The test results for the two sets of BC batteries are shown in the table below: Table 1 Summary of BC Battery Performance Test Results project Open circuit voltage (V) Short-circuit current (mA) Fill factor (%) efficiency(%) Experimental Example 745.7 13.97 84.32 26.52 Comparative Example 745.4 13.96 84.33 26.49 The performance test results of the BC battery show that the BC battery prepared by the process of the present invention has similar performance to that of the BC battery prepared by the conventional laser etching process, that is, it can meet the requirements for conventional BC battery use.
[0073] Based on the aforementioned test results, the BC battery fabrication process provided by this invention employs inkjet thermal fusion material for masking, combined with chemical etching, instead of the conventional masking and chemical etching process or the laser etching process. The chemical agents used in the masking steps do not conflict with the silicon substrate or the chemical agents used in other etching steps during BC battery fabrication, thus preventing product damage. This ensures the smooth integration of the thermal fusion material masking process and chemical etching, improving the yield rate of BC batteries while producing BC batteries that meet performance requirements. Furthermore, the reaction time and temperature of the steps in this invention have a wide adjustable range, facilitating adjustments to different steps in actual production to achieve close coordination between multiple steps, ensuring production continuity, and ultimately accelerating the overall processing speed of the BC battery fabrication process, thus promoting efficient BC battery production.
[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A BC battery manufacturing process, characterized in that, It includes the following steps: S1. The back side of the N-type silicon wafer is processed to sequentially form a SiO2 layer, a p-type polycrystalline silicon layer, and a borosilicate glass layer from the inside out on the back side of the N-type silicon wafer. S2. A hot-melt material is inkjet printed on the surface of the p-shaped poly region defined on the back of the N-type silicon wafer to form a mask region, and the borosilicate glass layer in the non-mask region is etched; the hot-melt material in the mask region is removed, and then the p-type polycrystalline silicon layer in the borosilicate glass removal region is etched again; S3. The back side of the N-type silicon wafer is processed to sequentially form a SiO2 layer, an n-type polycrystalline silicon layer, and a phosphosilicate glass layer from the inside out on the back side of the N-type silicon wafer. S4. Inkjet print hot melt material on the surface of the n-shaped poly area defined on the back of the N-type silicon wafer to form a mask area, and etch the phosphosilicate glass layer in the non-mask area; Remove the hot melt material in the mask area, then etch the phosphosilicate glass to remove the n-type polycrystalline silicon layer in the removal area and simultaneously texturize the front side of the N-type silicon wafer; S5. Passivate the front and back surfaces of the N-type silicon wafer; S6. Screen printing and sintering are performed on the back side of the N-type silicon wafer to prepare a metal electrode.
2. The BC battery manufacturing process according to claim 1, characterized in that, The hot melt material is selected from at least one of acrylate, rosin ester resin, C11-C22 alkyl acid, polypropylene wax, microcrystalline wax, polyethylene wax, and ethylene-vinyl acetate copolymer wax.
3. The BC battery manufacturing process according to claim 2, characterized in that, In S2 and S4, a cleaning solution is used to remove the hot-melt material in the mask area. The cleaning solution contains 1-10 wt% diethylene glycol butyl ether and 1-10 wt% NaOH. In S2 and S4, the cleaning time of the cleaning solution is 60-400 s.
4. The BC battery manufacturing process according to claim 1, characterized in that, In S2 and S4, the thickness of the mask layer formed by the hot melt material is 2~30 μm.
5. The BC battery manufacturing process according to claim 1, characterized in that, Between S4 and S5, the following steps are also included: Remove the borosilicate glass layer and phosphosilicate glass layer remaining on the back side of the N-type silicon wafer.
6. The BC battery manufacturing process according to claim 5, characterized in that, In S2 and S4, and between S4 and S5, when removing the residual borosilicate glass layer and phosphosilicate glass layer, the borosilicate glass layer and / or the phosphosilicate glass layer are etched with an acidic solution.
7. The BC battery manufacturing process according to claim 6, characterized in that, In S2, the volume concentration of the etching solution is 50-80%, and the reaction time is 20-180s; in S4, the volume concentration of the etching solution is 5-50%, and the reaction time is 15-150s; in S5, the volume concentration of the etching solution is 20-70%, and the reaction time is 20-180s.
8. The BC battery manufacturing process according to claim 1, characterized in that, In S2, a first reaction solution is used to etch the p-type polycrystalline silicon layer in the borosilicate glass removal area. The first reaction solution contains at least an alkaline solution, which is selected from at least one of NaOH solution and KOH solution, and the volume concentration of the alkaline solution is 0.5~10%.
9. The BC battery manufacturing process according to claim 8, characterized in that, The first reaction solution also contains an etching additive, which is selected from at least one of wetting agents, corrosion inhibitors, stabilizers, and complexing agents.
10. The BC battery manufacturing process according to claim 1, characterized in that, In S4, a second reaction solution is used to etch the n-type polycrystalline silicon layer in the phosphorosilicate glass removal zone and simultaneously texturing is performed. The second reaction solution contains at least an alkaline solution and a texturing additive. The alkaline solution is selected from at least one of NaOH solution and KOH solution, and its volume concentration is 0.5~10%.