A method to improve the luminous performance of AlGaInP red Micro LEDs

Abstract

This application discloses a method for improving the luminous performance of AlGaInP red Micro LEDs, comprising the following steps: S1, epitaxial structure fabrication: substrate and buffer layer treatment, etch barrier layer and ohmic contact layer growth, and functional layer stacking epitaxy; S2, silicon substrate patterning; S3, epitaxial wafer pretreatment and Mesa etching; S4, sidewall repair and wet oxidation treatment; S5, secondary epitaxy and sidewall passivation; S6, metal reflective layer and protective layer fabrication; S7, bonding and substrate removal; S8, n-side electrode and performance optimization. This application overcomes the defects of existing AlGaInP red Micro LEDs in small-size, high-PPI scenarios, such as increased non-radiative recombination at the sidewalls, lateral carrier leakage, and easy corrosion of the sidewalls, resulting in low luminous efficiency and poor stability. Through the fabrication method of "epitaxy layer wet oxide layer design + multi-process synergistic optimization", the luminous performance and working stability are improved simultaneously.

Description

Technical Field

[0001] This invention relates to the field of Micro LED chip fabrication technology, and specifically to a method for improving the luminous performance of AlGaInP red MicroLEDs. Background Technology

[0002] Micro LED, as a next-generation display technology, has become a core development direction in the high-end display field due to its advantages such as high brightness (peak brightness can reach over 1000 nits), high color saturation (NTSC color gamut coverage of over 90%), fast response speed (nanosecond level), and long lifespan (over 100,000 hours). Among them, AlGaInP material is the preferred material for preparing red Micro LEDs because its bandgap can be precisely matched to the red light band (620-660nm) and its room temperature luminescence quantum efficiency is high (theoretical value >80%).

[0003] However, as display products increasingly demand higher PPI (e.g., AR devices require a PPI > 3000), Micro LED chip sizes need to be reduced to the 1-10μm level. At this point, existing AlGaInP red Micro LEDs face three major technological shortcomings:

[0004] 1. Increased nonradiative recombination on sidewalls: After chip etching (Mesa etching), a large number of defects (such as dangling bonds, dislocations, and impurity adsorption) are generated on the sidewalls, forming nonradiative recombination centers; the surface area / volume ratio of small-sized chips increases significantly, and the proportion of nonradiative recombination on sidewalls can exceed 50%, which makes it impossible for charge carriers to effectively participate in radiative recombination, resulting in a significant decrease in luminous efficiency.

[0005] 2. Uncontrolled lateral transport of charge carriers: In traditional AlGaInP epitaxial structures, charge carriers tend to leak laterally along the chip sidewalls rather than vertically accumulating in the quantum well (MQW) light-emitting region; in small-sized chips, the proportion of laterally leaked charge carriers can reach more than 30%, further aggravating light emission loss;

[0006] 3. Poor sidewall stability: AlGaInP material itself has weak chemical stability. When the chip sidewall is exposed to the external environment (such as humidity, heat, acid and alkali) or subsequent processes (such as bonding and packaging), it is prone to chemical corrosion or physical damage, which leads to a shortened chip life.

[0007] Existing technologies have significant limitations in addressing the above problems:

[0008] Some schemes involve deposition , Passivation layers improve sidewall stability, but can only cover surface defects and cannot eliminate deep nonradiative recombination centers in the sidewalls, and it is difficult to control the carrier transport path.

[0009] Another approach involves adjusting the epitaxial layer structure (such as thickening the confinement layer), but no dedicated integrated carrier confinement and passivation structure is designed for the "confinement layer-spacer layer", and the problem of lateral carrier leakage is not fundamentally solved.

[0010] A few approaches have attempted wet oxidation, but the material composition, growth parameters, and synergistic relationship with other processes (such as secondary epitaxy and hybrid bonding) of the wet oxide layer have not been clearly defined, resulting in insufficient oxide layer density or obstruction of the luminescent area, thus limiting the optimization effect.

[0011] Therefore, there is an urgent need for a three-in-one technical solution that can achieve "sidewall defect repair - longitudinal carrier constraint - long-term sidewall stability" to break through the performance bottleneck of small-sized AlGaInP red Micro LED. Summary of the Invention

[0012] The purpose of this invention is to overcome the shortcomings of existing AlGaInP red micro LEDs in small-size (1-10μm) and high-PPI (>3000) scenarios, which are characterized by low luminous efficiency and poor stability due to increased non-radiative recombination on the sidewalls, lateral leakage of charge carriers, and easy corrosion of the sidewalls. This invention provides a method to improve the luminous performance of AlGaInP red micro LEDs. Through the fabrication method of "epitaxy layer wet oxide layer design + multi-process synergistic optimization", the luminous performance and operational stability are improved simultaneously.

[0013] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0014] A method for improving the luminous performance of AlGaInP red Micro LEDs includes the following steps:

[0015] S1, Epitaxial Structure Preparation:

[0016] Substrate and buffer layer treatment: n-type GaAs substrate is selected. After cleaning, an n-type GaAs buffer layer is grown by MOCVD epitaxy, and the doping concentration, thickness and film formation temperature are controlled.

[0017] Etching barrier layer and ohmic contact layer growth: Epitaxial growth of n-type on the buffer layer An etch barrier layer is formed, followed by epitaxial growth of an n-type GaN / InGaN ohmic contact layer on the etch barrier layer;

[0018] Functional layer stacking epitaxy: n-type AlInP confinement layer, n-type superlattice structure, n-type wet oxide layer, n-type spacer layer, quantum well structure, p-type spacer layer, p-type wet oxide layer, p-type confinement layer, p-type superlattice structure, p-type gradient layer and p-type heavily doped layer are epitaxially grown sequentially on the ohmic contact layer, with precise control of the parameters of each layer;

[0019] S2, Patterning of silicon substrate:

[0020] Cleaning silicon wafers / silicon-based CMOS and depositing via PECVD The dielectric layer, after coating, exposure, and development, forms a Cr mask, which is used for... After etching the dielectric layer, a seed layer is deposited by sputtering and then electroplated with Cu metal, followed by CMP polishing. The height difference between the dielectric layer and the Cu metal and The root mean square roughness of the dielectric layer is measured to ensure it is within the required range;

[0021] S3, Epitaxial wafer pretreatment and Mesa etching:

[0022] After cleaning the epitaxial wafer, a p-type ITO layer is deposited using electron beam evaporation, sputtering, or reactive plasma source. A mask is then prepared by coating, exposure, and development. Mesa etching is performed on the dielectric layer, ITO layer and epitaxial wafer to etch through the quantum well structure. During the etching process, lateral etching occurs in the n-type wet oxide layer or p-type wet oxide layer near the sidewall region.

[0023] S4, Sidewall Repair and Wet Oxidation Treatment:

[0024] The ALE (Alternating Electrode) equipment was used to repair the etched layer on the sidewalls of Mesa to ensure the integrity of the top mask. High-temperature, high-humidity wet oxidation was employed to transform the wet oxide layer in the etched sidewall region into a dense structure. layer;

[0025] S5, secondary epitaxy and sidewall passivation:

[0026] p-type AlInP or GaP layers were grown using MOCVD for secondary epitaxial growth; after cleaning, a sidewall passivation layer was deposited using an ALD device.

[0027] S6, Preparation of the metal reflective layer and protective layer:

[0028] After spin coating, exposure, and development, the top passivation layer of the Mesa layer is etched until the ITO layer is exposed. After resist removal, spin coating, exposure, and development are repeated to deposit a metal reflective layer. The resist is then removed again. Growth occurs on the surface of the epitaxial layer. A protective layer is deposited on the back side of the wafer. Layer; sediment After eliminating porosity anomalies in the membrane layer and cleaning, CMP polishing is performed to ensure... The root mean square roughness of the film is within the required range;

[0029] S7, Bonding and Substrate Removal:

[0030] Repeat the patterning process of S2, in A Cr mask, a Cu seed layer, and a Cu metal pattern were fabricated on the film layer; the patterned silicon substrate was then mixed and bonded to the epitaxial wafer; the back side of the wafer was removed using ICP etching. The GaAs substrate and n-type GaAs buffer layer are then removed; wet etching is performed until the n-type GaN / InGaN ohmic contact layer is exposed.

[0031] S8, n-side electrode and performance optimization:

[0032] After cleaning, an n-type ITO layer is deposited by electron beam evaporation, sputtering, or reactive plasma source; a mask is prepared by coating, exposure, and development; the n-type ITO layer and epitaxial layer pattern are adjusted by ICP etching; after removing the mask and cleaning, an electrode metal film is deposited by coating, coating, exposure, and development, and a microlens or metasurface structure is prepared to obtain a Micro LED device.

[0033] In a preferred embodiment, in step S1, the doping source of the n-type GaAs buffer layer is silane, and the doping concentration is [missing information]. The thickness is 100-300nm, and the film formation temperature is 620-700℃.

[0034] In a preferred embodiment, in step S1, the n-type In the etch barrier layer, x is 0.1-0.2, y is 0.5, the thickness is 100-300 nm, and the film formation temperature is 700-780℃; the doping source of the n-type GaN / InGaN ohmic contact layer is silane, and the doping concentration is [missing information]. The thickness is 10-40nm, the film formation temperature is 700-950℃, and the film formation method is "low V / III ratio rapid nucleation + high V / III ratio rapid film formation".

[0035] In a preferred embodiment, in step S1, the n-type wet oxide layer is A layer or AlAs layer, where x is 0.8-1.0, thickness is 5-60 nm, doping source is silane, and doping concentration is [missing information]. The film-forming temperature is 600-700℃; the p-type wet oxide layer is A layer or AlAs layer, where x is 0.8-1.0, thickness is 5-60 nm, and doping source is... The doping concentration is The film-forming temperature is 600-700℃.

[0036] In a preferred embodiment, in step S1, the quantum well structure is a 1-5 period undoped InGaP / The structure has x=0.7-0.8, y=0.5, and the InGaP well layer has a thickness of 2-4 nm. The thickness of the barrier layer is 5-8 nm, and the film formation temperature is 710-790℃; the n-type spacer layer is... The layer has a thickness of 40-80 nm, where x is 0.6-0.8 and y is 0.5.

[0037] In a preferred embodiment, in step S2, the The thickness of the dielectric layer is 1-3 μm; the seed layer is a Ti layer or a Cu layer with a thickness of 10-300 nm; after CMP polishing, AFM measurements show that the height difference between the dielectric layer and the Cu metal is 0-5 nm, the root mean square roughness Rq of the dielectric layer is <0.2 nm, the test area is 2 μm × 2 μm, and there are no particles larger than 1 μm in the 10 μm × 10 μm test area; the dielectric layer is etched using an ICP etching device, and the etching gas is... , Ar The mixed gas has an etching depth of 1-3 μm and an etching width of 1-5 μm.

[0038] In a preferred embodiment, in step S3, the thickness of the p-type ITO layer is 100-3000 Å, and after deposition, it is heated at 350-600℃. Annealing is performed in an atmospheric or oxygen atmosphere; the Mesa etching is performed using an ICP etching device, and the etching gas is... and The mixed gas, after etching, the diameter of the Mesa structure is 1-50μm and the pixel pitch is 2-75μm; the lateral etching length of the n-type wet oxide layer or p-type wet oxide layer near the sidewall region is 0.1-0.4μm.

[0039] In a preferred embodiment, in step S4, when the ALE device repairs the sidewall etched damage layer, the etching gas is... Ar The mixture of gases; the high-temperature, high-humidity oxidation treatment uses a tubular furnace, and the reaction chamber is vented with... Steam treatment at a temperature of 300-450℃ for 2-30 minutes.

[0040] In a preferred embodiment, in step S5, the thickness of the p-type AlInP or GaP layer grown in the secondary epitaxial growth is 20-60 nm, the film formation temperature is 600-800 °C, the film formation rate is 0.1-0.5 μm / h, and the doping source is... Or C, with a doping concentration of The growth morphology is membrane-like or three-dimensional island-like; the sidewall passivation layer is layer, Layer or Layers, with a thickness of 10-100 nm, or prepared using PECVD or ICPCVD equipment. / Layered structure.

[0041] In a preferred embodiment, in step S7, the bonding precision of the hybrid bonding is 50-100 nm, and the bonding interface quality is ensured by optimizing the bonding temperature and bonding pressure; the removal of the GaAs substrate and the n-type GaAs buffer layer is carried out using... and Mixed solution; the wet etching process exposes the n-type GaN / InGaN ohmic contact layer using HCl and... The mixed solution; in step S8: the thickness of the n-type ITO layer is 200-400 nm; the material of the electrode metal film layer is Cr, Au or Ag, and the thickness is 5-100 nm.

[0042] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows:

[0043] This invention achieves a significant improvement in the luminous performance and stability of AlGaInP red Micro LEDs through "wet oxide layer design + multi-process synergy," with the following specific benefits:

[0044] 1. Significantly improved luminous efficiency:

[0045] The dense high-Al content wet oxide layer is formed by wet oxidation. The layer can eliminate more than 80% of the non-radiative recombination centers on the sidewalls, while forcing carriers to propagate longitudinally into the quantum well (reducing the lateral leakage rate to below 5%). Combined with a metal reflective layer and microlenses, the light extraction efficiency (LEE) is improved by 50%-70%. At a driving current of 20mA, the light output power (LOP) is ≥5mW and the current efficiency (CE) is ≥40cd / A (30%-50% improvement compared to existing technologies).

[0046] 2. Job stability is significantly enhanced:

[0047] Layers and / The passivation layer forms a "double layer of protection," reducing water vapor permeability to less than [previous value]. After being tested for 1000 hours in a humid and hot environment of 85℃ / 85% RH, the optical output power attenuation rate was ≤20% (the attenuation rate of existing technologies often exceeds 40%); at the same time, The layer can resist acid and alkali corrosion (no significant damage after immersion in a solution with pH=2-12 for 24 hours), extending the device life to more than 100,000 hours.

[0048] 3. High process compatibility and controllability:

[0049] All processes (MOCVD, ICP, ALE, hybrid bonding) are based on existing semiconductor mass production equipment, eliminating the need for additional dedicated equipment and reducing industrialization costs. The parameters of each step (such as wet oxidation temperature and etching rate) can be precisely controlled to adapt to 2-12 inch wafer sizes and 1-50μm chip sizes, meeting the needs of display products with different PPI (1000-5000).

[0050] 4. Excellent integration:

[0051] The high-efficiency integration of AlGaInP epitaxial structure and silicon-based CMOS is achieved through hybrid bonding, with low bonding interface resistance (<10mΩ) and good current transmission uniformity. Furthermore, the design of the n-type ITO layer and electrode metal is directly compatible with existing driving circuits, simplifying the packaging process. Attached Figure Description

[0052] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0053] Figure 1 This is a flowchart of a method for improving the luminous performance of AlGaInP red Micro LEDs according to the present invention;

[0054] Figure 2 This is a schematic diagram of step S1 in the method of Embodiment 1 of the present invention;

[0055] Figure 3-6 This is a schematic diagram of step S2 in the method of Embodiment 1 of the present invention;

[0056] Figure 7 This is a schematic diagram of step S3 in the method of Embodiment 1 of the present invention;

[0057] Figure 8-10 This is a schematic diagram of steps S4-S6 in the method of Embodiment 1 of the present invention;

[0058] Figure 11-14 This is a schematic diagram of step S7 in the method of Embodiment 1 of the present invention;

[0059] Figure 15-16 This is a schematic diagram of step S8 in the method of Embodiment 1 of the present invention;

[0060] Among them, 1. GaAs substrate; 2. n-type GaAs buffer layer; 3. Etch barrier layer; 4. Ohmic contact layer; 5. n-type AlInP confinement layer; 6. n-type superlattice structure; 7. n-type wet oxide layer; 8. n-type spacer layer; 9. Quantum well structure; 10. p-type spacer layer; 11. p-type wet oxide layer; 12. p-type confinement layer; 13. p-type superlattice structure; 14. p-type graded layer; 15. p-type heavily doped layer; 16. Silicon wafer or silicon-based CMOS; 17. 18. Dielectric layer; 19. Cr mask; 20. Seed layer; 21. Cu metal; 22. p-type ITO layer; Layers; 23. p-type AlInP or GaP layer; 24. Passivation layer; 25. Metal reflective layer; 26. Membrane layer; 27. 28. Film layer; 29. ​​n-type ITO layer; 30. Electrode metal film layer; 41. Microlens. Detailed Implementation

[0061] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0062] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0063] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0064] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0065] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0066] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0067] Example 1

[0068] See appendix Figure 1-16 The present invention provides a method for improving the luminous performance of AlGaInP red Micro LEDs. The core idea is to introduce a high-Al content wet oxide layer into the n-type / p-type confinement layer 12 and the spacer layer of the AlGaInP red Micro LED through MOCVD epitaxy, and then combine this with high-temperature and high-humidity wet oxidation treatment to form a dense layer. The sidewall layer, combined with ALE sidewall repair, secondary epitaxy, and hybrid bonding processes, constructs an integrated structure of "defect repair - carrier confinement - stability protection." The specific steps are as follows, and the parameters and material selection for each step have undergone extensive experimental verification to ensure process feasibility and performance stability:

[0069] S1, Epitaxial structure fabrication (the core of which is the precise control of the wet oxide layer and quantum well structure 9):

[0070] The epitaxial structure uses n-type GaAs as a substrate, and each functional layer is grown sequentially using an MOCVD system to form a complete stack of "substrate-buffer layer-functional layer-heavily doped layer". Among them, the n-type / p-type wet oxide layer 11 and the quantum well structure 9 are key to performance optimization.

[0071] Substrate and buffer layer processing:

[0072] An n-type GaAs substrate 1 (wafer size can be 2-inch, 4-inch, 6-inch, 8-inch, or 12-inch, thickness 350μm or 650μm, single or double polishing is acceptable) is selected. The substrate is ultrasonically cleaned with acetone-isopropanol (IPA)-deionized water (10 min each) to remove surface oil and impurities. Subsequently, an n-type GaAs buffer layer 2 is grown epitaxially via MOCVD. The doping source is silane (high n-type doping efficiency and low diffusion coefficient), and the doping concentration is controlled to [value missing]. (Balancing conductivity and crystal quality), thickness 100-300nm (to cover substrate surface defects), film formation temperature 620-700℃ (to avoid excessive lattice mismatch between the substrate and the buffer layer).

[0073] Growth of etch barrier layer 3 and ohmic contact layer 4:

[0074] n-type epitaxial growth on the buffer layer Etching barrier layer 3, where x is 0.1-0.2 and y is 0.5 (the etching rate of the material under this composition is much lower than that of the adjacent layer, which can avoid excessive etching and damage to the quantum well in the future), with a thickness of 100-300 nm and a film formation temperature of 700-780 °C;

[0075] Subsequently, an n-type GaN / InGaN ohmic contact layer 4 is grown on the etch barrier layer 3, with silane as the doping source (suitable for nitride doping) and a doping concentration of [missing information]. (Reduce contact resistance), thickness 10-40nm, film formation temperature 700-950℃; adopt the method of "low V / III ratio rapid nucleation (three-dimensional island structure) + high V / III ratio rapid film formation" - low V / III ratio (V / III=50-100) can promote heterogeneous nucleation of GaN / InGaN, and high V / III ratio (V / III=300-500) can improve crystal density and reduce defects.

[0076] Functional layer stacking extension:

[0077] The following functional layers are sequentially grown on the ohmic contact layer 4, with the parameters of each layer precisely controlled to achieve synergy between "carrier confinement-luminescence-stabilization":

[0078] n-type AlInP confinement layer 5: thickness 10-400 nm, doping concentration The film formation temperature is 700-780℃, and its function is to confine carriers to quantum wells through the energy band structure.

[0079] n-type superlattice structure 6: 5-25 periods / Stacked (x1=0.1-0.2, x2=0.8-0.9, y1=y2=0.5), single-layer thickness 2.5-25nm, doping concentration The "quantum confinement effect" of superlattices is used to further enhance carrier confinement;

[0080] n-type wet oxide layer 7: Selected Layer or AlAs layer (x=0.8-1.0, high Al composition ensures fast oxidation rate and good selectivity), thickness 5-60nm, doping source silane, doping concentration The film-forming temperature is 600-700℃, which is conducive to subsequent wet oxidation. The layer provides raw materials;

[0081] n-type spacer layer 8: The spacer layer (x=0.6-0.8, y=0.5), with a thickness of 40-80nm and a film formation temperature of 700-780℃, serves to isolate the wet oxide layer from the quantum well and prevent damage to the light-emitting region during the oxidation process.

[0082] Quantum well structures 9 (MQWs): 1-5 period undoped InGaP / Stacked (x=0.7-0.8, y=0.5, this composition corresponds to the red light band 620-660nm), InGaP well layer thickness 2-4nm (too thick can easily lead to carrier overflow, too thin has too strong quantum confinement effect). The barrier layer thickness is 5-8 nm, and the film formation temperature is 710-790℃ (to ensure the crystal quality of InGaP and reduce luminescence defects).

[0083] p-type spacer layer 10: Consistent with the composition of n-type spacer layer 8 (x=0.8-0.9, y=0.5), thickness 40-80nm, doping source is magnesia-diocene ( p-type doping has high efficiency and good thermal stability; doping concentration Film formation temperature 700-780℃;

[0084] p-type wet oxide layer 11: Consistent with the composition of n-type wet oxide layer 7 ( Or AlAs, x=0.8-1.0), thickness 5-60nm, doping source doping concentration The film-forming temperature is 600-700℃, and it works in conjunction with the n-type wet oxide layer 7 to form a double-layer protection on the sidewall.

[0085] p-type confinement layer 12 and p-type superlattice structure 13: their parameters are consistent with those of the n-type confinement layer and the n-type superlattice, respectively, to achieve bidirectional confinement of charge carriers;

[0086] p-type gradient layer 14: Three layers Stacked layers (first layer x=0.8-0.9, thickness 20-60nm; second layer x gradually changes from 0.8-0.9 to 0.2-0.3, thickness 10-20nm; third layer x gradually changes from 0.2-0.3 to 0.01, thickness 10-20nm, y=0.5), doping concentration Its function is to reduce the contact resistance between the p-type layer and the subsequent GaP layer;

[0087] p-type heavily doped layer 15: includes GaP-1 (720-800℃, thickness 20-60nm, ... / C doping, concentrated GaP-2 (520-560℃, thickness 80-120nm, same doping as GaP-1), GaP-3 (520-560℃, thickness 10-30nm, C doping, concentration...) GaP materials exhibit excellent contact performance with ITO (transparent conductive layer), and heavy doping can further reduce contact resistance.

[0088] S2, Patterning of the silicon substrate (in preparation for subsequent hybrid bonding):

[0089] High-precision metal patterns need to be fabricated on silicon-based substrates (silicon wafers or silicon-based CMOS16) to ensure efficient bonding and current transport with the epitaxial wafer.

[0090] Substrate cleaning: Silicon wafers / silicon-based CMOS are ultrasonically cleaned with acetone-IPA-deionized water (15 min each) to remove surface organic matter and particles, and then dried with nitrogen gas;

[0091] Dielectric layer deposition: Growth via PECVD (Plasma Enhanced Chemical Vapor Deposition) equipment Dielectric layer 17 (thickness 1-3μm), film formation temperature controlled (300-400℃) / Flow ratio (1:5-1:10), pressure (200-500 mTorr), ensure The layer is dense (porosity <1%) to avoid the generation of interface bubbles during subsequent bonding;

[0092] Cr mask preparation: Coating (photoresist type AZ6130, thickness 1-2μm), exposure (UV exposure machine, energy 50-80). After development (AZ300MIF developer, development time 30-60s), a 50-150nm Cr mask is deposited using electron beam evaporation (E-beam) or sputtering equipment. 18 (Cr has good etching selectivity and can be used as...) Etched hard mask), followed by resist removal (immersion in acetone for 10-20 minutes);

[0093] Dielectric layer etching: ICP (Inductively Coupled Plasma) etching equipment is used for etching. The dielectric layer 17 is etched using an etching gas. , Ar The mixed gas (volume ratio 3:2:2:1:1) is used to etch a depth of 1-3 μm and a width of 1-5 μm (to match the size of the subsequent Cu metal 20 pattern). The etching rate is controlled at 100-200 nm / min to avoid over-etching and damaging the silicon substrate.

[0094] Seed layer 19 and Cu metal 20 deposition: A 10-300 nm Ti / Cu seed layer 19 (Ti as the adhesion layer, enhancing the adhesion between Cu and Cu) was deposited using a sputtering device. The bonding force; Cu is the conductive layer), and then Cu metal 20 is deposited using electroplating equipment (the electroplating solution is copper sulfate solution, current density 1-5). (Deposition time 30-60 min)

[0095] CMP polishing: Using chemical mechanical polishing (CMP) equipment to polish Cu, Ti, Cr, Film layer 27 was polished using a Cu-specific polishing solution (pH=3-5) at a pressure of 10-20 kPa. After polishing, the film was examined using AFM (atomic force microscopy). The height difference between Cu and Cu is 0-5 nm (to ensure a flat bonding interface). The root mean square roughness (Rq) is <0.2nm, the test area is 2μm×2μm, and there are no particles larger than 1μm in the 10μm×10μm area (to avoid poor interface contact during bonding).

[0096] S3, Epitaxial wafer pretreatment and Mesa etching (forming the core light-emitting unit of the chip):

[0097] Mesa etching requires precise control of depth and lateral etching amount to ensure that the quantum well is etched through while preserving the oxidizable areas of the wet oxide layer:

[0098] Epitaxial wafer cleaning: AlGaInP red light epitaxial wafers (2-12 inches) are ultrasonically cleaned with acetone-IPA-deionized water (10 min each) and dried with nitrogen.

[0099] p-type ITO layer deposition and annealing: A 100-3000 Å ITO layer (ITO is a transparent conductive material that does not block red light emission) is deposited using electron beam evaporation (E-beam), sputtering, or reactive plasma deposition (RPD), followed by annealing at 350-600℃. Alternatively, annealing in an oxygen atmosphere (holding time 30-60 min) can improve the conductivity of ITO (sheet resistance < 10 Ω / □, sheet resistance is the unit of ohms per square (Ω / □), which refers to the resistance value per unit area of ​​a unit thickness of material) and the contact performance with the p-type GaP layer.

[0100] Mask preparation and Mesa etching: Coating (same as step S2), exposure, development to prepare PR colloid / / Cr mask 18, sequentially etched using ICP etching equipment ITO and epitaxial layer (etching gas is and The mixture of gases (volume ratio 2:1) is used to etch the quantum well structure 9 to a depth that completely penetrates it (to avoid carrier crosstalk caused by incomplete etching). After etching, the diameter of the Mesa structure is 1-50 μm (to adapt to different PPI requirements), and the pixel pitch is 2-75 μm. During the etching process, by adjusting the ICP power (500-800W) and bias voltage (50-100V), a lateral etch of 0.1-0.4 μm is made in the region near the sidewall of the n-type / p-type wet oxide layer 11 (to provide sufficient reaction area for subsequent wet oxidation).

[0101] S4, Sidewall Repair and Wet Oxidation Treatment (Core Optimization Step, Solving Non-Radiative Composite and Stability Issues):

[0102] A dense structure is formed through ALE repair and wet oxidation. Layer 22, simultaneously eliminating etching damage:

[0103] Sidewall repair: The sidewall etch damage layer of Mesa was repaired using ALE (Atomic Layer Etching) equipment, with the etching gas being... Ar A mixed gas (volume ratio 1:1:2:0.5) is used, with an etching rate of 5-10 nm / cycle, for a total etching cycle of 2-5 cycles (removing only the 5-50 nm damaged layer on the sidewall surface); during the etching process, the top of Mesa must be ensured... With the mask intact (avoiding damage to the p-type ITO layer 21), the sidewall defect density can be reduced to [value missing] after repair. The following results show an improvement in light extraction efficiency (LEE) of 10%-15%;

[0104] Wet oxidation treatment: High-temperature and high-humidity wet oxidation treatment is carried out using a tubular furnace (furnace tube), with air introduced into the reaction chamber. Steam (partial pressure 50-80 kPa), processing temperature 300-450℃ (at this temperature) Alternatively, AlAs has a fast oxidation rate and will not damage the quantum well. The processing time is 2-30 minutes (adjusted according to the amount of lateral etching to ensure that the wet oxide layer in the lateral etching area is completely converted). During wet oxidation, Or Al in AlAs and Steam reaction produces dense Layer 22 (density 3.9-4.1) This layer can: ① cover sidewall defects and eliminate nonradiative recombination centers; ② block lateral carrier leakage and force carriers to transport longitudinally into the quantum well; ③ isolate the external corrosive environment and improve sidewall stability.

[0105] S5, Secondary epitaxy and sidewall passivation (further enhancing stability and carrier confinement):

[0106] Secondary epitaxy: p-type AlInP or GaP layers are grown using MOCVD (high lattice matching with adjacent layers to avoid new defects), with a thickness of 20-60 nm, a deposition temperature of 600-800℃, and a deposition rate of 0.1-0.5 μm / h (slow rate ensures crystal quality). The doping source is... Or C, doping concentration The growth morphology can be selected as film-like (covering the top of the sidewalls) or three-dimensional island-like (filling the tiny pores in the sidewalls). The secondary epitaxial layer can further enhance carrier confinement and fill the tiny gaps in the wet oxide layer.

[0107] Sidewall passivation: After the epitaxial wafer is cleaned with acetone-IPA-deionized water, a sidewall passivation layer 24 is deposited using an ALD (atomic layer deposition) system. The material is optional. (Refractive index 2.0-2.2, suitable for red light band) (Good density) or (Excellent insulation), thickness 10-100nm; for higher stability, PECVD or ICPCVD equipment can be used for preparation. / Layered structure ( Layer thickness 50-80nm, (Layer thickness 30-50nm), the water vapor permeability of the stacked structure can be lower than This significantly improves long-term stability.

[0108] S6, Preparation of metal reflective layer 25 and protective layer (to improve light extraction efficiency and damage resistance):

[0109] Preparation of metal reflective layer 25:

[0110] After spin coating (same as step S2), exposure, and development, the passivation layer 24 on top of Mesa is etched using ICP until the ITO layer is exposed (the etching gas is selected according to the material of the passivation layer 24, such as...). use / );

[0111] After removing the adhesive (soaking in acetone), the material is homogenized again, exposed, and developed. A 5-100 nm Cr / Au / Ag metal reflective layer 25 (Cr is the adhesive layer, and Au / Ag has a red light reflectivity >95%) is deposited by sputtering or electron beam evaporation. The reflective layer can reflect the red light emitted downward from the quantum well to the light-emitting surface, improving the light extraction efficiency by 20%-30%.

[0112] Finally, the adhesive is removed to obtain the complete metal reflective layer 25 structure;

[0113] Protective layer preparation:

[0114] 0.5-1.5 μm thick epitaxial layers are grown on the surface using PECVD or ICPCVD equipment. A protective layer (covering the metal reflective layer 25 and the passivation layer 24) is deposited on the back side of the wafer, while a 0.5-1 μm thick layer is also deposited. Floor 26 ( stress and Conversely, it can counteract wafer warpage and ensure smooth subsequent bonding.

[0115] To eliminate porosity anomalies generated during the process, a 0.5-2 μm thick layer is deposited again. Film layer 27, after cleaning, undergoes CMP polishing (parameters same as step S2) to ensure... The root mean square roughness (Rq) of film layer 27 is <0.2 nm (test area 2 μm × 2 μm) to avoid affecting the subsequent bonding quality.

[0116] S7, Bonding and Substrate Removal (Achieving Integration of Epitaxial Structure and Silicon-based Driver Circuit):

[0117] Patterning process repetition: Repeat the silicon-based patterning process of step S2, and the silicon-based patterning process prepared in step S6. A Cr mask 18, a Cu seed layer 19, and a Cu metal 20 pattern are fabricated on the protective layer (the pattern size is precisely matched with the metal pattern on the silicon substrate).

[0118] Hybrid bonding: The patterned silicon substrate and the epitaxial wafer are hybrid bonded using a high-precision bonding machine (alignment accuracy ±10nm), with bonding precision controlled at 50-100nm (ensuring precise alignment of the Cu metal 20 electrodes). By optimizing the bonding temperature (200-300℃) and bonding pressure (5-15kPa), metallic bonding is formed at the Cu-Cu interface. - The interface forms a covalent bond, and the interface resistance can be less than 10mΩ, which meets the current transport requirements.

[0119] Substrate removal:

[0120] ICP etching equipment is used to remove the back side of the wafer. Film 26 (etching gas) / );

[0121] use and The epitaxial wafer was soaked in a mixed solution (volume ratio 3:1) to remove the GaAs substrate 1 and the n-type GaAs buffer layer 2 (GaAs is etched at a rate of 1-5 μm / min in this solution without damaging the n-type GaN / InGaN ohmic contact layer 4).

[0122] Using HCl and Wet etching was performed using a mixed solution (volume ratio 1:3) to remove residual buffer layer fragments until the n-type GaN / InGaN ohmic contact layer 4 was fully exposed (etching time 5-10 min, and the exposure of the contact layer was confirmed by observation with an optical microscope).

[0123] S8, n-side electrode and performance optimization (complete chip fabrication, further improve luminescence performance):

[0124] n-type ITO layer 28 deposition: After the epitaxial wafer is cleaned with acetone-IPA-deionized water, an n-type ITO layer 28 of 200-400nm is deposited using electron beam evaporation, sputtering or reactive plasma source (thickness greater than p-side ITO to ensure uniform current distribution on the n-side), and the sheet resistance is controlled to be 5-15Ω / □.

[0125] Patterning etching: Mask preparation involves coating, exposure, and development; ICP etching equipment is used to adjust the pattern of the n-type ITO layer 28 and the epitaxial layer (etching gas). This ensures that the n-side electrodes of each Mesa unit are independent, avoiding crosstalk;

[0126] Electrode metal and microlens 30 fabrication:

[0127] After removing the mask and cleaning, an electrode metal film 29 (material is Cr / Au, Cr thickness 5-10nm, Au thickness 50-100nm) is deposited through coating (E-beam / Sputter), resist coating, exposure, and development. The electrode metal is used for subsequent wire bonding with the driving circuit.

[0128] Microlenses 30 or metasurface structures are fabricated using photoresist thermal melting or nanoimprinting processes: the diameter of microlenses 30 is 1.2-1.5 times that of the Mesa structure, and the focal length is 5-10 μm (which can converge diverging red light and further improve the light extraction efficiency by 15%-20%); the metasurface structure further optimizes the viewing angle characteristics by controlling the emission direction of red light through subwavelength grating design.

[0129] Final testing: The photoelectric performance of the fabricated Micro LED devices is tested to screen out qualified products.

[0130] Example 2

[0131] This application provides a method for fabricating a 4-inch AlGaInP red Micro LED chip (PPI=3000, chip size 5μm), including the following steps:

[0132] S1, Epitaxial Structure Fabrication (MOCVD Model: Aixtron G5+) Substrate: 4-inch n-type GaAs substrate 1 (thickness 650μm, double polishing, doping concentration) );

[0133] n-type GaAs buffer layer 2: grown at 650℃, 200nm thick, doped with silane (concentration...). );

[0134] n-type etch barrier layer 3: grown at 750℃, 200nm thick. (x=0.15, y=0.5);

[0135] n-type GaN ohmic contact layer 4: grown at 850℃, 25nm thick, silane doped (concentration) V / III ratio is 50 for lower stage and 400 for higher stage;

[0136] n-type AlInP confinement layer 5: grown at 750℃, 200nm thick, doped with silane (concentration) );

[0137] n-type superlattice structure 6: grown at 750℃, 15 periods / x1=0.15, x2=0.85, y1=y2=0.5, monolayer thickness 10nm, doping concentration ;

[0138] n-type wet oxide layer 7: grown at 650℃, 30nm thick. (x=0.9), silane doping (concentration) );

[0139] n-type spacer layer 8: grown at 750℃, 60nm thick. (x=0.7, y=0.5);

[0140] Quantum well structure 9: Grown at 750℃, 3-period InGaP / (x=0.75, y=0.5), InGaP thickness 3nm, barrier layer thickness 6nm;

[0141] p-type spacer layer 10: grown at 750℃, 60nm thick (x=0.85, y=0.5) Doping (concentration) );

[0142] p-type wet oxide layer 11: grown at 650℃, 30nm thick. (x=0.9) Doping (concentration) );

[0143] p-type confinement layer 12: grown at 750℃, 200 nm thick. Doping (concentration) );

[0144] p-type superlattice structure 13; grown at 750℃, 15-period. / x1=0.15, x2=0.85, y1=y2=0.5, monolayer thickness 10nm, doping concentration ;

[0145] p-type graded layer 14: grown at 750℃, first layer (20nm), The first layer has x=0.85 and y=0.5; the second layer has x=0.85 and y=0.5; the third layer has x=0.25 and y=0.25.

[0146] p-type heavily doped layer 15: GaP-1 (750℃, 40nm, Doping, ), GaP-2 (550℃, 100nm, Doping, GaP-3 (550℃, 20nm, C-doped) ).

[0147] Key parameters for chip fabrication steps:

[0148] S2 (Silicon-based Patterning): Thickness 2μm, Cr mask 100nm, Cu seed layer 50nm (Ti 10nm + Cu 40nm), height difference after CMP 3nm. Rq = 0.15nm;

[0149] S3 (Mesa etching): ITO thickness 1500Å, 500℃ Annealing for 30 min, Mesa diameter 5 μm, pixel pitch 10 μm, wet oxide layer side etching 0.2 μm;

[0150] S4 (wet oxidation): 400℃, Steam partial pressure 60 kPa, processing time 10 min. Layer 22 has a thickness of 0.2 μm;

[0151] S5 (secondary epitaxy): p-type AlInP, 40 nm thick, grown at 700 °C. Doping (concentration) ), film growth; passivation layer 24 is 50nm (ALD deposition);

[0152] S6 (Metal Reflective Layer 25): Ag thickness 50nm, 1μm protective layer on the back side Layer thickness 0.8μm;

[0153] S7 (Hybrid Bonding): Bonding temperature 250℃, pressure 10kPa, bonding precision 80nm; GaAs substrate 1 removal using a volume ratio of 3:1 and Mix the solution and soak for 30 minutes;

[0154] S8 (n-type ITO layer 28 and microlens 30): The thickness of the n-type ITO layer 28 is 300nm, the electrode metal is Cr 5nm + Au 80nm, the microlens 30 has a diameter of 6μm and a focal length of 8μm.

[0155] Performance test results:

[0156] Emission wavelength: 640nm (red light band);

[0157] 20mA drive current: optical output power 8.5mW, current efficiency 55cd / A, voltage 2.2V;

[0158] 85℃ / 85%RH damp heat test (1000h): optical output power attenuation rate 15%, voltage change rate <5%;

[0159] Light extraction efficiency: 68% (65% improvement compared to devices without a wet oxide layer).

[0160] Example 3

[0161] This application provides a method for fabricating a 6-inch AlGaInP red Micro LED chip (PPI=1500, chip size 10μm). The steps are the same as in Example 2, but the core differences are as follows:

[0162] Substrate: 6-inch n-type GaAs substrate 1 (thickness 350μm, single polishing);

[0163] Wet oxidation treatment: 380℃, Steam partial pressure 70 kPa, processing time 15 min;

[0164] Secondary epitaxial material: p-type GaP (50 nm thick, grown at 750 °C);

[0165] Passivation layer 24: / Stacked ( 60nm+ 40nm);

[0166] Mesa dimensions: 10μm diameter, 20μm pixel pitch.

[0167] Performance test results:

[0168] Emission wavelength: 635nm;

[0169] 20mA drive current: optical output power 7.8mW, current efficiency 52cd / A, voltage 2.1V;

[0170] 85℃ / 85%RH damp heat test (1000h): optical output power attenuation rate 18%;

[0171] Light extraction efficiency: 65%.

[0172] This invention achieves a significant improvement in the luminous performance and stability of AlGaInP red Micro LEDs through "wet oxide layer design + multi-process synergy," with the following specific benefits:

[0173] 1. Significantly improved luminous efficiency:

[0174] The dense high-Al content wet oxide layer is formed by wet oxidation. Layer 22 can eliminate more than 80% of the non-radiative recombination centers on the sidewalls, while forcing carriers to propagate longitudinally into the quantum well (reducing the lateral leakage rate to below 5%). Combined with the metal reflective layer 25 and microlens 30, the light extraction efficiency (LEE) is improved by 50%-70%. Under a driving current of 20mA, the light output power (LOP) is ≥5mW and the current efficiency (CE) is ≥40cd / A (30%-50% improvement compared to existing technologies).

[0175] 2. Job stability is significantly enhanced:

[0176] Layer 22 and / Passivation layer 24 forms a "double layer of protection", with a water vapor permeability lower than that of the previous layer. After being tested for 1000 hours in a humid and hot environment of 85℃ / 85% RH, the optical output power attenuation rate was ≤20% (the attenuation rate of existing technologies often exceeds 40%); at the same time, Layer 22 can resist acid and alkali corrosion (no significant damage after immersion in a solution with pH=2-12 for 24 hours), extending the device life to more than 100,000 hours.

[0177] 3. High process compatibility and controllability:

[0178] All processes (MOCVD, ICP, ALE, hybrid bonding) are based on existing semiconductor mass production equipment, eliminating the need for additional dedicated equipment and reducing industrialization costs. The parameters of each step (such as wet oxidation temperature and etching rate) can be precisely controlled to adapt to 2-12 inch wafer sizes and 1-50μm chip sizes, meeting the needs of display products with different PPI (1000-5000).

[0179] 4. Excellent integration:

[0180] The high-efficiency integration of AlGaInP epitaxial structure and silicon-based CMOS is achieved through hybrid bonding, with low bonding interface resistance (<10mΩ) and good current transmission uniformity. Furthermore, the design of the n-type ITO layer 28 and electrode metal is directly compatible with existing driving circuits, simplifying the packaging process.

[0181] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for improving the luminous performance of AlGaInP red Micro LEDs, characterized in that, Includes the following steps: S1, Epitaxial Structure Preparation: Substrate and buffer layer treatment: n-type GaAs substrate is selected. After cleaning, an n-type GaAs buffer layer is grown by MOCVD epitaxy, and the doping concentration, thickness and film formation temperature are controlled. Etching barrier layer and ohmic contact layer growth: Epitaxial growth of n-type on the buffer layer An etch barrier layer is formed, followed by epitaxial growth of an n-type GaN / InGaN ohmic contact layer on the etch barrier layer; Functional layer stacking epitaxy: n-type AlInP confinement layer, n-type superlattice structure, n-type wet oxide layer, n-type spacer layer, quantum well structure, p-type spacer layer, p-type wet oxide layer, p-type confinement layer, p-type superlattice structure, p-type gradient layer and p-type heavily doped layer are epitaxially grown sequentially on the ohmic contact layer, with precise control of the parameters of each layer; S2, Patterning of silicon substrate: Cleaning silicon wafers / silicon-based CMOS and depositing via PECVD The dielectric layer, after coating, exposure, and development, forms a Cr mask, which is used for... After etching the dielectric layer, a seed layer is deposited by sputtering and then electroplated with Cu metal, followed by CMP polishing. The height difference between the dielectric layer and the Cu metal and The root mean square roughness of the dielectric layer is measured to ensure it is within the required range; S3, Epitaxial wafer pretreatment and Mesa etching: After cleaning the epitaxial wafer, a p-type ITO layer is deposited using electron beam evaporation, sputtering, or reactive plasma source. A mask is then prepared by coating, exposure, and development. Mesa etching is performed on the dielectric layer, ITO layer and epitaxial wafer to etch through the quantum well structure. During the etching process, lateral lateral etching occurs in the n-type wet oxide layer or p-type wet oxide layer near the sidewall region. S4, Sidewall Repair and Wet Oxidation Treatment: The ALE (Alternating Electrode) equipment was used to repair the etched layer on the sidewalls of Mesa to ensure the integrity of the top mask. High-temperature, high-humidity wet oxidation was employed to transform the wet oxide layer in the etched sidewall region into a dense structure. layer; S5, secondary epitaxy and sidewall passivation: p-type AlInP or GaP layers were grown using MOCVD for secondary epitaxial growth; after cleaning, a sidewall passivation layer was deposited using an ALD device. S6, Preparation of the metal reflective layer and protective layer: After spin coating, exposure, and development, the top passivation layer of the Mesa layer is etched until the ITO layer is exposed. After resist removal, spin coating, exposure, and development are repeated to deposit a metal reflective layer. The resist is then removed again. Growth occurs on the surface of the epitaxial layer. A protective layer is deposited on the back side of the wafer. Layer; sediment After eliminating porosity anomalies in the membrane layer and cleaning, CMP polishing is performed to ensure... The root mean square roughness of the film is within the required range; S7, Bonding and Substrate Removal: Repeat the patterning process of S2, in A Cr mask, a Cu seed layer, and a Cu metal pattern were fabricated on the film layer; the patterned silicon substrate was then mixed and bonded to the epitaxial wafer; the back side of the wafer was removed using ICP etching. The GaAs substrate and n-type GaAs buffer layer are then removed; wet etching is performed until the n-type GaN / InGaN ohmic contact layer is exposed. S8, n-side electrode and performance optimization: After cleaning, an n-type ITO layer is deposited by electron beam evaporation, sputtering, or reactive plasma source; a mask is prepared by coating, exposure, and development; and the pattern of the n-type ITO layer and epitaxial layer is adjusted by ICP etching. After removing the mask and cleaning, the electrode metal film is deposited through coating, resist coating, exposure, and development, and microlenses or metasurface structures are fabricated to obtain Micro LED devices.

2. The method for improving the luminous efficacy of AlGaInP red Micro LEDs according to claim 1, characterized in that, In step S1, the doping source of the n-type GaAs buffer layer is silane, and the doping concentration is [missing information]. The thickness is 100-300nm, and the film formation temperature is 620-700℃.

3. The method for improving the luminous efficacy of AlGaInP red Micro LEDs according to claim 1, characterized in that, In step S1, the n-type In the etch barrier layer, x is 0.1-0.2, y is 0.5, the thickness is 100-300 nm, and the film formation temperature is 700-780℃; the doping source of the n-type GaN / InGaN ohmic contact layer is silane, and the doping concentration is [missing information]. The thickness is 10-40nm, the film formation temperature is 700-950℃, and the film formation method is "low V / III ratio rapid nucleation + high V / III ratio rapid film formation".

4. The method for improving the luminous efficacy of AlGaInP red Micro LEDs according to claim 1, characterized in that, In step S1, the n-type wet oxide layer is A layer or AlAs layer, where x is 0.8-1.0, thickness is 5-60 nm, doping source is silane, and doping concentration is [missing information]. The film-forming temperature is 600-700℃; the p-type wet oxide layer is A layer or AlAs layer, where x is 0.8-1.0, thickness is 5-60 nm, and doping source is... The doping concentration is The film-forming temperature is 600-700℃.

5. The method for improving the luminous efficacy of AlGaInP red Micro LEDs according to claim 1, characterized in that, In step S1, the quantum well structure is a 1-5 period undoped InGaP / The structure has x=0.7-0.8, y=0.5, and the InGaP well layer has a thickness of 2-4 nm. The thickness of the barrier layer is 5-8 nm, and the film formation temperature is 710-790℃; the n-type spacer layer is... The layer has a thickness of 40-80 nm, where x is 0.6-0.8 and y is 0.

5.

6. The method for improving the luminous efficacy of AlGaInP red Micro LEDs according to claim 1, characterized in that, In step S2, the The thickness of the dielectric layer is 1-3 μm; the seed layer is a Ti layer or a Cu layer with a thickness of 10-300 nm; after CMP polishing, AFM measurements show that the height difference between the dielectric layer and the Cu metal is 0-5 nm, the root mean square roughness Rq of the dielectric layer is <0.2 nm, the test area is 2 μm × 2 μm, and there are no particles larger than 1 μm in the 10 μm × 10 μm test area; the dielectric layer is etched using an ICP etching device, and the etching gas is... , Ar The mixed gas has an etching depth of 1-3 μm and an etching width of 1-5 μm.

7. The method for improving the luminous performance of AlGaInP red Micro LED according to claim 1, characterized in that, In step S3, the thickness of the p-type ITO layer is 100-3000 Å, and it is deposited at 350-600℃. Annealing is performed in an atmospheric or oxygen atmosphere; the Mesa etching is performed using an ICP etching device, and the etching gas is... and The mixed gas, after etching, the diameter of the Mesa structure is 1-50μm and the pixel pitch is 2-75μm; the lateral etching length of the n-type wet oxide layer or p-type wet oxide layer near the sidewall region is 0.1-0.4μm.

8. The method for improving the luminous efficacy of AlGaInP red Micro LEDs according to claim 1, characterized in that, In step S4, when the ALE device repairs the sidewall etched damage layer, the etching gas is... Ar The mixture of gases; the high-temperature, high-humidity oxidation treatment uses a tubular furnace, and the reaction chamber is vented with... Steam treatment at a temperature of 300-450℃ for 2-30 minutes.

9. The method for improving the luminous performance of AlGaInP red Micro LED according to claim 1, characterized in that, In step S5, the thickness of the p-type AlInP or GaP layer grown in the secondary epitaxial growth is 20-60 nm, the film formation temperature is 600-800℃, the film formation rate is 0.1-0.5 μm / h, and the doping source is... Or C, with a doping concentration of The growth morphology is membrane-like or three-dimensional island-like; the sidewall passivation layer is layer, Layer or Layers, with a thickness of 10-100 nm, or prepared using PECVD or ICPCVD equipment. / Layered structure.

10. The method for improving the luminous efficacy of AlGaInP red Micro LEDs according to claim 1, characterized in that, In step S7, the bonding precision of the hybrid bonding is 50-100 nm, and the bonding interface quality is ensured by optimizing the bonding temperature and bonding pressure; the removal of the GaAs substrate and n-type GaAs buffer layer is carried out using... and Mixed solution; the wet etching process exposes the n-type GaN / InGaN ohmic contact layer using HCl and... The mixed solution; in step S8: the thickness of the n-type ITO layer is 200-400 nm; the material of the electrode metal film layer is Cr, Au or Ag, and the thickness is 5-100 nm.

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