Capacitor preparation method
By using nanowire printing technology to separate electrode regions, the high cost and complex process of silicon-based capacitor electrode fabrication have been solved, achieving simplified processes and efficient production. This technology is suitable for ultrathin high-dielectric-constant dielectric capacitors.
Patent Information
- Application Number
- CN202410499521.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-24
- Publication Date
- 2025-10-31
AI Technical Summary
Existing electrode fabrication methods for silicon-based capacitors are expensive, involve complex processes, and the masks are prone to damaging other functional layers and causing step differences.
Electrode patterns are formed using nanowire printing technology. By separating the electrode areas with nanowires, the use of photomasks is avoided, and dual electrodes can be formed in one layer.
It simplifies process steps, reduces costs, improves yield and production efficiency, avoids dent problems, and is suitable for a wide range of applications.
Smart Images
Figure CN120882297A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a novel method for preparing capacitors. Background Technology
[0002] With the rapid development of technology, silicon-based capacitors are being used more and more widely in many fields, such as electronics, communications, and aerospace. However, the electrode patterning processes currently used for mass production of silicon-based capacitors still have some problems, such as high cost and complex process steps. These problems not only increase production costs but also limit the widespread application of silicon-based capacitors.
[0003] Furthermore, current methods for fabricating electrodes for silicon-based capacitors typically require photolithography for patterning, which is expensive and involves complex processes. Using masks to block out areas where electrodes are not needed can easily lead to the mask touching and damaging other functional layers. Moreover, after the electrodes are formed and the mask is removed, a step difference is created between the electrode surface and other surface areas, causing depressions during subsequent layer stacking.
[0004] Therefore, it is necessary to provide a novel capacitor manufacturing method to solve the above-mentioned problems existing in the prior art. Summary of the Invention
[0005] The purpose of this invention is to overcome the above-mentioned defects in the prior art and provide a method for manufacturing a capacitor.
[0006] To achieve the above objectives, the technical solution of the present invention is as follows:
[0007] This invention provides a method for manufacturing a capacitor, comprising the following steps:
[0008] Step S1: Provide the substrate;
[0009] Step S2: Form a first nanowire on the surface of the substrate to divide the surface of the substrate into two independent first regions and a second region through the first nanowire;
[0010] Step S3: Form a first electrode layer on the surface of the substrate to form a phase-separated first positive electrode and a first negative electrode on the first region and the second region on both sides of the first nanowire;
[0011] Step S4: Remove the first nanowire.
[0012] Furthermore, it also includes:
[0013] Step S5: Form a first dielectric layer on the surface of the first electrode layer to cover the first positive electrode and the first negative electrode.
[0014] Furthermore, it also includes:
[0015] Step S6: Form a second nanowire on the surface of the first dielectric layer to divide the surface of the first dielectric layer into two independent third and fourth regions by means of the second nanowire;
[0016] Step S7: Form a second electrode layer on the surface of the first dielectric layer to form a phase-separated second positive electrode and a second negative electrode on the third region and the fourth region on both sides of the second nanowire;
[0017] Step S8: Remove the second nanowire;
[0018] Step S9: Form a second dielectric layer on the surface of the second electrode layer to cover the second positive electrode and the second negative electrode;
[0019] Step S10: Repeat steps S2-S9 above until the target number of positive electrode layers m and the number of negative electrode layers n are obtained, where m and n are both positive integers and m=n≥2;
[0020] Step S11: Remove the substrate;
[0021] Step S12: Connect all the positive electrodes and connect all the negative electrodes.
[0022] Furthermore, when forming the second nanowire and the first nanowire, the second nanowire and the first nanowire are respectively located on opposite sides of the substrate.
[0023] Furthermore, the second nanowire and the first nanowire may be linear, polygonal, or curved.
[0024] Furthermore, the substrate material includes a rigid material or a flexible material; and / or, the second nanowire and the first nanowire are formed by nanowire printing technology; and / or, the second electrode layer and the first electrode layer are formed by physical deposition process or chemical deposition process; and / or, the second nanowire and the first nanowire are removed by physical tearing method, adhesive removal method or chemical solvent removal method; and / or, the substrate is removed by peeling, burning or grinding.
[0025] Furthermore, the linewidth of the second nanowire and the linewidth of the first nanowire are both 30 nm to 5000 nm.
[0026] Furthermore, by a cutting method, the opposite outer ends of the first positive electrode and the first negative electrode are exposed from the cut surfaces on both sides of the first dielectric layer, and the opposite outer ends of the second positive electrode and the second negative electrode are exposed from the cut surfaces on both sides of the second dielectric layer. By forming conductive layers on both sides of the second dielectric layer and the first dielectric layer, the first positive electrode and the second positive electrode are connected, as are the first negative electrode and the second negative electrode.
[0027] Further, the substrate material includes a temperature-sensitive shape memory polymer, polydimethylsiloxane, or silicon wafer; and / or, the first nanowire and the second nanowire material includes polypropylene, polyethylene, or polyvinyl chloride; and / or, the first dielectric layer and the second dielectric layer material includes at least one of metal oxide, metal alloy oxide, and silicate; and / or, the first electrode layer and the second electrode layer material includes copper or palladium; and / or, the conductive layer material includes silver, gold, copper, graphite, or conductive organic material.
[0028] The present invention has the following advantages:
[0029] (1) The present invention uses controllable nanowire printing technology to prepare electrode patterns, which can realize the preparation of dual electrodes in the same layer in one step, effectively saving processing time and processing cost, and simplifying the processing process.
[0030] (2) The present invention uses 3D printed nanowires instead of a mask, thus avoiding the problem of easy contact and damage to other functional layers caused by the use of a mask in the past, thereby reducing costs and improving yield and production efficiency.
[0031] (3) The present invention uses nanowires (first nanowires and second nanowires) to divide the positive electrode and negative electrode regions. It does not require the use of a mask to block other areas where electrodes are not formed, so it will not cause depressions in the subsequent stacking process due to missing height, thus avoiding the occurrence of device stacking misalignment, collapse and device failure.
[0032] Compared with existing electrode patterning processes used for mass production of silicon-based capacitors, the present invention has simpler process steps, can significantly reduce product prices, and can realize ultra-thin high dielectric constant dielectric capacitors, making it suitable for a wide range of applications. Attached Figure Description
[0033] Figure 1 This is a flowchart of a capacitor manufacturing method according to a preferred embodiment of the present invention.
[0034] Figures 2-11 This is a schematic diagram of the process steps for preparing a capacitor according to a preferred embodiment of the present invention.
[0035] Figures 12-13 This is a schematic diagram of the electrode structure before and after cutting, according to a preferred embodiment of the present invention.
[0036] Figure 14 This is a schematic diagram of the structure of an electrode according to a preferred embodiment of the present invention.
[0037] Figure 15 This is a schematic diagram of the structure of an electrode according to a preferred embodiment three of the present invention. Detailed Implementation
[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.
[0039] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.
[0040] refer to Figure 1 A capacitor manufacturing method according to the present invention includes the following steps:
[0041] Step S1: Provide the substrate.
[0042] like Figure 2 As shown, a substrate 10 with a flat surface is used to further fabricate a capacitor structure on the substrate 10 using the method of the present invention.
[0043] The material of the substrate 10 is not particularly limited and can be a rigid material substrate 10 or a flexible material substrate 10. In some embodiments, the material of the substrate 10 includes a temperature-sensitive (epoxy) shape memory polymer, polydimethylsiloxane (PDMS), or a silicon wafer.
[0044] Step S2: Form a first nanowire 11 on the surface of the substrate 10 to divide the surface of the substrate 10 into two independent first regions 101 and second regions 102.
[0045] In distance Figure 2At a certain position on the left edge of the substrate 10 shown, a 3D first nanowire 11 is formed on the surface of the substrate 10 using nanowire printing technology. The two ends of the printed first nanowire 11 are exposed at least from the edge of the surface of the substrate 10, thereby dividing the surface of the substrate 10 into two independent first regions 101 and second regions 102.
[0046] In some embodiments, nanowire printing technology includes, but is not limited to, high-precision digitally controllable nanowire printing, screen printing, spraying, and other processes.
[0047] In some embodiments, the first nanowire 11 material comprises an organic polymer material. For example, the first nanowire 11 material comprises polypropylene (PP), polyethylene (PE), or polyvinyl chloride (PVC).
[0048] In some embodiments, the linewidth of the first nanowire 11 is 30 nm to 5000 nm. Preferably, the linewidth of the first nanowire 11 is 300 nm.
[0049] Step S3: A first electrode layer is formed on the surface of the substrate 10 to form a phase-separated first positive electrode and a first negative electrode on the first region 101 and the second region 102 on both sides of the first nanowire 11.
[0050] like Figure 3 As shown, next, a first electrode layer 12 is formed on the surface of the substrate 10 using a physical deposition process or a chemical deposition process, covering the first region 101, the second region 102, and the first nanowire 11, so that a phase-separated first positive electrode 121 and a first negative electrode 122 are formed on the first region 101 and the second region 102 on both sides of the first nanowire 11 (for clarity, Figure 3 The first positive electrode 121 and the first negative electrode 122, located in the first region 101 and the second region 102, are distinguished by cross-sectional lines and dot matrix, respectively.
[0051] In some embodiments, physical deposition processes or chemical deposition processes include, but are not limited to, PVE, PVD, ALD, CVD, etc.
[0052] In some embodiments, the material of the first electrode layer 12 includes a conductive material, such as a conventional electrode metal material.
[0053] In some embodiments, the material of the first electrode layer 12 includes copper or palladium.
[0054] Step S4: Remove the first nanowire 11.
[0055] like Figure 4As shown, the first nanowire 11 is then removed from the surface of the substrate 10 by physical tearing, adhesive removal or chemical solvent removal, and the material of the first electrode layer 12 covering the first nanowire 11 is also removed at the same time.
[0056] It should be noted that the positions of the first region 101 and the second region 102 can be interchanged, the positions of the first positive electrode 121 and the first negative electrode 122 can also be interchanged, and the first nanowire 11 can also be formed at a certain position at any edge of the substrate 10.
[0057] Step S5: A first dielectric layer is formed on the surface of the first electrode layer 12 to cover the first positive electrode 121 and the first negative electrode 122.
[0058] like Figure 5 As shown, a first dielectric layer 13 is formed on the surface of the first electrode layer 12 using a dielectric deposition process, such as ALD process, and covers the first positive electrode 121 and the first negative electrode 122.
[0059] In some embodiments, the material of the first dielectric layer 13 includes a high dielectric constant dielectric material.
[0060] In some embodiments, the material of the first dielectric layer 13 includes at least one of dielectric materials such as metal oxide, metal alloy oxide, and silicate.
[0061] In some embodiments, the material of the first dielectric layer 13 includes alumina, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, and any combination thereof.
[0062] The steps S2 to S5 above are represented by process T1.
[0063] Step S6: Form a second nanowire on the surface of the first dielectric layer 13 to divide the surface of the first dielectric layer 13 into two independent third and fourth regions.
[0064] like Figure 6 As shown, at the right side of the first dielectric layer 13 (i.e., at the distance from...) Figure 2 At a certain position on the right edge of the substrate 10 (as shown), a 3D second nanowire 14 is formed on the surface of the substrate 10 using nanowire printing technology, such as high-precision digitally controllable nanowire printing. The printed second nanowire 14 is positioned such that both ends are exposed at least from the corresponding edges of the surface of the first dielectric layer 13, thereby dividing the surface of the first dielectric layer 13 into two independent (unconnected) third regions 131 and fourth regions 132. The third region 131 is on the same side (left) as the lower first region 101, and the fourth region 132 is on the same side (right) as the lower second region 102.
[0065] In some embodiments, the second nanowire 14 material comprises an organic polymer material. For example, the second nanowire 14 material comprises PP, PE, or PVC.
[0066] In some embodiments, the linewidth of the second nanowire 14 may be the same as or different from the linewidth of the first nanowire 11.
[0067] In some embodiments, the linewidth of the second nanowire 14 is 30 nm to 5000 nm. Preferably, the linewidth of the second nanowire 14 is 300 nm.
[0068] In some embodiments, the second nanowire 14 and the first nanowire 11 are, but are not limited to, straight, zigzag, or curved shapes. Furthermore, the shape of the second nanowire 14 is consistent with the shape of the first nanowire 11. For example, Figure 2 and Figure 6 The example shows the linear morphology of the first nanowire 11 and the second nanowire 14.
[0069] In some embodiments, when forming the second nanowire 14 and the first nanowire 11, the second nanowire 14 and the first nanowire 11 are respectively located on opposite sides of the substrate 10.
[0070] In some embodiments, when forming the second nanowire 14 and the first nanowire 11, the projections of the second nanowire 14 onto the surface of the substrate 10 and the projections of the first nanowire 11 onto the surface of the substrate 10 are symmetrically distributed with respect to the center of the surface of the substrate 10. For example, when the first nanowire 11 and the second nanowire 14 are... Figure 2 and Figure 6 When the linear shape is shown, the distance between the first nanowire 11 and the left side of the substrate 10 is the same as the distance between the second nanowire 14 and the right side of the substrate 10, and the second nanowire 14 is parallel to the first nanowire 11.
[0071] Step S7: A second electrode layer is formed on the surface of the first dielectric layer 13 to form a phase-separated second positive electrode and a second negative electrode on the third region 131 and the fourth region 132 on both sides of the second nanowire 14.
[0072] like Figure 7 As shown, next, a second electrode layer 15 is formed on the surface of the first dielectric layer 13 using a physical deposition process or a chemical deposition process, and the third region 131, the fourth region 132, and the second nanowire 14 are covered to form a phase-separated second positive electrode 151 and a second negative electrode 152 on the third region 131 and the fourth region 132 on both sides of the second nanowire 14 (for clarity, Figure 7The second positive electrode 151 and the second negative electrode 152, located in the third region 131 and the fourth region 132, are distinguished by cross-sectional lines and dot matrix, respectively.
[0073] In some embodiments, physical deposition processes or chemical deposition processes include, but are not limited to, PVE, PVD, ALD, CVD, etc.
[0074] In some embodiments, the material of the second electrode layer 15 includes a conductive material, such as a conventional electrode metal material.
[0075] In some embodiments, the material of the second electrode layer 15 includes copper or palladium.
[0076] Step S8: Remove the second nanowire 14.
[0077] like Figure 8 As shown, the second nanowire 14 is then removed from the surface of the first dielectric layer 13 by physical tearing, adhesive removal or chemical solvent removal, and the material of the second electrode layer 15 covering the second nanowire 14 is also removed at the same time.
[0078] It should be noted that the second positive electrode 151 needs to be located on the same side as the first positive electrode 121 of the lower layer (left side in the figure), and the second negative electrode 152 also needs to be located on the same side as the first negative electrode 122 of the lower layer (right side in the figure).
[0079] Step S9: A second dielectric layer is formed on the surface of the second electrode layer 15 to cover the second positive electrode 151 and the second negative electrode 152.
[0080] like Figure 9 As shown, a second dielectric layer 16 is formed on the surface of the second electrode layer 15 using a dielectric deposition process, such as ALD process, and covers the second positive electrode 151 and the second negative electrode 152.
[0081] In some embodiments, the material of the second dielectric layer 16 includes a high dielectric constant dielectric material.
[0082] In some embodiments, the material of the second dielectric layer 16 includes at least one of dielectric materials such as metal oxide, metal alloy oxide, and silicate.
[0083] In some embodiments, the material of the second dielectric layer 16 includes alumina, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, and any combination thereof.
[0084] The above steps S6 to S9 are represented by process T2.
[0085] In some embodiments, after the above-described processes T1 and T2 are completed, a stacked structure consisting of the first positive electrode 121 and the first negative electrode 122, the first dielectric layer 13, the second positive electrode 151 and the second negative electrode 152, and the second dielectric layer 16 can be repeatedly formed on the surface of the second dielectric layer 16 according to steps S2 to S5 (process T1) and S6 to S9 (process T2). That is, after the above-described processes T1 and T2 are completed for the first time, the steps of processes T1 and T2 are repeated (steps S2-S9 are repeated) until the target number of positive electrode layers m and the number of negative electrode layers n are obtained, where m and n are both positive integers and m = n ≥ 2. The only difference is that in this repeated process, the subsequent first nanowire 11 is formed on the surface of the second dielectric layer 16 rather than on the surface of the substrate 10. Then, the following step S11 is performed.
[0086] Step S11: Remove substrate 10.
[0087] like Figure 10 As shown, the diagram illustrates the layer-by-layer decomposition of the device structure before substrate 10 removal (left figure) and the layer-by-layer decomposition of the device structure after substrate 10 removal (right figure). In some embodiments, substrate 10 is removed by methods such as peeling, burning, or grinding. It can be seen that the device structure after substrate 10 removal includes a capacitor layer structure composed of alternating layers of a first electrode layer 12 (containing a first positive electrode 121 and a first negative electrode 122), a first dielectric layer 13, a second electrode layer 15 (containing a second positive electrode 151 and a second negative electrode 152), and a second dielectric layer 16.
[0088] Step S12: Connect all positive electrodes and connect all negative electrodes.
[0089] like Figure 11 As shown, a mechanical cutting method is used to longitudinally cut the two ends of the above-mentioned device structure from the left and right sides as shown in the figure. The purpose is to expose the opposite outer ends of the first positive electrode 121 and the first negative electrode 122 located in each corresponding layer from the cut surfaces on both sides of the first dielectric layer 13, and to expose the opposite outer ends of the second positive electrode 151 and the second negative electrode 152 located in each corresponding layer from the cut surfaces on both sides of the second dielectric layer 16. Figure 11 The figure below also shows the outer end cross-sectional state of the first positive electrode 121 and the second positive electrode 151 located in each corresponding layer after cutting, as well as the outer end cross-sectional state of the first negative electrode 122 and the second negative electrode 152 located in each corresponding layer.
[0090] Finally, by forming conductive layers on the cut surfaces on the left and right sides of the second dielectric layer 16 and the first dielectric layer 13 respectively, electrical connections are made to all positive electrodes (first positive electrode 121 and second positive electrode 151) on the left side and to all negative electrodes (first negative electrode 122 and second negative electrode 152) on the right side.
[0091] In some embodiments, the conductive layer material includes silver, gold, copper, graphite, or conductive organic materials.
[0092] To address the shortcomings of existing technologies that typically require photolithography for patterning silicon-based capacitor electrodes, which are expensive and involve complex processes, this invention introduces nanowire printing technology (such as high-precision digitally controlled nanowire printing) as a masking method for patterning electrodes. This technology offers several advantages. First, its high printing speed significantly improves production efficiency. Second, it avoids damage to other functional layers due to mask contact, thus reducing costs, increasing yield, and improving production efficiency. Finally, its high step coverage reduces defects and errors in the electrode pattern, enhancing product consistency and reliability. These advantages make high-precision digitally controlled nanowire printing a highly promising electrode patterning method. With continuous technological advancements and improvements, this technology is expected to see wider application in the future, bringing greater convenience and benefits to the production of silicon-based capacitors.
[0093] Example 1
[0094] refer to Figures 12-13 .
[0095] Step S21: Print a straight PP material first nanowire with a linewidth of 300 nm diagonally across the left corner edge of a 2cm × 1cm temperature-sensitive epoxy shape memory polymer substrate (figure omitted, see reference). Figure 12 (The position of the first nanowire trajectory marked in the middle);
[0096] Step S22: Using the PVE process, deposit a copper first electrode layer with a thickness of 80nm on the substrate;
[0097] Step S23: Immerse in acetone to remove the printed first nanowire while simultaneously removing the first electrode layer material covering the surface of the first nanowire. Figure 12 A copper first positive electrode 121 and a copper first negative electrode 122 are formed on both sides of the first nanowire trajectory shown in the figure;
[0098] Step S24: Deposit a 20 nm thick zirconium oxide (HZO) first dielectric layer 13 using the ALD process;
[0099] Step S25: At a diagonal distance of 500 micrometers from the right corner edge of the substrate 10, print linear PP material second nanowires with a linewidth of 300 nm on the surface of the first dielectric layer 13, forming second nanowires symmetrically distributed with the first nanowires (figure omitted, see reference). Figure 12 (the position of the second nanowire trajectory marked in the middle);
[0100] Step S26: Deposit a copper second electrode layer 15 with a thickness of 80 nm using the PVE process;
[0101] Step S27: Immerse in acetone to remove the printed second nanowire while simultaneously removing the second electrode layer 15 material covering the surface of the second nanowire. Figure 12 The second nanowire trajectory shown in the image forms a copper second positive electrode 151 and a copper second negative electrode 152 on both sides, forming a stacked structure as shown in the image. Figure 12 As shown;
[0102] Step S28: Deposit a 20nm thick HZO second dielectric layer using the ALD process (figure omitted);
[0103] Step S29: Repeat processes S21 to S28 1000 times (the repetition begins on the second dielectric layer of step S28);
[0104] Step S30: Heat the temperature-sensitive epoxy shape memory polymer substrate to reduce the adhesion of the substrate material to the first electrode layer and then peel it off from the first electrode layer (copper first positive electrode 121 and copper first negative electrode 122).
[0105] Step S31: Cut to expose electrodes on both sides, the resulting stacked structure is as follows Figure 13 As shown;
[0106] Step S32: Deposit conductive polymer encapsulation material on both sides and connect all electrodes on the same side.
[0107] Example 2
[0108] refer to Figure 14 .
[0109] Step S41: Print a zigzag-shaped PE material first nanowire with a linewidth of 200 nm at a distance of 500 micrometers from the left edge of a 1 mm × 1 mm PDMS substrate (figure omitted), forming a concave-turned first nanowire pattern (figure omitted, see reference). Figure 14 (The position of the first nanowire trajectory marked in the middle);
[0110] Step S42: Deposit a 50nm thick palladium first electrode layer using the PVE process;
[0111] Step S43: Immerse in acetone to remove the printed first nanowire while simultaneously removing the first electrode layer material covering the surface of the first nanowire. Figure 14 A palladium first positive electrode 121 and a palladium first negative electrode 122 are formed on both sides of the first nanowire trajectory shown in the figure;
[0112] Step S44: Deposit a 50nm thick titanium oxide first dielectric layer 13 using the ALD process;
[0113] Step S45: At a distance of 500 micrometers from the right edge of the substrate 10, a zigzag-shaped second nanowire of PE material with a linewidth of 200 nm is printed on the surface of the first dielectric layer 13, forming a second nanowire pattern with concave bends symmetrically distributed with the first nanowires (figure omitted, see reference). Figure 14 (the position of the second nanowire trajectory marked in the middle);
[0114] Step S46: Deposit a 50nm thick palladium second electrode layer using the PVE process;
[0115] Step S47: Immerse in acetone to remove the printed second nanowire while simultaneously removing the second electrode layer material covering the surface of the second nanowire. Figure 14 The second nanowire trajectory shown in the image forms a palladium second positive electrode 151 and a palladium second negative electrode 152 on both sides, forming a stacked structure as shown in the image. Figure 14 As shown;
[0116] Step S48: Deposit a 50 nm thick titanium oxide second dielectric layer using the ALD process (figure omitted);
[0117] Step S49: Repeat the process from S41 to S48 5000 times (the repetition begins on the second dielectric layer in step S48);
[0118] Step S50: Remove the PDMS substrate by ablation.
[0119] Step S51: Cut to expose electrodes on both sides;
[0120] Step S52: Deposit copper metal encapsulation material on both sides and connect all electrodes on the same side.
[0121] Example 3
[0122] refer to Figure 15 .
[0123] Step S61: Print an arc-shaped first nanowire of PVC material with a linewidth of 500nm at a distance of 100 micrometers from the left edge of a 3mm×2mm silicon wafer substrate (figure omitted, see reference). Figure 15 (The position of the first nanowire trajectory marked in the middle);
[0124] Step S62: Deposit a copper first electrode layer with a thickness of 100nm using the PVE process;
[0125] Step S63: Immerse in acetone to remove the printed first nanowire while simultaneously removing the first electrode layer material covering the surface of the first nanowire. Figure 15 A copper first positive electrode 121 and a copper first negative electrode 122 are formed on both sides of the first nanowire trajectory shown in the figure;
[0126] Step S64: Deposit a 20nm thick HZO first dielectric layer 13 using the ALD process;
[0127] Step S65: At a distance of 100 micrometers from the right edge of the substrate, print arc-shaped PVC material second nanowires with a linewidth of 50 nm on the surface of the first dielectric layer 13, forming an arc-shaped second nanowire pattern symmetrically distributed with the first nanowires (figure omitted, see reference). Figure 15 (the position of the second nanowire trajectory marked in the middle);
[0128] Step S66: Deposit a copper second electrode layer with a thickness of 100 nm using the PVE process;
[0129] Step S67: Immerse in acetone to remove the printed second nanowire while simultaneously removing the second electrode layer material covering the surface of the second nanowire. Figure 15 The second nanowire trajectory shown in the image forms a copper second positive electrode 151 and a copper second negative electrode 152 on both sides, forming a stacked structure as shown in the image. Figure 15 As shown;
[0130] Step S68: Deposit a 50nm thick HZO second dielectric layer using the ALD process (figure omitted);
[0131] Step S69: Repeat the process from S61 to S68 500 times (the repetition begins on the second dielectric layer in step S68);
[0132] Step S70: Use CMP process to grind the silicon wafer substrate to remove the silicon wafer substrate material.
[0133] Step S71: Cut to expose electrodes on both sides;
[0134] Step S72: Deposit encapsulating gold material on both sides and connect all electrodes on the same side.
[0135] The thickness of each film layer in the above embodiments can be varied as needed. The substrate size and the position and morphology of the nanowires are merely examples.
[0136] Using the capacitor fabrication method of the present invention described above, an ultrathin high dielectric constant dielectric capacitor structure having multiple layers can be fabricated by sequentially forming a first positive electrode 121 and a first negative electrode 122, a dielectric layer, a second positive electrode 151 and a second negative electrode 152, and a dielectric layer on a substrate.
[0137] In summary, this invention utilizes controllable nanowire printing technology to achieve electrode patterning, enabling the simultaneous fabrication of two electrodes in a single layer. This effectively saves processing time and costs, and simplifies the manufacturing process. Furthermore, by replacing photomasks with 3D-printed nanowires, this invention avoids the problems associated with photomasks, such as the risk of touching and damaging other functional layers, thus reducing costs and improving yield and production efficiency. Simultaneously, by using printed nanowires to separate the positive and negative electrode regions, this invention eliminates the need for photomasks to cover areas where electrodes are not required. Therefore, it avoids depressions caused by missing height during subsequent layer stacking, preventing device misalignment, collapse, and ultimately, device failure. Compared to existing electrode patterning processes used for mass-producing silicon-based capacitors, this invention offers simpler process steps, significantly reduces product prices, and enables the fabrication of ultrathin, high-dielectric-constant dielectric capacitors, making it suitable for a wide range of applications.
[0138] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.
Claims
1. A method for manufacturing a capacitor, characterized in that, Includes the following steps: Step S1: Provide the substrate; Step S2: Form a first nanowire on the surface of the substrate to divide the surface of the substrate into two independent first regions and a second region through the first nanowire; Step S3: Form a first electrode layer on the surface of the substrate to form a phase-separated first positive electrode and a first negative electrode on the first region and the second region on both sides of the first nanowire; Step S4: Remove the first nanowire.
2. The capacitor manufacturing method according to claim 1, characterized in that, Also includes: Step S5: Form a first dielectric layer on the surface of the first electrode layer to cover the first positive electrode and the first negative electrode.
3. The capacitor manufacturing method according to claim 2, characterized in that, Also includes: Step S6: Form a second nanowire on the surface of the first dielectric layer to divide the surface of the first dielectric layer into two independent third and fourth regions by means of the second nanowire; Step S7: Form a second electrode layer on the surface of the first dielectric layer to form a phase-separated second positive electrode and a second negative electrode on the third region and the fourth region on both sides of the second nanowire; Step S8: Remove the second nanowire; Step S9: Form a second dielectric layer on the surface of the second electrode layer to cover the second positive electrode and the second negative electrode; Step S10: Repeat steps S2-S9 above until the target number of positive electrode layers m and the number of negative electrode layers n are obtained, where m and n are both positive integers and m=n≥2; Step S11: Remove the substrate; Step S12: Connect all the positive electrodes and connect all the negative electrodes.
4. The capacitor manufacturing method according to claim 3, characterized in that, When forming the second nanowire and the first nanowire, the second nanowire and the first nanowire are respectively located on opposite sides of the substrate.
5. The capacitor manufacturing method according to claim 3, characterized in that, The second nanowire and the first nanowire may be linear, zigzag, or curved.
6. The capacitor manufacturing method according to claim 3, characterized in that, The substrate material includes rigid or flexible materials; and / or, the second nanowire and the first nanowire are formed by nanowire printing technology; and / or, the second electrode layer and the first electrode layer are formed by physical deposition or chemical deposition processes; and / or, the second nanowire and the first nanowire are removed by physical tearing, adhesive removal, or chemical solvent removal; and / or, the substrate is removed by peeling, burning, or grinding.
7. The capacitor manufacturing method according to claim 3, characterized in that, The linewidth of the second nanowire and the linewidth of the first nanowire are both 30 nm to 5000 nm.
8. The capacitor manufacturing method according to claim 3, characterized in that, By using a cutting method, the opposite outer ends of the first positive electrode and the first negative electrode are exposed from the cut surfaces on both sides of the first dielectric layer, and the opposite outer ends of the second positive electrode and the second negative electrode are exposed from the cut surfaces on both sides of the second dielectric layer. By forming conductive layers on both sides of the second dielectric layer and the first dielectric layer, the first positive electrode and the second positive electrode are connected, as are the first negative electrode and the second negative electrode.
9. The capacitor manufacturing method according to claim 8, characterized in that, The substrate material includes a temperature-sensitive shape memory polymer, polydimethylsiloxane, or silicon wafer; and / or, the first nanowire and the second nanowire material includes polypropylene, polyethylene, or polyvinyl chloride; and / or, the first dielectric layer and the second dielectric layer material includes at least one of metal oxide, metal alloy oxide, and silicate; and / or, the first electrode layer and the second electrode layer material includes copper or palladium; and / or, the conductive layer material includes silver, gold, copper, graphite, or conductive organic material.