Data error correction method, apparatus, device, and medium

Abstract

The application discloses a data error correction method, device, equipment and medium, relates to the technical field of data storage, and the data error correction method comprises the following steps: obtaining the state parameters of a target storage block, inputting the state parameters into a prediction model, predicting the error rate of data of the target storage block in a future target time period, and selecting a suitable error correction model based on the prediction result. In this way, the number of unnecessary re-reading times can be reduced, the error correction efficiency is improved, and the problem of performance degradation of a storage device caused by frequent re-reading operations in some technologies can be solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data storage, and in particular, to a data error correction method and device, equipment and medium. BACKGROUND

[0002] In storage technology, flash memory has a significantly faster read speed than a hard disk drive (HDD), and is therefore widely used in various storage devices such as solid state drives (SSDs), USB flash disks, SD cards, and the like.

[0003] QLC (Quad-Level Cell) is a kind of flash memory medium that stores 4-bit data by dividing the threshold voltage into 16 states. However, due to the narrow voltage distribution and the small voltage difference between states, when faced with interference, some threshold voltages will deviate from the original state, resulting in read errors. In some technologies, based on the read mechanism, read errors can be corrected by adjusting the read voltage. However, too many read operations will increase the read delay, and thus cause the performance of the storage device to decline. SUMMARY

[0004] The present application provides a data error correction method, data error correction device, electronic equipment, computer readable storage medium and computer program product to at least solve the problem of performance decline of the storage device caused by frequent read operations in the related art.

[0005] The present application provides a data error correction method, comprising:

[0006] obtaining a state parameter of a target storage block in a storage system;

[0007] based on the state parameter, predicting an error rate of the target storage block in a future target period;

[0008] determining a target error correction model corresponding to the target storage block based on at least the error rate;

[0009] based on the target error correction model, correcting data errors in the target storage block.

[0010] The present application also provides a data error correction device, comprising:

[0011] a data reading module configured to obtain a state parameter of a target storage block in a storage system;

[0012] an error rate prediction module configured to predict an error rate of the target storage block in a future target time period based on the state parameter;

[0013] a correction model confirmation module configured to determine a target correction model corresponding to the target storage block based on at least the error rate;

[0014] a parameter adjustment module configured to correct data errors of the target storage block based on the target correction model.

[0015] The present application also provides an electronic device, comprising a memory configured to store a computer program, and a processor configured to execute the computer program to implement the steps of any of the data correction methods.

[0016] The present application also provides a computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of any of the data correction methods.

[0017] The present application also provides a computer program product, which comprises a computer program, wherein the computer program is executed by a processor to implement the steps of any of the data correction methods.

[0018] In the technical solutions of some embodiments of the present application, by obtaining the state parameter of the target storage block, inputting the state parameter into a prediction model, predicting the error rate of the data of the target storage block in a future target time period, and selecting a suitable correction model based on the prediction result, the number of unnecessary re-reading operations can be reduced, the correction efficiency can be improved, and the problem of performance degradation of the storage device caused by frequent re-reading operations in some technologies can be solved. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 a schematic diagram of the relationship among the host, the storage controller and the flash memory provided by some embodiments of the present application;

[0021] Figure 2 a flowchart of the data correction method provided by the first embodiment of the present application;

[0022] Figure 3 a flowchart of the data correction method provided by the second embodiment of the present application;

[0023] Figure 4A flowchart illustrating the data error correction method provided in the third embodiment of this application;

[0024] Figure 5 A flowchart illustrating the data error correction method provided in the fourth embodiment of this application;

[0025] Figure 6 Schematic diagram of a data error correction device provided for some embodiments of this application;

[0026] Figure 7 A schematic diagram of the modules of an electronic device provided for some embodiments of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0028] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0029] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Currently, flash memory is mainly classified according to the number of bits that each flash memory cell (i.e., storage cell) can store, including SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), and QLC. SLC stores only 1 bit of data per cell and has only two charge states (0 and 1); MLC stores 2 bits of data per cell and has four different charge states (00, 01, 10, and 11); TLC stores 3 bits of data per cell and has eight different charge states; and QLC stores 4 bits of data per cell and has 16 different charge states. As storage density increases and the spacing between cells decreases, programming and erasing interference between adjacent cells, as well as changes in time and temperature, can all cause changes in the charge states of the cells, causing the threshold voltage to deviate from its original state, thus triggering read errors and increasing the error rate. Currently, some technologies use a reread mechanism to correct read errors by adjusting the read voltage. However, excessive rereading will increase read latency, which in turn will lead to a decrease in the performance of the storage device.

[0031] In view of this, this application provides a data error correction method that can solve the above problems. This data error correction method can be applied to a storage controller. The storage controller is located between the host and the flash memory. (See also...) Figure 1 This is a schematic diagram illustrating the relationship between the host, storage controller, and flash memory, provided for some embodiments of this application. Figure 1 In this system, the host performs data operations (such as reading, writing, modifying, and deleting data) in the flash memory through the storage controller.

[0032] See also Figure 2 The above is a flowchart illustrating a data error correction method provided in some embodiments of this application, such as... Figure 1 As shown, the data correction method includes the following steps S201 to S204.

[0033] Step S201: Obtain the status parameters of the target storage block in the storage system.

[0034] In this embodiment, the host sends a data read command to the storage controller. The data read command indicates the target data to be read by the host. The storage block containing the target data is called the target storage block. Specifically, in flash memory, each storage block may include multiple storage pages, and each storage page may include multiple storage cells. In flash memory, a storage page is the smallest logical unit for read / write operations, a storage block is the smallest physical unit for erase operations, and a storage cell is the smallest physical storage unit, typically a floating-gate transistor, where the number of injected electrons represents the stored data.

[0035] Status parameters may include, but are not limited to, wear parameters, error parameters, and environmental parameters (such as temperature records) of the target storage block. Among them, the wear parameter is the number of P / E (program / erase) cycles, and the error parameter is the RBER (Raw Bit Error Rate).

[0036] Step S202: Based on the state parameters, predict the error rate of the target storage block in the future target time period.

[0037] Specifically, during read operations, flash memory typically exhibits a high error rate, which is mainly caused by factors such as P / E interference between adjacent memory cells and temperature variations.

[0038] In this embodiment, preprocessing operations (including but not limited to normalization or feature extraction) are performed on the above-mentioned state parameters, and the preprocessed state parameters are input into the pre-trained prediction model to predict the error rate of the target storage block in the future target time period.

[0039] Step S203: Determine the target error correction model corresponding to the target storage block, based at least on the error rate.

[0040] Specifically, error correction models refer to the specific methods used to correct data errors in storage units. Error correction models include, but are not limited to, ECC (Error Correction Code), EECC (Enhanced Error Correction Code), RS (Reed-Solomon Code), and LDPC (Low-Density Parity-Check Code). ECC detects and locates errors by adding parity bits and is mainly used in scenarios with low reliability requirements, such as SLC and MLC flash memory devices. EECC was developed to address the ever-increasing error rate of flash memory. RS provides more parity bits and can handle scenarios with multiple consecutive bit errors, but it also requires higher system overhead. LDPC uses an iterative probabilistic decoding algorithm, combining software and hardware decoding to correct thousands of bit errors, and is mainly used in high-density storage scenarios with high reliability requirements, such as TLC and QLC flash memory devices.

[0041] In addition, error correction models can also include cascaded error correction models of RS+LDPC, which can give full play to the coding advantages of both models and solve scenarios where burst errors and random bit errors occur simultaneously.

[0042] In this embodiment, the predicted error rate can be compared with a preset threshold to determine the error correction model that the target storage block needs to adopt in the future target time period. Specifically, when the error rate is high, an error correction model with stronger error correction capabilities can be used to ensure that all errors can be corrected; when the error rate is low, an error correction model with lower computational complexity can be used to reduce resource consumption during algorithm operation.

[0043] Step S204: Correct data errors in the target storage block based on the target error correction model.

[0044] Specifically, after reading data from the target storage block, the target error correction model can be used to correct the read data, and the corrected data can be returned to the host.

[0045] The data error correction method provided in this embodiment obtains the state parameters of the target storage block, inputs these parameters into a prediction model, predicts the error rate of the data in the target storage block within a future target time period, and selects an appropriate error correction model based on the prediction results. This reduces unnecessary rereads, improves error correction efficiency, and addresses the performance degradation of storage devices caused by frequent reread operations in some technologies. It also extends the lifespan of flash memory. Furthermore, selecting an error correction model based on different error rates ensures data integrity for high-error-rate storage blocks and improves the data read rate for low-error-rate storage blocks.

[0046] In some embodiments, predicting the error rate of the target storage block in a future target time period based on state parameters in step S202 may include:

[0047] The state parameters are input into the trained prediction model to obtain the error rate. The prediction model includes a neural network sub-model and a physical sub-model. The neural network sub-model is used to output the initial error rate of the target storage block in the future target time period based on the state parameters. The physical sub-model is used to correct the initial error rate based on the weights of each state parameter to obtain the error rate. The weights of the state parameters are used to characterize the degree of correlation between each state parameter and the error rate.

[0048] In this embodiment, the relationship between the aforementioned state parameters and the error rate is not a simple linear one, but rather involves a complex, nonlinear interaction. For example, the combined effect of the P / E ratio and temperature recordings on the error rate is far greater than the individual effects of either factor. Traditional models struggle to predict such complex, coupled, nonlinear relationships. Neural networks, however, can automatically learn and extract the relationships between complex nonlinear features (such as higher-order coupling and abrupt changes), eliminating the need for manually pre-setting complex physical formulas. Therefore, by combining neural network sub-models with physical sub-models, accurate prediction of the error rate can be achieved.

[0049] Specifically, after inputting the state parameters into the neural network sub-model, the output of the neural network sub-model can be used as the initial error rate of the target storage block in the future target time period. Then, the physical sub-model is used to correct the initial error rate to obtain the final error rate. Among them, the neural network sub-model is used to capture the complex nonlinear characteristics between the state parameters, and the physical sub-model is used to ensure the correctness of the basic laws (such as the error rate monotonically increasing with the wear and tear of the storage block) and avoid absurd predictions.

[0050] Taking the P / E count, recent average RBER, and temperature records of the target storage block as examples, a fusion formula as shown in expression (1) can be set in the physical sub-model, and the initial error rate of the neural network sub-model output can be corrected based on this fusion formula.

[0051] (1)

[0052] in, This represents the error rate of the final output of the prediction model; , , These represent the number of P / E cycles, the recent average RBER, and the temperature record, respectively. This represents the initial error rate of the neural network sub-model output; , , , This represents the weight corresponding to each state parameter; This indicates noise or error that the model did not capture.

[0053] In this embodiment, the above expression (1) is obtained based on fitting a large amount of historical data. It should be noted that for the weights... , , , The settings need to be considered in conjunction with the actual operation of the flash memory. For example, taking the temperature recording feature as an example, when the temperature is too high, the impact on the threshold voltage of the storage cell will increase significantly. In this case, it is necessary to adjust the weight allocation so that the weight of temperature recording is higher than the weight of other features.

[0054] In the above embodiment, the state parameters are input into the trained neural network sub-model to obtain the initial prediction rate. Then, the initial error rate is corrected using the physical sub-model to obtain the final error rate output by the model. Using a combination of a neural network sub-model and a physical sub-model for error rate prediction leverages the powerful nonlinear fitting and multi-dimensional feature fusion capabilities of the neural network, while the physical model limits the output of the neural network, preventing overfitting and resulting prediction distortion. By dynamically allocating weights to each state parameter, the model can adaptively allocate weights based on the degree of parameter influence on the error rate under different circumstances, thereby improving the overall prediction accuracy.

[0055] In the data error correction method provided in this embodiment, in conjunction with reference to Figure 3 , Figure 3 This is a flowchart illustrating another data error correction method provided in an embodiment of this application. Figure 3 As shown, the prediction model in this data error correction method is obtained based on the following steps S301 to S304.

[0056] Step S301: Obtain the trained first model and the second model to be trained. The number of parameters in the first model is greater than the number of parameters in the second model.

[0057] Step S302: Input the state parameter samples into the first model and the second model respectively to obtain the first output result of the first model and the second output result of the second model.

[0058] Step S303: Train the second model based on the first output result, the second output result, and the labels of the state parameter samples.

[0059] Step S304: After the second model training is completed, the parameters of the second model are pruned based on the weights of each parameter in the second model to obtain the prediction model.

[0060] Specifically, the first model can be viewed as a teacher model, and the second model as a student model. The second model has fewer parameters than the first model, and at the same time, it can reduce model complexity while maintaining high prediction accuracy.

[0061] exist Figure 3 In the illustrated embodiment, the first model is trained using the following method:

[0062] 1) Collect state parameter samples from multiple storage blocks (such as P / E count, average RBER, and temperature records).

[0063] Specifically, state parameter samples can be collected using the following methods:

[0064] Obtain multiple initial state parameters of the target storage block;

[0065] Based on the correlation between each initial state parameter and the error rate, parameters with a correlation below a threshold are removed from the initial state parameters to obtain a state parameter sample.

[0066] Specifically, when obtaining multiple initial state parameters of the target storage block, these initial target parameters are constructed into a parameter set, which includes, but is not limited to, P / E cycle count, average RBER, temperature recording, average programming voltage, and block erase count. Then, for this parameter set, the correlation between each parameter and the error rate is evaluated through feature importance analysis. Finally, a correlation threshold is preset; initial state parameters below this threshold are considered redundant or noisy parameters. For example, the correlation between the parameter set and the error rate is verified using the Pearson product-moment correlation coefficient (PCCMCC) or XGBoost (eXtreme Gradient Boosting). The parameters with the highest importance (N) or those with correlation coefficients higher than the preset value are then retained as the final filtered state parameters.

[0067] In the above embodiments, by setting a preset correlation threshold, the initial state parameters are evaluated for correlation, and parameters with correlation below the preset correlation threshold are removed. This can significantly reduce the computational cost of the model while ensuring prediction accuracy, and is more conducive to embedding the model in resource-constrained hardware environments.

[0068] 2) Perform normalization preprocessing on the state parameter samples. Specifically, taking the P / E count as an example, the P / E count of multiple storage blocks can be normalized based on expression (2).

[0069] (2)

[0070] in, This represents the normalized P / E ratio; This represents the number of P / E cycles before normalization for the k-th memory block. It is the average number of P / E cycles across multiple storage blocks; It is the standard deviation of the P / E cycles for multiple storage blocks.

[0071] 3) Define the fusion formula as shown in expression (3).

[0072] (3)

[0073] Expression (3) is basically similar to expression (1), the main difference being that expression (3) includes parameters. It is used to characterize noise or error.

[0074] 4) The first model is trained based on the loss function shown in expression (4).

[0075] (4)

[0076] in, , , , That is, the weights corresponding to each state parameter; Indicates the number of state parameter samples; Indicates the first The prediction error rate of a sample of state parameters; Indicates the first The true error rate of a sample of state parameters; Represents the regularization coefficient, controlling the weight of the parameter. , , , The severity of the punishment.

[0077] After training the first model, the state parameter samples can be input into the trained teacher model (i.e., the first model) and student model (i.e., the second model) respectively to obtain the first output result of the teacher model and the second output result of the student model.

[0078] After obtaining the first and second output results, the parameters of the second model can be adjusted based on the loss function shown in expression (5) so that the output of the student model gradually approaches the output of the teacher model.

[0079] (5)

[0080] in, This represents the loss based on the true label. The loss represents the KL divergence. This represents the loss function, used to measure the difference between the output distributions of the student model and the teacher model.

[0081] The loss of the real label can be calculated as shown in expression (6).

[0082] (6)

[0083] in, Indicates the number of categories; Indicates the first The one-hot encoding of the true label of each category can set the correct category position to 1 and keep the rest positions to 0; Indicates the first The probability distribution of student network output under each category.

[0084] The KL divergence loss can be calculated as shown in expression (7).

[0085] (7)

[0086] Among them, regarding Please refer to the relevant description of expression (6) above, which will not be repeated here. , These represent the outputs of the teacher / student network models after temperature scaling, respectively.

[0087] The above , The calculation method can be shown in expression (8).

[0088] (8)

[0089] Among them, regarding Please refer to the relevant description of expression (6) above, which will not be repeated here. This represents the output of the (teacher / student) network model after temperature scaling. Indicates the first The original output under each category; This represents the temperature parameter.

[0090] The loss function design shown in expression (5) above comprehensively considers the supervision signal of the real labels and the key state features of teacher knowledge imitation inheritance. The supervision signal of the real labels guides the student model's learning of key state features, while the key state features of teacher knowledge imitation inheritance provide richer contextual information through the probability distribution of soft labels. Furthermore, the Kullback-Leibler divergence (KL divergence) measures the difference between the teacher model's output distribution and the student model's output distribution, further guiding the student model to learn the teacher model's knowledge and improving prediction accuracy.

[0091] After generating the student network model through the above steps, further pruning and compression are needed to reduce the model's complexity. At this point, you can choose to remove neurons that have little impact on the model output (such as nodes with weights close to 0), or remove redundant parameters that contribute little to model performance, retaining only key parameters, thus sparsifying the network structure and reducing model size and memory usage.

[0092] In this embodiment, INT4 quantization (4-bit Integer Quantization) can be used on the original model to convert the model parameters from 32-bit floating-point numbers (FP32) to 4-bit integers (INT4). For the compressed student network, a high compression ratio needs to be ensured, while the throughput of the NPU (Neural Network Processing Unit) also needs to be at a high level.

[0093] The compression ratio can be calculated as shown in expression (9).

[0094] (9)

[0095] in, Indicates the model compression ratio; This represents the original number of parameters in the model; This indicates the number of parameters retained in the model after pruning; This represents the sparsity rate, which is the proportion of parameters that have been pruned to zero out of the total number of parameters. The number of bits occupied by the data type representing the weights of the original model is usually a constant; The number of bits used to represent the data type of the compressed model weights is usually a constant.

[0096] The NPU throughput can be calculated as shown in expression (10).

[0097] (10)

[0098] in, Indicates NPU throughput; Indicates the batch size for parallel processing; Indicates the operating clock frequency of the NPU; This indicates the number of clock cycles required for each instruction.

[0099] In the above embodiments, knowledge distillation is employed to train the student network through the teacher network. This allows the student network to inherit key feature parameters, reducing the risk of overfitting on limited data. Then, the student network is compressed and pruned, removing neurons with minimal impact on output or redundant parameters that contribute little to model performance, thereby reducing model size while maintaining output accuracy.

[0100] In this embodiment, a data error correction method is provided, which is discussed in conjunction with the references. Figure 4 , Figure 4 A flowchart illustrating yet another data error correction method provided in this application embodiment is shown below. Figure 4 As shown, the above step S103 includes the following steps S401 to S403.

[0101] Step S401: Obtain the attribute parameters of the target storage block.

[0102] Specifically, after obtaining the prediction error rate output by the prediction model, the attribute parameters of the target storage block can be obtained. These attribute parameters include, but are not limited to, information from multiple dimensions such as the page type, inter-layer differences, physical location of flash memory, number of iterations of the current page, and standard deviation of voltage distribution of the target storage block.

[0103] Step S402: Based on the attribute parameters and error rate, determine the error correction score of the target storage block. The error correction score is used to characterize the severity of errors in the data in the target storage block.

[0104] Specifically, after obtaining the attribute parameters of the target storage block, and combining them with the predicted error rate, the error correction score of the target storage block can be calculated to assess the severity of errors in the data within the target storage block.

[0105] In some embodiments, step S402 includes steps S4021 to S4022.

[0106] Step S4021: Obtain the error rate weight and the parameter weight of the attribute parameter. The error rate weight represents the degree of influence of the error rate on the error correction score, and the parameter weight represents the degree of influence of each attribute parameter on the error correction score.

[0107] Specifically, if the error rate predicted by the model is high, the impact of the error rate on the error correction score is greater, and in this case, the weight of the error rate needs to be increased. Each attribute parameter also has a different degree of influence on the error correction score. For example, regarding page type, when the flash memory cells are SLC and QLC, SLC is more stable than QLC due to their different bit counts, so different parameter weights need to be selected according to different page types. Similarly, regarding the number of iterations of the current page, if the number of iterations of the current page is too high, it means that the data on the current page needs to be reread more times, and the degree of data error is higher; in this case, the weight of the parameter of the number of iterations of the current page needs to be increased.

[0108] Step S4022: Based on the error rate weight and parameter weight, perform a weighted fusion calculation on the error rate and each attribute parameter to obtain the error correction score.

[0109] Specifically, the error correction score is calculated as shown in expression (11).

[0110] (11)

[0111] Among them, regarding Please refer to the relevant description of expression (1) above, which will not be repeated here. Indicates the error correction score; ~ This indicates the weighting of error rate and attribute parameters; This indicates different values ​​corresponding to different page types (e.g., SLC is relatively stable, so a lower value is provided; QLC has poor reliability, so a higher value is provided). Interlayer RBER differences; This represents the physical location code, i.e., the page coordinate code; Indicates the current page iteration count; This represents the standard deviation of the threshold voltage distribution.

[0112] In the above embodiments, an error correction score is obtained by dynamically weighting the error rate and various attribute parameters and performing a weighted calculation. For storage pages with low error rates, after obtaining an error correction score through reasonable weight allocation, it is possible to avoid subsequently executing a high-capability error correction model, thus preventing resource waste. Simultaneously, for storage pages with high error rates, weight allocation can ensure that a high-capability error correction model can be triggered subsequently, thereby guaranteeing data integrity.

[0113] Step S403: Determine the target error correction model based on the error correction score. For details, please refer to [link to relevant documentation]. Figure 2 Step S203 of the illustrated embodiment will not be described again here.

[0114] In some embodiments, step S403 may include, but is not limited to, the following steps S4031 to S4032.

[0115] Step S4031: Among the preset multiple error correction scoring intervals, determine the target error correction scoring interval where the error correction score is located. Each error correction scoring interval has its own associated error correction model, and at least some error correction scoring intervals are associated with different error correction models.

[0116] Specifically, after calculating the error correction score, the error correction score interval corresponding to the error correction score is determined based on multiple preset error correction score intervals. The preset error correction score interval can be expressed as shown in equation (12).

[0117] (12)

[0118] in, Indicates an optional error correction model; , , , These represent different error correction models corresponding to different intervals.

[0119] Step S4032: The error correction model associated with the target error correction score interval is used as the target error correction model.

[0120] Specifically, after determining the error correction score range corresponding to the target error correction score, the corresponding error correction model is selected as the target error correction model, and subsequent operations are performed.

[0121] In some embodiments, when the error correction model is At the same time, it is also necessary to further calculate the number of LDPC iterations based on the error correction score. The calculation method of the number of LDPC iterations can be shown in expression (13).

[0122] (13)

[0123] in, Indicates the number of LDPC iterations; Indicates the number of basic iterations; This indicates the maximum allowed number of iterations.

[0124] In some embodiments, when the error correction model is At that time, the RS error correction code length needs to be further calculated based on the standard deviation of the threshold voltage distribution. The calculation method of the RS error correction code length can be expressed as shown in equation (14).

[0125] (14)

[0126] Among them, regarding Please refer to the relevant description of expression (11) above, which will not be repeated here. Indicates the length of the RS error correction code; Indicates the base code length.

[0127] In the above embodiments, by presetting different error correction score ranges, the calculated error correction scores can be mapped to different error correction models, so that when facing different scenarios, an appropriate error correction model can be selected for data error correction.

[0128] The data error correction method provided in this embodiment determines the data organization and access characteristics based on the previously statistical page types. Different page types may require different error correction strategies. Inter-layer differences and flash memory physical locations reflect the physical structural characteristics of the memory. Analyzing these differences helps to allocate error correction resources in a targeted manner. The current page iteration count reflects the complexity of the current error correction, while the voltage distribution standard deviation reveals the dispersion of the threshold voltage of the memory cell. Thus, by using the above attribute parameters and the predicted error rate, a weighted error correction score is calculated to determine the most suitable error correction model and achieve the best error correction effect.

[0129] In this embodiment, a data error correction method is provided, which is discussed in conjunction with the following: Figure 5 Figure 5 is a flowchart illustrating another data error correction method provided in an embodiment of this application. Figure 5 As shown, in this data error correction method, the target storage block includes multiple storage units. The threshold voltage of the storage unit is used to characterize the data stored in the storage unit. Different data have their own corresponding threshold voltage range. When reading data from each storage unit according to different reading voltages, the corresponding reread success rate is different. The method also includes the following steps S501 to S503.

[0130] Step S501: Based on the historical read records of the target storage block, determine the reread success rate corresponding to each historical read voltage.

[0131] Specifically, in flash memory, the reread success rate is a key metric used to quantify the probability that data is correctly read at a given read voltage.

[0132] In this embodiment, historical read records of the target storage block are obtained. These historical read records include, but are not limited to, the number of rereads, the number of successful rereads, the read voltage used for each reread, and the read voltage used when a reread is successful, under different voltage conditions and during a certain period. Then, based on the historical read voltage, the reread success rate under the corresponding voltage condition is calculated, and weighted according to time decay, so that the reread records closer to the current period have a greater impact on the reread success rate. The reread success rate can be calculated as shown in expression (15).

[0133] (15)

[0134] in, Indicates voltage Lowering the success rate of rereading; Indicates a selected time period; express Voltage at any moment The number of times the next read was successfully executed; express Voltage at any moment Total number of down-reads; This indicates that the weighting is based on time decay.

[0135] Step S502: Determine the current read voltage for different data based on the current threshold voltage distribution of the target storage block.

[0136] Specifically, to read the current threshold voltage of the memory cell in the target memory block, a threshold voltage distribution model can be constructed using a Gaussian mixture distribution, and then the current read voltage can be determined based on different data states (such as the 16 voltage states in QLC).

[0137] In some embodiments, the threshold voltage distribution in step S502 is obtained based on steps S5021 to S5023.

[0138] Step S5021: In the storage unit of the target storage block, according to the historical read record of the target storage block, obtain the storage data of the storage unit, divide the storage units storing the same data into a group, and obtain at least one group of storage units.

[0139] Specifically, in the storage unit of the target storage block, if the data stored in the target storage unit is known, or if the data stored in the target storage unit is unknown, the data can be obtained through historical read records. Then, the storage units storing the same data are divided into a group to obtain at least one group of storage units.

[0140] Step S5022: Statistically analyze the sub-threshold voltage distribution of each group of memory cells.

[0141] Specifically, the sub-threshold voltage distribution of each group of memory cells can be statistically analyzed based on the Gaussian distribution. The calculation method for this sub-threshold voltage distribution is shown in expression (16).

[0142] (16)

[0143] in, Indicates the first Threshold voltage distribution of the group of memory cells; Indicates the number of storage units in the current group; Indicates the first The mean of the threshold voltage state distribution of the group of memory cells; Indicates the first The standard deviation of the threshold voltage distribution of the group of memory cells.

[0144] Step S5023: Determine the threshold voltage distribution based on the proportion of each group of storage cells in the target storage block and the distribution of each sub-threshold voltage.

[0145] Specifically, after calculating the threshold voltage distribution of each group of storage cells using the above method, a weighted calculation can be performed based on the proportion of each group of storage cells in the target storage block to obtain the threshold voltage distribution of the target storage block. The calculation method for the threshold voltage distribution can be as shown in expression (17).

[0146] (17)

[0147] Among them, regarding Please refer to the relevant description of the above expression (16), which will not be repeated here. This represents the threshold voltage distribution of the target memory block, i.e., the Gaussian mixture distribution of the threshold voltage. Indicates the total number of groups of storage units; Indicates the first The threshold voltage state distribution weights of each memory cell group.

[0148] In the above embodiments, storage cells with identical data are grouped together, and the threshold voltage distribution of the corresponding group is calculated using a Gaussian distribution. Then, based on the proportion of each group of storage cells in the target storage block, the threshold voltage distribution of the target storage block is determined using a Gaussian mixture distribution. This allows for accurate modeling of the threshold voltage distribution of the target storage block, reducing the computational complexity of analyzing each storage cell individually, and laying the foundation for subsequent calculation of the global read voltage.

[0149] In some embodiments, the current read voltage of different data is determined based on the current threshold voltage distribution of the target storage block, and the current read voltage of different data is also determined based on the overlapping area between sub-threshold voltage distributions and the number of storage cells corresponding to each threshold voltage in each sub-threshold voltage distribution.

[0150] Specifically, after obtaining the threshold voltage distribution of the target memory block through a Gaussian mixture distribution, for the sub-threshold voltage distributions of adjacent voltage states, the optimal read voltage for different voltage states can be determined based on the overlapping area between the sub-threshold voltage distributions and the number of memory cells corresponding to each distribution. The optimal read voltage is the read voltage with the lowest error rate under each voltage state. The optimal read voltage for each voltage state is located outside the overlapping area of ​​the sub-threshold voltage distributions.

[0151] In this embodiment, based on the ratio between the error bit rate and the total bit rate under different voltage conditions and the threshold voltage distribution of the target memory block, the maximum voltage value of each sub-threshold voltage distribution is determined. This maximum voltage value can be used as the optimal read voltage under the voltage condition corresponding to the sub-threshold voltage distribution. The calculation method of this optimal read voltage can be as shown in expression (18).

[0152] (18)

[0153] Among them, regarding Please refer to the relevant description of the above expression (17), which will not be repeated here. Indicates the first The optimal read voltage for a group of memory cells. Represents the information quality function, used for voltage The ratio of the error bit rate to the total number of bits during read operations.

[0154] In this embodiment, the above information quality function can be calculated as shown in expression (19).

[0155] (19)

[0156] Among them, regarding , , , Please refer to the relevant descriptions of expressions (16) and (18) above, which will not be repeated here. Indicates the first The mean of the threshold voltage state distribution of the group of memory cells; Indicates the first The standard deviation of the threshold voltage state distribution of the group of memory cells. Indicates voltage Next, the Group storage unit bit error rate; Indicates voltage Next, the Bit error rate of the group storage unit.

[0157] In the above embodiments, the optimal read voltage for each voltage state is calculated using the threshold voltage of the target storage block and the information quality function. This allows for the detection of voltage drift in the storage unit caused by various factors, enabling dynamic adjustment of the optimal read voltage. This ensures that the read strategy always matches the storage state of the storage unit, thereby guaranteeing a low read error rate throughout the storage unit's lifespan.

[0158] Step S503: Based on the reread success rate corresponding to each historical read voltage and the current read voltage of different data, determine the global read voltage of the target storage block. The global read voltage refers to the uniform voltage used when reading different data from the target storage block.

[0159] In theory, when reading data from a target memory block, different data have their own corresponding read voltages. This means that a read voltage switch is required when reading different data from the target memory block. Since voltage switching is time-consuming, a unified global read voltage can be determined. Based on this global read voltage, multiple different data can be read, thus reducing the voltage switching time. However, the global read voltage is not the optimal read voltage for each individual data; therefore, there is a time consumption for data error correction during data reading. Determining the global read voltage involves finding the read voltage with the shortest overall error correction time for multiple data. For example, if 2.5V is used as the read voltage, the error correction time for data 0000 is 0.2 seconds, for data 0001 it is 0.25 seconds, and for data 0010 it is 0.1 seconds, then the overall error correction time for data 0000, 0001, and 0010 is 0.55 seconds. When 2.8V is used as the read voltage, the error correction time for data 0000 is 0.15 seconds, for data 0001 it is 0.12 seconds, and for data 0010 it is 0.1 seconds. Therefore, the overall error correction time for data 0000, 0001, and 0010 is 0.37 seconds. Since the overall error correction time for 2.8V is relatively short, this overall error correction time can be used as the global read voltage, thereby improving data read efficiency.

[0160] In some embodiments, step S503 above further includes steps S5031 to S5032.

[0161] Step S5031: For any historical read voltage, determine the sum of the voltage differences between the historical read voltage and the current read voltage of each data.

[0162] Specifically, for any historical read voltage, the voltage difference between it and the current read voltage can be found. Summing these voltage differences gives the degree to which the historical read voltage deviates from the current read voltage. The smaller the difference, the better the historical read voltage can meet the reading needs of all data states, meaning the overall error correction time for multiple data is shorter.

[0163] Step S5032: Determine the global read voltage based on the sum of voltage differences and the reread success rate corresponding to each of the historical read voltages.

[0164] Specifically, in addition to the deviation between the historical read voltage and the current read voltage, the determination of the global read voltage also needs to take into account the reread success rate corresponding to the historical read voltage. By comprehensively considering the two factors, the global read voltage is finally determined.

[0165] In some embodiments, step S5032 further includes:

[0166] The third weight for obtaining the sum of voltage differences and the fourth weight for the reread success rate;

[0167] For any historical read voltage, the reread success rate and voltage difference corresponding to the historical read voltage are weighted and calculated based on the third and fourth weights to obtain the corresponding calculation result;

[0168] The historical reading voltage corresponding to the maximum calculated result is used as the global reading voltage.

[0169] Specifically, the calculation method for the global read voltage can be shown in expression (20).

[0170] (20)

[0171] Among them, regarding , For details, please refer to the relevant descriptions of expressions (15) and (17) above, which will not be repeated here. Indicates global voltage reading. , These represent the third and fourth weights, respectively. This indicates the degree of deviation between the historical reading voltage and the current reading voltage.

[0172] In this embodiment, the allocation of the third and fourth weights has different emphases for different scenarios. For example, for scenarios that require long-term stability (such as stable environments like cold storage in data centers), the proportion of the third weight needs to be greater than that of the fourth weight, and in extreme cases, it may even need to approach 1; for scenarios that require rapid response to voltage fluctuations and reduced read latency (such as high-temperature operating conditions similar to mobile devices). The value will be as small as possible, and in extreme cases it may even approach 0.

[0173] In the above embodiments, by comprehensively considering the deviation between historical and current read voltages and the reread success rate, a global read voltage is determined. This combines historical experience (i.e., reread success rate) and theoretical predictions (i.e., voltage deviation), resulting in a highly reliable global read voltage. Furthermore, by dynamically adjusting the third and fourth weights, the global read voltage can be determined in different scenarios, thereby reducing frequent reread operations caused by voltage drift during data reading.

[0174] The data error correction method provided in this embodiment includes historical reread success records containing information on the success or failure of reread operations under different voltage settings in the past. By analyzing these records, the most suitable voltage adjustment scheme for the current situation can be selected. The distribution of cell threshold voltage is directly related to the accuracy of data reading. Adjusting the voltage according to its distribution characteristics can make the reading operation more accurately match the actual state of the storage cell, thereby improving the success rate of reading, reducing reading errors caused by voltage incompatibility, and further improving the reliability and performance of the system.

[0175] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0176] Corresponding to the data error correction method, this application also provides a data error correction apparatus. (See also...) Figure 6 This is a schematic diagram of a data error correction device provided in some embodiments of this application. Figure 6 The data error correction device includes:

[0177] Data reading module 601 is used to acquire the status parameters of the target storage block in the storage system;

[0178] Error rate prediction module 602 is used to predict the error rate of a target storage block in a future target time period based on status parameters;

[0179] Error correction model confirmation module 603 is used to determine the target error correction model corresponding to the target storage block based at least on the error rate;

[0180] The parameter adjustment module 604 is used to correct data errors in the target storage block based on the target error correction model.

[0181] In some embodiments, the error rate prediction module 602 is used for:

[0182] The state parameters are input into the trained prediction model to obtain the error rate. The prediction model includes a neural network sub-model and a physical sub-model. The neural network sub-model is used to output the initial error rate of the target storage block in the future target time period based on the state parameters. The physical sub-model is used to correct the initial error rate based on the weights of each state parameter to obtain the error rate. The weights of the state parameters are used to characterize the degree of correlation between each state parameter and the error rate.

[0183] In some embodiments, the error rate prediction module 602 is further configured to:

[0184] Obtain a pre-trained first model and a second model to be trained, where the number of parameters in the first model is greater than the number of parameters in the second model;

[0185] The state parameter samples are input into the first model and the second model respectively to obtain the first output result of the first model and the second output result of the second model.

[0186] The second model is trained based on the labels of the first output, the second output, and the state parameter samples.

[0187] Once the second model has been trained, the parameters of the second model are pruned based on the weights of each parameter in the second model to obtain the prediction model.

[0188] In some embodiments, the error rate prediction module 602 is further configured to:

[0189] Obtain multiple initial state parameter samples of the target storage block;

[0190] Based on the correlation between each initial state parameter sample and the error rate, parameters with a correlation below a threshold are removed from the initial state parameter samples to obtain the state parameter samples.

[0191] In some embodiments, the error correction model verification module 603 includes:

[0192] The attribute parameter retrieval unit is used to retrieve the attribute parameters of the target storage block.

[0193] The error correction score calculation unit is used to determine the error correction score of the target storage block based on attribute parameters and error rate. The error correction score is used to characterize the severity of errors in the data in the target storage block.

[0194] The error correction model determination unit is used to determine the target error correction model based on the error correction score.

[0195] In some embodiments, based on attribute parameters and the error rate, an error correction score for the target storage block is determined, and the error correction score calculation unit is further configured to:

[0196] Obtain the error rate weight and the parameter weight of each attribute parameter. The error rate weight represents the degree of influence of the error rate on the error correction score, and the parameter weight represents the degree of influence of each attribute parameter on the error correction score.

[0197] Based on error rate weights and parameter weights, the error rate and various attribute parameters are weighted and fused to obtain the error correction score.

[0198] In some embodiments, a target error correction model is determined based on an error correction score, and the error correction model determination unit is further configured to:

[0199] Among the multiple preset error correction scoring intervals, the target error correction scoring interval in which the error correction score is located is determined. Each error correction scoring interval has its own associated error correction model, and at least some error correction scoring intervals are associated with different error correction models.

[0200] The error correction model that correlates the target error correction score interval is used as the target error correction model.

[0201] In some embodiments, the target storage block includes multiple storage cells, and the threshold voltage of the storage cell is used to characterize the data stored in the storage cell. Different data have their own corresponding threshold voltage ranges. When reading data from each storage cell according to different read voltages, the corresponding reread success rates are different. The data error correction method further includes:

[0202] The historical read record acquisition module is used to determine the reread success rate corresponding to each historical read voltage based on the historical read records of the target storage block.

[0203] The threshold voltage distribution acquisition module is used to determine the current read voltage of different data based on the current threshold voltage distribution of the target storage block.

[0204] The global read voltage acquisition module is used to determine the global read voltage of the target storage block based on the reread success rate corresponding to each historical read voltage and the current read voltage of different data. The global read voltage refers to the uniform voltage used when reading different data from the target storage block.

[0205] In some embodiments, the threshold voltage distribution acquisition module is further configured to:

[0206] In the storage unit of the target storage block, based on the historical read records of the target storage block, the stored data of the storage unit is obtained, and the storage units storing the same data are divided into a group to obtain at least one group of storage units;

[0207] Statistically analyze the sub-threshold voltage distribution of each group of memory cells;

[0208] The threshold voltage distribution is determined based on the proportion of each group of storage cells in the target storage block and the distribution of each sub-threshold voltage.

[0209] In some embodiments, the current read voltage of different data is determined based on the current threshold voltage distribution of the target storage block. The threshold voltage distribution acquisition module is also used for:

[0210] Based on the overlapping area between sub-threshold voltage distributions and the number of storage units corresponding to each threshold voltage in each sub-threshold voltage distribution, the current read voltage of different data is determined.

[0211] In some embodiments, the global read voltage of the target storage block is determined based on the reread success rate corresponding to each historical read voltage and the current read voltage of different data. The global read voltage acquisition module is further configured to:

[0212] For any given historical read voltage, determine the sum of the voltage differences between the historical read voltage and the current read voltage of each data point;

[0213] The global read voltage is determined based on the sum of voltage differences and the reread success rate corresponding to each historical read voltage.

[0214] In some embodiments, the global read voltage is determined based on the sum of voltage differences and the reread success rate corresponding to each historical read voltage. The global read voltage acquisition module is further configured to:

[0215] The third weight for obtaining the sum of voltage differences and the fourth weight for the reread success rate;

[0216] For any historical read voltage, the reread success rate and voltage difference corresponding to the historical read voltage are weighted and fused based on the third and fourth weights to obtain the corresponding calculation result;

[0217] The historical reading voltage corresponding to the maximum calculated result is used as the global reading voltage.

[0218] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0219] See also Figure 7 Embodiments of this application also provide an electronic device including a memory 10 and a processor 20, wherein the memory 10 stores a computer program and the processor 20 is configured to run the computer program to perform the steps in any of the above-described data error correction method embodiments.

[0220] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described data error correction method embodiments at runtime.

[0221] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0222] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described data error correction method embodiments.

[0223] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described data error correction method embodiments.

[0224] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0225] The foregoing has provided a detailed description of a data error correction method, apparatus, device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A data error correction method, characterized in that, The method includes: Obtain the status parameters of the target storage block in the storage system; Based on the state parameters, predict the error rate of the target storage block in a future target time period; Based at least on the error rate, a target error correction model corresponding to the target storage block is determined, wherein the error correction model includes one or more of error correction codes, enhanced error correction codes, Reed-Solomon codes, and low-density parity-check codes; Based on the target error correction model, data errors in the target storage block are corrected. The step of predicting the error rate of the target storage block in a future target time period based on the state parameters includes: The state parameters are input into the trained prediction model to predict the error rate of the target storage block in a future target time period. The prediction model includes a neural network sub-model and a physical sub-model. The neural network sub-model is used to output the initial error rate of the target storage block in the future target time period based on the state parameters. The physical sub-model is used to correct the initial error rate based on the weights of each state parameter to obtain the error rate. The weights of the state parameters are used to characterize the degree of correlation between each state parameter and the error rate.

2. The method according to claim 1, characterized in that, The prediction model was trained using the following method: Obtain a pre-trained first model and a second model to be trained, wherein the number of parameters in the first model is greater than the number of parameters in the second model; The state parameter samples are input into the first model and the second model respectively to obtain the first output result of the first model and the second output result of the second model. The second model is trained based on the first output result, the second output result, and the labels of the state parameter samples; Once the second model has been trained, the parameters of the second model are pruned based on the weights of each parameter in the second model to obtain the prediction model.

3. The method according to claim 2, characterized in that, The state parameter samples are determined based on the following method: Obtain multiple initial state parameter samples of the target storage block; Based on the correlation between each initial state parameter sample and the error rate, parameters with a correlation value lower than a threshold are removed from the initial state parameter samples to obtain the state parameter samples.

4. The method according to claim 1, characterized in that, The step of determining the target error correction model corresponding to the target storage block based at least on the error rate includes: Obtain the attribute parameters of the target storage block; Based on the attribute parameters and the error rate, an error correction score is determined for the target storage block, and the error correction score is used to characterize the severity of errors in the data in the target storage block; Based on the error correction score, the target error correction model is determined.

5. The method according to claim 4, characterized in that, The step of determining the error correction score of the target storage block based on the attribute parameters and the error rate includes: Obtain the error rate weight and the parameter weight of each attribute parameter, wherein the error rate weight represents the degree of influence of the error rate on the error correction score, and the parameter weight represents the degree of influence of each attribute parameter on the error correction score; Based on the error rate weight and the parameter weight, the error rate and each of the attribute parameters are weighted and fused to obtain the error correction score.

6. The method according to claim 4, characterized in that, The step of determining the target error correction model based on the error correction score includes: Among a plurality of preset error correction scoring intervals, a target error correction scoring interval in which the error correction score is located is determined, wherein each error correction scoring interval has its own associated error correction model, and at least some error correction scoring intervals are associated with different error correction models. The error correction model associated with the target error correction score interval is used as the target error correction model.

7. The method according to claim 1, characterized in that, The target storage block includes multiple storage cells. The threshold voltage of each storage cell characterizes the data stored within it. Different data types have their own corresponding threshold voltage ranges. When reading data from each storage cell using different read voltages, the corresponding reread success rates differ. The method further includes: Based on the historical read records of the target storage block, determine the reread success rate corresponding to each historical read voltage; Based on the current threshold voltage distribution of the target storage block, determine the current read voltage for different data. Based on the reread success rate corresponding to each historical read voltage and the current read voltage of different data, the global read voltage of the target storage block is determined. The global read voltage refers to the uniform voltage used when reading different data from the target storage block.

8. The method according to claim 7, characterized in that, The threshold voltage distribution was obtained statistically based on the following method: In the storage units of the target storage block, based on the historical read records of the target storage block, the storage units storing the same data are divided into a group to obtain at least one group of storage units; Statistically analyze the sub-threshold voltage distribution of each group of memory cells; The threshold voltage distribution is determined based on the proportion of each group of storage cells in the target storage block and the distribution of each sub-threshold voltage.

9. The method according to claim 8, characterized in that, The step of determining the current read voltage for different data based on the current threshold voltage distribution of the target storage block includes: Based on the overlapping area between sub-threshold voltage distributions and the number of storage units corresponding to each threshold voltage in each sub-threshold voltage distribution, the current read voltage of different data is determined.

10. The method according to claim 8, characterized in that, The process of determining the global read voltage of the target storage block based on the reread success rate corresponding to each historical read voltage and the current read voltage of different data includes: For any of the historical read voltages, determine the sum of the voltage differences between the historical read voltage and the current read voltage of each data. The global read voltage is determined based on the sum of the voltage differences and the reread success rate corresponding to each of the historical read voltages.

11. The method according to claim 10, characterized in that, The determination of the global read voltage based on the sum of the voltage differences and the reread success rate corresponding to each of the historical read voltages includes: The third weight for obtaining the sum of voltage differences and the fourth weight for the reread success rate; For any of the historical read voltages, based on the third weight and the fourth weight, a weighted fusion calculation is performed on the sum of the reread success rate and the voltage difference corresponding to the historical read voltage to obtain the corresponding calculation result; The historical reading voltage corresponding to the maximum calculated result is taken as the global reading voltage.

12. A data error correction device, characterized in that, The device includes: The data reading module is used to obtain the status parameters of the target storage block in the storage system; An error rate prediction module is used to predict the error rate of the target storage block in a future target time period based on the state parameters. Specifically, the state parameters are input into a trained prediction model to predict the error rate of the target storage block in the future target time period. The prediction model includes a neural network sub-model and a physical sub-model. The neural network sub-model is used to output the initial error rate of the target storage block in the future target time period based on the state parameters. The physical sub-model is used to correct the initial error rate based on the weights of each state parameter to obtain the error rate. The weights of the state parameters are used to characterize the degree of correlation between each state parameter and the error rate. The error correction model confirmation module is used to determine the target error correction model corresponding to the target storage block based at least on the error rate, wherein the error correction model includes one or more of error correction codes, enhanced error correction codes, Reed-Solomon codes, and low-density parity-check codes. The parameter adjustment module is used to correct data errors in the target storage block based on the target error correction model.

13. An electronic device, characterized in that, include: Memory: Used to store computer programs; A processor for executing the computer program to implement the steps of the data error correction method as described in any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the data error correction method as described in any one of claims 1 to 11.

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