Chip temperature determination method, chip temperature control method and electronic equipment

Abstract

The invention discloses a chip temperature determining method, a chip temperature control method and electronic equipment, and relates to the field of information processing.The chip temperature determining method, the chip temperature control method and the electronic equipment are included, and a target chip comprises at least one execution unit. The chip temperature determination method comprises the steps of obtaining first detection temperatures detected by at least two temperature sensors, wherein the at least two temperature sensors are used for detecting temperatures of at least two detection positions of a target chip; obtaining the actual power consumption of each execution unit in the target chip and the evaluation power consumption of the external structure; determining the target temperature of the target chip according to the coupling thermal resistance characteristic parameter of the target chip, the first detection temperature, the actual power consumption of each execution unit and the evaluated power consumption of the external structure; the coupling thermal resistance characteristic parameter represents thermal coupling information of each execution unit and the external structure at each target position, and the target position comprises the at least two detection positions and the position corresponding to the target temperature.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of information processing, and in particular to a chip temperature determination method, a chip temperature control method and an electronic device. BACKGROUND

[0002] With the increasing demand for mobile electronic devices, the requirements for thinness and integration of chips in mobile electronic devices are increasingly high, and the power consumption and power density of chips in mobile devices are also increasingly high, but the thermal risk and thermal problems of chips are increasingly serious. Precise and effective control of chip temperature is an important means to affect chip heat and performance. Excessive temperature control will inhibit chip performance, and loose temperature control will increase the thermal risk of the chip.

[0003] In order to realize the temperature control of the chip, a temperature sensor is arranged on the chip, and the temperature fed back by the temperature sensor is used as a control quantity.

[0004] However, the temperature sensor is not accurately positioned, so that the temperature detected by the temperature sensor is not the highest temperature of the chip, resulting in a certain error between the control quantity and the actual highest temperature of the chip, thereby affecting the effectiveness of the chip temperature control. SUMMARY

[0005] The first aspect of the present application provides a chip temperature determination method, the target chip contains at least one execution unit, comprising:

[0006] Obtaining a first detection temperature detected by at least two temperature sensors, the at least two temperature sensors are used to detect the temperature of at least two detection positions of the target chip;

[0007] Obtaining the actual power consumption of each execution unit in the target chip and the estimated power consumption of the external structure;

[0008] According to the coupling thermal resistance characteristic parameter of the target chip, the first detection temperature, the actual power consumption of each execution unit and the estimated power consumption of the external structure, the target temperature of the target chip is determined; the coupling thermal resistance characteristic parameter represents the thermal coupling information of each execution unit and the external structure at each target position, and the target position includes the at least two detection positions and the target temperature corresponding position.

[0009] In a possible implementation, the coupling thermal resistance characteristic parameter of the target chip includes a coupling thermal resistance matrix, and each element in the matrix represents the coupling thermal resistance of each execution unit and the external structure at each target position. The forming method of the coupling thermal resistance matrix comprises:

[0010] Obtaining at least two groups of power consumptions, each group of power consumptions including the power consumption of each execution unit in the target chip and the power consumption of the corresponding external structure;

[0011] Simulate, by using a thermal simulation model, the at least two groups of power consumptions to obtain at least two groups of simulation temperatures, each group of simulation temperatures including a preset number of simulation temperatures, the preset number being the number of temperature sensors plus 1, and the preset number of simulation temperatures including simulation values of temperatures detected by the at least two temperature sensors and a first simulation temperature of the target chip, the first simulation temperature matching the target temperature;

[0012] Determine the coupling thermal resistance characteristic parameter according to the at least two groups of power consumptions and the at least two groups of simulation temperatures.

[0013] In a possible implementation, the thermal simulation model is obtained by performing first calibration on an initial thermal simulation model, and the first calibration process includes:

[0014] In turn, in a process of controlling the target chip to run by using any one of the at least two power consumption distributions, obtain second detection temperatures detected by the at least two temperature sensors; in different power consumption distributions, power consumptions of each execution unit in the target chip are different;

[0015] For each power consumption distribution, determine a corresponding relationship between power consumption and detection temperature of the target chip according to the second detection temperatures detected by the at least two temperature sensors;

[0016] Calibrate the thermal simulation model by using the corresponding relationship.

[0017] In a possible implementation, the determining the target temperature of the target chip according to the coupling thermal resistance matrix, the first detection temperature, and the power consumptions of the execution units includes:

[0018] Obtain a first power consumption matrix according to actual power consumptions of the execution units and an evaluation power consumption of the external structure;

[0019] Determine the target temperature of the target chip according to a first temperature matrix, the first power consumption matrix, and the coupling thermal resistance matrix, the first temperature matrix including the first detection temperatures detected by the at least two temperature sensors.

[0020] In a possible implementation, the evaluation power consumption of the external structure is obtained by second calibration, and the second calibration process includes:

[0021] Obtain a preset sub-matrix in the coupling thermal resistance matrix, elements in the preset sub-matrix representing coupling thermal resistances of the external structure at target positions;

[0022] Obtain a temperature offset matrix;

[0023] Determine the evaluation power consumption of the external structure based on the preset sub-matrix and the temperature offset matrix.

[0024] In a possible implementation, the method for forming the temperature offset matrix comprises the following steps.

[0025] According to actual power consumptions of each execution unit in the target chip and the evaluation power consumption of the external structure being zero, a second power consumption matrix is obtained.

[0026] According to the second power consumption matrix, a second temperature matrix is obtained, wherein each element in the second temperature matrix represents a third detection temperature of a corresponding detection position of each temperature sensor when the evaluation power consumption of the external structure is zero.

[0027] Based on the first temperature matrix and the second temperature matrix, a temperature offset matrix is obtained, wherein each element in the temperature offset matrix represents a deviation between the first detection temperature measured by each sensor and the third detection temperature, and a deviation between the target temperature and the temperature of the corresponding position.

[0028] In a possible implementation, the method for determining the evaluation power consumption of the external structure based on the preset sub-matrix and the temperature offset matrix comprises the following steps.

[0029] Based on the correspondence between the preset sub-matrix, the evaluation power consumption of the external structure and the preset temperature offset matrix, the evaluation power consumption of the external structure is fitted.

[0030] The second aspect of the present application provides a chip temperature control method, comprising the following steps.

[0031] Obtaining detection temperatures detected by at least two temperature sensors, wherein the at least two temperature sensors are used to detect temperatures of at least two detection positions of the target chip.

[0032] Obtaining actual power consumptions of each execution unit in the target chip.

[0033] According to a coupling thermal resistance characteristic parameter of the target chip, the detection temperatures and the power consumptions of each execution unit, a target temperature of the target chip is determined, wherein the coupling thermal resistance characteristic parameter represents thermal coupling information of each execution unit and the external structure at each target position, and the target position includes the at least two detection positions and a position corresponding to the target temperature.

[0034] Based on the target temperature of the target chip, a running state of the target chip is controlled.

[0035] In a possible implementation, the method for controlling the running state of the target chip based on the target temperature of the target chip comprises the following steps.

[0036] Based on the target temperature satisfying a preset control condition, a control strategy is called, wherein the control strategy is used to adjust the running state of the target chip.

[0037] The third aspect of the present application provides an electronic device, comprising:

[0038] a target chip, the target chip comprising at least one execution unit;

[0039] an external structure;

[0040] at least two temperature sensors configured to detect temperatures at at least two detection positions on the target chip;

[0041] a processor configured to obtain first detection temperatures detected by the at least two temperature sensors, obtain power consumptions of the execution units in the target chip, and determine a target temperature of the target chip based on a coupling thermal resistance matrix, the first detection temperatures, and the power consumptions of the execution units, the coupling thermal resistance matrix representing thermal coupling information of the execution units and the external structure at target positions, the target positions comprising the at least two detection positions and a position corresponding to the target temperature.

[0042] The fourth aspect of the present application provides a computer program product, comprising computer readable instructions, when the computer readable instructions are executed on an electronic device, the electronic device is caused to implement the chip temperature determination method of the first aspect or any implementation manner of the first aspect, or the electronic device is caused to implement the chip temperature control method of the second aspect or any implementation manner of the second aspect.

[0043] The fifth aspect of the present application provides an electronic device, comprising at least one processor and a memory connected to the processor, wherein:

[0044] the memory is configured to store a computer program;

[0045] the processor is configured to execute the computer program, so that the electronic device is capable of implementing the chip temperature determination method of the first aspect or any implementation manner of the first aspect, or the electronic device is caused to implement the chip temperature control method of the second aspect or any implementation manner of the second aspect.

[0046] The sixth aspect of the present application provides a computer storage medium, the storage medium carrying one or more computer programs, when the one or more computer programs are executed by an electronic device, the electronic device is caused to implement the chip temperature determination method of the first aspect or any implementation manner of the first aspect, or the electronic device is caused to implement the chip temperature control method of the second aspect or any implementation manner of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0047] The above and other features, advantages, and aspects of embodiments of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: like reference numerals refer to like elements throughout. It should be understood that the drawings are schematic and elements in the drawings are not necessarily to scale.

[0048] Figure 1 is a flowchart of a chip temperature determination method provided by an embodiment of the present application;

[0049] Figure 2 is a structural diagram of a target chip provided by an embodiment of the present application;

[0050] Figure 3 is a flowchart of a forming method of a coupling thermal resistance matrix provided by an embodiment of the present application;

[0051] Figure 4 is a flowchart of a process of performing a first calibration on an initial thermal simulation model to obtain a thermal simulation model provided by an embodiment of the present application;

[0052] Figure 5 is a flowchart of a process of determining a target temperature of a target chip according to a coupling thermal resistance matrix, a first detection temperature, actual power consumptions of each execution unit, and an evaluation power consumption of an external structure provided by an embodiment of the present application;

[0053] Figure 6 is a flowchart of a process of obtaining an evaluation power consumption of an external structure through a second calibration provided by an embodiment of the present application;

[0054] Figure 7 is a flowchart of a process of forming a temperature offset matrix provided by an embodiment of the present application;

[0055] Figure 8 is a flowchart of a chip temperature control method provided by an embodiment of the present application;

[0056] Figure 9 is a structural diagram of an electronic device provided by an embodiment of the present application;

[0057] Figure 10 is a hardware structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0058] The embodiments of the present application are described below in conjunction with the accompanying drawings. The terms used in the embodiment part of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0059] The embodiments of the present application are described below in conjunction with the accompanying drawings. It is known to those of ordinary skill in the art that, as technology develops and new scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0060] The terms "first", "second", and the like in the description and in the claims of the present application and above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the terms used in this way can be interchanged, as appropriate, and are merely used in the description of the embodiments of the present application to distinguish between objects of the same attribute when describing. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product or apparatus including a series of units does not have to be limited to those units, but can include other units not clearly listed or inherent to the process, method, product or apparatus.

[0061] Referring to Figure 1 , Figure 1 is a flowchart of a chip temperature determination method provided by an embodiment of the present application, as shown in Figure 1 A chip temperature determination method provided by an embodiment of the present application can include steps 101 to 103, which will be described in detail below.

[0062] 101, obtaining a first detection temperature detected by at least two temperature sensors for detecting the temperature of at least two detection positions of a target chip;

[0063] The temperature sensors are arranged at at least two detection positions on the chip, and the temperature detected by the temperature sensors at the corresponding detection position. Among the at least two temperatures detected, there can be the highest temperature of the chip, or there can not be the highest temperature of the chip.

[0064] The target chip can be a multi-core structure, which includes a plurality of execution units, each execution unit can execute a task alone or cooperatively, and the specific function of each execution unit of the target chip is not limited in the present application.

[0065] As an example, the target chip can be a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Processing Unit), SOC (System on Chip), etc. structure, and the specific form of the target chip is not limited in the present application.

[0066] If the target chip is a multi-core structure such as CPU, GPU and NPU, the execution unit can be a core in the processor.

[0067] If the target chip is an SOC chip, the SOC chip integrates multiple functional units such as CPUs, GPUs, NPUs, and the like, and each execution unit can be each functional unit, and each execution unit generates power consumption during operation.

[0068] Figure 2 FIG. 1 is a structural schematic diagram of a target chip provided by an embodiment of the present application. In the schematic diagram, the target chip includes four execution units 201, and the four execution units are arranged in sequence, and each execution unit can perform data transmission through a bus 202.

[0069] It should be noted that the Figure 2 This is only used to schematically show the structure of the target chip, and in specific implementation, the number of execution units included in the target chip, the arrangement manner of the execution units, and the structure used for data transmission are not limited thereto, and can be set according to actual conditions.

[0070] 102, obtaining actual power consumption of each execution unit in the target chip and evaluation power consumption of an external structure;

[0071] The external structure is arranged in the same electronic device as the target chip, and the external structure is a structure in an environment of the target chip, which can affect the temperature of the target chip.

[0072] The execution units in the target chip generate heat during operation, and the external structure also generates heat during operation, and both of them can affect the temperature of the target structure. The heat generated by the target chip during operation is related to the actual power consumption thereof, and the greater the power consumption, the greater the heat generated, which can cause the temperature of the target chip to increase more. The external structure generates more heat during operation, which causes the temperature of the temperature environment in which the target chip is located to increase, which can affect the heat dissipation of the target chip and can exacerbate the temperature increase of the target chip. If the external structure generates little heat or does not operate, it does not cause the temperature of the temperature environment in which the target chip is located to increase; if the function of the external structure is to reduce the temperature, the operation thereof can cause the temperature around the target chip to decrease, and the operation of the external structure can improve the heat dissipation effect of the target chip.

[0073] Therefore, the target temperature of the target chip can be determined in combination with the actual power consumption of each execution unit in the target chip and the evaluation power consumption of the external structure.

[0074] The actual power consumption of the execution unit can be obtained by reading the operation log of the target chip, and can be obtained by intercepting operation information through an interface of an operating system, and the present application does not limit the obtaining manner of the actual power consumption of each execution unit.

[0075] The external structure can include multiple structures in the electronic device, each structure has different distances from the target chip, and different heat dissipation conditions caused by the actual power consumption of each structure, so the power consumption of the temperature influence of the target chip by each structure cannot directly use the actual power consumption, therefore, in the present application, the power consumption of the temperature influence of the target chip by the external structure is evaluated, and the evaluation power consumption can be obtained through a set evaluation process.

[0076] As an example, when the target chip is a CPU independently arranged, the external structure is a structure in the external environment of the CPU in the electronic device, which can be a heat source that can affect the CPU.

[0077] As an example, when the target chip is a CPU arranged in a SOC, the external structure can be other subsystems in the SOC, such as GPU, etc.

[0078] As an example, when the target chip is a SOC, the external structure can be a structure in the external environment of the SOC in the electronic device, which can be a heat source that can affect the SOC.

[0079] 103、According to the coupling thermal resistance characteristic parameter of the target chip, the first detection temperature, the actual power consumption of each execution unit and the evaluation power consumption of the external structure, the target temperature of the target chip is determined; the coupling thermal resistance characteristic parameter represents the thermal coupling information of each execution unit and the external structure at each target position, and the target position includes at least two detection positions and a target temperature corresponding position.

[0080] There is a thermal resistance model in the field of heat dissipation, which can reflect the relationship between temperature, thermal resistance and heat generation. The thermal resistance model can be represented by the following formula:

[0081] T=R×P (1)

[0082] Where T represents temperature, R represents thermal resistance, and P represents heat generation (heat consumption).

[0083] Since the target chip has multiple execution units that can act as heat sources, and the external structure can also act as a heat source, and the temperature of multiple detection positions can be measured on the target chip, each heat source has a thermal coupling relationship, and the coupling thermal resistance of each heat source can be determined. The coupling thermal resistance characteristic parameter can be the coupling thermal resistance value of each heat source.

[0084] The heat source described above can include a positive heat source and a negative heat source. The positive heat source can be a heat source that has a positive effect on the temperature rise of the target chip, and the negative heat source is a heat source that has a negative effect on the temperature rise of the target chip.

[0085] The target temperature of the target chip can be the highest temperature of the chip or the lowest temperature of the chip, and the type of the target temperature can be set according to actual conditions, which is not limited in the present application.

[0086] The coupling thermal resistance characteristic parameter includes thermal coupling information of each execution unit and external structure as a heat source at each target position on the target chip, and the thermal coupling information represents information that the corresponding structure (the execution unit or the external structure) can affect the temperature of the target position.

[0087] In a possible implementation, a first detection temperature of each execution unit in the target chip is composed into a multi-dimensional matrix, and a target temperature with an unknown value is added to the matrix to obtain a temperature matrix; thermal coupling information of each execution unit and external structure at each target position is composed into a multi-dimensional matrix to obtain a thermal resistance matrix, and actual power consumption of each execution unit and estimated power consumption of the external structure are composed into a multi-dimensional matrix to obtain a heat generation matrix. The temperature matrix, the thermal resistance matrix, and the heat generation matrix can be substituted into the formula (1), and the value of the target temperature can be obtained through calculation.

[0088] The power consumption / actual power consumption of each execution unit and the power consumption / estimated power consumption of the external structure in the present application can represent the heat generation.

[0089] In the embodiment, the target chip includes at least one execution unit, and the chip temperature determination method includes: obtaining a first detection temperature detected by at least two temperature sensors, the at least two temperature sensors being used to detect temperatures of at least two detection positions of the target chip; obtaining actual power consumption of each execution unit in the target chip and estimated power consumption of the external structure; determining a target temperature of the target chip according to a coupling thermal resistance characteristic parameter of the target chip, the first detection temperature, the actual power consumption of each execution unit, and the estimated power consumption of the external structure; and the coupling thermal resistance characteristic parameter represents thermal coupling information of each execution unit and external structure at each target position, and the target position includes at least two detection positions and a position corresponding to the target temperature. The first detection temperature detected by the multiple detection positions on the target chip, the actual power consumption of the multiple execution units in the target chip as a heat source, the estimated power consumption of the external structure outside the target chip as a heat source, and the coupling thermal resistance characteristic parameter of the target chip can be used to calculate the target temperature of the target chip. The highest temperature of the target chip can be obtained through analysis and calculation, which can provide an accurate basis for temperature control of the target chip and improve the effectiveness of temperature control. In the present solution, the thermal coupling relationship between each execution unit and the external structure in the target chip as a heat source is considered. Compared with the temperature detected by the sensor, the highest temperature determined in the present solution is more accurate when the target temperature is the highest temperature, and the effect of subsequent temperature control using the highest temperature is better.

[0090] In a possible implementation, the coupling thermal resistance characteristic parameter of the target chip includes a coupling thermal resistance matrix, and each element in the matrix represents the coupling thermal resistance of each execution unit and external structure at each target position.

[0091] The thermal coupling information of each execution unit and external structure for the plurality of target positions on the target chip is determined in sequence, and the thermal coupling information can be coupling thermal resistance.

[0092] Figure 3 FIG. 1 is a flowchart of a method for forming a coupling thermal resistance matrix according to an embodiment of the present application, which can include steps 201 to 303, which are described in detail as follows.

[0093] 301. Obtain at least two groups of power consumptions, each group of power consumptions including the power consumptions of each execution unit in the target chip and the power consumptions of the corresponding external structure;

[0094] One group of power consumptions corresponds to one application scenario of the target chip, and one group or multiple groups of power consumptions can be set in the same application scenario.

[0095] The power consumptions included in one group of power consumptions are the power consumptions of each execution unit in the target chip and the power consumptions of the external structure in the corresponding application scenario.

[0096] The at least two groups of power consumptions can be obtained by collecting different application scenarios during the operation of the same type of device, and recording the application scenarios and the corresponding groups of power consumptions.

[0097] In a possible implementation, multiple groups of power consumptions can be obtained for the same application scenario, and the multiple groups of power consumptions can be averaged or subjected to variance calculation to obtain one group of power consumptions that can represent the application scenario, so as to reduce the input data in the subsequent simulation process.

[0098] 302. Simulate the at least two groups of power consumptions by using a thermal simulation model to obtain at least two groups of simulation temperatures corresponding to the at least two groups of power consumptions, each group of simulation temperatures including a preset number of simulation temperatures, the preset number being the number of temperature sensors plus 1, and the preset number of simulation temperatures including simulation values of temperatures detected by at least two temperature sensors and a first simulation temperature of the target chip, the first simulation temperature matching the target temperature.

[0099] In order to make the thermal simulation model compatible with multiple application scenarios, as many groups of power consumptions as possible corresponding to different application scenarios can be used to obtain one group of simulation temperatures corresponding to different application scenarios by using the power consumptions in the different scenarios.

[0100] The thermal simulation model is used to simulate the multiple sets of power consumptions to obtain a set of simulation temperatures corresponding to each set of power consumptions. The simulation temperatures include simulation values of temperatures corresponding to the temperature sensors. Moreover, the thermal simulation model is also capable of simulating a preset type of temperature of the target chip, and when simulating each set of power consumptions, a first simulation temperature of the target chip is also obtained.

[0101] In a possible implementation, a condition corresponding to the target temperature can be set in the thermal simulation model.

[0102] For example, a condition of outputting the highest temperature can be set in the thermal simulation model, and accordingly, the thermal simulation model is capable of simulating the highest temperature of the target model; a condition of outputting the lowest temperature can be set in the thermal simulation model, and accordingly, the thermal simulation model is capable of simulating the lowest temperature of the target model.

[0103] As an example, M temperature sensors are set on the target chip, where M is an integer greater than 1, and each set of simulation temperatures obtained by simulation in the thermal simulation model includes M+1 temperatures, of which M temperatures are simulation temperatures of the temperature sensors, and the remaining one temperature is the first simulation temperature of the target chip.

[0104] The simulation temperatures of the temperature sensors corresponding to different sets of power consumptions are different.

[0105] The first simulation temperature of the target chip is a temperature of the same type as the target temperature.

[0106] For example, the first simulation temperature and the target temperature are both the highest temperature of the target chip; for another example, the first simulation temperature and the target temperature are both the lowest temperature of the target chip.

[0107] 303. Determine the coupling thermal resistance characteristic parameter according to at least two sets of power consumptions and corresponding at least two sets of simulation temperatures.

[0108] The coupling thermal resistance characteristic parameter corresponding to each set of power consumptions can be obtained by using the aforementioned formula (1) and the at least two sets of power consumptions and corresponding at least two sets of simulation temperatures.

[0109] In a possible implementation, each set of power consumptions is grouped into a power consumption matrix, corresponding to P in the aforementioned formula (1), each set of simulation temperatures is grouped into a temperature matrix, corresponding to T in the aforementioned formula (1), and the power consumption matrix and the temperature matrix are calculated by using the aforementioned formula (1) to obtain the coupling thermal resistance characteristic parameter.

[0110] In a possible implementation, since the number of each execution unit is determined and the external structure is fixed, the coupling thermal resistance characteristic parameters corresponding to each set of power consumptions are processed by using the least square method to obtain a coupling thermal resistance matrix, and each element in the matrix represents the coupling thermal resistance of each execution unit and the external structure at each target position.

[0111] In this embodiment, at least two groups of power consumptions are obtained, each group of power consumptions including power consumptions of each execution unit in the target chip and power consumptions of corresponding external structures; a thermal simulation model is used to simulate the at least two groups of power consumptions to obtain corresponding at least two groups of simulation temperatures, each group of simulation temperatures containing a preset number of simulation temperatures, the preset number being the number of temperature sensors plus 1, and the preset number of simulation temperatures including simulation values of temperatures detected by the at least two temperature sensors and a first simulation temperature of the target chip, which matches the target temperature; the coupling thermal resistance characteristic parameter is determined according to the at least two groups of power consumptions and the corresponding at least two groups of simulation temperatures. The power consumptions of each execution unit and the power consumptions of external structures in different scenarios are simulated to obtain the simulation values of temperatures of each temperature sensor in each scenario and the first simulation temperature matching the target temperature, and then the simulation values of temperatures and the power consumptions in different scenarios are used for calculation and processing to obtain the coupling thermal resistance characteristic parameter of the target chip, thereby realizing quantitative calculation of the coupling thermal resistance matrix of the target chip and providing a basis for subsequent determination of the target temperature of the target chip.

[0112] In a possible implementation, the thermal simulation model is obtained by first calibrating an initial thermal simulation model.

[0113] Figure 4 is a flowchart of a process of first calibrating an initial thermal simulation model to obtain a thermal simulation model provided by the embodiments of the present application, which can include steps 401 to 403, which will be described in detail below.

[0114] 401. In the process of controlling the target chip to run by using any one of the at least two power consumption distributions in turn, second detection temperatures detected by the at least two temperature sensors are obtained; the power consumptions of each execution unit in the target chip are different under different power consumption distributions;

[0115] Under the same power consumption distribution, the power consumptions of each execution unit in the target chip are different, the heat generated by each execution unit is different, and the temperatures at different positions of the target chip are different.

[0116] If the power consumptions of the same execution unit in the target chip are different under different power consumption distributions of the target chip, this will cause the temperatures at the same position of the target chip to be different.

[0117] Under various power consumption distributions, the total power consumption of the target chip can be the same or different, which is not limited in the present application.

[0118] In order to accurately understand the temperatures and power consumptions of the target chip during the running process, temperature detection needs to be performed on each detection position in the target chip under various power consumption distributions to obtain the second detection temperature.

[0119] The target chip on temperature sensor is fixed in position, which can be temperature detection of several fixed detection positions, to obtain the second detection temperature of each detection position under various power consumption distribution.

[0120] As an example, the target chip contains 4 execution units, in one power consumption distribution, the power consumption of the 4 execution units is 4W (watt), 2W, 1.8W and 5W, in another power consumption distribution, the power consumption of the 4 execution units is 0.2W, 5W, 3W and 4W.

[0121] 402、For each power consumption distribution, determine the corresponding relationship between the power consumption and the detection temperature of the target chip according to the second detection temperature detected by the at least two temperature sensors;

[0122] The target chip runs in each power consumption distribution, and the temperature sensor at each detection position on the target chip detects the second detection temperature.

[0123] When each execution unit on the target chip runs at the power consumption corresponding to the power consumption distribution, the heat dissipation causes the target chip to heat up, and the temperature of the plurality of detection positions is the second detection temperature, which represents the temperature of the target chip when each execution unit on the target chip runs at the power consumption corresponding to the power consumption distribution.

[0124] In one possible implementation, the target chip can be controlled to run at different total power consumption, the power consumption of each execution unit of the target chip is obtained, and each temperature sensor detects the second detection temperature, thereby realizing the obtaining of a plurality of power consumption distributions and corresponding second detection temperatures.

[0125] The corresponding relationship between the power consumption and the detection temperature of the target chip can be established according to each power consumption distribution and the corresponding second detection temperature.

[0126] In one possible implementation, a temperature response curve corresponding to each power consumption distribution can be constructed to obtain a plurality of power-temperature response curves.

[0127] 403、Calibrate the thermal simulation model using the corresponding relationship.

[0128] The thermal simulation model has established a correlation between temperature and power consumption, and the corresponding temperature can be simulated using the input power consumption. However, the thermal simulation model may not match the target chip in the present application, and therefore needs to be corrected.

[0129] The corresponding relationship determined in the foregoing step is the corresponding relationship between the power consumption and the temperature of the target chip, and therefore the thermal simulation model can be calibrated using the foregoing corresponding relationship.

[0130] In a possible implementation, a corresponding relationship between the power consumption of the target chip and the detected temperature is utilized, a set of power consumptions and a corresponding set of detected temperatures are selected, a thermal simulation model can be input with the set of power consumptions, and a simulation temperature output by the thermal simulation model is compared with the detected temperature to determine a difference therebetween. The difference is utilized to adjust parameters in the thermal simulation model until the simulation temperature output by the thermal simulation model is consistent with the detected temperature, and a calibration process is completed.

[0131] In this embodiment, the second detected temperatures detected by the at least two temperature sensors are obtained in a process in which the target chip is controlled to operate by using any one of the at least two power consumption distributions; the power consumptions of the execution units in the target chip are different under different power consumption distributions; for each power consumption distribution, a corresponding relationship between the power consumption of the target chip and the detected temperature is determined according to the second detected temperatures detected by the at least two temperature sensors; and the thermal simulation model is calibrated by using the corresponding relationship. The corresponding second detected temperatures on the target chip can be determined for different power consumption distributions, and the thermal simulation model is calibrated by using the corresponding relationship between the different power consumption distributions and the second detected temperatures, so that the calibration for the thermal simulation model is implemented, and a basis is provided for subsequent simulation of the operation of the target chip under various power consumptions.

[0132] Figure 5 FIG. 1 is a flowchart of a process for determining a target temperature of a target chip according to a coupling thermal resistance matrix, a first detected temperature, actual power consumptions of execution units, and an evaluation power consumption of an external structure, which can include steps 501 and 502, which are described below in detail.

[0133] 501. Obtain a first power consumption matrix according to the actual power consumptions of the execution units and the evaluation power consumption of the external structure.

[0134] The actual power consumptions of the execution units and the evaluation power consumption of the external structure are combined to obtain the first power consumption matrix.

[0135] As an example, the number of execution units is N (N is an integer greater than 1), and the elements in the first power consumption matrix can include P core1 , P core2 , …, P coreN , and P other . Wherein, P core1 represents the actual power consumption of the execution unit 1, P core2 represents the actual power consumption of the execution unit 2, and so on, P coreN represents the actual power consumption of the execution unit N, and P other represents the evaluation power consumption of the external structure.

[0136] 502、determining a target temperature of the target chip according to the first temperature matrix, the first power consumption matrix and the coupling thermal resistance matrix, the first temperature matrix comprising first detection temperatures detected by the at least two temperature sensors.

[0137] The first temperature matrix is a matrix composed of first detection temperatures detected by the temperature sensors.

[0138] As an example, the target chip is provided with M (M is an integer greater than 1) temperature sensors, then the elements in the first temperature matrix can comprise T m1 , T m2 , …, T mM . Wherein, T m1 represents the first detection temperature detected by the first temperature sensor, T m2 represents the first detection temperature detected by the second temperature sensor, and so on, T mM represents the first detection temperature detected by the Mth temperature sensor.

[0139] By using the foregoing formula (1), the coupling thermal resistance matrix is replaced by R, the first power consumption matrix is replaced by P, and the matrix composed of the first temperature matrix and the to-be-determined target temperature is replaced by T, according to which, the foregoing formula (1) can be extended to the following formula:

[0140] (2)

[0141] Wherein, M represents the number of temperature sensors provided in the target chip; N represents the number of execution units in the target chip; T represents temperature, T m1 ~T mM represents detection temperatures detected by the M temperature sensors, T target represents the target temperature; R represents coupling thermal resistance, R 1,1 represents the coupling thermal resistance of the execution unit 1 at the detection position 1, R 1,N represents the coupling thermal resistance of the execution unit N at the detection position 1, R 1,N+1 represents the coupling thermal resistance of the external structure at the detection position 1, R M,1 represents the coupling thermal resistance of the execution unit 1 at the detection position M, R M,N represents the coupling thermal resistance of the execution unit N at the detection position M, R M,N+1 represents the coupling thermal resistance of the external structure at the detection position M, R M+1,1 represents the coupling thermal resistance of the external structure at the position corresponding to the target temperature, R M+1,N represents the coupling thermal resistance of the execution unit N at the position corresponding to the target temperature, R M+1,N+1 represents the coupling thermal resistance of the external structure at the position corresponding to the target temperature; P represents power consumption, P core1 represents the actual power consumption of the execution unit 1, Pcore2 P represents the actual power consumption of execution unit 2. coreN P represents the actual power consumption of execution unit N. other This indicates the power consumption of the external structure.

[0142] Since the characteristic parameters of each coupling thermal resistance are known, the actual power consumption of each execution unit and the evaluation power consumption of the external structure are known, and the first detection temperature of each detection position of the target chip detected by each temperature sensor is known, the T can be calculated using Formula 2. target This enabled the determination of the target temperature.

[0143] In this embodiment, a first power consumption matrix is ​​obtained based on the actual power consumption of each execution unit and the evaluated power consumption of the external structure. The target temperature of the target chip is determined based on the first temperature matrix, the first power consumption matrix, and the coupling thermal resistance matrix. The first temperature matrix includes the first detected temperatures obtained by at least two temperature sensors. Using the thermal resistance model, and employing the first power consumption matrix composed of the actual power consumption of each execution unit and the evaluated power consumption of the external structure, the coupling thermal resistance matrix, and the first temperature matrix composed of the first detected temperatures obtained by two temperature sensors, the target temperature of the target chip can be calculated. This achieves quantitative calculation of the target temperature and enables accurate calculation of the target temperature.

[0144] In one possible implementation, the power consumption of the external structure is obtained through a second calibration.

[0145] Since T = R × P and T' = R × P', then ΔT = T - T', and correspondingly, ΔT = R × (P - P').

[0146] In this application, to simplify the processing, P' can be set to zero power consumption of the external structure, resulting in the following formula:

[0147] (3)

[0148] Among them, T m1 '~T mM 'T' represents the temperature at each detection location when the power consumption of the external structure is set to zero. This temperature can be detected. target ' indicates the target temperature of the target chip when the power consumption of the external structure is set to zero; this temperature is unknown.

[0149] Simplifying the above formula (3), we can obtain the following formula for calculating the temperature offset matrix:

[0150] (4)

[0151] Where, ΔT m1 ~ ΔT mMtemperature offset of each detection position, ΔT target temperature offset of target temperature.

[0152] According to the above, the relationship between the temperature offset matrix and the evaluation power consumption of the external structure and the preset sub-matrix, the extraction of the preset sub-matrix in the known coupling thermal resistance matrix, and the determination of the temperature of each detection position under the influence of the external structure and the influence of the external structure, the evaluation power consumption of the external structure can be determined.

[0153] Figure 6 is a flowchart of the process of obtaining the evaluation power consumption of the external structure through the second calibration provided by the embodiment of the application, which can include steps 601 to 603, which will be described in detail below.

[0154] 601, obtain a preset sub-matrix in a coupling thermal resistance matrix, and the elements in the preset sub-matrix represent the coupling thermal resistance of the external structure at the target position;

[0155] In the coupling thermal resistance matrix, the coupling thermal resistance of the external structure at each detection position and the coupling thermal resistance of the external structure to the position of the target temperature involved in the above formula (4) can be extracted.

[0156] Correspondingly, the elements in the preset sub-matrix can include R 1, N+1 , R 2,N+1 , …, R M,N+1 , R M+1,N+1 .

[0157] 602, obtain a temperature offset matrix;

[0158] Each element in the temperature offset matrix can be the temperature offset of each detection position in the target chip under the influence of the power consumption of the external structure and under the influence of the power consumption of the external structure.

[0159] In the temperature offset matrix, the difference between the temperature with the power consumption of the external structure and the temperature without the power consumption of the external structure can be determined to obtain the temperature offset of each detection position.

[0160] In one possible implementation, the temperature of each detection position in the target chip can be detected by the temperature sensor under the condition that the external structure is turned off so that the external structure power consumption is zero, to obtain the corresponding detection temperature, and then the detection temperature and the first detection temperature are used to obtain the temperature offset matrix.

[0161] In the temperature offset matrix, the temperature offset of each detection position is known, and the temperature offset corresponding to the target temperature is unknown.

[0162] The temperature offset matrix can refer to the above formula (4) and include ΔTm1 , ΔT m2 , …, ΔT mM , ΔT target , ΔT m1 , ΔT mM , ΔT target , ΔT

[0163] 603, determine the evaluation power consumption of the external structure based on the preset sub-matrix and the temperature offset matrix.

[0164] In a possible implementation, the evaluation power consumption of the external structure is fitted based on a correspondence between the preset sub-matrix and the preset temperature offset matrix.

[0165] As can be seen from the foregoing formula (4), the correspondence can be that the product of the preset sub-matrix and the evaluation power consumption of the external structure is equal to the temperature offset matrix.

[0166] Since the target temperature is unknown and the evaluation power consumption of the external structure is unknown, what is known in the correspondence is the elements in the preset sub-matrix and the unknown temperature offsets in the temperature offset matrix. Through the fitting manner, the optimal evaluation power consumption can be determined.

[0167] In a possible implementation, the fitting process includes the following processes.

[0168] 1. Determine the equation form, variables and known quantities

[0169] Rewrite formula (4) into a linear regression form ΔT = RX, where ΔT represents the temperature offset matrix on the left side of formula (4), R represents the preset sub-matrix on the right side of formula (4), and X represents the to-be-solved quantity P other .

[0170] 2. Construct a least square objective function

[0171] The error vector e = ΔT - RX, and the objective of the least square is to minimize the sum of squares of errors S, and the following formula is obtained:

[0172] S = e T e = (ΔT - RX) T (ΔT - RX) (5)

[0173] Wherein, e T represents the transpose of e

[0174] Expand (5) to obtain the following formula:

[0175] S = ΔT T ΔT - 2XR T ΔT + X2 R T R(6)

[0176] 3. Least squares solution (mathematical derivation)

[0177] Take the derivative of S with respect to X and find the minimum point by setting the derivative to 0:

[0178] (1) Take the derivative: (7)

[0179] (2) Set the derivative to 0 and solve the equation

[0180] -2R T ΔT+ 2 XR T R=0 (8)

[0181] (3) Simplify to get the least squares solution:

[0182] X=(R T R) -1 R T ΔT (9)

[0183] Here is the typical pseudo-inverse matrix (when R is not a square matrix, use pseudo-inverse to solve the least squares solution of over-determined equations), and P can be obtained by substituting it into the formula (2) to get the best fitting value. other

[0184] It should be noted that the above fitting process is only an example, and in specific implementation, other ways can also be used to fit to obtain the best evaluation power consumption.

[0185] Correspondingly, after obtaining the value of the evaluation power consumption, it is substituted into the formula (2) above, and T target can be calculated to achieve the purpose of calculating the target temperature.

[0186] In this embodiment, a preset sub-matrix in the coupling thermal resistance matrix is obtained, and the elements in the preset sub-matrix represent the coupling thermal resistance of the external structure at the target position. A temperature offset matrix is obtained. Based on the preset sub-matrix and the temperature offset matrix, the evaluation power consumption of the external structure is determined. The preset sub-matrix corresponding to the thermal coupling relationship related to the external structure and the temperature offset matrix can be used to calculate the evaluation power consumption of the external structure, thereby realizing the process of calculating the evaluation power consumption, fitting the best evaluation power consumption in the current scenario, and providing a basis for subsequent determination of the target temperature.

[0187] Figure 7 is a flowchart for forming a temperature offset matrix provided by the embodiments of the present application, which can include steps 701 to 703, which will be described in detail below.

[0188] ​701、According to the actual power consumptions of each execution unit in the target chip and the evaluation power consumption of the external structure being zero, a second power consumption matrix is obtained;

[0189] The execution units in the target chip maintain running, the evaluation power consumption of the external structure is set to zero, the running of the target chip can be maintained unchanged, the running of the external structure is ended, and the temperatures of the detection positions are measured in this state.

[0190] Correspondingly, in the obtained second power consumption matrix, the actual power consumptions of each execution unit are known, and the evaluation power consumption of the external structure is zero.

[0191] In a possible implementation, the actual power consumptions of each execution unit in the target chip can be maintained unchanged, and the running of the external structure is stopped so that the evaluation power consumption thereof is zero.

[0192] In a possible implementation, the execution units in the target chip can maintain running, the actual power consumptions thereof change, but the values of the actual power consumptions are known, and the running of the external structure is stopped so that the evaluation power consumption thereof is zero.

[0193] 702、According to the second power consumption matrix, a second temperature matrix is obtained, and each element in the second temperature matrix represents a third detection temperature of a detection position corresponding to a temperature sensor under the condition that the evaluation power consumption of the external structure is zero.

[0194] The target chip runs according to the power consumption values of each element in the second power consumption matrix, and third detection temperatures of each detection position are detected by using the temperature sensors arranged on the target chip, and the third detection temperatures form the second temperature matrix.

[0195] The second temperature matrix includes elements T m1 ’ 、T m2 ’、…、T mM ’ respectively, which represent third detection temperatures detected by each temperature sensor arranged at the detection positions 1 to M when the power consumption of the external structure is zero.

[0196] 703、Based on the first temperature matrix and the second temperature matrix, a temperature offset matrix is obtained, and each element in the matrix represents a deviation between a first detection temperature measured by each sensor and a third detection temperature, a deviation between a target temperature and a temperature of a corresponding position.

[0197] The first temperature matrix and the second temperature matrix are subtracted to obtain a temperature offset of each detection position, and the temperature offsets of each detection position form the temperature offset matrix, and the temperature offset of each detection position in the temperature offset matrix is a known value.

[0198] In a possible implementation, an element is added to the first temperature matrix, and the element represents a target temperature T target, the value of the element in the first temperature matrix is unknown; an element is added in the second temperature matrix, which is used to represent the target temperature T target the temperature T of the external structure in the case of zero evaluation power consumption target , the value of the element in the second temperature matrix is unknown. Then, in the process of determining the temperature offset matrix, the target temperature and the temperature T target ' are subtracted to obtain the offset of the two, and the offset is added to the temperature offset matrix, which is used in the process of determining the evaluation power consumption of the external structure.

[0199] In this embodiment, the second power consumption matrix is obtained according to the actual power consumption of each execution unit in the target chip and the evaluation power consumption of the external structure is zero; the second temperature matrix is obtained according to the second power consumption matrix, and each element in the second temperature matrix represents the third detection temperature of the corresponding detection position of each temperature sensor in the case of zero evaluation power consumption of the external structure; the temperature offset matrix is obtained based on the first temperature matrix and the second temperature matrix, and each element in the matrix represents the deviation between the first detection temperature measured by each sensor and the third detection temperature, and the deviation between the target temperature and the temperature of the corresponding position. By setting the evaluation power consumption of the external structure to zero, the second temperature matrix is obtained by detecting the temperature of each detection position, and the temperature offset matrix is determined by using the first temperature matrix and the second temperature matrix. By setting the evaluation power consumption of the external structure to zero and detecting the temperature by the temperature sensor, the temperature offset matrix can be obtained by simple calculation, which provides a basis for determining the evaluation power consumption of the external structure.

[0200] The above introduces a chip temperature control method provided by the embodiment of the application, and the embodiment of the application also provides a temperature control method embodiment.

[0201] Figure 8 is a flowchart of a chip temperature control method provided by the embodiment of the application, as shown in Figure 8 The chip temperature control method provided by the embodiment of the application can include steps 801 to 804, which will be described in detail below.

[0202] 801, obtain the detection temperature detected by at least two temperature sensors, the at least two temperature sensors are used to detect the temperature of at least two detection positions of a target chip;

[0203] 802, obtain the actual power consumption of each execution unit in the target chip;

[0204] 803、determining a target temperature of the target chip according to a coupling thermal resistance characteristic parameter of the target chip, a detection temperature, and power consumptions of the execution units; the coupling thermal resistance characteristic parameter representing thermal coupling information of the execution units and the external structure at target positions, the target positions including at least two detection positions and a target temperature corresponding position;

[0205] Wherein, the explanation of steps 801-803, please refer to the aforementioned chip temperature determination method embodiment, this embodiment will not be repeated.

[0206] 804、controlling a running state of the target chip based on the target temperature of the target chip.

[0207] Since the temperature of the electronic component is too high during the running process, which will affect its service life, therefore, after determining the target temperature of the target chip, the target temperature can be used to control the running state of the target chip.

[0208] As an example, the target temperature of the target chip is high, the power consumption of the target chip can be controlled to reduce the heat dissipation, so as to reduce the temperature of the target chip.

[0209] As an example, the target temperature of the target chip is low, the power consumption of the target chip can be increased according to the demand, so as to improve the performance of the target chip.

[0210] In a possible implementation, the running state of the external structure can also be controlled based on the target temperature of the target chip, so as to reduce the influence of the external structure on the temperature of the target chip, and improve the efficiency of heat dissipation of the target chip to the outside.

[0211] In a possible implementation, a control strategy is called based on that the target temperature meets a preset control condition, and the control strategy is used to adjust the running state of the target chip.

[0212] Different control strategies can be set for different target temperatures of the target chip, so that the running state of the target chip corresponds to the target temperature thereof.

[0213] The preset control condition can include that the target temperature is greater than a preset upper limit of temperature, and the corresponding control strategy can be to control the target chip to run with reduced power consumption; the preset control condition can include that the target temperature is less than a preset lower limit of temperature, and the corresponding control strategy can be to control the target chip to run with increased power consumption.

[0214] The preset control condition can be that the change trend of the target temperature increases, and the change trend can be a temperature rising trend. If the temperature rising trend of the target temperature increases, it indicates that the temperature of the target chip rises sharply, and the corresponding control strategy can be to control the target chip to run with reduced power consumption.

[0215] In this embodiment, after the target temperature of the target chip is determined, the running state of the target chip is controlled by using the target temperature, so that the running state of the target chip can be adjusted according to the target temperature, and the performance of the target chip can be accurately controlled.

[0216] The chip temperature determination method and the chip temperature control method provided in the embodiments of the present application are introduced above, and the electronic device for executing the chip temperature determination method and the chip temperature control method will be introduced below.

[0217] Please refer to Figure 9 , Figure 9 is a structural schematic diagram of an electronic device provided in the embodiments of the present application. As shown in Figure 9 , the electronic device 900 includes:

[0218] a target chip 901, the target chip including at least one execution unit;

[0219] an external structure 902;

[0220] at least two temperature sensors 903, configured to detect temperatures at at least two detection positions on the target chip;

[0221] a processor 904, configured to: obtain a first detection temperature detected by the at least two temperature sensors; obtain power consumptions of each execution unit in the target chip; determine a target temperature of the target chip based on a coupling thermal resistance matrix, the first detection temperature, and the power consumptions of each execution unit; and a coupling thermal resistance characteristic parameter represents thermal coupling information of each execution unit and the external structure at each target position, the target position including the at least two detection positions and a target temperature corresponding position.

[0222] The processor can be a functional structure in the target chip, or a functional structure in the external structure, and the Figure 8 In this embodiment, the processor is a functional structure in the target chip, but is not limited thereto. In specific implementation, the processor can be determined to belong to the external structure or the target chip according to requirements.

[0223] The execution unit can be a functional unit in the target chip, and the processor can be one of the execution units.

[0224] If the target chip is a multi-core structure such as a CPU, a GPU, and an NPU, each core in the target chip can be an execution unit.

[0225] If the target chip is an SOC chip, the SOC chip integrates a plurality of functional units such as a CPU, a GPU, and an NPU, each functional unit can be an execution unit, and each execution unit generates power consumption during running.

[0226] In a possible implementation, the coupling thermal resistance characteristic parameter of the target chip includes a coupling thermal resistance matrix, and each element in the matrix represents the coupling thermal resistance of each execution unit and external structure at each target position. The process of forming the coupling thermal resistance matrix by the processor includes:

[0227] At least two groups of power consumptions are obtained, each group of power consumptions including the power consumptions of each execution unit in the target chip and the power consumptions of the corresponding external structure.

[0228] The at least two groups of power consumptions are simulated by using a thermal simulation model to obtain at least two groups of simulation temperatures, each group of simulation temperatures including a preset number of simulation temperatures, the preset number being the number of temperature sensors plus one, and the preset number of simulation temperatures including simulation values of temperatures detected by the at least two temperature sensors and a first simulation temperature of the target chip, the first simulation temperature matching the target temperature.

[0229] The coupling thermal resistance characteristic parameter is determined according to the at least two groups of power consumptions and the at least two groups of simulation temperatures.

[0230] In a possible implementation, the thermal simulation model is obtained by first calibration on an initial thermal simulation model, and the first calibration process includes:

[0231] Second detection temperatures detected by the at least two temperature sensors are obtained in turn in a process in which the target chip is controlled to run by using any one of the at least two power consumption distributions, and the power consumptions of each execution unit in the target chip are different under different power consumption distributions.

[0232] For each power consumption distribution, a corresponding relationship between the power consumption and the detection temperature of the target chip is determined according to the second detection temperatures detected by the at least two temperature sensors.

[0233] The thermal simulation model is calibrated by using the corresponding relationship.

[0234] In a possible implementation, the target temperature of the target chip is determined according to the coupling thermal resistance matrix, the first detection temperature, and the power consumptions of each execution unit, and includes:

[0235] A first power consumption matrix is obtained according to the actual power consumptions of each execution unit and the estimated power consumptions of the external structure.

[0236] The target temperature of the target chip is determined according to the first temperature matrix, the first power consumption matrix, and the coupling thermal resistance matrix, and the first temperature matrix includes the first detection temperatures detected by the at least two temperature sensors.

[0237] In a possible implementation, the estimated power consumptions of the external structure are obtained by second calibration, and the second calibration process performed by the processor includes:

[0238] obtain a preset sub-matrix in the coupling thermal resistance matrix, and elements in the preset sub-matrix represent coupling thermal resistance of the external structure at the target position;

[0239] obtain a temperature offset matrix;

[0240] determine the evaluation power consumption of the external structure based on the preset sub-matrix and the temperature offset matrix.

[0241] In a possible implementation, the process in which the processor forms the temperature offset matrix includes:

[0242] obtain a second power consumption matrix according to actual power consumptions of each execution unit in the target chip and the evaluation power consumption of the external structure being zero;

[0243] obtain a second temperature matrix according to the second power consumption matrix, and each element in the second temperature matrix represents a third detection temperature of the corresponding detection position of each temperature sensor in the case that the evaluation power consumption of the external structure is zero;

[0244] obtain the temperature offset matrix based on the first temperature matrix and the second temperature matrix, and each element in the matrix represents a deviation between the first detection temperature measured by each sensor and the third detection temperature, and a deviation between the target temperature and the temperature of the corresponding position.

[0245] In a possible implementation, the determination of the evaluation power consumption of the external structure based on the preset sub-matrix and the temperature offset matrix includes:

[0246] fit the evaluation power consumption of the external structure based on the corresponding relationship between the preset sub-matrix and the preset temperature offset matrix and the evaluation power consumption of the external structure.

[0247] In the case that the electronic device executes the chip temperature control method, the processor of the electronic device is further configured to:

[0248] control the running state of the target chip based on the target temperature of the target chip.

[0249] In a possible implementation, the processor is specifically configured to:

[0250] invoke a control strategy for adjusting the running state of the target chip based on the target temperature satisfying a preset control condition.

[0251] It should be noted that the functions of the constituent structures in the electronic device provided in the embodiments of the present application are explained with reference to the explanations in the foregoing method embodiments, and will not be repeated here.

[0252] In this embodiment, the electronic device includes: a target chip, which contains at least one execution unit; an external structure; at least two temperature sensors for detecting the temperature at at least two detection locations on the target chip; a processor for obtaining a first detected temperature from the at least two temperature sensors; obtaining the power consumption of each execution unit within the target chip; determining a target temperature of the target chip based on the coupling thermal resistance matrix, the first detected temperature, and the power consumption of each execution unit; and coupling thermal resistance characteristic parameters characterizing the thermal coupling information of each execution unit and the external structure at each target location, wherein the target location includes at least two detection locations and a location corresponding to the target temperature. Using the first detected temperature obtained from multiple detection locations on the target chip, the actual power consumption of multiple execution units acting as heat sources within the target chip, the evaluated power consumption of the external structure acting as a heat source outside the target chip, and the coupling thermal resistance characteristic parameters of the target chip, the target temperature of the target chip can be calculated. The maximum temperature of the target chip can be obtained through analysis and calculation, providing an accurate basis for temperature control of the target chip and improving the effectiveness of temperature control.

[0253] This application also provides an electronic device in its embodiments. (See reference...) Figure 10 The diagram illustrates a hardware structure suitable for implementing the electronic devices described in the embodiments of this application. The electronic devices in these embodiments may include, but are not limited to, fixed terminals such as mobile phones, laptops, PDAs (personal digital assistants), PADs (tablet computers), desktop computers, etc. Figure 10 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0254] like Figure 10 As shown, the electronic device may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 into a random access memory (RAM) 1003. When the electronic device is powered on, the RAM 1003 also stores various programs and data required for the operation of the electronic device. The processing unit 1001, ROM 1002, and RAM 1003 are interconnected via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0255] In general, the following devices can be connected to the I / O interface 1005: input devices 1006, including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, and the like; output devices 1007, including, for example, a liquid crystal display (LCD), a speaker, a vibrator, and the like; storage devices 1008, including, for example, a memory card, a hard disk, and the like; and communication devices 1009. The communication devices 1009 can allow the electronic device to communicate wirelessly or through a wired connection with other devices to exchange data. Although Figure 10 Electronic devices having various devices are shown, but it is understood that all of the shown devices are not required to be implemented or present. More or less devices can alternatively be implemented or present.

[0256] The embodiments of the present application further provide a computer program product comprising computer readable instructions, which, when executed on an electronic device, cause the electronic device to implement any of the chip temperature determination method or the chip temperature control method provided by the embodiments of the present application.

[0257] The embodiments of the present application further provide a computer readable storage medium carrying one or more computer programs, which, when executed by an electronic device, can cause the electronic device to implement any of the chip temperature determination method or the chip temperature control method provided by the embodiments of the present application.

[0258] It should be further noted that the apparatus embodiments described above are only schematic and that actual configurations of the apparatus can differ from that described above. For example, one or more components illustrated as separate components can be implemented integrally with other components, and vice versa. The embodiments of this application can be implemented by hardware, software, or firmware, or any combination thereof. When implemented in software, the embodiments of this application can be stored in computer-readable storage medium, such as RAM, flash memory, ROM, EEPROM, EEPROM, registers, hard disk, disk, CD-ROM, or database, or any other form of storage medium.

[0259] Those skilled in the art can clearly understand that the application can be implemented by means of software plus necessary universal hardware, and of course can also be implemented by means of dedicated hardware including special integrated circuit, special CPU, special memory, special component, etc. Generally, any function completed by computer program can be easily implemented by corresponding hardware, and the specific hardware structure for implementing the same function can also be various, such as analog circuit, digital circuit or special circuit, etc. However, for the application, software program implementation is a better embodiment. Based on such understanding, the technical solution of the application or the part of the application which makes contribution to the prior art can be embodied in the form of software product, which is stored in readable storage medium, such as computer floppy disk, U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., and includes a plurality of instructions for making a computer device (which can be personal computer, training device or network device, etc.) execute the method described in various embodiments of the application.

[0260] In the above embodiments, the implementation can be achieved by software, hardware, firmware or any combination thereof, entirely or partially. When implemented by software, the implementation can be achieved in the form of a computer program product, entirely or partially.

[0261] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the flow or function described in the embodiments of the application is generated entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another, for example, the computer instructions can be transmitted from one website, computer, training device or data center to another website, computer, training device or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be stored by the computer or a data storage device such as training device, data center, etc. integrated with one or more available media sets. The available medium can be magnetic medium (such as floppy disk, hard disk, magnetic tape), optical medium (such as DVD) or semiconductor medium (such as solid state disk (SSD)) etc.

Claims

1. A method for determining chip temperature, wherein the target chip includes at least one execution unit, comprising: A first detection temperature is obtained from at least two temperature sensors, wherein the at least two temperature sensors are used to detect the temperature at at least two detection locations of the target chip; The actual power consumption of each execution unit within the target chip and the estimated power consumption of the external structure are obtained. The target temperature of the target chip is determined based on the coupling thermal resistance characteristic parameters of the target chip, the first detection temperature, the actual power consumption of each execution unit, and the evaluated power consumption of the external structure. The coupling thermal resistance characteristic parameters characterize the thermal coupling information of each execution unit and the external structure at each target location. The target location includes the at least two detection locations and the location corresponding to the target temperature.

2. The chip temperature determination method according to claim 1, wherein the coupling thermal resistance characteristic parameters of the target chip include a coupling thermal resistance matrix, wherein each element in the matrix represents the coupling thermal resistance of each execution unit and external structure at each target location, and the method for forming the coupling thermal resistance matrix includes: At least two sets of power consumption are obtained, each set of power consumption including the power consumption of each execution unit in the target chip and the power consumption of the corresponding external structure; Using a thermal simulation model, simulations are performed on the at least two sets of power consumption to obtain at least two sets of corresponding simulation temperatures. Each set of simulation temperatures includes a preset number of simulation temperatures, which is the number of temperature sensors plus 1. The preset number of simulation temperatures includes the simulation temperature values ​​detected by at least two temperature sensors and the first simulation temperature of the target chip, which matches the target temperature. Based on the at least two sets of power consumption and the corresponding at least two sets of simulation temperatures, the characteristic parameters of the coupling thermal resistance are determined.

3. The chip temperature determination method according to claim 2, wherein the thermal simulation model is obtained by performing a first calibration on an initial thermal simulation model, the first calibration process comprising: During the process of controlling the operation of the target chip using at least two power consumption distributions, the second detection temperature detected by the at least two temperature sensors is obtained; under different power consumption distributions, the power consumption distribution of each execution unit in the target chip is different; For each power consumption distribution, the correspondence between the power consumption of the target chip and the detection temperature is determined based on the second detection temperature obtained from the at least two temperature sensors. The thermal simulation model is calibrated using the aforementioned correspondence.

4. The chip temperature determination method according to claim 1, wherein determining the target temperature of the target chip based on the coupling thermal resistance matrix, the first detected temperature, and the power consumption of each execution unit includes: Based on the actual power consumption of each execution unit and the estimated power consumption of the external structure, the first power consumption matrix is ​​obtained; The target temperature of the target chip is determined based on the first temperature matrix, the first power consumption matrix, and the coupling thermal resistance matrix. The first temperature matrix includes the first detection temperature detected by the at least two temperature sensors.

5. The chip temperature determination method according to claim 2, wherein the power consumption of the external structure is evaluated through a second calibration, the second calibration process comprising: Obtain a preset submatrix in the coupling thermal resistance matrix, wherein the elements in the preset submatrix characterize the coupling thermal resistance of the external structure at the target location; Obtain the temperature offset matrix; Based on the preset submatrix and temperature offset matrix, the power consumption of the external structure is determined.

6. The chip temperature determination method according to claim 5, wherein the method for forming the temperature offset matrix includes: Based on the actual power consumption of each execution unit in the target chip and the zero power consumption of the external structure, a second power consumption matrix is ​​obtained; Based on the second power consumption matrix, a second temperature matrix is ​​obtained. Each element in the second temperature matrix represents the third detection temperature of each temperature sensor at the corresponding detection position when the evaluation power consumption of the external structure is zero. Based on the first temperature matrix and the second temperature matrix, a temperature offset matrix is ​​obtained. Each element in the matrix represents the deviation between the first and third detection temperatures measured by each sensor, and the deviation between the target temperature and the temperature at the corresponding location.

7. The chip temperature determination method according to claim 5, wherein determining the evaluation power consumption of the external structure based on the preset sub-matrix and the temperature offset matrix includes: Based on the correspondence between the preset submatrix and the external structure's power consumption and the preset temperature offset matrix, the external structure's power consumption is fitted to obtain the power consumption.

8. A chip temperature control method, comprising: The detection temperature is obtained from at least two temperature sensors, wherein the at least two temperature sensors are used to detect the temperature at at least two detection locations of the target chip; Obtain the actual power consumption of each execution unit within the target chip; The target temperature of the target chip is determined based on the coupling thermal resistance characteristic parameters of the target chip, the detection temperature, and the power consumption of each execution unit; the coupling thermal resistance characteristic parameters characterize the thermal coupling information of each execution unit and external structure at each target location, and the target location includes the at least two detection locations and the location corresponding to the target temperature; The operating state of the target chip is controlled based on the target temperature of the target chip.

9. The chip temperature control method according to claim 1, wherein controlling the operating state of the target chip based on the target temperature of the target chip includes: Based on the target temperature meeting preset control conditions, a control strategy is invoked, which is used to adjust the operating state of the target chip.

10. An electronic device, comprising: The target chip includes at least one execution unit; External structure; At least two temperature sensors are used to detect the temperature at at least two detection locations on the target chip; A processor is configured to obtain a first detected temperature from the at least two temperature sensors; Obtain the power consumption of each execution unit within the target chip; The target temperature of the target chip is determined based on the coupling thermal resistance matrix, the first detection temperature, and the power consumption of each execution unit. The coupling thermal resistance characteristic parameters characterize the thermal coupling information of each execution unit and external structure at each target location. The target location includes the at least two detection locations and the location corresponding to the target temperature.

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