Memory device and operating method thereof

Abstract

The present disclosure provides a memory device and an operating method thereof, the operating method of the memory device including: after the memory device receives a first operation command, starting a first operation cycle including a voltage setting period, a first operation setting period, a first operation execution period, and a first operation recovery period; when the memory device receives a second operation command before the first operation recovery period ends, the memory device directly enters a second operation cycle after the first operation recovery period ends. The second operation cycle includes a second operation setting period, a second operation execution period, and a second operation recovery period. The first operation recovery period is adjacent to the second operation setting period. When the first operation recovery period and the second operation recovery period start, the cache is switched from the busy state to the ready state, so that the data in the cache can be accessed.

Description

TECHNICAL FIELD

[0001] The technology relates to the technical field of semiconductor device, for example, the operation of cache in semiconductor device. BACKGROUND

[0002] Semiconductor devices, such as memory devices, are becoming smaller and faster. Many applications require support for faster operating frequencies, such as read frequencies. However, when data is transferred among elements within a memory device, such as registers, buffers, caches, input / output, etc., the timing of the operations of the elements need to be coordinated with each other, causing delays in operations, such as read delays. SUMMARY

[0003] The present disclosure describes methods, devices, systems, and techniques for operating a cache in a semiconductor device, such as a non-volatile memory device, such as a flash memory device, to reduce the delay of access operations.

[0004] One aspect of the present disclosure features a method of operating a memory device, comprising: starting a first operation cycle after the memory device receives a first operation command, the first operation cycle comprising a voltage setup period, a first operation setup period, a first operation execution period, and a first operation recovery period. The cache enters a busy state at the start of the voltage setup period. During the first operation execution period, the cache receives data. The cache exits the busy state and switches to a ready state at the start of the first operation recovery period, in which data in the cache is accessible. When the memory device receives a second operation command before the end of the first operation recovery period, the memory device enters a second operation cycle directly after the end of the first operation recovery period. The second operation cycle comprises a second operation setup period, a second operation execution period, and a second operation recovery period. The first operation recovery period is adjacent to the second operation setup period. The cache switches from the busy state to the ready state at the start of the second operation recovery period, making data in the cache accessible.

[0005] In some embodiments, when the memory device receives the second operation command after the end of the first operation recovery period, the memory device enters the first operation cycle again after receiving the second operation command, and the cache switches to the busy state. The second operation cycle has a shorter time length than the first operation cycle.

[0006] In some embodiments, the cache corresponds to a ready-busy indication signal, the ready-busy indication signal being at a first level to indicate that the cache is in a ready state, and the ready-busy indication signal being at a second level to indicate that the cache is in a busy state. A plurality of falling edges of the ready-busy indication signal from the first level to the second level corresponds to a beginning of the voltage setting period and an end of the first operation command, or corresponds to an end of a second operation command in the first operation resume period, and a plurality of rising edges of the busy state indication signal from the second level to the first level corresponds to a beginning of the first operation resume period and a beginning of the second operation resume period.

[0007] In some embodiments, a time length of the first operating current of the memory device corresponds to a time length of the first operation cycle. When a second operation command is received after the end of the first operation resume period, a time length of a standby current of the memory device corresponds to a time period between the end of the first operation resume period and the end of the second operation command. A time length between two adjacent falling edges of the ready-busy indication signal corresponds to a sum of the time lengths of the operating current and the standby current of the memory device.

[0008] In some embodiments, when a second operation command is received before the end of the first operation resume period, the cache enters the busy state after receiving the second operation command. A time length of a second operating current of the memory device corresponds to a time length of the second operation cycle, and one of the plurality of falling edges of the ready-busy indication signal corresponds to an end of the second operation command in the first operation resume period, such that a time length between two adjacent falling edges of the ready-busy indication signal is shorter than the time length of the first operating current of the memory device.

[0009] In some embodiments, the memory device is a NAND memory device, the NAND memory device includes a page buffer, and the first operation cycle further includes a first page buffer to cache period, the first page buffer to cache period being between the first operation execution period and the first operation resume period, and during the first page buffer to cache period, data is transferred between the page buffer and the cache.

[0010] In some embodiments, the NAND memory device includes a memory cell array, the first operation command includes a first read command, and the first operation execution period includes at least a first read execution period and a second read execution period. Data in the memory cell array is read and transferred to the page buffer, and during the first operation resume period, data in the cache is output.

[0011] In some embodiments, the second operation command comprises a second read command, and the second operation cycle further comprises a second page buffer to cache period. The second page buffer to cache period is between the second operation execution period and the second operation resume period, and during the second page buffer to cache period, data is transferred between the page buffer and the cache.

[0012] In some embodiments, the NAND memory device comprises an array of memory cells, the second operation execution period comprises at least a third read execution period and a fourth read execution period for reading data in the array of memory cells and transferring to a page buffer, and during the second operation resume period, data in the cache is output.

[0013] In some embodiments, a time length of the first operation current of the NAND memory device corresponds to a time length of the first operation cycle. When a second read command is received before the end of the first operation resume period, one of a plurality of falling edges of a ready / busy indication signal of the memory device corresponding to the end of the second read command in the first operation resume period causes the first operation current to remain present after the falling of the ready / busy indication signal and before the end of the first operation cycle, the first operation current being greater than or equal to a predetermined value.

[0014] In some embodiments, the memory device is a NOR memory device, the NOR memory device further comprises a scratchpad, and the first operation command comprises a first read command, the first operation execution period is for reading data in the scratchpad to a cache, and during the first operation resume period, data in the cache is output.

[0015] In some embodiments, the memory device is a NOR memory device, the NOR memory device further comprises a scratchpad, and the second operation command comprises a second read command, the second operation execution period is for reading data in the scratchpad to a cache, and during the second operation resume period, data in the cache is output.

[0016] In some embodiments, the first operation command comprises a first write command, and during the first operation resume period, data in the cache is written to the memory device. The second operation command comprises a second write command, and during the second operation resume period, data in the cache is written to the memory device.

[0017] Another aspect of the disclosure features a memory device, including: an array of memory cells to store data; a control circuit coupled to the array of memory cells, the control circuit including a command interface and an operation flow controller; and a cache coupled to the array of memory cells and the control circuit. The control circuit controls the memory device to start a first operation cycle in response to the operation flow controller receiving a first operation command through the command interface. The first operation cycle includes a voltage setup period, a first operation setup period, a first operation execution period, and a first operation recovery period. The operation flow controller controls the cache to: enter a busy state at a beginning of the voltage setup period; receive data in the cache during the first operation execution period; exit the busy state and switch to a ready state at a beginning of the first operation recovery period, in which data in the cache is accessible; and control the control circuit to cause the memory device to directly enter a second operation cycle after the first operation recovery period in response to the command interface receiving a second operation command before an end of the first operation recovery period. The second operation cycle includes a second operation setup period, a second operation execution period, and a second operation recovery period. The first operation recovery period is adjacent to the second operation setup period. The operation flow controller switches the cache from the busy state to the ready state at a beginning of the second operation recovery period, in which data in the cache is accessible.

[0018] In some embodiments, the memory device is a NAND memory device, the NAND memory device further includes: a page buffer coupled between the cache and the array of memory cells; and a data input / output circuit coupled to the cache. The first operation command includes a first read command.

[0019] In some embodiments, the first operation cycle further includes a first page buffer to cache period between the first operation recovery period and the first operation execution period, during which data is transferred between the page buffer and the cache.

[0020] In some embodiments, the first operation execution period includes at least a first read execution period and a second read execution period to read data from the array of memory cells and transfer the data to the page buffer, and during the first operation recovery period, data in the cache is output to the data input / output circuit.

[0021] In some embodiments, the second operation command includes a second read command, and the second operation cycle further includes a second page buffer to cache period between the second operation recovery period and the second operation execution period, during which data is transferred between the page buffer and the cache.

[0022] In some embodiments, the second operation includes at least a third read execution period and a fourth read execution period for reading data in the memory cell array and transferring to the page buffer, and during the second operation resume period, the data in the cache is output to the data input / output circuit.

[0023] In some embodiments, the time length of the first operation current of the NAND memory device corresponds to a time length of a first operation cycle. When a second read command is received before the end of the first operation resume period, a falling edge of a ready / busy indication signal of the memory device corresponds to when the second read command ends in the first operation resume period, the first operation current remains present between the falling edge of the ready / busy indication signal and before the end of the first operation cycle, the first operation current being greater than or equal to a predetermined value.

[0024] Embodiments of the described techniques include methods, systems, circuits, computer program products, and computer-readable media. In one example, a method can include the actions described above. In another example, a computer program product is adapted to be embodied in a non-transitory machine-readable medium that stores instructions executable by one or more processors. The instructions are to cause the one or more processors to perform the actions described above. A computer-readable medium stores instructions. The instructions are to cause one or more processors to perform the actions described above when executed by the one or more processors.

[0025] In the present disclosure, the term "read latency" means a time delay for data to be read, which is associated with a time duration or period for reading the data.

[0026] In the present disclosure, the term "time diagram" or "timing profile" can refer to a graph for durations associated with different actions of an operation. In some examples, the time diagram or timing profile includes at least one of a voltage setup period, an operation setup period, an operation execution period, and an operation resume period of an operation cycle. Each period can be defined by a corresponding number of clock cycles or a corresponding duration.

[0027] For a better understanding of the above-described and other aspects and features of the present disclosure, a more particular description of the exemplary embodiments will be rendered by reference to specific examples thereof, which are illustrated in the appended drawings. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A schematic diagram illustrating an example of a timing line diagram for an operation of a memory device in accordance with one or more embodiments of the present disclosure.

[0029] Figure 2 A schematic diagram illustrating a timing comparison of a plurality of different example timing diagrams for an operation of a memory device in accordance with one or more embodiments of the present disclosure.

[0030] Figure 3 A schematic diagram illustrating a timing comparison of a plurality of different example timing diagrams for a read operation of a NAND memory device in accordance with one or more embodiments of the present disclosure.

[0031] Figure 4 A schematic diagram illustrating an example timing line diagram for an operation of a memory device in accordance with one or more embodiments of the present disclosure.

[0032] Figure 5 A flowchart of a procedure illustrating an example timing diagram for Figure 4 .

[0033] Figure 6 A schematic diagram illustrating an example timing diagram for a read operation of a NAND memory device in accordance with one or more embodiments of the present disclosure.

[0034] Figure 7 A schematic diagram illustrating a timing comparison of a plurality of different example timing diagrams for a read operation of a NAND memory device in accordance with Figure 2 and Figure 6 .

[0035] Like reference numerals or designations in the various drawings indicate like elements. It is also to be understood that the various illustrative embodiments shown in the Figures are only examples and that other embodiments can be used.

[0036] Legend of Reference Numerals

[0037] 100: memory device

[0038] 110: memory cell array

[0039] 120: control circuit

[0040] 121: operation control interface

[0041] 122: command interface

[0042] 130: page buffer

[0043] 140: cache

[0044] 150: data input / output circuit

[0045] 160: voltage generator

[0046] 170: address decoder

[0047] 200, 300, 700: timing comparison

[0048] 200a, 200b, 300a, 300b, 400, 600, 700a, 700b, 700c: timing chart

[0049] 240, 340, 440, 640, 740: first operation current

[0050] 241, 341, 741: standby current

[0051] 442, 642, 742: second operation current

[0052] 500: program

[0053] 501, 502, 503, 504: step

[0054] ACS1, ACS2: data access

[0055] C1: first operation cycle

[0056] C2: second operation cycle

[0057] CMD1: first operation command

[0058] CMD2: second operation command

[0059] CS: internal clock

[0060] DOUT1, DOUT2: data output

[0061] DL2 CDL: buffer to cache period

[0062] P11: voltage setting period

[0063] P12: first operation setting period

[0064] P13: first operation execution period

[0065] P131: first read execution period

[0066] P132: second read execution period

[0067] P14: first operation recovery period

[0068] P22: second operation setting period

[0069] P23: second operation execution period

[0070] P24: second operation recovery period

[0071] P231 : third read execution period

[0072] P232 fourth read execution period

[0073] S1 : ready / busy indication signal

[0074] SH: first level

[0075] SL: second level

[0076] RT1, RT2: reduced operation time DETAILED DESCRIPTION

[0077] Various embodiments of the present disclosure provide techniques for non-volatile memory devices, such as flash memory devices, to speed up cache operations. The techniques ensure that the cache in the memory device can reduce operation time (latency). Alternatively, the techniques enable the cache in the memory device to reduce the operation cycle to speed up data access in the cache, achieve higher read / write or other operation performance, and reduce latency by determining in which period the operation command is received.

[0078] For example, if the operation command is received before the end of the operation recovery period, the techniques enable the memory device to enter a shorter operation cycle without resetting the (high) voltage to operate the cache. Even, the operating current to the memory device can be continuous without entering standby current to reduce the interval for cache access and reduce latency.

[0079] These techniques can be applied to external and / or internal clock designs. These techniques can be applied to different types of semiconductor devices, such as non-volatile memory devices, e.g., NOR flash memory, NAND flash memory, resistive random-access memory (RRAM), phase change random access memory (PCRAM), or others. The techniques can likewise be applied to different memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices, e.g., 2-level cell devices, triple-level cell (TLC) devices, quad-level cell (QLC) devices, or penta-level cell (PLC) devices. Additionally and alternatively, the techniques can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, or others. For purposes of illustration in this disclosure, memory devices are illustrated as examples of semiconductor devices.

[0080] Figure 1 A schematic diagram illustrating an example of a memory device 100 in accordance with one or more embodiments of the present disclosure is shown. The memory device 100 can have a memory cell array 110 that can include a plurality of memory cells. The memory cell array can be coupled in series to a number of word lines, and to a number of rows of bit lines. Each memory cell can include at least one memory transistor to serve as a storage element to store data. The memory transistor can include a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, a floating gate transistor, a nitride read only memory (NROM) transistor, or any suitable non-volatile memory metal-oxide-semiconductor (MOS) device that can store charge.

[0081] The memory device 100 can include a voltage generator 160 and an address decoder 170. Each memory cell can be coupled to the address decoder 170 via a corresponding word line. As such, each memory cell can be selected by the address decoder 170 for a read or write operation through the corresponding word line.

[0082] The memory device 100 can include a data input / output circuit 150 that can have a plurality of pins for coupling to an external device. These pins can include SI / SIOO for serial data in / serial data in and out, SO / SIOI for serial data out / serial data in and out, SIO2 for serial data in or out, SIO3 for serial data in or out, RESET# for hardware reset pin active low, CS# for chip select, and ECS# for Error Correction Code (ECC) correction signal, and R / B# pins for indicating the ready or busy status of the memory device 100. ECS is an abbreviation for Error Correction Code (ECC) Correction Signal. The data input / output circuit 150 can also include one or more other pins, such as WP# for write protect active low and / or Hold# for holding input signals.

[0083] In some embodiments, the memory device 100 includes a page buffer 130, a cache 140, and a control circuit 120. The control circuit 120, including a command interface 122 and an operation flow controller 121, can receive and generate commands, such as read commands and / or write commands that can be executed to read data from and / or write data to the memory device 100, respectively. Data written to or read from the memory cell array 110 can be communicated or transferred between the memory device 100 and the control circuit 120 and / or other elements via a data bus, such as a system bus, which can be a multi-bit data bus. In some embodiments, the control circuit 120 can receive a read data or write operation command through the command interface 122 therein and determine a time point at which the operation command is received, and the operation flow controller 121 in the control circuit 120 can control the cache 140 according to a result of the determination. The page buffer 130 and the cache 140 of the memory device 100 are used to buffer and cache data input or output from the memory cell array 110 to the data input / output circuit 150.

[0084] In some embodiments, during a read operation, the memory device 100 receives a read command (or read instruction) through the control circuit 120, such as according to the SPI protocol or the QPI protocol. The read instruction can be transmitted using SDR or DDR. The voltage generator 160 can provide a voltage to the address decoder 170 to select a memory cell.

[0085] In some embodiments, upon receiving a first operation command (e.g., a read command or a read instruction) through the command interface 122, the operation flow controller 121 of the control circuit 120 controls the memory device 100 to start a first operation cycle, including a voltage setup period, a first operation setup period, a first operation execution period, and a first operation recovery period. At the beginning of the voltage setup period, the operation flow controller 121 controls the cache 140 to enter a busy state. During the first operation execution period, the cache 140 receives data, e.g., from the page buffer 130 in a read operation, or from the data input / output circuit 150 in a write operation. At the beginning of the first operation recovery period, the operation flow controller 121 controls the cache 140 to exit the busy state and switch to a ready state, in which data in the cache 140 can be accessed, e.g., output to the input / output circuit 150 and / or received from the page buffer 130 in a read operation, or received from the data input / output circuit 150 and / or transmitted to the page buffer 130 in a write operation.

[0086] In some embodiments, when a second operation command (e.g., a read command or a read instruction) is received through the command interface 122 before the end of the first operation recovery period, the control circuit 120 controls the memory device 100 to enter a second operation cycle, including a second operation setup period, a second operation execution period, and a second operation recovery period, directly after the end of the first operation recovery period, and the first operation recovery period is adjacent to the second operation setup period. Similar to the first operation cycle, the operation flow controller 121 controls the cache 140 to switch from the busy state to the ready state at the beginning of the second operation recovery period, in which data in the cache 140 can be accessed, e.g., output to the input / output circuit 150 and / or received from the page buffer 130 in a read operation, or received from the data input / output circuit 150 and / or transmitted to the page buffer 130 in a write operation.

[0087] In some embodiments, the page buffer 130 can be replaced by a register, e.g., when the memory device 100 is a NOR memory device, in which a register can also be used to access data in the cache 140 and the memory cell array 110.

[0088] As discussed above and explained in more detail below, various embodiments of the present disclosure provide techniques to enable a semiconductor device to determine a time point at which an operation command is received, e.g., whether it is during an operation recovery period, to shorten an operation cycle, to speed up data access in a cache, and to achieve higher read / write or other operation performance.

[0089] For example, if a read command is received before the end of the operation recovery period, the semiconductor device enters a shorter read operation cycle that does not include the voltage setting period, achieving higher read performance and reducing read latency.

[0090] Figure 2 A schematic diagram illustrating timing comparison 200 of several different example timing diagrams (timing diagram 200a, timing diagram 200b) for operation of a memory device according to one or more embodiments of the present disclosure. Figure 2 Several example timing diagrams (timing diagram 200a, timing diagram 200b) can be applied to memory devices, for example, in Figure 1 The memory device 100 shown. In timing diagrams 200a and 200b, after receiving the first operation command CMD1 (e.g., at... Figure 1 In the command interface 122, the memory device enters the first operation cycle C1 to cache the memory device (e.g., in the command interface 122). Figure 1 The operation is performed using the cache 140 in the cache. The first operation loop C1 can be, for example, an operation loop that executes a write or read operation command. Figure 2 As shown, the operation cycle C1 may include (or be divided into) a voltage setting period P11, a first operation setting period P12, a first operation execution period P13, and a first operation recovery period P14.

[0091] In timing diagrams 200a and 200b, corresponding to the first operation cycle C1, the memory device cache (e.g., in...) Figure 1 The cache 140 in the figure corresponds to the ready-to-work indicator signal S1. As shown in the figure, when the ready-to-work indicator signal S1 is at the first level SH, it indicates that the cache is in the ready state, and when the ready-to-work indicator signal S1 is at the second level SL, it indicates that the cache is in the busy state. The cache enters the busy state at the start of the voltage setting period P11 corresponding to the first operating cycle C1 (e.g., via...). Figure 1 (Controlled by the operation flow controller 121), at this time, the ready-to-work indicator signal S1 enters the second level SL, which indicates that the cache is in a busy state. Similarly, at this time, the corresponding ready-to-work indicator signal S1 has a falling edge. Then, during the first operation execution period P13, the cache receives data (e.g., from...). Figure 1 (The page buffer 130 or the data input / output circuit 150 receives the data).

[0092] In timing diagram 200a, timing diagram 200b, the memory device also has a first operating current 240 and a standby current 241 corresponding to the first operation cycle C1. The first operating current 240 corresponds to the current flowing through the memory device when the memory device is operating, and the standby current 241 corresponds to the current flowing through the memory device when the memory device is in standby. In some embodiments, the first operating current 240 fluctuates during operation of the memory (e.g., corresponding to the first operation cycle C1), and the first operating current 240 is greater than or equal to a predetermined value. As seen in the figures, the standby current 241 corresponds to the interval between two first operation cycles C1, that is, the memory device is in standby between two first operation cycles C1.

[0093] Continuing to refer to FIGS. 2A and 2B, Figure 2 The difference between timing diagram 200a and timing diagram 200b is that the data access ACS1 corresponding to the first operation command CMD1 is located after the end of the first operation recovery period P14 or is located in the first operation recovery period P14. As in timing diagram 200b, when the data access ACS1 is located in the first operation recovery period P14, the interval between two first operation cycles C1 can be shortened. In order to have the data access ACS1 located in the first operation recovery period P14, that is, to access the data in the cache during the first operation recovery period P14, the cache needs to be switched to a ready state at the beginning of the first operation recovery period P14 (e.g., by the operation flow controller 121) so that the data in the cache can be accessed. Corresponding to the ready state of the cache, the ready busy indication signal S1 enters the first level SH, so that the ready busy indication signal S1 has a rising edge at the beginning of the first operation recovery period P14, as shown in timing diagram 200b. Figure 1

[0094] Next, after receiving the second operation command CMD2 (e.g., at the command interface 122 in FIG. 1B), the memory device re-enters the first operation cycle C1 to operate the cache of the memory device. Similarly, corresponding to the second operation command CMD2, the data access ACS2 can be located in the first operation recovery period P14 or after the end of the first operation recovery period P14 according to different selections. Comparing timing diagram 200a and timing diagram 200b, by switching the cache to a ready state at the beginning of the first operation recovery period P14, the data access ACS1 is located in the first operation recovery period P14, and after two consecutive first operation cycles C1, the operation time RT1 can be shortened, as shown in timing diagram 200b. Figure 1

[0095] Figure 3 ​​A schematic diagram illustrating a timing comparison 300 of several different example timing diagrams (timing diagram 300a, timing diagram 300b) for read operations on a NAND memory device according to one or more embodiments of the present disclosure. Similar to... Figure 2 , Figure 3 Several example timing diagrams (timing diagram 300a, timing diagram 300b) can be applied to memory devices, and are particularly suitable for NAND memory devices (e.g., Figure 1 The following are examples of timing diagrams illustrating read operations of the memory device 100, but are not limited to these examples. Figure 3 As shown, after receiving the first operation command CMD1 as a read command (e.g., at... Figure 1 In the command interface 122, the memory device enters the first operation cycle C1 to cache the memory device (e.g., in the command interface 122). Figure 1 The first operation cycle C1 is a read operation cycle that executes a read operation command. The first operation cycle C1 may include (or be divided into) a voltage setting period P11 (e.g., high voltage set, HVSET), a first operation setting period P12 (e.g., read set, RSET), a first operation execution period P13 (e.g., read, RD), a page buffer to cache period DL2CDL (e.g., page buffer to cache, DL2CDL), and a first operation recovery period P14 (e.g., read recovery, RREC). The first operation execution period P13 also includes a first read execution period P131 (e.g., first read, RD1) and a second read execution period P132 (e.g., second read, RD2) for reading the memory cell array (e.g., ... Figure 1 Data in the memory cell array 110 is transferred to the page buffer (e.g., ...). Figure 1 (Page buffer 130 in the NAND flash memory). In some embodiments, the first operation execution period P13 may include more read execution periods (e.g., corresponding to RD1 and RD2 of a three-level cell (TLC) device), corresponding to different memory types, such as at least two read execution periods corresponding to a three-level cell (TLC) device, at least three read execution periods corresponding to a four-level cell (QLC) device, or at least four read execution periods corresponding to a five-level cell (PLC) device, etc. These read execution periods are used to read data from multiple pages in the NAND flash memory device, such as reading the low page (TLC Low Page) of a three-level cell device.

[0096] Because NAND memory devices typically include page buffers (e.g.Figure 1 The page buffer 130 is used, so in this example of a read operation for a NAND memory device, the page buffer to cache period DL2CDL is located between the first operation execution period P13 and the first operation recovery period P14, for reading data from the page buffer into the cache. The NAND memory has an internal clock CS for providing a reference clock for each period and corresponding operation.

[0097] Similar to Figure 2 Timing diagrams 200a and 200b are... Figure 3 In timing diagrams 300a and 300b, corresponding to the first operation cycle C1, the memory device cache (e.g., in...) Figure 1 The cache 140 in the image corresponds to the ready / busy indicator signal S1. The ready / busy indicator signal S1 has a first level SH and a second level SL, representing that the cache is in a ready state or a busy state, respectively. (Regarding...) Figure 3 The correspondence between the ready-to-work indicator signal S1 and the first operating cycle C1, as well as the first operating current 340 and standby current 341 of the memory device, is similar to... Figure 2 The correspondence between the ready-to-work indication signal S1 and the first operating cycle C1, as well as the first operating current 240 and standby current 241 of the memory device, will not be described further here. In some embodiments, the first operating current 340 fluctuates during NAND memory operation (e.g., corresponding to the first operating cycle C1) and is greater than or equal to a predetermined value. In an example of performing a read operation on the NAND memory, the predetermined value is 5mA.

[0098] Similar to Figure 2 In the case of, Figure 3 The difference between timing diagram 300 and timing diagram 300b is that the data output DOUT1 in the read operation (corresponding to...) Figure 2 The data access ACS1 in the cache is located either after the first operation recovery period P14 or during the first operation recovery period P14. When the data output DOUT1 is located during the first operation recovery period P14, the interval between the two first operation cycles C1 can be shortened, as shown in timing diagram 300b. Similarly, in order to make the data output DOUT1 located during the first operation recovery period P14, that is, to output the data in the cache during the first operation recovery period P14, the cache needs to be switched to the ready state at the beginning of the first operation recovery period P14 (e.g., by...). Figure 1 The operation flow controller 121 enables the data in the cache to be output. Corresponding to the ready state of the cache, the ready-busy indicator signal S1 enters the first level SH, so that the ready-busy indicator signal S1 has a rising edge at the beginning of the first operation recovery period P14, as shown in the timing diagram 300b.

[0099] Next, after receiving the second operation command CMD2 as a read command, the memory device re-enters the first operation cycle CI to operate the cache of the memory device. Similarly, corresponding to the second operation command CMD2 as a read command, the data output DOUT2 can be located in the first operation recovery period P14 or after the end of the first operation recovery period P14 according to different selections. Comparing the timing diagram 300a and the timing diagram 300b, by switching the cache to the ready state at the beginning of the first operation recovery period P14, the data output DOUT1 is located in the first operation recovery period P14, and after two consecutive first operation cycles CI, the operation time RT1 can be shortened, as shown in the timing diagram 300b. Figure 3

[0100] In contrast to switching the cache to the ready state at the end of the operation cycle, in the above example of the read operation of the NAND memory device, the technique of switching the cache to the ready state at the beginning of the operation recovery period is used, so that the data output can be performed in the operation recovery period, shortening the interval between two operation cycles and shortening the delay time of the read. Based on this, in a plurality of embodiments, the present disclosure provides a technique capable of further reducing the interval between two operation cycles to further shorten the delay time of the read, which will be described in detail below.

[0101] Figure 4 A schematic diagram illustrating an example timing diagram 400 for operations of a memory device according to one or more embodiments of the present disclosure is shown. The memory device can be the memory device 100 of Figure 1 . Similarly to the timing diagram 200b of Figure 2 In the timing diagram 400, after receiving the first operation command CMD1 (e.g., at the command interface 122 in the memory device 100 of Figure 1 ), the memory device enters the first operation cycle CI to operate the cache (e.g., the cache 140 in the memory device 100 of Figure 1 ) of the memory device. The first operation cycle CI may, for example, be an operation cycle for executing one write or read operation command. The operation cycle CI can also include (or be distinguished into) a voltage setting period P11, a first operation setting period P12, a first operation execution period P13, and a first operation recovery period P14.

[0102] Similarly to the timing diagram 200b of Figure 2 In the timing diagram 400, corresponding to the first operation cycle CI, the cache (e.g., the cache 140 in the memory device 100 of Figure 1 ​corresponds to the ready-busy indication signal S1 having the first level SH and the second level SL representing the cache being in the ready state or the busy state, respectively. The time length of the first operating current 440 of the memory device corresponds to the time length of the first operation cycle C1.

[0103] Similar to the timing diagram 200b of Figure 2 , in the timing diagram 400 of Figure 4 , in order to enable the data access ACS1 corresponding to the first operation command CMD1 to be located in the first operation recovery period P14, correspondingly, the cache is switched to the ready state (for example, by the operation flow controller 121 of Figure 1 ) at the beginning of the first operation recovery period P14, so that the data in the cache can be accessed. Different from the timing diagram 200b of Figure 2 , in order to further shorten the interval between operation cycles, in the example of the timing diagram 400 of Figure 4 , the second operation command CMD2 can be input to the memory device before the end of the first operation recovery period P14. In this case, the cache is switched to the busy state after the memory device receives the second operation command CMD2, and correspondingly, the ready-busy indication signal S1 is switched from the first level SH to the second level SL, so that the ready-busy indication signal S1 has a falling edge at the end of the second operation command CMD2, as shown in Figure 4 .

[0104] Subsequently, after the first operation recovery period P14 ends, the memory device directly enters a second operation cycle C2, which includes a second operation setup period P22, a second operation execution period P23, and a second operation recovery period P24. The time length of the second operation current 442 of the memory device corresponds to the time length of the second operation cycle C2. Unlike the first operation cycle Cl, the second operation cycle C2 does not have a voltage setup period Pl l. It can be understood that the time length of the second operation cycle C2 is less than that of the first operation cycle Cl. Since the memory device directly enters the second operation cycle C2 after the first operation recovery period P14 ends, there is no interval between the first operation cycle Cl and the second operation cycle C2, that is, the first operation recovery period P14 is adjacent to the second operation setup period P22. Therefore, the first operation current 440 and the second operation current 442 of the memory device corresponding to the first operation cycle Cl and the second operation cycle C2, respectively, are also adjacent, and there is no standby current. In such an operation, the second operation cycle C2 can not have a voltage setup period, so that the memory device directly performs the corresponding operation under a specific operation command without the need to set the voltage at the beginning of the operation cycle. Since the falling edge of the ready busy indication signal S1 corresponds to the end of the second operation command CMD2 in the first operation recovery period P14, the first operation current 440 still appears between the falling of the ready busy indication signal S1 and the end of the first operation cycle Cl. Correspondingly, the time length of the second operation current 442 is less than that of the first operation current 440. In some embodiments, the first operation current 440 and the second operation current 442 are fluctuating during the operation of the memory device (for example, corresponding to the first operation cycle Cl and the second operation cycle C2, respectively) and are greater than or equal to a predetermined value.

[0105] In the second operation cycle C2, at the beginning of the second operation recovery period P24, the cache is switched from the busy state to the ready state, so that the data in the cache can be accessed (for example, data access ACS2 in the figure), and the ready busy indication signal S1 is switched from the second level SL to the first level SH, so that the ready busy indication signal S1 has a rising edge at the beginning of the second operation recovery period P24. Similarly, the data access ACS2 corresponding to the second operation command CMD2 can be located in the second operation recovery period P24 or after the end of the second operation recovery period P24 according to different selections.

[0106] In the above example, the technology provided by the present disclosure can determine whether the memory device enters the first operation cycle after the end of the second operation command according to the time point at which the second operation command is received (determined before or after the end of the first operation recovery period). For example, in the first operation cycle Cl, the memory device enters the first operation cycle after the end of the second operation command, and in the second operation cycle C2, the memory device enters the second operation cycle after the end of the second operation command. Figure 2(as shown in timing diagram 200b) or directly enter the second operation cycle after the first operation recovery period ends (e.g., in... Figure 4 (As shown in timing diagram 400). To illustrate this decision process, refer to... Figure 5 The following explanation is provided.

[0107] Figure 5 Drawing for Figure 4 The example timing diagram 400 is a flowchart of program 500. (See example timing diagram 400 for the flowchart of program 500.) Figure 5 As shown, in step 501, the memory device receives a second operation command, and then proceeds to step 502. In step 502, it is determined whether the time point of the received second operation command is within the first operation recovery period. If not, the process proceeds to step 503 to execute the first loop (e.g., in...). Figure 2 (as shown in timing diagram 200b); if so, proceed to step 504, and execute the second operation loop after the second operation recovery period ends (e.g., in...). Figure 4 (As shown in timing diagram 400).

[0108] Figure 6 A schematic diagram of an example timing diagram 600 for a read operation of a NAND memory device according to one or more embodiments of the present disclosure is shown. Similar to... Figure 3 Timing diagram 300b, Figure 6 The example timing diagram 600 in the diagram can be applied to memory devices, and is particularly suitable for NAND memory devices (e.g., Figure 1 The timing diagram 600 illustrating a read operation of a memory device 100 is provided as an example, but is not limited thereto. Figure 6 As shown, after receiving the first operation command CMD1 as a read command (e.g., at... Figure 1 In the command interface 122, the memory device enters the first operation cycle C1 to cache the memory device (e.g., in the command interface 122). Figure 1read operation. The first operation cycle CI is a read operation cycle that performs one read operation command. The first operation cycle CI can include (or be distinguished into) a voltage set period P11 (e.g., high voltage set, HVSET), a first operation set period P12 (e.g., read set, RSET), a first operation perform period P13 (e.g., read, RD), a page buffer to cache period DL2CDL (e.g., page buffer to cache, DL2CDL), and a first operation recovery period P14 (e.g., read recovery, RREC). The first operation perform period P13 further includes a first read perform period P131 (e.g., first read, RD1) and a second read perform period P132 (e.g., second read, RD2) for reading data from the memory cell array (e.g., memory cell array 110 in Figure 1 ) in the memory device and transferring the data to the page buffer (e.g., page buffer 130 in Figure 1 ). In some embodiments, the first operation perform period P13 can include more read perform periods (e.g., RD1 and RD2 corresponding to a triple-level cell (TLC) device), corresponding to different memory types, such as at least two read perform periods for a triple-level cell (TLC) device, at least three read perform periods for a quad-level cell (QLC) device, or at least four read perform periods for a penta-level cell (PLC) device, and so on. These read perform periods are for reading data for multiple pages in the NAND memory device, such as reading a low page (TLC Low Page) for a triple-level cell device.

[0109] Since a NAND memory device typically includes a page buffer (e.g., page buffer 130 in Figure 1 ), in this example for a read operation for a NAND memory device, the page buffer to cache period DL2CDL is included between the first operation perform period P13 and the first operation recovery period P14 for reading data from the page buffer to the cache.

[0110] Similar to timing diagram 400 of Figure 4 , in timing diagram 600 of Figure 6 , corresponding to the first operation cycle CI, the cache of the memory device (e.g., cache 140 in Figure 1 ) corresponds to a ready busy indication signal SI, which has a first level SH and a second level SL, representing the cache being in a ready state or a busy state, respectively. With respect to Figure 6the ready busy indication signal S1 in the first operation cycle C1, the second operation cycle C2, and the corresponding relationship between the first operation current 640 and the second operation current 642 of the memory device, similar to Figure 4 the ready busy indication signal S1, the first operation cycle C1, the second operation cycle C2, and the corresponding relationship between the first operation current 440 and the second operation current 442 of the memory device, which is not further described herein.

[0111] Similar to the case in Figure 4 , in the timing diagram 600, in order to have the data corresponding to the first operation command CMD1 output in the first operation recovery period P14, the cache is correspondingly switched to the ready state at the beginning of the first operation recovery period P14 (e.g., by the operation flow controller 121 of Figure 1 ), so that the data in the cache can be output. Also, in order to further shorten the interval between the operation cycles (the first operation cycle C1 and the second operation cycle C2), in the example of the timing diagram 600, the second operation command CMD2 as a read command can be input to the NAND memory device before the end of the first operation recovery period P14. In this case, the cache is switched to the busy state after the memory device receives the second operation command CMD2, and the corresponding ready busy indication signal S1 is switched from the first level SH to the second level SL, so that the ready busy indication signal S1 has a falling edge at the end of the second operation command CMD2, as shown in Figure 6 .

[0112] Then, after the end of the first operation recovery period P14, the memory device directly enters the second operation cycle C2. Similar to the first operation cycle C1, the second operation cycle C2 can include (or be divided into) a second operation setting period P22 (e.g., read set, RSET), a second operation execution period P23 (e.g., read, RD), a page buffer to cache period DL2CDL (e.g., page buffer to cache, DL2CDL), and a second operation recovery period P24 (e.g., read recovery, RREC). The time length of the second operation current 642 of the NAND memory device corresponds to the time length of the second operation cycle C2. The second operation execution period P23 further includes a third read execution period P231 and a fourth read execution period P232 for reading data in the memory cell array (e.g., the memory cell array 110 in Figure 1 ) and transferring to the page buffer (e.g., the page buffer 120 in Figure 1The second operation execution period P23 of the second operation cycle C2 can include more read execution periods (e.g., RD1 and RD2 corresponding to a three-level cell (TLC) device) corresponding to different memory types, such as at least two read execution periods corresponding to a three-level cell (TLC) device, at least three read execution periods corresponding to a quad-level cell (QLC) device, or at least four read execution periods corresponding to a penta-level cell (PLC) device, and so forth. These read execution periods are used to read data for multiple pages in the NAND memory device, such as reading a low page (TLC Low Page) of a three-level cell device.

[0113] Likewise, since a NAND memory device typically includes a page buffer (e.g., page buffer 130 of FIG. 1 Figure 1 Thus, in the example of a read operation for a NAND memory device herein, a page buffer to cache period DL2CDL is included between the second operation execution period P23 and the second operation recovery period P24 for reading data from the page buffer into the cache.

[0114] Unlike the first operation cycle CI, the second operation cycle C2 does not have the voltage setting period Pll. It is appreciated that the second operation cycle C2 is shorter than the first operation cycle CI. Since the memory device enters the second operation cycle C2 directly after the end of the first operation resume period P14, there is no gap between the first operation cycle CI and the second operation cycle C2, i.e., the first operation resume period P14 is adjacent to the second operation setting period P22. Therefore, the first operation current 640 corresponding to the first operation cycle CI and the second operation current 642 corresponding to the second operation cycle C2 are also adjacent, and there is no standby current therebetween. In such an operation, the second operation cycle C2 can not have a voltage setting period, so that the memory device can perform the corresponding operation directly under the specific operation command without the need of voltage setting at the beginning of the operation cycle. Correspondingly, the second operation current 642 is shorter than the first operation current 640. In some embodiments, the first operation current 640 and the second operation current 642 are fluctuating during the NAND memory operation (e.g., corresponding to the first operation cycle CI and the second operation cycle C2, respectively) and are greater than or equal to a predetermined value. In the example of read operation on the NAND memory, the predetermined value is 5 mA. Since the falling edge of the ready / busy indication signal SI corresponds to the end of the second operation command CMD2 in the first operation resume period P14, the operation current 640 still appears between the falling of the ready / busy indication signal SI and the end of the first operation cycle CI, i.e., there is an operation current 640 greater than or equal to the predetermined value 5 mA between the falling of the ready / busy indication signal SI and the end of the first operation cycle CI, instead of the standby current (e.g., as shown in the timing diagram 300a and the timing diagram 300b in Figure 3

[0115] In the second operation cycle C2, at the beginning of the second operation resume period P24, the cache is switched from the busy state to the ready state, so that the data in the cache can be outputted. Correspondingly, the ready / busy indication signal SI is switched from the second level SL to the first level SH, so that the ready / busy indication signal SI has a rising edge at the beginning of the second operation resume period P24. Similarly, the data output DOUT2 can be selected to be in the second operation resume period P24 or after the end of the second operation resume period P24 according to different second operation commands CMD2.

[0116] ​It is understood that, although not shown in the figures, according to the technology provided in this disclosure, in the second operation cycle C2, if the memory device receives the next operation command before the end of the second operation recovery period P24, then the second operation cycle C2 begins after the end of the second operation recovery period P24; if it receives the next operation command after the end of the second operation recovery period P24, then the first operation cycle C1 begins upon receiving the next operation command. The elements of the memory device perform corresponding functions according to the aforementioned correspondence, which will not be described in detail here.

[0117] Figure 7 Drawing based on Figure 3 and Figure 6 A schematic diagram of timing comparison 700 for several different example timing diagrams (timing diagram 700a, timing diagram 700b, timing diagram 700c) used for read operations on NAND memory devices. Similar to Figure 3 Timing diagrams 300a, 300b and Figure 6 The timing diagram 600, Figure 7 Timing diagrams 700a, 700b, and 700c can be applied to memory devices, and are particularly suitable for NAND memory devices (e.g., Figure 1 The following timing diagrams 700a, 700b, and 700c illustrate example read operations of memory device 100, but are not limited to these examples. Figure 7 As shown, timing diagram 700a (similar to Figure 3 Timing diagram 300a), timing diagram 700b (similar to...) Figure 3 Timing diagram 300b) and timing diagram 700c (similar to) Figure 6the time point of the second operation command CMD2 being received (in timing diagram 700a and timing diagram 700b, the second operation command CMD2 is received after the end of the first operation recovery period P14, while in timing diagram 700c, the second operation command CMD2 is received during the first operation recovery period P14) causes a difference in the time required to perform two operation cycles (two first operation cycles C1 in timing diagram 700a and timing diagram 700b, and a first operation cycle C1 and a second operation cycle C2 in timing diagram 700c). As shown in the figures, in this example of a read operation for a NAND memory device, timing diagram 700b has a shortened operation time RT1 compared to timing diagram 700a, while timing diagram 700c has a shortened operation time RT2 compared to timing diagram 700a, and the shortened operation time RT2 is greater than the shortened operation time RT1, that is, more read operation time is saved in timing diagram 700c, and the read latency of the memory device is reduced.

[0118] In some embodiments, the first operation command (e.g., first operation command CMD1) and the second operation command (e.g., second operation command CMD2) received by the memory device (e.g., memory device 100) can be write commands, and the memory device can also reduce the latency of a write operation (e.g., using a first operation cycle C1 or a second operation cycle C2 as in FIG. 7) by the time point at which the write command is received (e.g., after the operation recovery period or during the operation recovery period). Figure 1 Figure 2 Figure 4 Figure 2 Figure 4 Figure 4 Figure 4

[0119] ​​​​​​​According to the above embodiments and examples, the technology provided by the present disclosure can be used to reduce the delay of memory access operations according to the requirements or specific operation commands and the timing points of receiving the operation commands to cooperate with different operation cycles.

[0120] The present disclosure and other examples can be implemented as one or more computer program products, e.g., one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination of one or more of them. The term "data processing apparatus" encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0121] A computer program (also known as a program, software, software application, instructions for operation, or program code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more instructions stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of programs). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and are interconnected by a communication network.

[0122] The programs and logic flows described herein can be executed by one or more programmable processors that execute one or more computer programs to perform the functions described herein. The programs and logic flows can also be executed by special purpose logic circuitry, and the devices can also be implemented by special purpose logic circuitry, for example, field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs).

[0123] Processors suitable for executing computer programs include, for example, both general-purpose microprocessors and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor receives instructions and data from read-only memory or random access memory, or both. The basic elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer may also include or be operatively coupled to one or more mass storage devices for storing data, to receive data from, or to transfer data to, or both of these mass storage devices. Examples of such mass storage devices are magnetic disks, magneto-optical disks, or optical disks. However, a computer does not necessarily need to have such devices. Computer-readable media suitable for storing computer program instructions and data may include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks. Processors and memory may be supplemented by or incorporated into special-purpose logic circuitry.

[0124] While this document may describe many details, these details should not be construed as limiting the scope of the invention as claimed or potentially claimed, but rather as descriptions of features specific to particular embodiments. Certain features described herein in separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although multiple features may be described above as operating in certain combinations and even initially claimed in this manner, one or more features from the claimed combinations may in some cases be excluded from the said combinations, and the claimed combinations may be for sub-combinations or variations thereof. Similarly, although multiple operations are depicted in a specific order in the drawings, it should not be construed that these operations must be performed in the specific order shown or in sequential order, or that all described operations must be performed to achieve the desired result.

[0125] Only a few examples and implementations are described. Variations, modifications, and enhancements of the described examples and implementations and other implementations can occur based on the disclosure.

[0126] In view of the foregoing, it will be seen that the several advantages of the application are achieved and other advantages attained. Certain changes can be made in the above process without departing from the spirit and scope of the application and, accordingly, reference should be made to the appended claims for an understanding of the full scope of the application.

Claims

1. A method of operating a memory device, comprising: After receiving a first operation command, the memory device begins a first operation cycle, which includes a voltage setting period, a first operation setting period, a first operation execution period, and a first operation recovery period. At the start of this voltage setting period, the cache enters a busy state; During the execution of the first operation, the cache receives data; At the start of the first operation recovery period, the cache ends the busy state and switches to a ready state, in which the data in the cache can be accessed; as well as When the memory device receives a second operation command before the end of the first operation recovery period, the memory device directly enters a second operation cycle after the end of the first operation recovery period. The second operation cycle includes a second operation setting period, a second operation execution period, and a second operation recovery period. The first operation recovery period is adjacent to the second operation setting period. During the second operation recovery period, the cache switches from the busy state to the ready state, making the data in the cache accessible.

2. The operation method according to claim 1, wherein when the memory device receives the second operation command after the first operation recovery period ends, the memory device re-enters the first operation cycle after receiving the second operation command, and the cache switches to the busy state; in, The second operation cycle has a shorter duration than the first operation cycle.

3. The operation method according to claim 2, wherein the cache corresponds to a ready-busy indicator signal, and when the ready-busy indicator signal is at a first level, it indicates that the cache is in the ready state, and when the ready-busy indicator signal is at a second level, it indicates that the cache is in the busy state; in, The multiple falling edges of the ready-to-work indicator signal switching from the first level to the second level correspond to the start of the voltage setting period and the end of the first operation command, or to the end of the second operation command during the first operation recovery period. The multiple rising edges of the busy status indicator signal switching from the second level to the first level correspond to the start of the first operation recovery period and the start of the second operation recovery period.

4. The operation method according to claim 3, wherein the duration of a first operating current of the memory device corresponds to the duration of the first operating cycle; in, When the second operation command is received after the first operation recovery period ends, the duration of a standby current of the memory device corresponds to the time between the end of the first operation recovery period and the end of the second operation command. The time length between two adjacent falling edges of the ready-to-work indicator signal corresponds to the sum of the operating current and the standby current of the memory device.

5. The operation method according to claim 4, when the second operation command is received before the end of the first operation recovery period, the cache enters the busy state after receiving the second operation command; The duration of a second operating current of the memory device corresponds to the duration of the second operating cycle, and one of the falling edges of the ready-busy indicator signal corresponds to the end of the second operating command during the first operating recovery period, such that the duration between two adjacent falling edges of the ready-busy indicator signal is shorter than the duration of the first operating current of the memory device.

6. The method of operation according to claim 3, wherein the memory device is a NAND memory device, the NAND memory device includes a page buffer, the first operation cycle further includes a first page buffer to cache period, the first page buffer to cache period being located between the first operation execution period and the first operation recovery period, during the first page buffer to cache period, data is transferred between the page buffer and the cache.

7. The operation method of claim 6, wherein the NAND memory device includes a memory cell array, the first operation command includes a first read command, and the first operation execution period includes at least a first read execution period and a second read execution period for reading data in the memory cell array and transmitting it to the page buffer, and during the first operation recovery period, the data in the cache is output.

8. The method of operation according to claim 6, wherein the NAND memory device includes a memory cell array, the second operation command includes a second read command, the second operation cycle further includes a second page buffer to cache period, the second page buffer to cache period being located between the second operation execution period and the second operation recovery period, during the second page buffer to cache period, data is transferred between the page buffer and the cache.

9. The operating method according to claim 8, wherein, The second operation execution period includes at least a third read execution period and a fourth read execution period for reading data in the memory cell array and transferring it to the page buffer, and during the second operation recovery period, the data in the cache is output.

10. The operation method of claim 8, wherein the duration of a first operating current of the NAND memory device corresponds to the duration of the first operating cycle; in, When the second read command is received before the end of the first operation recovery period, one of the falling edges of the ready-busy indicator signal of the memory device corresponds to the end of the second read command in the first operation recovery period, such that the first operating current still appears between the fall of the ready-busy indicator signal and the end of the first operation cycle, and the first operating current is greater than or equal to a predetermined value.

11. The method of operation according to claim 2, wherein the memory device is a NOR memory device, the NOR memory device further includes a register, and the first operation command includes a first read command, wherein during the execution of the first operation, data in the register is read into the cache, and during the recovery of the first operation, the data in the cache is output.

12. The method of operation according to claim 2, wherein the memory device is a NOR memory device, the NOR memory device further includes a register, and the second operation command includes a second read command, wherein during the execution of the second operation, data in the register is read into a cache, and during the recovery of the second operation, the data in the cache is output.

13. The operating method according to claim 2, wherein, The first operation command includes a first write command, and during the first operation recovery, the data in the cache is written to the memory device; The second operation command includes a second write command, and during the second operation recovery period, the data in the cache is written to the memory device.

14. A memory device, comprising: An array of memory cells used to store data; A control circuit is coupled to the memory cell array, the control circuit including a command interface and an operation flow controller; as well as A cache is coupled to the memory cell array and the control circuit. Wherein, after the operation process controller receives a first operation command through the command interface, the control circuit controls the memory device to start a first operation cycle. The first operation cycle includes a voltage setting period, a first operation setting period, a first operation execution period, and a first operation recovery period. The process controller controls the cache to perform the following operations: At the start of the voltage setting period, the cache enters a busy state; During the execution of the first operation, the cache receives data; At the start of the first operation recovery period, the cache ends its busy state and switches to a ready state, in which data in the cache becomes accessible; and When the command interface receives a second operation command before the end of the first operation recovery period, the control circuit controls the memory device to directly enter a second operation cycle after the end of the first operation recovery period. The second operation cycle includes a second operation setting period, a second operation execution period, and a second operation recovery period. The first operation recovery period is adjacent to the second operation setting period. At the start of the second operation recovery period, the process controller switches the cache from the busy state to the ready state, so that the data in the cache can be accessed.

15. The memory device of claim 14, wherein the memory device is a NAND memory device, the NAND memory device further comprising: A page buffer is coupled between the cache and the memory cell array; as well as A data input / output circuit is coupled to this cache; The first operation command includes a first read command.

16. The memory device of claim 15, wherein the first operation cycle further includes a first page buffer to cache period between the first operation recovery period and the first operation execution period, during which data is transferred between the page buffer and the cache.

17. The memory device of claim 16, wherein the first operation execution period includes at least a first read execution period and a second read execution period for reading data in the memory cell array and transferring it to the page buffer, and during the first operation recovery period, the data in the cache is output to the data input / output circuit.

18. The memory device of claim 15, wherein the second operation command includes a second read command, wherein the second operation cycle further includes a second page buffer to cache period between the second operation recovery period and the second operation execution period, during which data is transferred between the page buffer and the cache.

19. The memory device of claim 18, wherein the second operation execution period includes at least a third read execution period and a fourth read execution period for reading data in the memory cell array and transferring it to the page buffer, and during the second operation recovery period, the data in the cache is output to the data input / output circuit.

20. The memory device of claim 16, wherein the duration of a first operating current of the NAND memory device corresponds to the duration of the first operating cycle; in, When the second read command is received before the end of the first operation recovery period, a falling edge of a ready-busy indicator signal of the memory device corresponds to the end of the second read command in the first operation recovery period, so that the first operating current still appears between the falling edge of the ready-busy indicator signal and the end of the first operation cycle, and the first operating current is greater than or equal to a predetermined voltage difference.

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