Calibration method of memory and storage device

Abstract

The application discloses a memory calibration method and a storage device, relates to the technical field of storage, and systematically calibrates reference voltage, receiving delay and sending delay of a first signal, and receiving delay and sending delay of each data line through staged steps, so that the influence caused by individual differences of memory hardware and other factors can be effectively eliminated, data can be accurately sampled and recognized in the transmission process, the data read / write error rate is greatly reduced, and the data transmission reliability is improved. Meanwhile, by extending the reference voltage range and testing multiple preset delay values, the target receiving delay and sending delay of the reference voltage, the first signal and each data line can be screened out, which are most suitable for the current memory work, and the storage performance of the memory is effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, and particularly relates to a calibration method of a memory and a storage device. BACKGROUND

[0002] With the rapid development of information technology, the performance and reliability of the memory as the core component of data storage and processing are crucial to the operation of the entire electronic system. In the related art, the memory runs by using preset fixed working parameters.

[0003] However, the fixed working parameters are difficult to cover different hardware configurations, so that the running states of different batches of memories are unstable, resulting in poor storage performance of part of the memories. SUMMARY

[0004] The present application provides a calibration method of a memory and a storage device to at least solve the problem of poor storage performance of the memory in the related art.

[0005] The present application provides a calibration method of a memory, comprising:

[0006] determining an initial reference voltage and a first receiving delay of each data line in the memory, the first receiving delay being determined based on a second receiving delay of a first signal, the first signal being used for synchronous data transmission;

[0007] extending the initial reference voltage to obtain a plurality of first reference voltages, and determining a second reference voltage for data reading of the memory and a target receiving delay of the first signal based on the plurality of first reference voltages, a plurality of preset receiving delays of the first signal and the first receiving delay of each data line;

[0008] calibrating the first receiving delay of each data line based on the second reference voltage and the target receiving delay of the first signal to obtain a target receiving delay of each data line;

[0009] calibrating a sending delay of the first signal and a sending delay of each data line based on the second reference voltage, the target receiving delay of the first signal and the target receiving delay of each data line.

[0010] The present application also provides a calibration device of a memory, comprising:

[0011] a determining module configured to determine an initial reference voltage and a first receiving delay of each data line in the memory, the first receiving delay being determined based on a second receiving delay of a first signal, the first signal being used for synchronous data transmission;

[0012] The processing module is configured to perform extension processing on the initial reference voltage to obtain a plurality of first reference voltages, and determine a second reference voltage for data reading of the memory and a target receiving delay of the first signal based on the plurality of first reference voltages, a plurality of preset receiving delays of the first signal, and a first receiving delay of each data line.

[0013] The calibration module is configured to calibrate the first receiving delay of each data line based on the second reference voltage and the target receiving delay of the first signal to obtain a target receiving delay of each data line.

[0014] The calibration module is further configured to calibrate a sending delay of the first signal and a sending delay of each data line based on the second reference voltage, the target receiving delay of the first signal, and the target receiving delay of each data line.

[0015] The application further provides an electronic device, including a memory configured to store a computer program, and a processor configured to execute the computer program to implement the steps of the calibration method of the memory.

[0016] The application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the calibration method of the memory.

[0017] The application further provides a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the steps of the calibration method of the memory.

[0018] The calibration method of the memory and the storage device provided by the application can effectively eliminate the influence of factors such as individual differences of the memory hardware, ensure that the data is accurately sampled and recognized in the transmission process, greatly reduce the data read / write error rate, and improve the data transmission reliability. Meanwhile, by extending the reference voltage range and testing a plurality of preset delay values, the most suitable reference voltage, target receiving delay and sending delay of the first signal, and target receiving delay and sending delay of each data line for the current memory can be screened out, and the storage performance of the memory is effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0020] Figure 1A flowchart of a calibration method of a memory provided by an embodiment of the present application Figure 1 ;

[0021] Figure 2 A flowchart of a calibration method of a memory provided by an embodiment of the present application Figure 2 ;

[0022] Figure 3 A schematic diagram of a target receiving delay of a second reference voltage and a first signal provided by an embodiment of the present application

[0023] Figure 4 A schematic diagram of a target sending delay of a fourth reference voltage and a first signal provided by an embodiment of the present application

[0024] Figure 5 A structural schematic diagram of a calibration device of a memory provided by an embodiment of the present application

[0025] Figure 6 A structural schematic diagram of a storage device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, any other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0027] It should be noted that, in the description of the present application, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0028] The storage device includes a memory and a processor, and the processor controls the memory to perform read and write operations according to working parameters (for example, driving strength, on-chip terminal resistance, reference voltage, receiving delay and sending delay, etc.), so that appropriate working parameters can effectively improve the storage performance of the memory.

[0029] In the related art, a manufacturer of a storage device selects a small number of samples from a large number of finished storage devices, tests and calibrates the samples to obtain fixed working parameters, and writes the fixed working parameters into the storage device. When the storage device is powered on each time, the processor calls the fixed working parameters to control the storage to perform read and write operations.

[0030] However, due to the limited number of test samples and the hardware differences between the processors and memories of different batches of storage devices, the fixed working parameters cannot be applied to each storage device, resulting in poor storage performance of part of the memory.

[0031] To solve the above technical problems, the following technical concept is proposed: Since the fixed working parameters do not take into account the individual differences of the memory, the fixed working parameters can be calibrated based on the hardware of the storage device when the storage device is powered on, to obtain working parameters more suitable for the memory, thereby improving the storage performance of the memory.

[0032] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Figure 1 Flowchart of the calibration method of the memory provided by the embodiments of the present application Figure 1 The embodiments of the present application provide a calibration method of a memory applied to any storage device. As shown in Figure 1 The method comprises the following steps.

[0034] In a possible implementation, before S101, the pre-stored test data in the memory is subjected to write data test and read data test to obtain an error code number, and the read-write speed of the memory is less than a first threshold. If the error code number is less than or equal to a second threshold, it is determined that the hardware of the memory is normal. If the error code number is greater than the second threshold, it is determined that the hardware of the memory is abnormal, and the calibration of the memory is terminated.

[0035] In the low-speed scenario where the read-write speed of the memory is less than the first threshold, by performing write and read tests on the pre-stored test data and counting the error code number, it can not only exclude non-hardware essential problem interference in the low-speed environment to accurately judge whether the hardware of the memory is normal, but also terminate invalid calibration in advance when the hardware is abnormal to save system resources and improve process efficiency. In addition, it can avoid subsequent data risks caused by hardware failure from the source, and the low complexity of low-speed testing also reduces the cost of testing and calibration, thereby providing an efficient, reliable and economical solution for hardware "admission screening" before calibration of the memory.

[0036] S101, determine an initial reference voltage and a first receiving delay of each data line in the memory, the first receiving delay being determined based on a second receiving delay of a first signal, the first signal being used for synchronizing data transmission.

[0037] The reference voltage is used as a reference voltage for judging the high and low level state of the data signal, and is used to determine whether the signal transmitted in the Q channel is logic "0" or logic "1". The data line is used to indicate the physical line in the memory for transmitting data, and each data line corresponds to an independent data transmission channel. The first receiving delay is used to indicate the delay parameter of the data line when receiving data, which is used to ensure that the data is sampled in the correct time window. The first signal is used to indicate the clock signal or control signal of the synchronous data transmission, which ensures the timing consistency of data transmission and reception. The second receiving delay is used to indicate the receiving delay of the first signal itself, which is the reference for determining the receiving delay of the data line.

[0038] Specifically, the initial reference voltage is usually determined based on fixed operating parameters. Since the first signal is the synchronization reference of data transmission, the second receiving delay will directly affect the receiving timing of the data line. Therefore, the second receiving delay of the first signal is obtained first, and then the first receiving delay of each data line is calculated or measured based on this reference, to ensure that the initial receiving timing of the data line matches the synchronization signal.

[0039] For example, the initial reference voltage can be set to 0.5V (assuming the power supply voltage is 1V, taking the middle value as the reference). The first signal is a data strobe signal (DataStrobe, DQS), and its second receiving delay is measured to be 5ns. For 8 data lines (DQ0-DQ7, DQ indicating data line) of the memory, the first receiving delay of each data line needs to be adjusted based on the 5ns delay of DQS, for example, the first receiving delay of DQ0 is finally determined to be 5.2ns, the first receiving delay of DQ1 is 4.9ns, etc., to preliminarily ensure the synchronization of data and DQS signal.

[0040] In one possible implementation, each preset receiving delay is traversed, the memory is read data bus trained, the middle value of the maximum receiving delay and the minimum receiving delay of the successful read data bus training is determined as the second receiving delay of the first signal, and the read and write rate of the memory is greater than or equal to a first threshold; based on the second receiving delay of the first signal, the memory is read data bus trained, and the successful receiving delay is determined as the first receiving delay of each data line in the memory.

[0041] S102, the initial reference voltage is expanded to obtain a plurality of first reference voltages, and based on the plurality of first reference voltages, a plurality of preset receiving delays of the first signal and the first receiving delay of each data line, a second reference voltage for data reading of the memory and a target receiving delay of the first signal are determined.

[0042] The extension processing is used to indicate that the initial reference voltage is adjusted up and down to generate a series of different voltage values to cover the possible voltage fluctuation range. The first reference voltage is used to indicate a plurality of reference voltages obtained after the extension processing, which are used to test the performance of the memory under different voltages. The preset receiving delay is used to indicate a series of delay values preset for the first signal, which are used to test the synchronization effect under different timings. The second reference voltage is used to indicate the reference voltage determined after testing and verification for data reading, which has higher stability and compatibility. The target receiving delay of the first signal is used to indicate the optimal receiving delay of the first signal determined after testing, which ensures the timing accuracy of the synchronization signal.

[0043] Specifically, the initial reference voltage is extended to generate a plurality of first reference voltages. A plurality of preset receiving delays are set for the first signal. In the first reference voltage, the data reading test is performed in combination with the preset receiving delay of the first signal and the first receiving delay of each data line. According to the test result, the voltage value (i.e., the second reference voltage) that makes the data reading most stable and the delay value (i.e., the target receiving delay of the first signal) of the first signal are selected.

[0044] For example, the first signal is a DQS signal, and the initial reference voltage 0.5V is extended to obtain five first reference voltages 0.3V, 0.4V, 0.5V, 0.6V, and 0.7V. Five preset receiving delays 3ns, 4ns, 5ns, 6ns, and 7ns are set for the DQS signal. When the DQS delay is 5ns under the voltage 0.5V, the data reading error rate is 0. However, even if the DQS delay is adjusted to 6ns under the voltage 0.3V, the error rate is still high. Finally, the second reference voltage is selected as 0.5V, and the target receiving delay of the DQS is 5ns.

[0045] S103, based on the second reference voltage and the target receiving delay of the first signal, calibrating the first receiving delay of each data line to obtain a target receiving delay of each data line.

[0046] The calibration is used to indicate that the delay parameter of the data line is adjusted according to the determined reference parameter (the second reference voltage and the target receiving delay of the first signal) to eliminate the timing deviation caused by individual differences or environmental interference. The target receiving delay of the data line is used to indicate the optimal receiving delay of the data line after calibration, which ensures that each data line can accurately receive data under the second reference voltage and the target delay of the first signal.

[0047] Specifically, on the basis of the determined second reference voltage and the target receiving delay of the first signal, the first receiving delay of each data line is tested one by one to see whether it can meet the requirement of accurate data receiving. Due to the difference in physical characteristics of different data lines, even if the initial delay is the same, the actual receiving effect can be different. Therefore, the receiving delay of each data line needs to be fine-tuned until each data line can stably receive data under the current voltage and synchronous signal delay, and finally the target receiving delay of each data line is obtained.

[0048] For example, the first signal is a DQS signal. On the basis of the second reference voltage of 0.5 V and the target receiving delay of the DQS signal of 5 ns, it is found that when the first receiving delay of DQ0 is 5.2 ns, there is an occasional error, which is eliminated after being adjusted to 5.3 ns; when the first receiving delay of DQ1 is 4.9 ns, the signal is unstable, which returns to normal after being adjusted to 4.8 ns. Finally, it is determined that the target receiving delay of DQ0 is 5.3 ns, and the target receiving delay of DQ1 is 4.8 ns, and so on to complete the calibration of each data line.

[0049] S104, based on the second reference voltage, the target receiving delay of the first signal and the target receiving delay of each data line, the sending delay of the first signal and the sending delay of each data line are calibrated.

[0050] The sending delay is used to indicate the delay required for data to be transmitted from the sending end to the receiving end, which together with the receiving delay determines the complete transmission timing. The sending delay of the first signal is used to indicate the delay of the first signal from the sending end to the receiving end, which needs to be matched with the receiving delay to ensure the synchronization accuracy. The sending delay of the data line is used to indicate the sending delay of the data signal on the data line, which needs to be matched with its target receiving delay to ensure the correct overall transmission timing.

[0051] Specifically, on the basis of the determined second reference voltage, the target receiving delay of the first signal and the target receiving delay of each data line, the sending delay of the first signal and the sending delay of each data line are adjusted respectively. For the first signal, the sum of the sending delay and the target receiving delay needs to meet the timing requirement of the system design. For each data line, the sending delay needs to be matched with its target receiving delay to ensure the stable total delay of the data signal from sending to receiving, and finally the timing of the sending end and the receiving end is completely matched to ensure the reliability of data transmission.

[0052] For example, it is assumed that the system requires the total delay of the DQS signal to be 10 ns, and the target receiving delay of the DQS signal is known to be 5 ns, so the sending delay of the DQS signal needs to be calibrated to 5 ns. For DQ0, the target receiving delay is 5.3 ns, and if the total delay of the data signal is required to be 11 ns, the sending delay of DQ0 needs to be calibrated to 5.7 ns to ensure the timing consistency of data sending and receiving.

[0053] In a possible implementation, a preset sending delay is traversed, a middle value of a maximum sending delay and a minimum sending delay successfully written in the write data bus training is determined as the sending delay of the first signal by performing the write data bus training on the memory; and based on the sending delay of the first signal, the memory is subjected to the write data bus training, and a sending delay successfully written is determined as the sending delay of each data line.

[0054] In a possible implementation, between the steps of S101 to S104, the processor in the storage device performs at least one of long zero quantization calibration and short zero quantization calibration on the memory; and differential clock calibration is performed on the memory.

[0055] The calibration method of the memory provided by the embodiments of the present application can effectively eliminate the influence of individual differences of the memory hardware and other factors, ensure that the data is accurately sampled and recognized in the transmission process, greatly reduce the data read / write error rate, and improve the data transmission reliability. Meanwhile, by expanding the reference voltage range and testing multiple preset delay values, the most suitable reference voltage, target receiving delay and sending delay of the first signal, and target receiving delay and sending delay of each data line for the current memory can be screened out, effectively improving the storage performance of the memory.

[0056] Figure 2 Flowchart of the calibration method of the memory provided by the embodiments of the present application Figure 2 As shown in Figure 2 , the method comprises:

[0057] S201, determining an initial reference voltage and a first receiving delay of each data line in the memory, the first receiving delay being determined based on a second receiving delay of a first signal, the first signal being used for synchronizing data transmission.

[0058] S202, performing extension processing on the initial reference voltage to obtain multiple first reference voltages.

[0059] S203, performing data read test on the memory based on the multiple first reference voltages, multiple preset receiving delays of the first signal, and the first receiving delay of each data line, to obtain multiple data read results of the multiple preset receiving delays corresponding to each first reference voltage.

[0060] The data read test is used to indicate sending a read instruction (for example, ChangeReadColumn (random data out)) to the memory, and a verification process of checking whether the data read result is correct. The data read result is used to indicate the output of the data read test, and is usually "correct" or "incorrect", which is used to judge the effectiveness of the current parameter combination.

[0061] S204. Based on multiple data reading results of multiple preset receiving delays corresponding to each first reference voltage, determine a second reference voltage among multiple first reference voltages.

[0062] Specifically, based on the test results corresponding to each first reference voltage, the most suitable data reading reference voltage, i.e., the second reference voltage, is selected from multiple first reference voltages. Based on the determined second reference voltage, the optimal value is selected from its corresponding preset receiving delay as the target receiving delay of the first signal.

[0063] In one possible implementation, for any first reference voltage, a plurality of preset receiving delays for which the data reading result is correct are determined, and the difference between the maximum and minimum values ​​among the plurality of preset receiving delays for which the data reading result is correct is determined; among the plurality of differences, the largest difference is determined, and the first reference voltage corresponding to the largest difference is determined as the second reference voltage.

[0064] Specifically, Figure 3 A schematic diagram of the second reference voltage and the target reception delay of the first signal provided in the embodiments of this application is shown below. Figure 3 As shown, for the first reference voltage, preset receiving delays that ensure correct data reading are first selected, and the difference between the maximum and minimum values ​​of these delays is calculated. Then, the differences corresponding to each first reference voltage are compared, and the reference voltage with the largest difference is selected as the second reference voltage. The larger the difference, the higher the tolerance of the reference voltage to fluctuations in the first signal delay, and the better it can adapt to timing deviations in actual operation, resulting in stronger stability.

[0065] In one possible implementation, a first interval is determined based on multiple preset reception delays where the data reading result corresponding to the second reference voltage is correct; the preset reception delay corresponding to the midpoint of the first interval is determined as the target reception delay of the first signal.

[0066] Specifically, such as Figure 3 As shown, the first interval is the interval between the maximum preset reception delay and the minimum preset reception delay corresponding to the second reference voltage when the data reading result is correct. The target reception delay of the first signal is the midpoint of the first interval, that is, the midpoint between the minimum and maximum values.

[0067] In one possible implementation, multiple third reception delays corresponding to the data line are determined; based on the second reference voltage, the target reception delay of the first signal, and the multiple third reception delays, a data read test is performed on the memory to obtain the data read results for each third reception delay; based on the third reception delay where the data read results are correct, the target reception delay of the data line is determined.

[0068] Specifically, short zero-ohm calibration is performed. A series of preset reception delay values of a single data line are determined as a plurality of third reception delays, and the third reception delays are used to test the reception effect of the data line at different delays. In the fixed condition of the second reference voltage and the first signal target reception delay, data read test is performed in combination with the third reception delay, and it is recorded which delay value corresponds to correct read result. According to the third reception delay corresponding to the correct result, the target reception delay of the data line is determined.

[0069] For example, taking the DQ0 data line as an example, the first reception delay thereof is 5.2 ns, and the third reception delays are set as 5.0 ns, 5.1 ns, 5.2 ns, 5.3 ns and 5.4 ns. In the condition of the second reference voltage 0.5 V and the first signal target delay 5 ns, it is found that the read is correct at 5.1 ns, 5.2 ns and 5.3 ns. Based on these results, the target reception delay of the DQ0 can be determined.

[0070] In a possible implementation, a second interval is determined based on the third reception delay at which the data read result is correct; and the third reception delay corresponding to the midpoint of the second interval is determined as the target reception delay of the data line.

[0071] The second interval is used to indicate a continuous range (from the minimum value to the maximum value) of the third reception delays at which the data read is correct for a single data line in the read test.

[0072] Specifically, for a single data line, a continuous second interval (such as from the minimum delay value to the maximum delay value) is determined according to the third reception delays at which the data read is correct. The midpoint of the second interval is calculated, and the delay value corresponding to the midpoint is taken as the target reception delay of the data line.

[0073] S205, determining the target reception delay of the first signal based on the second reference voltage.

[0074] S206, calibrating the first reception delay of each data line based on the second reference voltage and the target reception delay of the first signal, to obtain the target reception delay of each data line.

[0075] S207, calibrating the transmission delay of the first signal and the transmission delay of each data line based on the second reference voltage, the target reception delay of the first signal and the target reception delay of each data line.

[0076] In a possible implementation, a first transmission delay of each data line is determined, the first transmission delay being determined based on a second transmission delay of the first signal; the second reference voltage is expanded to obtain a plurality of third reference voltages; based on the plurality of third reference voltages, a plurality of preset transmission delays of the first signal, the first transmission delay of each data line, a target reception delay of the first signal, and a target reception delay of each data line, a fourth reference voltage for data writing of the memory and a target transmission delay of the first signal are determined; and based on the fourth reference voltage and the target transmission delay of the first signal, the first transmission delay of each data line is calibrated to obtain a target transmission delay of each data line.

[0077] The first transmission delay is used to indicate an initial delay parameter when the data line transmits data, and is determined based on the second transmission delay of the first signal. The third reference voltage is used to indicate a plurality of voltage values obtained by expanding the second reference voltage, and is used to test voltage adaptability during data writing. The preset transmission delay is used to indicate a series of preset transmission delay values of the first signal, and is used to test data writing effects under different transmission timings. The fourth reference voltage is used to indicate an optimal reference voltage determined through testing for data writing. The target transmission delay of the first signal is used to indicate an optimal delay value determined through testing when the first signal is transmitted.

[0078] Specifically, the first transmission delay of each data line is determined as an initial transmission delay parameter. The second reference voltage is expanded to obtain a plurality of third reference voltages, covering a possible writing voltage range. In combination with the plurality of third reference voltages, a plurality of preset transmission delays of the first signal, the first transmission delay of each data line, and a determined target reception delay of the first signal and a target reception delay of the data line, data writing testing is performed to determine a fourth reference voltage suitable for data writing and a target transmission delay of the first signal. Based on the fourth reference voltage and the target transmission delay of the first signal, the first transmission delay of each data line is calibrated to obtain a target transmission delay.

[0079] In a possible implementation, based on the plurality of third reference voltages, the plurality of preset transmission delays of the first signal, the first transmission delay of each data line, the target reception delay of the first signal, and the target reception delay of each data line, data writing testing is performed on the memory to obtain a plurality of data writing results of the plurality of preset transmission delays corresponding to each third reference voltage; based on the plurality of data writing results of the plurality of preset transmission delays corresponding to each third reference voltage, the fourth reference voltage is determined from the plurality of third reference voltages; and based on the correct plurality of preset transmission delays corresponding to the data writing result of the fourth reference voltage, the target transmission delay of the first signal is determined.

[0080] The data write test is used to indicate a process of sending a write instruction to the memory and verifying whether the data is correctly stored. The data write result is used to indicate an output of the data write test, usually "correct" or "incorrect", to determine the validity of the write parameters.

[0081] Specifically, in combination with the plurality of third reference voltages, the plurality of preset transmission delays of the first signal, the first transmission delay of each data line, and the determined target reception delay of the first signal and the target reception delay of the data line, a plurality of groups of data write tests are performed, and the write result under each group of parameter combinations is recorded. Figure 4 A schematic diagram of the fourth reference voltage and the target transmission delay of the first signal provided by the embodiment of the present application is shown in Figure 4 As shown, for the third reference voltage, the preset transmission delays that enable correct data reading are first selected, and the difference between the maximum value and the minimum value of these delays is calculated. Then, the difference values corresponding to each first reference voltage are compared, and the reference voltage with the largest difference value is selected as the fourth reference voltage. Based on the preset transmission delays that enable correct writing under the fourth reference voltage, the target transmission delay of the first signal is the intermediate value of the minimum value and the maximum value.

[0082] In a possible implementation, the fourth reference voltage, the target reception delay of the first signal, the target transmission delay of the first signal, the target reception delay of each data line, and the target transmission delay of each data line are stored; when the memory is powered on, the stored fourth reference voltage, target reception delay of the first signal, target transmission delay of the first signal, target reception delay of each data line, and target transmission delay of each data line are read to set the memory.

[0083] The storage is used to indicate that the parameters calibrated are saved to the non-volatile area of the memory, so as to ensure that the parameters are not lost after power-off.

[0084] Specifically, the key parameters calibrated are stored to avoid repeated calibration each time. When the memory is powered on, the pre-stored parameters are automatically read, the hardware circuit is configured according to the parameters, and the memory directly enters the working state after calibration.

[0085] The calibration method of the memory provided by the embodiments of the present application can effectively eliminate the influence of individual differences of memory hardware and other factors, ensure that data is accurately sampled and recognized in the transmission process, greatly reduce the data read / write error rate, and improve the data transmission reliability. At the same time, by expanding the reference voltage range and testing multiple preset delay values, the reference voltage, the target receiving delay and the target sending delay of the first signal, and the target receiving delay and the target sending delay of each data line that are most suitable for the current memory operation can be screened out, effectively improving the storage performance of the memory. Moreover, by clearly performing data read testing based on multiple sets of reference voltages and preset delays, and then screening the second reference voltage and the target receiving delay of the first signal according to the test results, it can be ensured that the selected parameters are actually verified, avoiding the deviation between theoretical settings and actual hardware characteristics, improving the scientificity and reliability of parameter selection, and laying an accurate foundation for subsequent calibration steps.

[0086] By calculating the boundary value difference of the effective receiving delay under each reference voltage, and selecting the reference voltage with the largest difference value as the second reference voltage, the working voltage with the highest tolerance to delay fluctuation can be screened out. This selection method makes the memory more adaptable to factors such as timing offset and hardware difference in actual work, significantly improving the stability and anti-interference ability of data reading.

[0087] Determining the target receiving delay of the first signal as the midpoint of the effective delay interval can make the target delay at the center position of the safe range, and maximize the distance from the upper and lower boundaries. This design can effectively deal with the delay fluctuation that may occur in actual work, reduce the risk of data errors caused by delay exceeding the effective range, and further ensure the reliability of the synchronization signal.

[0088] By setting multiple third receiving delays for each data line and testing, and then determining the target receiving delay according to the correct result, the receiving timing deviation caused by the physical characteristic difference of different data lines can be targetedly eliminated. This fine calibration ensures that each data line can work at the optimal delay, improving the consistency and accuracy of the overall data transmission.

[0089] Determining the target receiving delay of the data line as the midpoint of its effective delay interval can make the receiving delay of a single data line at the center of the safe range, reducing the influence of delay offset caused by environmental interference or hardware aging on data reception. This design further improves the anti-interference ability of a single data line, ensuring that each data line can stably receive data under complex working conditions.

[0090] The symmetric calibration of the sending parameters and the matching with the determined receiving parameters form a complete "receiving-sending" closed-loop calibration mechanism. This mechanism ensures the timing consistency of the whole data transmission link, solves the sending-receiving mismatch problem caused by only calibrating the receiving, and improves the reliability of data writing.

[0091] The fourth reference voltage and the first signal target sending delay are screened through actual data writing tests, ensuring the matching of the writing parameters with the actual characteristics of the hardware. In particular, the screening logic of the reference receiving end parameters enables the sending end parameters to also have high anti-volatility capability, further ensuring the stability of data writing, complementing the receiving end calibration, and improving the overall read-write performance of the memory.

[0092] By storing the calibration parameters and automatically loading them at power-on, the calibration process is avoided from being repeatedly performed each time the memory is started, significantly shortening the start-up time of the memory and reducing the system resource consumption. At the same time, the pre-stored optimal parameters ensure that the memory can directly enter the appropriate working state after each power-on, improving the stability and convenience of the system, and being particularly suitable for application scenarios that require start-up speed.

[0093] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.

[0094] Figure 5 The structure diagram of the calibration device of the memory provided by the embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the embodiments of the present application also provide a calibration device 50 of a memory, which comprises a determination module 501, a processing module 502 and a calibration module 503. Figure 5 The determination module 501 is configured to determine an initial reference voltage and a first receiving delay of each data line in the memory, the first receiving delay being determined based on a second receiving delay of a first signal, the first signal being used for synchronizing data transmission.

[0095] The processing module 502 is configured to perform extension processing on the initial reference voltage to obtain a plurality of first reference voltages, and determine a second reference voltage for data reading of the memory and a target receiving delay of the first signal based on the plurality of first reference voltages, a plurality of preset receiving delays of the first signal and the first receiving delay of each data line.

[0096] The calibration module 503 is configured to calibrate the first receiving delay of each data line based on the second reference voltage and the target receiving delay of the first signal to obtain a target receiving delay of each data line.

[0097]

[0098] ​The calibration module 503 is further configured to calibrate the transmission delay of the first signal and the transmission delay of each data line based on the second reference voltage, the target reception delay of the first signal, and the target reception delay of each data line.

[0099] In a possible implementation, the processing module 502 is specifically configured to:

[0100] perform a data read test on the memory based on the plurality of first reference voltages, the plurality of preset reception delays of the first signal, and the first reception delay of each data line, to obtain a plurality of data read results of the plurality of preset reception delays corresponding to each first reference voltage;

[0101] determine the second reference voltage from the plurality of first reference voltages based on the plurality of data read results of the plurality of preset reception delays corresponding to each first reference voltage;

[0102] determine the target reception delay of the first signal based on the second reference voltage.

[0103] In a possible implementation, the processing module 502 is specifically configured to:

[0104] for any one first reference voltage, determine a plurality of preset reception delays with correct data read results, and determine a difference between a maximum value and a minimum value from the plurality of preset reception delays with correct data read results;

[0105] determine a maximum difference from the plurality of differences, and determine the first reference voltage corresponding to the maximum difference as the second reference voltage.

[0106] In a possible implementation, the processing module 502 is specifically configured to:

[0107] determine a first interval based on the plurality of preset reception delays with correct data read results corresponding to the second reference voltage;

[0108] determine a preset reception delay corresponding to a midpoint of the first interval as the target reception delay of the first signal.

[0109] In a possible implementation, the processing module 502 is specifically configured to:

[0110] determine a plurality of third reception delays corresponding to the data line;

[0111] perform a data read test on the memory based on the second reference voltage, the target reception delay of the first signal, and the plurality of third reception delays, to obtain a data read result of each third reception delay;

[0112] determine the target reception delay of the data line based on the third reception delay with correct data read result.

[0113] In a possible implementation, the processing module 502 is specifically configured to:

[0114] determine the second interval based on the third receiving delay corresponding to the correct data reading result;

[0115] determine the third receiving delay corresponding to the midpoint of the second interval as the target receiving delay of the data line.

[0116] In a possible implementation, the calibration module 503 is specifically configured to:

[0117] determine the first sending delay of each data line, the first sending delay being determined based on the second sending delay of the first signal;

[0118] perform extension processing on the second reference voltage to obtain a plurality of third reference voltages;

[0119] determine the fourth reference voltage for data writing of the memory and the target sending delay of the first signal based on the plurality of third reference voltages, the plurality of preset sending delays of the first signal, the first sending delay of each data line, the target receiving delay of the first signal, and the target receiving delay of each data line;

[0120] perform calibration on the first sending delay of each data line based on the fourth reference voltage and the target sending delay of the first signal to obtain the target sending delay of each data line.

[0121] In a possible implementation, the calibration module 503 is specifically configured to:

[0122] perform data writing test on the memory based on the plurality of third reference voltages, the plurality of preset sending delays of the first signal, the first sending delay of each data line, the target receiving delay of the first signal, and the target receiving delay of each data line, to obtain a plurality of data writing results of the plurality of preset sending delays corresponding to each third reference voltage;

[0123] determine the fourth reference voltage from the plurality of third reference voltages based on the plurality of data writing results of the plurality of preset sending delays corresponding to each third reference voltage;

[0124] determine the target sending delay of the first signal based on the plurality of preset sending delays corresponding to the correct data writing result of the fourth reference voltage.

[0125] In a possible implementation, the calibration module 503 is further configured to:

[0126] store the fourth reference voltage, the target receiving delay of the first signal, the target sending delay of the first signal, the target receiving delay of each data line, and the target sending delay of each data line;

[0127] When the memory is powered on, the fourth reference voltage, the target receiving delay of the first signal, the target sending delay of the first signal, the target receiving delay of each data line, and the target sending delay of each data line stored are read, and the setting of the memory is performed.

[0128] The features of the embodiments of the calibration device of the memory can be referred to the related descriptions of the embodiments of the calibration method of the memory, which will not be repeated here.

[0129] Figure 6 The structural schematic diagram of the storage device provided by the embodiments of the present application is shown in the figure. Figure 6 As shown in the figure, the storage device 60 provided by the embodiments of the present application includes at least one processor 601 and a memory 602. Optionally, the storage device 60 further includes a communication component 603. The processor 601, the memory 602 and the communication component 603 are connected through a bus.

[0130] In the specific implementation process, the at least one processor 601 executes the computer execution instructions stored in the memory 602, so that the at least one processor 601 executes the above-mentioned calibration method embodiments of the memory.

[0131] The specific implementation process of the processor 601 can be referred to the above-mentioned method embodiments, which has similar implementation principles and technical effects, and will not be repeated here.

[0132] In the above-mentioned embodiments, it should be understood that the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC) and the like. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor and the like. The steps of the method disclosed in the application can be directly embodied as the execution of the hardware processor, or executed by the combination of the hardware and software modules in the processor.

[0133] The memory can include a random access memory (RAM), and can also include a non-volatile memory (NVM), for example, at least one disk memory.

[0134] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application does not limit to only one bus or one type of bus.

[0135] Embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above XX method embodiments when running.

[0136] In an example embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0137] Embodiments of the present application also provide a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the steps in any of the above memory calibration method embodiments.

[0138] Embodiments of the present application also provide another computer program product, which includes a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above memory calibration method embodiments.

[0139] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for a specific application, but such implementation should not be considered beyond the scope of the present application.

[0140] The above describes in detail the calibration method of the memory and the storage device provided by the present application. The principles and implementation manners of the present application are described by using specific examples, and the above description of the embodiments is only used to help understand the method of the present application and the core idea thereof. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A calibration method of a memory, characterized by, The method comprises the following steps: determining an initial reference voltage and a first receiving delay of each data line in the memory, wherein the first receiving delay is determined based on a second receiving delay of a first signal used for synchronizing data transmission; performing extension processing on the initial reference voltage to obtain a plurality of first reference voltages, and determining a second reference voltage for data reading of the memory and a target receiving delay of the first signal based on the plurality of first reference voltages, a plurality of preset receiving delays of the first signal and the first receiving delay of each data line; calibrating the first receiving delay of each data line based on the second reference voltage and the target receiving delay of the first signal to obtain a target receiving delay of each data line; calibrating a sending delay of the first signal and a sending delay of each data line based on the second reference voltage, the target receiving delay of the first signal and the target receiving delay of each data line; calibrating a sending delay of the first signal and a sending delay of each data line based on the second reference voltage, the target receiving delay of the first signal and the target receiving delay of each data line, comprising: determining a first sending delay of each data line, wherein the first sending delay is determined based on a second sending delay of the first signal; performing extension processing on the second reference voltage to obtain a plurality of third reference voltages; determining a fourth reference voltage for data writing of the memory and a target sending delay of the first signal based on the plurality of third reference voltages, a plurality of preset sending delays of the first signal, the first sending delay of each data line, the target receiving delay of the first signal and the target receiving delay of each data line; calibrating the first sending delay of each data line based on the fourth reference voltage and the target sending delay of the first signal to obtain a target sending delay of each data line; The method further comprises: storing the fourth reference voltage, the target receiving delay of the first signal, the target sending delay of the first signal, the target receiving delay of each data line and the target sending delay of each data line; when the memory is powered on, reading the stored fourth reference voltage, target receiving delay of the first signal, target sending delay of the first signal, target receiving delay of each data line and target sending delay of each data line to set the memory.

2. The method of claim 1, wherein, determining the second reference voltage for data reading of the memory and the target receiving delay of the first signal based on the plurality of first reference voltages, a plurality of preset receiving delays of the first signal and the first receiving delay of each data line, comprises: performing data reading test on the memory based on the plurality of first reference voltages, a plurality of preset receiving delays of the first signal and the first receiving delay of each data line to obtain a plurality of data reading results of a plurality of preset receiving delays corresponding to each first reference voltage; determining the second reference voltage from the plurality of first reference voltages based on a plurality of data read results corresponding to a plurality of preset receiving delays corresponding to each of the first reference voltages; determining the target receiving delay of the first signal based on the second reference voltage.

3. The method of claim 2, wherein, determining the second reference voltage from the plurality of first reference voltages based on a plurality of data read results corresponding to a plurality of preset receiving delays corresponding to each of the first reference voltages, comprises: determining, for any one of the first reference voltages, a plurality of preset receiving delays with correct data read results, and determining a difference between a maximum value and a minimum value of the plurality of preset receiving delays with correct data read results; determining a maximum difference from a plurality of differences, and determining the second reference voltage corresponding to the maximum difference as the second reference voltage.

4. The method of claim 3, wherein, determining the target receiving delay of the first signal based on the second reference voltage, comprises: determining a first interval based on a plurality of preset receiving delays with correct data read results corresponding to the second reference voltage; determining a preset receiving delay corresponding to a midpoint of the first interval as the target receiving delay of the first signal.

5. The method according to any one of claims 1 to 4, characterized in that, determining, for any one of the data lines, a target receiving delay of the data line based on the second reference voltage and the target receiving delay of the first signal, comprises: determining a plurality of third receiving delays corresponding to the data line; performing data read test on the memory based on the second reference voltage, the target receiving delay of the first signal, and the plurality of third receiving delays, to obtain a data read result of each of the third receiving delays; determining the target receiving delay of the data line based on a third receiving delay with correct data read result.

6. The method of claim 5, wherein, determining, for any one of the data lines, a target receiving delay of the data line based on the second reference voltage and the target receiving delay of the first signal, comprises: determining a second interval based on a third receiving delay with correct data read result; determining a third receiving delay corresponding to a midpoint of the second interval as the target receiving delay of the data line.

7. The method of claim 1, wherein, determining a fourth reference voltage for data write of the memory and a target sending delay of the first signal based on the plurality of third reference voltages, a plurality of preset sending delays of the first signal, a first sending delay of each of the data lines, the second reference voltage, the target receiving delay of the first signal, and a target receiving delay of each of the data lines, comprises: performing data write test on the memory based on the plurality of third reference voltages, a plurality of preset sending delays of the first signal, a first sending delay of each of the data lines, the target receiving delay of the first signal, and a target receiving delay of each of the data lines, to obtain a plurality of data write results corresponding to a plurality of preset sending delays corresponding to each of the third reference voltages; determining the fourth reference voltage from the plurality of third reference voltages based on a plurality of data write results corresponding to a plurality of preset sending delays corresponding to each of the third reference voltages; determining the target sending delay of the first signal based on a plurality of preset sending delays with correct data write results corresponding to the fourth reference voltage.

8. A storage device, comprising: comprises: a memory for storing a computer program; a processor for implementing the steps of the calibration method of the memory according to any one of claims 1 to 7 when executing the computer program.

Images