Adaptive block family error avoidance in memory subsystem

Abstract

The invention relates to adaptive block family error avoidance in a memory subsystem. A system includes a memory device; and a processing device operably coupled with the memory device to perform operations including: receiving a read command specifying a logical address; translating the logical address into a physical address that references a physical block stored on the memory device; identifying a word line group associated with the physical address; identifying a block family associated with the physical block and the word line group based on block family metadata associated with the memory device; determining a first threshold voltage offset associated with the family of blocks; and reading data from the physical block using the first threshold voltage offset.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to implementing adaptive block family error avoidance (BFEA) in a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store and retrieve data at and from the memory devices. SUMMARY

[0003] According to an aspect of the present disclosure, a system is provided. The system includes a memory device and a processing device operably coupled with the memory device to perform operations comprising receiving a read command specifying a logical address, translating the logical address to a physical address referencing a physical block stored on the memory device, identifying a word line group associated with the physical address, identifying a block family associated with the physical block and the word line group based on block family metadata associated with the memory device, determining a first threshold voltage offset associated with the block family, and reading data from the physical block using the first threshold voltage offset.

[0004] According to another aspect of the present disclosure, a method is provided. The method includes receiving a read command specifying a logical address, translating the logical address to a physical address referencing a physical block stored on a memory device, identifying a word line group associated with the physical address, identifying a block family associated with the physical block and the word line group based on block family metadata associated with the memory device, determining a first threshold voltage offset associated with the block family, and reading data from the physical block using the first threshold voltage offset.

[0005] According to yet another aspect of the present disclosure, a non-transitory computer- readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions that, when executed by a processing device, cause the processing device to perform operations comprising receiving a read command specifying a logical address, translating the logical address to a physical address referencing a physical block stored on a memory device, identifying a word line group associated with the physical address, identifying a block family associated with the physical block and the word line group based on block family metadata associated with the memory device, determining a first threshold voltage offset associated with the block family, and reading data from the physical block using the first threshold voltage offset. BRIEF DESCRIPTION OF DRAWINGS

[0006] The disclosure can be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, in which:

[0007] Fig. 1A A diagram of an example array of portions of memory cells included in a memory device is shown and described.

[0008] Fig. 1B A block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system according to some embodiments of the disclosure.

[0009] Figs. 2A to 2C A diagram of an example array of portions of memory cells included in a memory device is shown and described.

[0010] Figs. 3A to 3B A diagram of a threshold voltage distribution illustrating an example implementation of adaptive block family error avoidance (BFEA) in a memory sub-system according to some embodiments of the disclosure.

[0011] Fig. 4 A simplified block diagram of a block table 410, a family table 420, and a word line group offset table 430 in a memory sub-system according to some embodiments of the disclosure.

[0012] Fig. 5 A flow diagram of an example method for implementing adaptive block family error avoidance (BFEA) in a memory sub-system according to some embodiments of the disclosure.

[0013] Fig. 6 A block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0014] Aspects of the disclosure relate to implementing adaptive block family error avoidance (BFEA) in a memory sub-system. The memory sub-system can be a storage device, a memory module, or a combination of a storage device and a memory module. Example storage devices and memory modules are described below in connection with Figs. 1A to 1B An example storage device and an example memory module are described. Generally, a host system can utilize a memory sub-system that includes one or more components, such as a memory device that stores data. The host system can provide data for storage at the memory sub-system and can request data retrieved from the memory sub-system.

[0015] A memory sub-system can include high-density non-volatile memory devices in which it is desirable to retain data when power is not supplied to the memory device. One example of a non-volatile memory device is a NAND memory device. Other examples of non-volatile memory devices are described below in connection with Figs. 1A to 1Bare described. A non-volatile memory device is a package of one or more dies. Each die includes one or more planes. For some types of non-volatile memory devices, such as NAND devices, each plane includes a set of physical blocks. Each block is made up of a set of pages. Each page includes a set of memory cells. A memory cell is an electronic circuit for storing information. Depending on the type of memory cell, the memory cell can store one or more binary bits of information and have various logic states related to the number of bits stored. The logic states can be represented by binary values such as “0” and “1” or combinations of such values.

[0016] A memory device can include a plurality of memory cells arranged in a two- dimensional or three-dimensional grid. The memory cells are formed on a silicon wafer in an array of rows and columns. The memory device can further include conductive lines, referred to as word lines and bit lines, connected to respective ones of the memory cells. A word line can connect to one or more rows of memory cells of the memory device and a bit line can connect to one or more columns of memory cells. The intersection of a bit line and a word line constitutes an address of a memory cell. One or more word lines can together comprise a word line group. Each word line group can include a predetermined number (K) of adjacent word lines. For example, a first word line group can include word lines 1 through K, a second word line group can include word lines (K+1) through 2K, a third word line group can include word lines (2K+1) through 3K, and so on. A block refers hereinafter to a unit of the memory device for storing data and can include a group of memory cells connected to a particular subset of word lines of the memory device. One or more blocks can be grouped together to form a plane of the memory device in order to allow concurrent operations to occur on each plane. The memory device can include circuitry to perform concurrent memory page accesses of two or more memory planes. For example, the memory device can include a respective access line driver circuit and power circuit for each plane of the memory device to facilitate concurrent access of pages, including different page types, of two or more memory planes.

[0017] Some memory devices can be three-dimensional (3D) memory devices, such as 3D NAND devices. For example, a 3D memory device can include memory cells placed between several sets of layers including pillars (e.g., polysilicon pillars), tunnel oxide layers, charge trapping (CT) layers, and dielectric (e.g., oxide) layers. For example, a 3D memory device can be a 3D replacement gate memory device with replacement gate structures using word line stacks.

[0018] A memory cell (“cell”) can be programmed (e.g., written) by applying a particular voltage to the cell, which causes charge to be held by the cell. For example, a voltage signal V CGA control electrode can be applied to the cell to turn the cell on to allow current to flow across the cell between the source electrode and the drain electrode. More specifically, for each individual cell (which has a charge Q stored on it), there can be a threshold control gate voltage V T (also referred to as "threshold voltage") such that the source-drain current is lower when the control gate voltage (V CG ) is below the threshold voltage (V CG T ) and increases substantially after the control gate voltage exceeds the threshold voltage (V CG > V T ). Because the actual geometry of the electrodes and gates varies from cell to cell, the threshold voltage can vary even for cells implemented on the same die. Thus, a cell can be characterized by a distribution P of threshold voltages, P(Q, V T ) = dW / dV T , where dW represents the probability that any given cell has its threshold voltage in the interval [V T , V T + dV T ] when a charge Q is placed on the cell.

[0019] A memory device can exhibit a threshold voltage distribution P(Q, V T ) that is narrower than the operating range of control voltages tolerated by the cells of the device. Thus, multiple non-overlapping distributions P(Q k , V T ) ("valleys") can fit within the operating range, allowing multiple values of charge Q k , k = 1, 2, 3... to be stored and reliably detected. The distributions (valleys) are interspersed with voltage intervals ("valley margins") in which the cells of the device do not (or rarely) have their threshold voltages. Thus, such valley margins can be used to separate the various charge states Q k . The logical state of a cell can be determined by detecting in which two valley margins the respective threshold voltage V T of the cell resides during a read operation. Specifically, a read operation can be performed by comparing a measured threshold voltage V T exhibited by a memory cell to one or more reference voltage levels corresponding to known valley margins (e.g., the center of a margin) of the memory device.

[0020] One type of cell is a single-level cell (SLC) that stores 1 bit per cell and defines 2 logical states ("states") each corresponding to a respective V T level ("1" or "L0" and "0" or "L1"). For example, the "1" state can be an erased state (L0) and the "0" state can be a programmed state (L1). Another type of cell is a multi-level cell (MLC) that stores 2 bits per cell and defines 4 logical states each corresponding to a respective V​T four states of levels ("11" or "L0", "10" or "L1", "01" or "L2", and "00" or "L3"). For example, the "11" state can be an erase state, and the "01", "10", and "00" states can each be a respective program state. Another type of cell is a triple-level cell (TLC), which stores 3 bits per cell and defines 8 states L0 to L7, each corresponding to a respective V T eight states of levels ("111" or "L0", "110" or "L1", "101" or "L2", "100" or "L3", "011" or "L4", "010" or "L5", "001" or "L6", and "000" or "L7"). For example, the "111" state can be an erase state, and each of the other states can be a respective program state. Another type of cell is a quad-level cell (QLC), which stores 4 bits per cell and defines 16 states L0 to L15, with L0 corresponding to "1111" and L15 corresponding to "0000". Another type of cell is a penta-level cell (PLC), which stores 5 bits per cell and defines 32 states. Other types of cells can also be considered. A memory device can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, etc., or any combination thereof. For example, a memory device can include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of cells.

[0021] A valley margin can also be referred to as a read window. For example, in an SLC cell, there is one read window present with respect to 2 V T A valley margin can also be referred to as a read window. For example, in an SLC cell, there is one read window present with respect to 2 V T A valley margin can also be referred to as a read window. For example, in an SLC cell, there is one read window present with respect to 2 V T A valley margin can also be referred to as a read window. For example, in an SLC cell, there is one read window present with respect to 2 V

[0022] As data is repeatedly written and erased in a memory device, such as a flash memory, the memory device can be more susceptible to errors caused by various types of noise and interference mechanisms inherent within the memory cells, which can be exacerbated with programming repetitions. As a result, the raw bit error rate (RBER) of the memory device can increase over time. In view of this pattern, the end-of-life RBER of these devices is much higher compared to the beginning-of-life RBER of the respective devices.

[0023] To address read errors, memory sub-systems can use error handling techniques to correct errors and verify that data written into memory devices is the same as data read from respective memory devices. In some embodiments, error handling techniques can include performing one or more read retries using different parameters, such as a threshold voltage offset variation compared to an initial threshold voltage offset applied when performing a read operation on a set of memory cells.

[0024] One phenomenon observed in memory devices is slow charge loss (SCL), which can vary with elapsed time and / or temperature since programming. Charge loss can cause V T distribution to shift, where V T distribution shifts towards lower voltage levels. That is, V T distribution shift can be proportional to elapsed time and / or temperature from a program operation to a read operation. Charge loss and corresponding V T distribution shift can cause an elevated bit error rate (e.g., raw bit error rate (RBER)) over time, which requires an increased amount of error correction to address and thus an increased amount of system resources.

[0025] Depending on system workloads and program-erase cycles, elapsed time since programming can vary across blocks. If programming of blocks is spaced far apart in time, these variations in elapsed time since programming can cause varying, non-uniform V T distribution shifts for respective blocks. Due to these non-uniform V T distribution shifts, it can be difficult to predict an optimal threshold voltage offset that needs to be applied to a majority of blocks across word lines to address charge loss without compromising performance.

[0026] In some implementations, charge loss can be tracked by implementing block family error avoidance (BFEA), which involves assigning each block of a memory device to a respective predefined block family (BF). Each BF can define a grouping of blocks with substantially similar elapsed time since programming (e.g., programmed at or nearly at the same time). Each BF can be assigned to a respective threshold voltage offset bin (“bin”), where each BFEA bin includes a set of threshold level offsets applied to a respective program voltage level to account for V T distribution shifts over time caused by slow charge loss. As described above, an amount of charge loss for a block can be a function of elapsed time and / or temperature from a program operation. Each BFEA bin can be assigned a respective bin index representing a bin number.

[0027] When a block is initially programmed at time 0, the block can initially be assigned to a currently open BF, where the currently open BF is associated with a first bin (e.g., bin 1). A particular respective V TPeriodically (e.g., every few hours) at a lower level, a media scan operation is performed on a representative block of each BF to determine whether the threshold voltage offset of the block and thus the BFEA bin assignment should be updated to better track V over time T Distribution shift. For example, if the media scan operation indicates that the threshold voltage offset should be updated to the threshold voltage offset assigned to a second bin (e.g., bin 2), the block can be reassigned to the second bin.

[0028] As discussed above, changes in the time elapsed since programming across blocks can result in changes, non-uniform V T Distribution shift. Thus, applying a single threshold voltage offset to each block assigned to a respective BFEA bin fails to compensate for changes across different word line groups of the memory device. More specifically, blocks included in a particular word line group can experience changes, non-uniform V T Distribution shift.

[0029] Aspects of the disclosure address the above and other shortcomings by assigning each word line group of a given block to a corresponding block family (rather than assigning the entire block to a block family), thereby accounting for inter-word line variations in V T Distribution shift.

[0030] The threshold voltage offset corresponding to the particular word line group can then be applied when performing a non-sequential read operation on a group of memory cells addressable by the word lines of the particular word line group. In some implementations, the threshold voltage offset assigned to a particular bin can be updated in response to detecting a read error when performing a read operation on a group of memory cells addressable by the word lines of the particular word line group. In response to detecting the read error, an error handling operation can be performed on the group of memory cells to successfully recover data stored in the group of memory cells. The memory sub-system controller can then update the particular BFEA bin with the threshold voltage offset identified by the error handling operation, as described herein with respect to Fig. 5 More detail. Thus, even during non-sequential read operations, updated threshold voltage offsets can be determined and then stored for use in subsequent read operations performed on memory cells assigned to a particular BFEA bin. Moreover, using updated threshold voltage offsets can also account for changes in V T distribution shift caused by charge loss and different V T Corresponding V T distribution shift resulting in read errors.

[0031] Advantages of the disclosure include improving memory device performance and reliability. For example, embodiments described herein can enable improved performance consistency across SCL conditions. Thus, embodiments described herein can be implemented to reduce read errors and increase the lifetime of a memory device.

[0032] The method can be implemented with any suitable memory device architecture in accordance with the embodiments described herein. In one embodiment, the method can be implemented with a memory device implementing a replacement gate NAND (RG NAND) technology. A replacement gate (RG) NAND device is a NAND device that implements an RG architecture rather than a floating gate (FG) architecture. The RG NAND architecture removes the cell gaps that are commonly found in FG NAND architectures, thereby reducing or eliminating the capacitance caused by these cell gaps. More specifically, the RG NAND architecture corresponds to a single insulator structure. Compared to FG NAND architectures, the RG NAND architecture can enable smaller sizes, improved read and write latencies, and increased transfer rates. Further details regarding implementing adaptive block family error avoidance (BFEA) in a memory sub-system will be described below with reference to Figs. 1A to 6 are described.

[0033] Fig. 1A An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the disclosure is illustrated. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination thereof.

[0034] The memory sub-system 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0035] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) capable device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or a computing device that includes a memory and a processing device such as this computing device.

[0036] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to multiple memory sub-systems 110 of different types. Fig. 1AAn example of a host system 120 coupled to a memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0037] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, memory controllers (e.g., NVDIMM controllers), and storage protocol controllers (e.g., PCIe controllers, SATA controllers, CXL controllers). The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110.

[0038] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Compute Express Link (CXL) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a fiber channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface that supports Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe or CXL bus), the host system 120 can further access components (e.g., memory devices 130) utilizing a NVM Express (NVMe) interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Fig. 1A The memory sub-system 110 is illustrated. In general, a host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0039] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0040] Some examples of non-volatile memory devices, such as memory devices 130, include negative-and (NAND)-type flash memory and in-place write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory cells can perform bit storage based on bulk resistance changes in conjunction with a stackable cross-grid format data access array. Further, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0041] Each of memory devices 130 can include one or more arrays of memory cells. One type of memory cell, such as a single-level memory cell (SLC), can store one bit per memory cell. Other types of memory cells, such as a multi-level memory cell (MLC), a triple-level memory cell (TLC), a quad-level memory cell (QLC), and a penta-level memory cell (PLC), can store multiple bits per memory cell. In some embodiments, each of memory devices 130 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device can include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of memory devices 130 can be grouped into pages, which can refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages can be grouped to form blocks.

[0042] Although non-volatile memory components are described, such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND), memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or negative-or (NOR) flash memory or electrically erasable programmable read-only memory (EEPROM).

[0043] The memory sub-system controller 115 (or simply the controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0044] The memory sub-system controller 115 can include a processing device configured to execute instructions stored in local memory 119, including one or more processors (e.g., processor 117). In an illustrative example, the local memory 119 of the memory sub-system controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0045] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetch data, etc. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the example memory sub-system 110 has been illustrated as including the memory sub-system controller 115, in another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but can instead rely upon external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system). Fig. 1A

[0046] In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., a logical block address (LBA), a namespace) and a physical address (e.g., a physical block address) associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 130, but also convert responses associated with the memory devices 130 into information for the host system 120.​

[0047] The memory sub-system 110 can also include additional circuitry or components not shown. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive an address from the memory sub-system controller 115 and decode the address to access the memory devices 130.

[0048] In some embodiments, the memory devices 130 include a local media controller 135 that operates in conjunction with the memory sub-system controller 115 to perform operations on one or more memory cells of the memory devices 130. An external controller (e.g., the memory sub-system controller 115) can externally manage the memory devices 130 (e.g., perform media management operations on the memory devices 130). In some embodiments, the memory sub-system 110 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local controller 135) on-die and a controller (e.g., the memory sub-system controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0049] The local media controller 135 can implement a block family error avoidance (BFEA) component 137. The BFEA component 137 can receive a set of bins. The set of bins can be predefined and stored on the local media controller 135. Each bin in the set of bins corresponds to a block grouping of the memory devices 130. Each bin in the set of bins is assigned to a set of respective threshold voltage offsets (e.g., for read levels 0-7, as discussed above).

[0050] The local media controller 135 can maintain a set of bins. Each block family of the memory devices is assigned to a respective bin based on an elapsed time since the blocks were programmed. Further, each bin in the set of bins can be associated with a set of respective threshold voltage offsets that can be used to read the blocks assigned to the bin. Maintaining the set of bins can include updating the set of bins, as discussed in more detail with respect to Fig. 5

[0051] ​A local media controller can receive a read command specifying a logical address. For example, the read command can be received from a host system 120 via a memory sub-system controller 115. Upon receiving the request, the BFEA component 137 can translate the logical address to a physical address, where the physical address references a physical block stored on a memory device. The BFEA component 137 can then identify a word line group associated with the physical address. The BFEA component 137 can then identify (e.g., based on block family metadata) a block family that includes the physical block and the word line group. The BFEA component 137 can determine a first threshold voltage offset for the block family. More specifically, the BFEA component 137 can identify a bank in a bank group to which the block family is assigned and select a threshold voltage offset assigned to the block family for the word line group. The BFEA component 137 can use the threshold voltage offset to read data from the physical block. More details regarding the operations of the BFEA component 137 will be described below with reference to Figs. 3A to 5 .

[0052] Fig. 1B is a simplified block diagram of a first device in the form of a memory device 130 in communication with a second device in the form of a memory sub-system controller 115 of a memory sub-system (e.g., memory sub-system 110) in accordance with an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home electronics, vehicles, wireless devices, mobile telephones, and the like. The memory sub-system controller 115 (e.g., a controller external to the memory device 130) can be a memory controller or other external host device. Fig. 1A

[0053] The memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. The memory cells of a logical row are connected to the same access line (e.g., word line), while the memory cells of a logical column are selectively connected to the same data line (e.g., bit line). A single access line can be associated with more than one logical row of memory cells and a single data line can be associated with more than one logical column. The memory cells of at least a portion of the array 104 of memory cells (not shown in FIG. 1) are capable of being programmed to one of at least two target data states. Fig. 1B

[0054] ​​Row decode circuitry 108 and column decode circuitry 112 are provided to decode address signals. The address signals are received and decoded to access the memory cell array 104. The memory device 130 also includes input / output (I / O) control circuitry 160 for managing inputs to and outputs from the memory device 130 of commands, address, and data. An address register 114 is in communication with the I / O control circuitry 160 and the row decode circuitry 108 and the column decode circuitry 112 to latch the address signals prior to decoding. A command register 124 is in communication with the I / O control circuitry 160 and the local media controller 135 to latch incoming commands.

[0055] The controller, such as the local media controller 135 internal to the memory device 130, controls access to the memory cell array 104 in response to commands and generates status information for the external memory sub-system controller 115, i.e., the local media controller 135 is configured to perform access operations, such as read operations, program operations, and / or erase operations, to the memory cell array 104. The local media controller 135 is in communication with the row decode circuitry 108 and the column decode circuitry 112 to control the row decode circuitry 108 and the column decode circuitry 112 in response to addresses. In one embodiment, the local media controller 135 includes a BFEA component 137.

[0056] The local media controller 135 is also in communication with a cache register 118. The cache register 118 latches incoming or outgoing data for temporary storage of data according to the direction of the local media controller 135 when the memory cell array 104 is busy writing or reading other data, respectively. During a program operation, such as a write operation, data can be transferred from the cache register 118 to a data register 170 for transfer to the memory cell array 104; then, new data can be latched from the I / O control circuitry 160 in the cache register 118. During a read operation, data can be transferred from the cache register 118 to the I / O control circuitry 160 for output to the memory sub-system controller 115; then, new data can be transferred from the data register 170 to the cache register 118. The cache register 118 and / or the data register 170 can form a page buffer of the memory device 130, such as can form a portion of the page buffer. The page buffer can further include a sensing device (not shown in FIG. 1) for sensing a data state of a memory cell connected to the memory cell array 104, such as by sensing a state of a data line of the memory cell. Fig. 1B The status register 122 can be in communication with the I / O control circuitry 160 and the local media controller 135 to latch status information for output to the memory sub-system controller 115.

[0057] Memory device 130 causes local media controller 135 to receive control signals at memory subsystem controller 115 via control link 132. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can be received via control link 132 depending on the nature of memory device 130. In one embodiment, memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from memory subsystem controller 115 via a multiplexed input / output (I / O) bus 136 and outputs data to memory subsystem controller 115 via I / O bus 136.

[0058] For example, commands can be received at I / O control circuitry 160 via I / O pins [7:0] of input / output (I / O) bus 136 and then can be written into command register 124. Addresses can be received at I / O control circuitry 160 via input / output (I / O) pins [7:0] of I / O bus 136 and then can be written into address register 114. Data can be received at I / O control circuitry 160 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then can be written into cache register 118. Data can then be written into data register 170 for programming memory cell array 104.

[0059] In an embodiment, cache register 118 can be omitted and data can be written directly into data register 170. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although reference can be made to I / O pins, they can include any electrically conductive node, such as a commonly used electrically conductive pad or electrically conductive bump, that provides an electrical connection to memory device 130 by an external device, such as memory subsystem controller 115.

[0060] Those skilled in the art will appreciate that additional circuitry and signals can be provided and that the Figs. 1A to 1B memory device 130 has been simplified Figs. 1A to 1B It should be recognized that the functionality of the various block components described Figs. 1A to 1B may not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device can be adapted to perform the functionality of more than one block component described Figs. 1A to 1Bthe functionality of the individual block components. Additionally, while specific I / O pins have been described in accordance with popular convention for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) can be used in various embodiments.

[0061] Figs. 2A to 2C is a portion of an example array of memory cells included in a memory device in accordance with some embodiments of the present disclosure. For example, Fig. 2A is a schematic diagram of a portion of a memory cell array 200A that can be used in a memory device, for example as part of a memory cell array 104. The memory array 200A includes access lines (e.g., word lines 2020-202 N ) and data lines (e.g., bit lines 204). The word lines 202 can be connected to global access lines (e.g., global word lines) Fig. 2A (not shown in FIG. 2A) in a many-to-one relationship. For some embodiments, the memory array 200A can be formed over a semiconductor, which can be conductively doped, for example, to have a conductivity type, for example, p-type conductivity, for example, for forming a p-well, or n-type conductivity, for example, for forming an n-well.

[0062] The memory array 200A can be arranged in rows each corresponding to a respective word line 202 and columns each corresponding to a respective bit line 204. Rows of memory cells 208 can be divided into one or more physical page groups of memory cells 208, and a physical page of memory cells 208 can include every other memory cell 208 that can be commonly addressed by a given word line 202. For example, memory cells 208 that can be commonly addressed by a word line 202 N and selectively connected to even bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be one physical page of memory cells 208 (e.g., even memory cells), while memory cells 208 that can be commonly addressed by a word line 202 N and selectively connected to odd bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of memory cells 208 (e.g., odd memory cells). Although bit lines 2043-2045 are not explicitly depicted in Fig. 2A FIG. 2A, it is apparent from the figure that bit lines 204 of the memory cell array 200A can be from bit line 2040 to bit line 204 MContiguously numbered. Other groups of memory cells 208 that are commonly addressed by a given word line 202 can also define a physical page of memory cells 208. For a particular memory device, all memory cells that are commonly addressed by a given word line 202 can be considered a physical page of memory cells. Portions of a physical page of memory cells (which in some embodiments can still be a full row) that are read during a single read operation or programmed during a single program operation (e.g., an upper page or a lower page of memory cells) can be considered a logical page of memory cells. A block of memory cells can include those memory cells configured to be erased together, such as all strings 206 sharing a common word line 2020to 202 N All memory cells that are commonly addressed (e.g., all strings 206 sharing a common word line 202). References to a page of memory cells herein can refer to memory cells of a logical page of memory cells.

[0063] Each column can include a string of serially connected memory cells (e.g., non-volatile memory cells), such as strings 2060to 206 M Each string 206 can be connected (e.g., selectively connected) to a source line 216 (SRC) and can include memory cells 2080to 208 N Each string 206 of memory cells 208 can be serially connected between a select gate 210 (e.g., one of select gates 2100to 210 M and a select gate 212 (e.g., one of select gates 2120to 212 M In some embodiments, select gates 2100to 210 M are source side select gates (SGS) and select gates 2120to 212 M are drain side select gates. Select gates 2100to 210 M may be connected to a select line 214 (e.g., a source side select line) and select gates 2120to 212 M may be connected to a select line 215 (e.g., a drain side select line). Select gates 210 and 212 can represent a plurality of select gates connected in series, where each select gate in series is configured to receive the same or independent control signals. A source of each select gate 210 can be connected to SRC 216, and a drain of each select gate 210 can be connected to memory cells 2080of a corresponding string 206. Thus, each select gate 210 can be configured to selectively connect a corresponding string 206 to SRC 216. A control gate of each select gate 210 can be connected to select line 214. A drain of each select gate 212 can be connected to a bit line 204 of a corresponding string 206. A source of each select gate 212 can be connected to memory cells 208 NAccordingly, each select gate 212 can be configured to selectively connect a corresponding string 206 to a bit line 204. A control gate of each select gate 212 can be connected to a select line 215.

[0064] In some embodiments and as described below with reference to Fig. 2B will be described in greater detail, Fig. 2A The memory array in is a three-dimensional memory array in which the strings 206 extend substantially perpendicular to a plane containing the SRCs 216 and to a plane containing the plurality of bit lines 204, which can extend substantially parallel to the plane containing the SRCs 216.

[0065] Fig. 2B is another schematic diagram of a portion of a memory cell array 200B (e.g., a portion of the memory cell array 104) arranged in a three-dimensional memory array structure. The three-dimensional memory array 200B can incorporate vertical structures that can include semiconductor pillars, in which a portion of the pillars can function as channel regions for memory cells of the strings 206. The strings 206 can each be selectively connected to a bit line 2040to 204 M and to a SRC 216 through a select gate 210. Multiple strings 206 can be selectively connected to the same bit line 204. Several groups of strings 206 can be selectively activated to connect to their respective bit lines 204 by biasing select lines 2150to 215 L The select gates 210 can be activated by biasing the select line 214. Each word line 202 can be connected to a plurality of rows of memory cells of the memory array 200B. Rows of memory cells that can be commonly addressed with a particular word line 202 can be collectively referred to as a tier.

[0066] Fig. 2C is a diagram of a portion of a memory cell array 200C (e.g., a portion of the memory cell array 104). Channel regions (e.g., semiconductor pillars) 238 represent different strings of series-connected memory cells (e.g., strings 206 of Figs. 2A to 2B ) that are selectively connected to bit lines 2040and / or bit lines 2041. Memory cells (not depicted in Fig. 2C ) can be formed at each intersection of a word line 202 and a channel region 238, and the memory cells corresponding to a single channel region 238 can collectively form a string of series-connected memory cells (e.g., strings 206 of Figs. 2A to 2B ). Additional features can be common in such structures, such as dummy word lines, segmented channel regions with intervening conductive regions, etc.

[0067] Figs. 3A to 3B is a VT A plot of the distribution. For example, Fig. 3A A left V T distribution 310L and a right V T distribution 310R. For example, the first time can be a programming time (e.g., time 0). A center read level 320 can exist at V T the valley between the distributions 310L and 310R. The valley defines a read window. A left V T distribution 310L can be identified and a right V T distribution 310R can be identified. The distance between the center read level 320 and the boundary 330L defines a left portion 340L of the read window. The boundaries 330L and 330R-1 can each be identified from a threshold bit error rate (e.g., RBER). The boundaries 330L and 330R-1 can be empirically identified by analyzing charge loss after the memory device is manufactured. The distance between the center read level 320 and the boundary 330R-1 defines a right portion 340R-1 of the read window.

[0068] Fig. 3B A left V T distribution 310L and a right V T distribution 310R. Due to charge loss that occurs between the first time and the second time, at least the right V T distribution 310R has shifted left. If Fig. 3A the boundary 330R-1 remains in the same location, this will cause the bit error rate to exceed the threshold bit error rate. Thus, to address the shift of the right V T distribution 310R, the boundary 330R-1 is updated to boundary 330R-2, which results in an updated distance between the center read level 320 and the boundary 330R-2 defining a right portion 340R-2 of the read window. The updated distance is less than the previous distance, and thus the right portion 340R-2 of the read window is less than the right portion 340R-1 of the read window. Furthermore, the read window itself has been reduced due to the shift of the right V T distribution 310R.

[0069] Fig. 4 is a simplified block diagram of a set of data structures including a block table 410, a family table 420, and a word line group "1" offset table 430 in a memory sub-system according to some embodiments of the present disclosure.

[0070] Each of the block table 410, the family table 420, and the word line group "1" offset table 430 can be stored in Fig. 1A the memory device 130. In this example, each table can be a lookup table that can be accessed by the memory sub-system controller to identify a particular BFEA bin mapped to a particular word line group.

[0071] Each record of the block table 410 specifies a block family and a word line group associated with a specified block. In some implementations, the block table record can further include a time and temperature value associated with the specified block and word line group combination. Word lines can be grouped together based on the position of the word line relative to other word lines of the block. Word lines that are physically close to one another, such as adjacent to one another, can be grouped together into a particular word line group. In some embodiments, the maximum amount of word lines that can be grouped together into a particular word line group can be predefined, such as during manufacturing and / or design of the memory device using offline testing and experimental data.

[0072] The family table 420 is indexed by block family number, such that each record of the family table 420 specifies, for the block family referenced by the record’s index, a set of threshold voltage offset bins (such as BFEA bins) associated with the block family.

[0073] Finally, there can be a set of word line group offset tables, where for a particular word line group, each word line group offset table maps a particular set of threshold voltage offsets to a particular BFEA bin. For example, for word line group 1, a word line group 1 offset table 430 can map a particular set of threshold voltage offsets to a particular BFEA bin. In particular, the word line group 1 offset table 430 is indexed by bin number. Each record of the offset table 430 specifies, for a particular BFEA bin, a set of threshold voltage offsets (such as read levels 0-7, as discussed above) associated with the particular BFEA bin. There can be a word line group offset table for each word line group (such as word line group 1 through word line group n).

[0074] In some embodiments, the memory sub-system controller can use the block table 410 and / or another data structure in the memory sub-system to identify, for each BFEA bin associated with a particular block family, an associated temperature value and / or a read level offset modification calculation. In some embodiments, the temperature value is a read temperature value measured at the time a request is received to perform a read operation at a set of memory cells included in the block. In some embodiments, the temperature value can be a temperature value measured at the time the block family is created. In some embodiments, the temperature value can be measured using a temperature sensor of the memory device 130, such as an on-die temperature sensor. In some embodiments, the temperature sensor can be located in other locations in the memory sub-system 110. In some embodiments, the read level offset modification calculation defines a calculation performed to modify the threshold voltage offset of a particular BFEA bin. In some embodiments, the read level offset modification calculation can be initialized during manufacturing and / or design of the memory device using offline testing and experimental data.

[0075] In some embodiments, the memory sub-system controller can update the threshold voltage offset assigned to a particular BFEA bin, as discussed with respect to Fig. 5Further discussion. In some embodiments, using the word line group 1 offset table 430 as an example, to update the threshold voltage offset assigned to a particular BFEA bin of word line group 1, the memory sub-system controller can identify an entry of the offset table 430 that includes an identifier of the particular BFEA bin. For example, for a program operation performed on a memory cell along word line group 1 that maps to bin "1" (where the bin can be identified using the family table 420 described above), the memory sub-system controller can identify the entry bin "1" in the offset table 430. The memory sub-system controller can identify that bin "1" maps to a set of threshold voltage offsets in the corresponding row for bin "1." In some embodiments, the memory sub-system controller can update the threshold voltage offset by replacing the threshold voltage offset with the updated threshold voltage offset. In some embodiments, the memory sub-system controller can determine the updated threshold voltage offset by performing a modification to the threshold voltage offset, as described above with respect to the family table 420. In some embodiments, the memory sub-system controller can determine the updated threshold voltage offset by performing a modification to the threshold voltage offset, as described above with respect to the family table 420. Fig. 4 Further discussion. Fig. 5 Further discussion.

[0076] Fig. 5 is a flow diagram of an example method 500 for implementing adaptive block family error avoidance (BFEA) in a memory sub-system according to some embodiments of the present disclosure. The method 500 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by the BFEA component 137 of the memory sub-system 100. Fig. 1A Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0077] At operation 501, the processing logic receives a read command specifying a logical address for which a read operation is to be performed. In some embodiments, the processing logic can receive the read command from a host system (e.g., the host system 120 of the memory sub-system 100). Fig. 1A At operation 501, the processing logic receives a read command specifying a logical address for which a read operation is to be performed. In some embodiments, the processing logic can receive the read command from a host system (e.g., the host system 120 of the memory sub-system 100).

[0078] At operation 503, in response to receiving the read command, the processing logic can translate the logical address specified by the read command to a reference stored in a memory device (e.g., the memory device 110 of the memory sub-system 100). Fig. 1Aa physical address of a physical block on the memory device 130). For example, the processing logic can use a logical-to-physical (L2P) address mapping data structure to translate the logical address to the physical address. In some implementations, the L2P address mapping data structure can be stored on the memory device, and each entry of the L2P address mapping data structure can include a logical address and a corresponding physical address.

[0079] At operation 505, the processing logic can identify a word line group associated with the physical address. For example, using a component of the physical address (e.g., a physical block number), the processing logic can use the block table 410 to identify a word line group corresponding to the physical block number. Fig. 4

[0080] At operation 507, the processing logic can identify a block family associated with the physical block and the word line group identified at operation 505. For example, the processing logic can use block family metadata (e.g., the block table 410) to identify the block family. Fig. 4

[0081] At operation 509, the processing device can determine a first threshold voltage offset associated with the block family identified at operation 507. For example, the processing logic can use the block family identifier as an index to use the family table 420 to identify a bin assigned to the block family. Then, the processing logic can use the word line group identifier (e.g., word line group 1) and the identified bin assigned to the block family as an index to use the offset table 430 to identify a first threshold voltage offset in a set of threshold voltage offsets.

[0082] At operation 511, in response to identifying the set of threshold voltage offsets assigned to the identified bin for the particular word line group at operation 509, the processing logic can read data from the physical block using the first threshold voltage offset in the set of threshold voltage offsets.

[0083] In some embodiments, at operation 513, the processing logic can update the first threshold voltage offset in response to detecting a read error in response to reading data from the physical block using the first threshold voltage offset. For example, the processing logic can perform an error handling operation on a set of memory cells addressable by the word line group. A "read error" refers to a failure of the memory sub-system to confirm that one or more data items have been retrieved from the memory device in response to a read command. For example, a read error can be indicated by a measured threshold voltage V T ​​Mismatches with threshold voltage levels due to SCL, as discussed above. In some embodiments, the error handling operation can include performing one or more read retries using different parameters (e.g., a threshold voltage offset variation compared to an initial threshold voltage offset applied when performing a read operation on the set of memory cells). The processing logic identifies a threshold voltage offset that results in successful recovery of data stored in the set of memory cells.

[0084] In response to identifying a threshold voltage offset that results in successful recovery of data stored in the set of memory cells, the processing logic can update the first threshold voltage offset in an entry of the offset table 430 with the threshold voltage offset that results in successful recovery of data stored in the set of memory cells. In some embodiments, the processing logic can retrieve the offset table 430. In response to retrieving the offset table 430, the processing logic can identify an entry of the offset table 430, where the entry includes an identifier of the bin. In response to identifying the entry that includes the identifier of the bin, the processing logic can identify a set of threshold voltage offsets assigned to the bin. In response to identifying the set of threshold voltage offsets assigned to the bin, the processing logic can update the threshold voltage offset corresponding to the appropriate threshold voltage level by replacing the threshold voltage offset (e.g., the first threshold voltage offset) with the threshold voltage offset that results in successful recovery of data stored in the set of memory cells.

[0085] In some embodiments, the processing logic can perform a modification to the first threshold voltage offset assigned to the bin. Performing the modification can include using a predefined parameter and the first threshold voltage offset. For example, performing the modification can include performing a calculation that adds the first threshold voltage offset to the threshold voltage offset that results in successful recovery of data stored in the set of memory cells. In some embodiments, performing the modification can include applying a parameter, where the parameter is a value, e.g., less than 1, that is predefined to avoid overfitting errors when performing the calculation. For example, an example calculation to perform the modification can be the following:

[0086] the modified read level offset = (rd_offset_old + a * rd_offset_new) / (1 + a),

[0087] where rd_offset_old is the first threshold voltage offset assigned to the bin, rd_offset_new is the new threshold voltage offset (e.g., the threshold voltage offset that results in successful recovery of data stored in the set of memory cells), and a is a predefined parameter. In some embodiments, a can be a value less than 1.

[0088] In response to performing the modification to the first threshold voltage offset, the processing logic can update the identified entry of the data structure by assigning the modified threshold voltage offset to the bin. For example, the processing logic can replace the assigned first threshold voltage offset with the modified threshold voltage offset.

[0089] In some embodiments, in response to updating the first threshold voltage offset, the processing logic can receive another (e.g., second) read command for a set of memory cells addressable by the same word line group as the read command received at operation 501. The processing logic can perform a read operation using the updated threshold voltage offset.

[0090] In some embodiments, to update the threshold voltage offset, the processing logic can perform a media scan operation for the set of memory cells addressable by the first word line of the word line group. For example, performing the media scan operation can include performing a data integrity check to verify that data stored on the set of memory cells addressable by the first word line does not include any errors. During the data integrity check, one or more reliability statistics for the data stored on the set of memory cells addressable by the first word line are determined. One example of a reliability statistic is a raw bit error rate (RBER). In some embodiments, in response to performing the media scan operation, the processing logic can identify another (e.g., second) threshold voltage offset associated with performing the media scan operation. For example, the second threshold voltage offset can be a threshold voltage offset used to obtain a minimum and / or optimal RBER for the data stored on the set of memory cells addressable by the first word line. In response to identifying the threshold voltage offset, the processing logic can update the threshold voltage offset assigned to the bank with the second threshold voltage offset, as described above.

[0091] In some embodiments, to update the threshold voltage offset, the processing logic can identify a temperature of the block family. For example, the processing logic can measure the temperature using a temperature sensor associated with the memory device. In response to identifying the temperature of the block family, the processing logic can update an entry of a data structure stored on the memory device 130, such as Fig. 1A For example, the processing logic can retrieve the block table 410. In response to retrieving the block table 410, the processing logic can identify an entry of the block table 410, where the entry includes an identifier of a bank. In response to identifying the entry including the identifier of the block family, the processing logic can identify a temperature associated with the block family. In response to identifying the temperature associated with the block family, the processing logic can update the associated temperature included in the entry with the identified temperature. For example, the processing logic can replace the associated temperature with the identified temperature.

[0092] Fig. 6 An example machine, the computer system 600, within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed, is illustrated in FIG. 6. In some embodiments, the computer system 600 can correspond to a host system (e.g., the host system 120) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110). Fig. 1A An example machine, the computer system 600, within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed, is illustrated in FIG. 6. In some embodiments, the computer system 600 can correspond to a host system (e.g., the host system 120) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110). Fig. 1AThe memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Fig. 1A (Operation of BFEA component 137). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0093] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a storage cellular phone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0094] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or RDRAM)), a static memory 606 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 618, which communicate with each other via a bus 630.

[0095] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0096] Data storage system 618 can include a machine-readable storage medium 624 (also known as computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 can also reside, completely or at least partially, within the main memories 604 and / or within processing devices 602 during execution thereof by the computer system 600, the main memories 604 and the processing devices 602 also constituting machine-readable storage media. The machine-readable storage medium 624, data storage system 618, and / or main memories 604 can correspond to Fig. 1A memory subsystem 110.

[0097] In one embodiment, the instructions 626 include instructions to implement functionality corresponding to a BFEA component (e.g., BFEA component 137 of FIG. 1). Fig. 1A While the machine-readable storage medium 624 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0098] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These

[0099] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0100] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0101] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure described herein.

[0102] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer (or other electronic devices) to perform a process according to the present disclosure. The machine-readable medium can include any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as read only memory ("ROM"), volatile memory, such as random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0103] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: Memory devices; and A processing device operatively coupled to the memory device to perform operations including: Receives a read command for a specified logical address; The logical address is translated into a physical address that references the physical block stored on the memory device; Identify the word line group associated with the physical address; The block families associated with the physical blocks and the word line groups are identified based on the block family metadata associated with the memory device. Determine the first threshold voltage offset associated with the block family; and The data from the physical block is read using the first threshold voltage offset.

2. The system of claim 1, wherein determining the first threshold voltage offset associated with the block family further comprises: Identify a first repository among a plurality of repositories associated with the block family based on the block family metadata associated with the memory device, wherein each of the plurality of repositories defines a corresponding word line group based on time elapsed since programming; and The first threshold voltage offset is determined based on the first compartment associated with the block family and the word line group.

3. The system according to claim 2, wherein the operation further comprises: A read error is detected in response to performing a read operation on a plurality of memory cells that can be addressed via word lines of the word line group associated with the physical address; Perform error handling operations on the plurality of memory cells that can be addressed via the word lines; In response to determining that the error handling operation has successfully recovered data regarding the plurality of memory cells addressable via the word lines, a second threshold voltage offset associated with the execution of the error handling operation is identified; and The first compartment is updated using the second threshold voltage offset.

4. The system of claim 3, wherein updating the first compartment with the second threshold voltage offset further comprises: Retrieve a data structure comprising multiple entries, wherein each entry includes an identifier of a bin among the multiple bins and multiple threshold voltage offsets assigned to the bin; The data structure is used to identify a first entry including the identifier of the first compartment and the first threshold voltage offset assigned to the first compartment. and The first entry of the data structure is updated by assigning the second threshold voltage offset to the first bin.

5. The system of claim 3, wherein updating the first compartment with the second threshold voltage offset further comprises: Retrieve a data structure comprising multiple entries, wherein each entry includes an identifier of a bin among the multiple bins and multiple threshold voltage offsets assigned to the bin; Based on the data structure, identify the identifier of the first compartment and the first entry of the first threshold voltage offset assigned to the first compartment; The second threshold voltage offset is modified using predefined parameters and the first threshold voltage offset; and The first entry of the data structure is updated by assigning the modified threshold voltage offset to the first compartment.

6. The system of claim 3, wherein the operation further comprises: Perform a media scan operation on multiple memory cells that can be addressed via the first word line of the word line group; Identify and associate the threshold voltage offset with the execution of the media scanning operation; and The first compartment is updated using the second threshold voltage offset.

7. The system of claim 1, wherein the operation further comprises: Identify the temperature of the block family; Retrieve a data structure that includes multiple entries, each entry including an identifier of a word line group in multiple word line groups, an associated block family in multiple block families, and an associated temperature; and The first entry of the data structure is updated using the temperature of the block family.

8. A method comprising: Receives a read command for a specified logical address; The logical address is translated into a physical address that references a physical block stored on the memory device; Identify the word line group associated with the physical address; The block families associated with the physical blocks and the word line groups are identified based on the block family metadata associated with the memory device. Determine the first threshold voltage offset associated with the block family; and The data from the physical block is read using the first threshold voltage offset.

9. The method of claim 8, wherein determining the first threshold voltage offset associated with the block family further comprises: Identify a first repository among a plurality of repositories associated with the block family based on the block family metadata associated with the memory device, wherein each of the plurality of repositories defines a corresponding word line group based on time elapsed since programming; and The first threshold voltage offset is determined based on the first compartment associated with the block family and the word line group.

10. The method of claim 9, further comprising: A read error is detected in response to performing a read operation on a plurality of memory cells that can be addressed via word lines of the word line group associated with the physical address; Perform error handling operations on the plurality of memory cells that can be addressed via the word lines; In response to determining that the error handling operation has successfully recovered data regarding the plurality of memory cells addressable via the word lines, a second threshold voltage offset associated with the execution of the error handling operation is identified; and The first compartment is updated using the second threshold voltage offset.

11. The method of claim 10, wherein updating the first cell with the second threshold voltage offset further comprises: Retrieve a data structure comprising multiple entries, wherein each entry includes an identifier of a bin among the multiple bins and multiple threshold voltage offsets assigned to the bin; The data structure is used to identify a first entry including the identifier of the first compartment and the first threshold voltage offset assigned to the first compartment. and The first entry of the data structure is updated by assigning the second threshold voltage offset to the first bin.

12. The method of claim 10, wherein updating the first cell with the second threshold voltage offset further comprises: Retrieve a data structure comprising multiple entries, wherein each entry includes an identifier of a bin among the multiple bins and multiple threshold voltage offsets assigned to the bin; Based on the data structure, identify the identifier of the first compartment and the first entry of the first threshold voltage offset assigned to the first compartment; The second threshold voltage offset is modified using predefined parameters and the first threshold voltage offset; and The first entry of the data structure is updated by assigning the modified threshold voltage offset to the first compartment.

13. The method of claim 10, further comprising: Perform a media scan operation on multiple memory cells that can be addressed via the first word line of the word line group; Identify and associate the threshold voltage offset with the execution of the media scanning operation; and The first compartment is updated using the second threshold voltage offset.

14. The method of claim 8, further comprising: Identify the temperature of the block family; Retrieve a data structure that includes multiple entries, each entry including an identifier of a word line group in multiple word line groups, an associated block family in multiple block families, and an associated temperature; and The first entry of the data structure is updated using the temperature of the block family.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: Receives a read command for a specified logical address; The logical address is translated into a physical address that references a physical block stored on the memory device; Identify the word line group associated with the physical address; The block families associated with the physical blocks and the word line groups are identified based on the block family metadata associated with the memory device. Determine the first threshold voltage offset associated with the block family; and The data from the physical block is read using the first threshold voltage offset.

16. The non-transitory computer-readable storage medium of claim 15, wherein determining the first threshold voltage offset associated with the block family further comprises: Identify a first repository among a plurality of repositories associated with the block family based on the block family metadata associated with the memory device, wherein each of the plurality of repositories defines a corresponding word line group based on time elapsed since programming; and The first threshold voltage offset is determined based on the first compartment associated with the block family and the word line group.

17. The non-transitory computer-readable storage medium of claim 16, wherein the operation further comprises: A read error is detected in response to performing a read operation on a plurality of memory cells that can be addressed via word lines of the word line group associated with the physical address; Perform error handling operations on the plurality of memory cells that can be addressed via the word lines; In response to determining that the error handling operation has successfully recovered data regarding the plurality of memory cells addressable via the word lines, a second threshold voltage offset associated with the execution of the error handling operation is identified; and The first compartment is updated using the second threshold voltage offset.

18. The non-transitory computer-readable storage medium of claim 16, wherein updating the first compartment with the second threshold voltage offset further comprises: Retrieve a data structure comprising multiple entries, wherein each entry includes an identifier of a bin among the multiple bins and multiple threshold voltage offsets assigned to the bin; The data structure is used to identify a first entry including the identifier of the first compartment and the first threshold voltage offset assigned to the first compartment. and The first entry of the data structure is updated by assigning the second threshold voltage offset to the first bin.

19. The non-transitory computer-readable storage medium of claim 16, wherein updating the first compartment with the second threshold voltage offset further comprises: Retrieve a data structure comprising multiple entries, wherein each entry includes an identifier of a bin among the multiple bins and multiple threshold voltage offsets assigned to the bin; Based on the data structure, identify the identifier of the first compartment and the first entry of the first threshold voltage offset assigned to the first compartment; The second threshold voltage offset is modified using predefined parameters and the first threshold voltage offset; and The first entry of the data structure is updated by assigning the modified threshold voltage offset to the first compartment.

20. The non-transitory computer-readable storage medium of claim 15, wherein the operation further comprises: Identify the temperature of the block family; Retrieve a data structure that includes multiple entries, each entry including an identifier of a word line group in multiple word line groups, an associated block family in multiple block families, and an associated temperature; and The first entry of the data structure is updated using the temperature of the block family.

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