A controllable power distribution board for a drone

Abstract

The application discloses a controllable power distribution board for a UAV, comprising a load main passage, a pre-charging circuit, a pre-charging delay circuit, a switch circuit and a fault detection circuit, the load main passage is connected with the switch circuit, the pre-charging circuit and the fault detection circuit respectively, the input end of the load main passage is connected with an input power supply, the output end of the load main passage is connected with a load, and the pre-charging delay circuit is connected with the pre-charging circuit; the pre-charging circuit is used for pre-charging operation of the load main passage; and the pre-charging delay circuit is used for controlling the duration of the pre-charging operation of the pre-charging circuit. The application sets an upper power buffering mechanism composed of the pre-charging circuit and the pre-charging delay circuit on the controllable power distribution board, sets the switch circuit and the fault detection circuit, forms switch on-off protection and fault detection protection for the load main passage, and improves the operation safety and stability of the UAV, and optimizes the working efficiency of the UAV.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of unmanned aerial vehicle circuit control, and particularly relates to a controllable circuit board for unmanned aerial vehicle. BACKGROUND

[0002] In the power system of an unmanned aerial vehicle, a distribution board is a connection hub of a battery and various electrical equipment, and its reliability directly affects the safe operation of the unmanned aerial vehicle. A traditional unmanned aerial vehicle distribution board usually adopts a structure of directly connecting the battery and the load, that is, after the battery plug is inserted, the load is directly powered on, and no special power-on buffer mechanism is set in the circuit design. When powered on for the first time, due to the instantaneous large current impact between the battery and the capacitive load (such as a motor drive module, an energy storage capacitor, etc.), the battery plug is prone to power-on sparking, which not only accelerates the oxidation of the plug contacts and shortens the service life, but also may cause circuit failure and even endanger the flight safety of the unmanned aerial vehicle. SUMMARY

[0003] The present application aims at overcoming the shortcomings of the prior art, and provides a controllable distribution board for unmanned aerial vehicle, which is provided with a power-on buffer mechanism composed of a pre-charging circuit and a pre-charging delay circuit, and is provided with a switching circuit and a fault detection circuit to form switching on-off protection and fault detection protection for a load main path, thereby improving the operation safety and stability of the unmanned aerial vehicle and optimizing the working efficiency of the unmanned aerial vehicle.

[0004] The present application provides a controllable distribution board for unmanned aerial vehicle, which comprises a load main path, a pre-charging circuit, a pre-charging delay circuit, a switching circuit and a fault detection circuit, the load main path is connected with the switching circuit, the pre-charging circuit and the fault detection circuit respectively, an input end of the load main path is connected with an input power supply, and an output end of the load main path is connected with a load, and the pre-charging delay circuit is connected with the pre-charging circuit.

[0005] The pre-charging circuit is used for pre-charging operation of the load main path, and comprises a pre-charging MOS tube Q6, a resistor R8, a diode D8 and a pre-charging resistor R4, a gate of the pre-charging MOS tube Q6 is connected with a first end of the resistor R8 and an anode of the diode D8, a drain of the pre-charging MOS tube Q6 is connected with a first end of the pre-charging resistor R4, a second end of the pre-charging resistor R4 is connected with the input power supply, and a second end of the resistor R8 is connected with a cathode of the diode D8.

[0006] The pre-charge delay circuit is used for controlling the duration of the pre-charge operation of the pre-charge circuit, and the pre-charge delay circuit comprises a NE555 timer U7, a resistor R24, a resistor R27, a capacitor C18, a capacitor C22 and a diode D14, a pin 4, a pin 8 of the NE555 timer U7, a first end of the resistor R24, a first end of the resistor R27, a cathode of the diode D14 are connected to a pre-charge delay circuit power positive pole, a pin 5 of the NE555 timer U7 is connected to a first end of the capacitor C18, a pin 2, a pin 6 of the NE555 timer U7 are connected to a second end of the resistor R24, an anode of the diode D14, a first end of the capacitor C22, a pin 1 of the NE555 timer U7, a second end of the capacitor C18, a second end of the capacitor C22 and a second end of the resistor R27 are grounded.

[0007] Further, the load main path comprises a plurality of load branches, the plurality of load branches are connected in parallel, and any one of the load branches comprises a load MOS tube, a gate drive circuit and a differential amplification circuit, the gate drive circuit is connected to a gate of the load MOS tube, and the differential amplification circuit is connected in parallel between the gate and a source of the load MOS tube.

[0008] Further, the gate drive circuit comprises a gate drive chip U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a capacitor C3, a diode D1, a diode D2, a diode D3 and a diode D4.

[0009] A first end of the capacitor C1 and a pin 1 of the gate drive chip U1 are connected to a driving power positive pole.

[0010] A first end of the capacitor C2, a cathode of the diode D2 and a cathode of the diode D4 are connected to a pin 5 of the gate drive chip U1.

[0011] A first end of the resistor R3 is connected to a pin 6 of the gate drive chip U1.

[0012] A second end of the capacitor C2, an anode of the diode D3, an anode of the diode D4 and a first end of the resistor R2 are connected to a pin 7 of the gate drive chip U1.

[0013] A first end of the resistor R1 and a cathode of the diode D1 are connected to a pin 8 of the gate drive chip U1.

[0014] An anode of the diode D2, a first end of the capacitor C3 and a cathode of the diode D3 are connected.

[0015] A second end of the capacitor C3 is connected to a second end of the resistor R1.

[0016] The pin 4 of the gate drive chip U1, the second end of the capacitor C1, the anode of the diode D1, and the second end of the resistor R2 are grounded.

[0017] Further, the differential amplification circuit comprises an amplifier U26, a resistor R89, a resistor R93, a resistor R96, a resistor R99, and a resistor R103.

[0018] The positive input end of the amplifier U26 is connected to the first end of the resistor R89 and the first end of the resistor R93.

[0019] The negative input end of the amplifier U26 is connected to the first end of the resistor R99 and the first end of the resistor R103.

[0020] The output end of the amplifier U26 is connected to the first end of the resistor R96 and the second end of the resistor R103.

[0021] The second end of the resistor R93 and the second end of the resistor R99 are connected to the load MOS tube.

[0022] The second end of the resistor R96 is connected to the input end of the four-input NAND gate circuit.

[0023] Further, the switch circuit comprises a double-pole double-throw switch SW, a resistor R75, a resistor R84, a resistor R81, a resistor R85, a resistor R79, a capacitor C48, a capacitor C51, and a triode Q12.

[0024] The first end of the resistor R75 is connected to the positive pole of the first switch power supply.

[0025] The second end of the resistor R75 is connected to the second end of the double-pole double-throw switch SW and the first end of the resistor R84.

[0026] The third end of the double-pole double-throw switch SW is connected to the first end of the capacitor C48.

[0027] The first end of the double-pole double-throw switch SW is connected to the first end of the resistor R81, the first end of the capacitor C51, the first end of the resistor R85, and the base of the triode Q12.

[0028] The first end of the resistor R79 is connected to the positive pole of the second switch power supply.

[0029] The second end of the resistor R79 is connected to the second end of the capacitor C48 and the collector of the triode Q12.

[0030] The second end of the resistor R84, the second end of the capacitor C51, the second end of the resistor R85, and the emitter of the triode Q12 are grounded.

[0031] Further, the fault detection circuit comprises a four-input NAND gate circuit and a PWM circuit, an output end of the four-input NAND gate circuit being connected to an input end of the PWM circuit.

[0032] Further, the controllable distribution board further comprises a pre-charge driving circuit, the pre-charge driving circuit being connected to the pre-charge circuit.

[0033] The pre-charge driving circuit comprises a pre-charge driving chip U18, a resistor R67, a resistor R73, a resistor R65, a resistor R69, a capacitor C43 and a capacitor C46.

[0034] A first end of the resistor R67 is connected to a pin 1 of the pre-charge driving chip U18, and a pre-charge driving power supply is connected to the pin 1.

[0035] A first end of the resistor R65 is connected to a pin 2 of the pre-charge driving chip U18.

[0036] A pin 4 of the pre-charge driving chip U18 is connected to the pre-charge circuit.

[0037] A second end of the resistor R67 and a first end of the resistor R73 are connected to a pin 5 of the pre-charge driving chip U18.

[0038] A first end of the resistor R69 is connected to a pin 7 of the pre-charge driving chip U18.

[0039] A second end of the resistor R69 and a first end of the capacitor C46 are connected to a pin 6 of the pre-charge driving chip U18.

[0040] A first end of the capacitor C43 is connected to a pin 9 of the pre-charge driving chip U18.

[0041] A second end of the capacitor C43 is connected to a pin 8 of the pre-charge driving chip U18.

[0042] A pin 3 and a pin 11 of the pre-charge driving chip U18, a second end of the resistor R73, a second end of the resistor R65 and a second end of the capacitor C46 are grounded.

[0043] Further, the controllable distribution board further comprises a load delay circuit, the load delay circuit being connected to the load main passage.

[0044] Further, the controllable distribution board further comprises a step-down circuit, an input end of the step-down circuit being connected to the switch circuit, and an output end of the step-down circuit being connected to the fault detection circuit.

[0045] The voltage reduction circuit comprises two DC-DC voltage reduction branches and three LDO voltage reduction branches, the two DC-DC voltage reduction branches are connected in parallel, the three LDO voltage reduction branches are connected in parallel, and the output ends of the two DC-DC voltage reduction branches are connected to the input ends of the three LDO voltage reduction branches.

[0046] Further, the controllable power distribution board further comprises a pre-charge independent switch circuit connected to the pre-charge circuit.

[0047] The application provides a controllable power distribution board for a UAV, wherein a load main path is arranged on the controllable power distribution board, a plurality of parallel load branches composed of load MOS tubes, gate drive circuits and differential amplification circuits are arranged on the load main path, parallel redundancy design is formed, and input power distribution stability is improved; a power-on buffer mechanism composed of a pre-charge circuit and a pre-charge delay circuit is arranged, which can effectively avoid the phenomenon that a circuit fails due to a transient large current impact during the first power-on, realize surge impact protection, and prolong the service life of the controllable power distribution board; a switch circuit is arranged to form switch on-off protection for the circuit; a fault detection circuit is arranged to timely detect circuit failure phenomena and form fault detection protection for the circuit, thereby improving the operation safety and stability of the controllable power distribution board and even the UAV, and optimizing the working efficiency of the UAV. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0049] Figure 1 is a circuit module architecture diagram of the controllable power distribution board in the embodiment of the present application;

[0050] Figure 2 is a circuit module architecture diagram of the load branch in the embodiment of the present application;

[0051] Figure 3 is a circuit principle diagram of the gate drive circuit in the embodiment of the present application;

[0052] Figure 4 is a circuit principle diagram of the differential amplification circuit in the embodiment of the present application;

[0053] Figure 5 is a circuit principle diagram of the switch circuit in the embodiment of the present application;

[0054] Figure 6 is a circuit principle diagram of the pre-charge circuit in the embodiment of the present application;

[0055] Figure 7 is a circuit schematic diagram of a pre-charge delay circuit in an embodiment of the present application;

[0056] Figure 8 is a circuit schematic diagram of a pre-charge driving circuit in an embodiment of the present application;

[0057] Figure 9 is a circuit module architecture diagram of a fault detection circuit in an embodiment of the present application;

[0058] Figure 10 is a circuit schematic diagram of a four-input NAND gate circuit in an embodiment of the present application;

[0059] Figure 11 is a circuit module architecture diagram of a voltage reduction circuit in an embodiment of the present application;

[0060] Figure 12 is a circuit schematic diagram of a first DC-DC voltage reduction branch in an embodiment of the present application;

[0061] Figure 13 is a circuit schematic diagram of a first LDO voltage reduction branch in an embodiment of the present application;

[0062] Figure 14 is a circuit schematic diagram of a third LDO voltage reduction branch in an embodiment of the present application. DETAILED DESCRIPTION

[0063] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0064] In the present application, it should be understood that terms such as “include” or “have” are intended to indicate that there exist the features, numbers, steps, actions, components, parts or combinations thereof disclosed in the specification, and do not exclude the possibility that one or more other features, numbers, steps, actions, components, parts or combinations thereof exist or are added.

[0065] In addition, it should be further noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0066] The embodiment of the present application provides a controllable power distribution board for a UAV, the controllable power distribution board comprises a load main path, a pre-charging circuit, a pre-charging delay circuit, a switching circuit and a fault detection circuit, the load main path is connected with the switching circuit, the pre-charging circuit and the fault detection circuit respectively, an input end of the load main path is connected with an input power supply, and an output end of the load main path is connected with a load, and the pre-charging delay circuit is connected with the pre-charging circuit.

[0067] In an optional implementation of the embodiment, as shown in Figure 1 , Figure 1 The circuit module architecture diagram of the controllable power distribution board in the embodiment of the present application is shown, the controllable power distribution board comprises a load main path, a pre-charging circuit, a pre-charging delay circuit, a switching circuit and a fault detection circuit, the load main path is connected with the switching circuit, the pre-charging circuit and the fault detection circuit respectively, an input end of the load main path is connected with an input power supply, and an output end of the load main path is connected with a load, and the pre-charging delay circuit is connected with the pre-charging circuit.

[0068] In an optional implementation of the embodiment, the load main path comprises a plurality of load branches, the plurality of load branches are connected in parallel, any one load branch comprises a load MOS tube, a gate drive circuit and a differential amplification circuit, the gate drive circuit is connected with the gate of the load MOS tube, and the differential amplification circuit is connected in parallel between the gate and the source of the load MOS tube.

[0069] Specifically, as shown in Figure 2 , Figure 2 The circuit module architecture diagram of the load branch in the embodiment of the present application is shown, five parallel load branches are arranged in the embodiment, the circuit structures of each load branch are completely consistent, each load branch comprises a load MOS tube, a gate drive circuit and a differential amplification circuit, the connection relationship is also completely consistent, the gate drive circuit is connected with the gate of the load MOS tube, and the differential amplification circuit is connected in parallel between the gate and the source of the load MOS tube.

[0070] It should be noted that, since the circuit structures of each load branch are completely consistent, and the connection relationship is also completely consistent, only the circuit structure of one load branch is shown in the drawing.

[0071] In an optional implementation of the embodiment, the working principle of the load main path comprises:

[0072] The load main path is composed of five parallel load branches, the rated current of the load MOS tube in a single load branch is 300 A, and the five parallel load branches can bear 1500 A current after parallel connection, so that large redundancy design is realized, and the large power requirement of the multi-motor UAV in the application scenario of the embodiment is met.

[0073] The load branches do not interfere with each other, and if one branch is damaged, the other branches can still continue to work normally.

[0074] In an optional implementation of this embodiment, the load MOSFET is model IPT015N10N5.

[0075] Specifically, the IPT015N10N5 is an N-channel enhancement-mode MOSFET, commonly used in applications such as load switching and power management, and has the advantages of high cost-effectiveness, low power consumption, and strong adaptability.

[0076] In one optional implementation of this embodiment, such as Figure 3 As shown, Figure 3 The circuit diagram of the gate driving circuit in an embodiment of the present invention is shown. The gate driving circuit includes a gate driving chip U1, resistors R1, R2, and R3, capacitors C1, C2, and C3, diodes D1, D2, D3, and D4.

[0077] Pin 1 of the gate driver chip U1 and the first end of capacitor C1 are connected to the positive terminal of the drive power supply.

[0078] Pin 5 of the gate driver chip U1 is connected to the first terminal of the capacitor C2, the cathode of the diode D2, and the cathode of the diode D4.

[0079] Pin 6 of the gate driver chip U1 is connected to the first end of the resistor R3;

[0080] Pin 7 of the gate driver chip U1 is connected to the second terminal of the capacitor C2, the anode of the diode D3, the anode of the diode D4, and the first terminal of the resistor R2.

[0081] Pin 8 of the gate driver chip U1 is connected to the cathode of the diode D1 and the first end of the resistor R1.

[0082] The anode of diode D2 is connected to the cathode of diode D3 and the first terminal of capacitor C3;

[0083] The second end of the resistor R1 is connected to the second end of the capacitor C3;

[0084] Pin 4 of the gate driver chip U1, the second terminal of capacitor C1, the anode of diode D1, and the second terminal of resistor R2 are grounded.

[0085] Furthermore, such as Figure 3 As shown, Figure 3The diagram also shows a load MOSFET M1 located on the same load branch as the gate drive circuit. The second end of resistor R3 is connected to the source of the load MOSFET M1, and pin 7 of the gate drive chip U1, the second end of capacitor C2, the anode of diode D3, the anode of diode D4, and the first end of resistor R2 are connected to the gate of the load MOSFET M1.

[0086] Furthermore, the gate driver chip is model LTC7001IMSE.

[0087] Specifically, the LTC7001IMSE is an N-channel enhancement-mode MOSFET, commonly used in applications such as load switching and power management, and has the advantages of high cost-effectiveness, low power consumption, and strong adaptability.

[0088] Furthermore, the capacitance values ​​of capacitors C1 and C2 are 1uF, the capacitance value of capacitor C3 is 50nF, the rated voltage is 250V, the resistance value of resistor R1 is 10Ω, the resistance value of resistor R2 is 500kΩ, the resistance value of resistor R3 is 750Ω, and the diodes D1 and D4 are Schottky diodes.

[0089] In an optional implementation of this embodiment, the operating principle of the gate drive circuit includes:

[0090] The gate drive circuit in each load branch drives the load MOSFET in the corresponding load branch independently based on the gate drive chip. The load branches do not interfere with each other and can effectively drive the load MOSFET.

[0091] Here, a gate drive circuit is set up to drive the load MOSFET, thereby realizing the drive control of the load MOSFET.

[0092] In one optional implementation of this embodiment, such as Figure 4 As shown, Figure 4 The circuit diagram of the differential amplifier circuit in an embodiment of the present invention is shown. The differential amplifier circuit includes amplifier U26, resistor R89, resistor R93, resistor R96, resistor R99 and resistor R103.

[0093] The positive input terminal of the amplifier U26 is connected to the first terminal of the resistor R89 ​​and the first terminal of the resistor R93;

[0094] The negative input terminal of the amplifier U26 is connected to the first terminal of the resistor R99 and the first terminal of the resistor R103;

[0095] The output terminal of the amplifier U26 is connected to the first terminal of the resistor R96 and the second terminal of the resistor R103.

[0096] The second end of the resistor R93 and the second end of the resistor R99 are connected to the load MOS tube;

[0097] The second end of the resistor R96 is connected to the input end of the four-input NAND gate circuit.

[0098] Further, the model of the amplifier U26 is LMV321-TR, the resistance values of the resistor R89 and the resistor R103 are 4K, and the resistance values of the resistor R93, the resistor R99 and the resistor R96 are 1K.

[0099] In an optional implementation manner of the embodiment, the working principle of the differential amplification circuit comprises:

[0100] After the output voltage of the load MOS tube is amplified by the amplifier, the output voltage is input into the subsequent fault detection circuit for detection.

[0101] Here, the differential amplification circuit is arranged to amplify the output of the load MOS tube, facilitating the subsequent load fault detection work,

[0102] In an optional implementation manner of the embodiment, as shown in Figure 5 Figure 5 The circuit principle diagram of the switch circuit in the embodiment of the application is shown, and the switch circuit comprises a double-pole double-throw switch SW, a resistor R75, a resistor R84, a resistor R81, a resistor R85, a resistor R79, a capacitor C48, a capacitor C51 and a triode Q12.

[0103] The first end of the resistor R75 is connected to the positive pole of the first switch power supply.

[0104] The second end of the resistor R75 is connected to the second end of the double-pole double-throw switch SW and the first end of the resistor R84.

[0105] The third end of the double-pole double-throw switch SW is connected to the first end of the capacitor C48.

[0106] The first end of the double-pole double-throw switch SW is connected to the first end of the resistor R81, the first end of the capacitor C51, the first end of the resistor R85 and the base of the triode Q12.

[0107] The first end of the resistor R79 is connected to the positive pole of the second switch power supply.

[0108] The second end of the resistor R79 is connected to the second end of the capacitor C48 and the collector of the triode Q12.

[0109] The second end of the resistor R84, the second end of the capacitor C51, the second end of the resistor R85 and the emitter of the triode Q12 are grounded.

[0110] ​Further, the resistance value of the resistor R75 is 45K, the resistance value of the resistor R84 and the resistor R81 is 4.99K, the resistance value of the resistor R85 is 100K, the resistance value of the resistor R79 is 12K, the capacitance value of the capacitor C48 and the capacitor C51 is 1uF, and the transistor Q12 is an NPN channel type MOS tube.

[0111] In an optional implementation of the embodiment, the working principle of the switch circuit comprises:

[0112] The power supply control of the controllable distribution board is realized by the dialing of the double-pole double-throw switch SW. When the double-pole double-throw switch SW is dialed to the second end and the third end, it is in an "ON" state, the power supply is turned on, and the distribution board normally works. When the double-pole double-throw switch SW is dialed to the first end and the third end, it is in an "OFF" state, the power supply is cut off, and the distribution board stops working.

[0113] Here, the switch circuit is set, and the double-pole double-throw switch is set to form switch on-off protection for the load main path and realize switching of the working state.

[0114] In an optional implementation of the embodiment, the pre-charge circuit is used to perform pre-charge operation on the load main path.

[0115] Specifically, as shown in Figure 6 , Figure 6 a circuit principle diagram of the pre-charge circuit in the embodiment is shown, the pre-charge circuit comprises a pre-charge MOS tube Q6, a resistor R8, a diode D8, and a pre-charge resistor R4;

[0116] The gate of the pre-charge MOS tube Q6 is connected to the first end of the resistor R8 and the anode of the diode D8.

[0117] The drain of the pre-charge MOS tube Q6 is connected to the first end of the pre-charge resistor R4.

[0118] The second end of the pre-charge resistor R4 is connected to an input power supply.

[0119] The second end of the resistor R8 is connected to the cathode of the diode D8.

[0120] Further, the model of the pre-charge MOS tube Q6 is IPT015N10N5, the resistance value of the resistor R8 is 33, and the resistance value of the pre-charge resistor R4 is 10.

[0121] Further, the resistance value of the pre-charge resistor R4 can be adjusted according to actual needs, and a programmable resistor can be used instead.

[0122] In an optional implementation of the embodiment, the working principle of the pre-charge circuit comprises:

[0123] The pre-charging circuit is connected in parallel with the load main channel composed of multiple load branches in parallel, and is realized by a pre-charging MOS tube and a pre-charging resistor in series, thereby effectively eliminating the large current impact in the power-on moment.

[0124] The specific working process includes: the power-on of the power distribution board, the conduction of the pre-charging MOS tube Q6, the slow charging of the capacitive load of the load main channel by the input power supply through the pre-charging resistor R4, and the control of the pre-charging current size by the pre-charging resistor R4 through the setting of the resistance value, thereby avoiding the risk of the large current in the power-on moment to the circuit.

[0125] Here, the pre-charging circuit is set to perform the pre-charging operation on the load main channel, thereby avoiding the damage caused by the impact of the large current of the power distribution board in the power-on moment and realizing the power-on buffer mechanism protection of the circuit.

[0126] In an optional implementation of the embodiment, the pre-charging delay circuit is used to control the duration of the pre-charging operation of the pre-charging circuit.

[0127] Specifically, as shown in Figure 7 , the pre-charging delay circuit includes a NE555 timer U7, a resistor R24, a resistor R27, a capacitor C18, a capacitor C22, and a diode D14. Figure 7 In addition to the circuit principle diagram of the pre-charging delay circuit in the embodiment of the application, the pre-charging delay circuit includes a NE555 timer U7, a resistor R24, a resistor R27, a capacitor C18, a capacitor C22, and a diode D14.

[0128] The pin 4 and the pin 8 of the NE555 timer U7, the first end of the resistor R24, the first end of the resistor R27, and the cathode of the diode D14 are connected to the positive electrode of the delay circuit power supply.

[0129] The pin 5 of the NE555 timer U7 is connected to the first end of the capacitor C18.

[0130] The pin 2 and the pin 6 of the NE555 timer U7 are connected to the second end of the resistor R24, the anode of the diode D14, and the first end of the capacitor C22.

[0131] The pin 1 of the NE555 timer U7, the second end of the capacitor C18, the second end of the capacitor C22, and the second end of the resistor R27 are grounded.

[0132] Further, the resistance value of the resistor R24 is 200K, the resistance value of the resistor R27 is 4.99K, the capacitance value of the capacitor C18 is 0.01uF, the capacitance value of the capacitor C22 is 6.8uF, and the diode D14 is a Schottky diode.

[0133] In an optional implementation of the embodiment, the working principle of the pre-charging delay circuit includes:

[0134] The delay circuit is constructed by using NE555 timer, after power on, the NE555 timer outputs high level, controls the pre-charge MOS tube to be turned on, and lasts for a period of time (the pre-charge time can be adjusted by the RC circuit), after the pre-charge is completed, the NE555 timer outputs low level, and controls the pre-charge MOS tube to be cut off.

[0135] Further, the NE555 timer U7 works in a monostable trigger mode, when the pin 2 voltage of the NE555 timer U7 is <1 / 3VCC, the input trigger state is entered, the pin 3 outputs a high level pulse with a fixed pulse width, and the fixed pulse width is determined by the charging resistor R24 and the energy storage capacitor C22, the pin 4 is connected to VCC to prohibit reset, and the pin 5 is connected to the capacitor C18, which is used for stabilizing the threshold level, and ensuring the stability of the reference voltages 1 / 3VCC and 2 / 3VCC.

[0136] The diode D14 is used as a Schottky diode to accelerate the charging and discharging of the capacitor, so as to ensure the timing accuracy, when the diode D14 is turned on in the forward direction, the charging loop resistor is small, and the capacitor is accelerated to charge; when the diode D14 is cut off in the reverse direction, the capacitor is forced to discharge quickly through the small resistance R27, and the circuit recovery period is shortened.

[0137] The working principle of the NE555 timer triggering and outputting a level pulse includes that the pin 3 of the NE555 timer is connected to a Schmitt trigger, when the NE555 timer outputs a high level pulse, the Schmitt trigger outputs a low level; when the NE555 timer outputs a low level pulse, the Schmitt trigger outputs a high level, and the output end of the Schmitt trigger is connected to the gate drive chip U1, so as to realize the mechanism of high level enabling and low level disabling.

[0138] Here, the pre-charge delay circuit is arranged to force the pre-charge operation to last for a fixed time, so as to ensure that the capacitive load of the pre-charge circuit is switched to the main load path after the charging is completed, and voltage mutation is avoided; the parameters of the resistor R24 and the capacitor C22 are adjusted to adapt to the load demand of different capacities, and better safety and adaptability are achieved.

[0139] In an optional implementation of the embodiment, the controllable distribution board further includes a pre-charge driving circuit, and the pre-charge driving circuit is connected to the pre-charge circuit.

[0140] Specifically, as shown in Figure 8 , Figure 8 The circuit principle diagram of the pre-charge driving circuit in the embodiment of the application is shown, and the pre-charge driving circuit includes a pre-charge driving chip U18, a resistor R67, a resistor R73, a resistor R65, a resistor R69, a capacitor C43 and a capacitor C46.

[0141] The pin 1 of the pre-charge driving chip U18 is connected to the first end of the resistor R67 and connected to a pre-charge driving power supply.

[0142] Pin 2 of the pre-charge driving chip U18 is connected to the first end of the resistor R65;

[0143] Pin 4 of the pre-charge driving chip U18 is connected to the pre-charge circuit;

[0144] Pin 5 of the pre-charge driving chip U18 is connected to the second end of the resistor R67 and the first end of the resistor R73;

[0145] Pin 7 of the pre-charge driving chip U18 is connected to the first end of the resistor R69;

[0146] Pin 6 of the pre-charge driving chip U18 is connected to the second end of the resistor R69 and the first end of the capacitor C46;

[0147] Pin 9 of the pre-charge driving chip U18 is connected to the first end of the capacitor C43;

[0148] Pin 8 of the pre-charge driving chip U18 is connected to the second end of the capacitor C43;

[0149] Pin 3 and Pin 11 of the pre-charge driving chip U18, the second end of the resistor R73, the second end of the resistor R65, and the second end of the capacitor C46 are grounded.

[0150] Further, the model of the pre-charge driving chip U18 is LTC7001, the resistance value of the resistor R67 is 590k, the resistance value of the resistor R73 is 12k, the resistance value of the resistor R65 is 71.5k, the resistance value of the resistor R69 is 220k, the capacitance value of the capacitor C43 is 0.1uF, and the capacitance value of the capacitor C46 is 0.47uF with a rated voltage of 100V.

[0151] In an optional implementation manner of the embodiment, the pre-charge driving circuit is used to drive the pre-charge circuit to work, and the working principle of the pre-charge driving circuit includes that the pre-charge driving chip U18 drives the pre-charge circuit to work.

[0152] In an optional implementation manner of the embodiment, the overall working principle of the pre-charge circuit, the pre-charge delay circuit, and the pre-charge driving circuit includes that:

[0153] Based on the timing logic of "pre-charge first start, load main loop start later", after the power distribution board is powered on, the pre-charge driving circuit drives the pre-charge MOS tube in the pre-charge circuit to trigger, and based on the control output high level of the pre-charge delay circuit, and lasts for 2.2 seconds; the load MOS tube of the load main loop is triggered after the power distribution board is powered on, outputs high level, lasts for 1.5 seconds, and the timing difference of the pre-charge MOS tube and the load MOS tube is 0.7 seconds, which ensures the timing logic of "pre-charge first start, load main loop start later", and improves the stability of the overall circuit.

[0154] In one optional implementation manner of the embodiment, as shown in Figure 9 , Figure 9 The circuit module architecture diagram of the fault detection circuit in the embodiment of the application is shown, the fault detection circuit comprises a four-input NAND gate circuit and a PWM circuit, and an output end of the four-input NAND gate circuit is connected to an input end of the PWM circuit.

[0155] In one optional implementation manner of the embodiment, as shown in Figure 10 , Figure 10 The circuit principle diagram of the four-input NAND gate circuit in the embodiment of the application is shown, the four-input NAND gate circuit comprises a four-input NAND gate U20, and the model of the four-input NAND gate circuit is 74HC00PW,118.

[0156] In one optional implementation manner of the embodiment, the fault detection circuit further comprises an LED indicator lamp, and the LED indicator lamp is connected to an output end of the PWM circuit.

[0157] In one optional implementation manner of the embodiment, the working principle of the fault detection circuit comprises:

[0158] A differential amplification circuit is connected in parallel between the source and the gate of the load MOS tube of the load branch, and the source-gate voltage difference is 12V when normally turned on, and when damage occurs, the source-gate voltage deviates from the threshold value (<6V), and a low level is output to the four-input NAND gate;

[0159] The output signals of the multiple load branches are connected to the four-input NAND gate, when any one of them fails, the NAND gate outputs a high level to the PWM circuit, drives the LED indicator lamp to flicker, and realizes visual alarm of the fault;

[0160] In one optional implementation manner of the embodiment, as shown in Figure 1 , the controllable power distribution board further comprises a load delay circuit, and the load delay circuit is connected to the load main path.

[0161] Specifically, the load delay circuit comprises an NE555 timer, which is used for controlling the conduction and cutoff of the load MOS tube in the load branch in the load main path.

[0162] When the pre-charge MOS tube in the pre-charge circuit is cut off, a high level is outputted to make the load MOS tube in the load branch conductive.

[0163] In an optional implementation of the embodiment, the controllable distribution board further comprises a voltage reduction circuit, an input end of the voltage reduction circuit being connected to the switch circuit, and an output end of the voltage reduction circuit being connected to the fault detection circuit.

[0164] Specifically, as shown in Figure 11 Figure 11 A circuit module architecture diagram of the voltage reduction circuit in the embodiment is shown, the voltage reduction circuit comprising two DC-DC voltage reduction branches and three LDO voltage reduction branches, the two DC-DC voltage reduction branches being connected in parallel, the three LDO voltage reduction branches being connected in parallel, and output ends of the two DC-DC voltage reduction branches being connected to input ends of the three LDO voltage reduction branches.

[0165] Further, the two DC-DC voltage reduction branches comprise a first DC-DC voltage reduction branch and a second DC-DC voltage reduction branch, the first DC-DC voltage reduction branch and the second DC-DC voltage reduction branch being connected in parallel, and circuit structures of the first DC-DC voltage reduction branch and the second DC-DC voltage reduction branch being completely identical.

[0166] The three LDO voltage reduction branches comprise a first LDO voltage reduction branch, a second LDO voltage reduction branch and a third LDO voltage reduction branch, the first LDO voltage reduction branch, the second LDO voltage reduction branch and the third LDO voltage reduction branch being connected in parallel, and circuit structures of the first LDO voltage reduction branch and the second LDO voltage reduction branch being completely identical.

[0167] In an optional implementation of the embodiment, as shown in Figure 12 Figure 12 A circuit principle diagram of the first DC-DC voltage reduction branch in the embodiment is shown, the first DC-DC voltage reduction branch comprising a DC-DC voltage reduction chip U6, a capacitor C14, a capacitor C15, a resistor R21, a capacitor C8, a resistor R16, a capacitor C16, a capacitor C11, an inductor L1, a resistor R19, a resistor R23, a capacitor C17, a resistor R17, a resistor R22 and a diode D10.

[0168] A first end of the capacitor C14, a first end of the capacitor C15 and a pin 2 of the DC-DC voltage reduction chip U6 are connected to an input power supply;

[0169] A pin 3 of the DC-DC voltage reduction chip U6 is connected to the switch circuit;

[0170] A first end of the resistor R21 is connected to a pin 4 of the DC-DC voltage reduction chip U6.​​

[0171] The pin 5 of the DC-DC step-down chip U6 is connected with the first end of the capacitor C16, the first end of the resistor R19, and the first end of the resistor R23.

[0172] The pin 7 of the DC-DC step-down chip U6 is connected with the first end of the capacitor C8.

[0173] The pin 8 of the DC-DC step-down chip U6 is connected with the second end of the capacitor C8, the first end of the inductor L1, and the first end of the resistor R16.

[0174] The second end of the resistor R16, the first end of the capacitor C11, and the second end of the capacitor C16 are connected with each other.

[0175] The second end of the inductor L1, the second end of the capacitor C11, the second end of the resistor R19, the first end of the capacitor C17, the first end of the resistor R17, and the anode of the diode D10 are connected with each other.

[0176] The pin 1 and the pin 9 of the DC-DC step-down chip U6, the second end of the capacitor C14, the second end of the capacitor C15, the second end of the resistor R21, the second end of the resistor R23, the second end of the capacitor C17, and the first end of the resistor R22 are grounded.

[0177] The second end of the resistor R17 and the second end of the resistor R22 are connected with the fault detection circuit.

[0178] Further, the capacitance value of the capacitor C14 and the capacitor C17 is 10uF, the capacitance value of the capacitor C15 is 4.7uF, the capacitance value of the capacitor C8 and the capacitor C11 is 2.2nF, the capacitance value of the capacitor C16 is 47pF, the resistance value of the resistor R21 is 82.5k, the resistance value of the resistor R16 is 511K, the resistance value of the resistor R19 is 732K, the resistance value of the resistor R23 is 101K, the resistance value of the resistor R17 is 5.76K, the resistance value of the resistor R22 is 4K, the inductance value of the inductor L1 is 56uH, and the diode D10 is a Schottky diode.

[0179] The model of the DC-DC step-down chip U6 is LM5164DDAR.

[0180] It should be noted that, since the circuit structures of the first DC-DC step-down branch and the second DC-DC step-down branch are completely consistent, only the circuit schematic diagram of the first DC-DC step-down branch is shown here.

[0181] The working principle of the two DC-DC step-down branches in parallel includes:

[0182] The level signal of the switching circuit is received through the pin 3 of the DC-DC voltage reduction chip, when the received level signal is greater than 1.2V, the DC-DC voltage reduction branch works, and the input power is reduced to 10V output.

[0183] Here, two DC-DC voltage reduction branches are connected in parallel to prevent the voltage reduction operation from being unable to be performed when one branch is damaged.

[0184] In an optional implementation of the embodiment, as shown in Figure 13 , Figure 13 The circuit schematic diagram of the first LDO voltage reduction branch in the embodiment is shown, the first LDO voltage reduction branch comprises an LDO voltage reduction chip U12, a capacitor C35, a capacitor C34, and a diode D17.

[0185] The pin 1 of the LDO voltage reduction chip U12 is connected to the first end of the capacitor C34 and the anode of the diode D17.

[0186] The pin 2 of the LDO voltage reduction chip U12 and the first end of the capacitor C35 are connected to the output end of the two DC-DC voltage reduction branches.

[0187] The pin 3 of the LDO voltage reduction chip U12, the second end of the capacitor C34, and the second end of the capacitor C35 are grounded.

[0188] Further, the capacitance value of the capacitor C34 is 0.1uF, the capacitance value of the capacitor C35 is 0.33uF, the diode D17 is a Schottky diode, and the model of the LDO voltage reduction chip U12 is CJ78L05.

[0189] It should be noted that, since the circuit structures of the first LDO voltage reduction branch and the second LDO voltage reduction branch are completely consistent, only the circuit schematic diagram of the first LDO voltage reduction branch is shown here.

[0190] In an optional implementation of the embodiment, as shown in Figure 14 , Figure 14 The circuit schematic diagram of the third LDO voltage reduction branch in the embodiment is shown, the third LDO voltage reduction branch comprises an LDO voltage reduction chip U14, a capacitor C32, an inductor L3, a resistor R44, a capacitor C33, and a diode D16.

[0191] The pin 2 and 3 of the LDO voltage reduction chip U14 and the first end of the capacitor C32 are connected to the output end of the three DC-DC voltage reduction branches.

[0192] The pin 6 of the LDO voltage reduction chip U14 is connected to the first end of the resistor R44, the first end of the inductor L3, the first end of the capacitor C33, and the anode of the diode D16.

[0193] The pin 7 of the LDO step-down chip U14 is connected to the second end of the inductor L3.

[0194] The pin 8 of the LDO step-down chip U14 is connected to the second end of the resistor R44.

[0195] The pins 1, 4, 5, 9 of the LDO step-down chip U14, the second end of the capacitor C32, and the second end of the capacitor C33 are grounded.

[0196] Further, the capacitance values of the capacitors C32 and C33 are 10uF, the resistance value of the resistor R44 is 100K, the inductance value of the inductor L3 is 2.2uH, the diode D16 is a Schottky diode, and the model of the LDO step-down chip U14 is TPS62163DSGR.

[0197] The working principle of the three-way parallel LDO step-down branch includes:

[0198] The 10V voltage output by the two-way DC-DC step-down branch is reduced to 5V voltage output, meeting the power supply requirements of some circuit devices.

[0199] In an optional implementation manner of the embodiment, the fault detection circuit further includes a fault detection MCU, which is connected to the four-input NAND gate circuit and the PWM circuit respectively, and is connected to the step-down circuit.

[0200] Specifically, the circuit connected to the fault detection MCU of the step-down circuit is an independent electronic switch path, and the EN pin of the step-down circuit is pulled high by the fault detection MCU to realize circuit shutdown.

[0201] In an optional implementation manner of the embodiment, the controllable distribution board further includes a pre-charge independent switch circuit, which is connected to the pre-charge circuit.

[0202] Specifically, the pre-charge independent switch circuit is used to control the separate on-off operation of the pre-charge circuit.

[0203] Working principle: the double-pole double-throw switch in the switch circuit is switched from the first end to the third end, the step-down circuit works, the controllable distribution board is powered, the pre-charge delay circuit starts, the pre-charge circuit is turned on, and the pre-charge operation starts;

[0204] After the pre-charge operation, the load delay circuit starts, and the load main path is turned on.

[0205] The source and the gate of the load MOS tube of the load main channel are provided with a differential amplification circuit, and an opening voltage detection mechanism is set: when the load MOS tube is in the on state, the gate drive circuit applies a voltage of about 12V at the source-gate of the load MOS tube, and outputs a high level to the four-input NAND gate through the differential amplification circuit, when the output is low level, the four-input NAND gate outputs high level, and fault indication is performed.

[0206] In summary, the embodiment of the present application provides a controllable power distribution board for a UAV, a load main channel is arranged on the controllable power distribution board, and a plurality of parallel load branches composed of a load MOS tube, a gate drive circuit and a differential amplification circuit are arranged, parallel redundancy design is formed, and input power distribution stability is improved; a power-on buffering mechanism composed of a pre-charge circuit and a pre-charge delay circuit is arranged, which effectively avoids the phenomenon that a circuit fails due to a large instantaneous current impact during the first power-on, realizes surge impact protection, and prolongs the service life of the controllable power distribution board; a switching circuit is arranged to form switching on-off protection for the circuit; a fault detection circuit is arranged to detect circuit failure in a timely manner, and form fault detection protection for the circuit, thereby improving the operation safety and stability of the controllable power distribution board and even the UAV, and optimizing the work efficiency of the UAV.

[0207] The above describes in detail the controllable power distribution board for a UAV provided by the present application, and those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by programs instructing related hardware, and the programs can be stored in a computer readable storage medium, and the storage medium can include a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0208] In addition, the above describes in detail the embodiment of the present application, and the principles and implementation manners of the present application are described by using specific examples; the above embodiment is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will be changed, and the above description should not be understood as a limitation of the present application.

Claims

1. A controllable power panel for a drone, comprising: The controllable distribution board comprises a load main path, a pre-charging circuit, a pre-charging delay circuit, a switch circuit and a fault detection circuit, the load main path is connected with the switch circuit, the pre-charging circuit and the fault detection circuit respectively, an input end of the load main path is connected with an input power supply, and an output end of the load main path is connected with a load. The pre-charging circuit is used for pre-charging the load main path, and comprises a pre-charging MOS tube Q6, a resistor R8, a diode D8 and a pre-charging resistor R4. The pre-charging delay circuit is used for controlling the duration of the pre-charging operation of the pre-charging circuit, and comprises an NE555 timer U7, a resistor R24, a resistor R27, a capacitor C18, a capacitor C22 and a diode D14.

2. The controllable power panel for a drone of claim 1, wherein, The load main path comprises a plurality of load branches, the plurality of load branches are connected in parallel, and any one load branch comprises a load MOS tube, a gate drive circuit and a differential amplification circuit.

3. The controllable power panel for a drone of claim 2, wherein, The gate drive circuit comprises a gate drive chip U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a capacitor C3, a diode D1, a diode D2, a diode D3 and a diode D4. A pin 1 of the gate drive chip U1 and a first end of the capacitor C1 are connected with a driving power supply positive pole. A pin 5 of the gate drive chip U1 is connected with a first end of the capacitor C2, a cathode of the diode D2 and a cathode of the diode D4. A pin 6 of the gate drive chip U1 is connected with a first end of the resistor R3. A pin 7 of the gate drive chip U1 is connected with a second end of the capacitor C2, an anode of the diode D3, an anode of the diode D4 and a first end of the resistor R2. A pin 8 of the gate drive chip U1 is connected with a cathode of the diode D1 and a first end of the resistor R1. An anode of the diode D2 is connected with a cathode of the diode D3 and a first end of the capacitor C3. A second end of the resistor R1 is connected with a second end of the capacitor C3. The pin 4 of the gate drive chip U1, the second end of the capacitor C1, the anode of the diode D1, and the second end of the resistor R2 are grounded.

4. The controllable power panel for a drone of claim 2, wherein, The differential amplifier circuit comprises an amplifier U26, resistors R89, R93, R96, R99, and R103; The positive input end of the amplifier U26 is connected to the first end of the resistor R89 and the first end of the resistor R93; The negative input end of the amplifier U26 is connected to the first end of the resistor R99 and the first end of the resistor R103; The output end of the amplifier U26 is connected to the first end of the resistor R96 and the second end of the resistor R103; The second end of the resistor R93 and the second end of the resistor R99 are connected to the load MOS tube; The second end of the resistor R96 is connected to the input end of the fault detection circuit.

5. The controllable power panel for a drone of claim 1, wherein, The switch circuit comprises a double-pole double-throw switch SW, resistors R75, R84, R81, R85, R79, capacitors C48 and C51, and a triode Q12; The first end of the resistor R75 is connected to the second end of the double-pole double-throw switch SW and the first end of the resistor R84; The third end of the double-pole double-throw switch SW is connected to the first end of the capacitor C48; The first end of the double-pole double-throw switch SW is connected to the first end of the resistor R81, the first end of the capacitor C51, the first end of the resistor R85, and the base of the triode Q12; The first end of the resistor R79 is connected to the second end of the capacitor C48 and the collector of the triode Q12; The second end of the resistor R84, the second end of the capacitor C51, the second end of the resistor R85, and the emitter of the triode Q12 are grounded.

6. The controllable power panel for a drone of claim 1, wherein, The fault detection circuit comprises a four-input NAND gate circuit and a PWM circuit, and the output end of the four-input NAND gate circuit is connected to the input end of the PWM circuit.

7. The controllable power panel for a drone of claim 1, wherein, The controllable distribution board further comprises a pre-charge driving circuit connected to the pre-charge circuit. The pre-charge driving circuit comprises a pre-charge driving chip U18, resistors R67, R73, R65, R69, capacitors C43 and C46; Pin 1 of the pre-charge driving chip U18 is connected to the first end of the resistor R67 and a pre-charge driving power supply; Pin 2 of the pre-charge driving chip U18 is connected to the first end of the resistor R65; Pin 4 of the pre-charge driving chip U18 is connected to the pre-charge circuit; Pin 5 of the pre-charge driving chip U18 is connected to the second end of the resistor R67 and the first end of the resistor R73; Pin 7 of the pre-charge driving chip U18 is connected to the first end of the resistor R69; Pin 6 of the pre-charge driving chip U18 is connected to the second end of the resistor R69 and the first end of the capacitor C46; Pin 9 of the pre-charge driving chip U18 is connected to the first end of the capacitor C43; Pin 8 of the pre-charge driving chip U18 is connected to the second end of the capacitor C43; Pin 3 and pin 11 of the pre-charge driving chip U18, the second end of the resistor R73, the second end of the resistor R65, and the second end of the capacitor C46 are grounded.

8. The controllable power panel for a drone of claim 1, wherein, The controllable distribution board further comprises a load delay circuit, and the load delay circuit is connected to the load main passage.

9. The controllable power panel for a drone of claim 1, wherein, The controllable distribution board further comprises a voltage reduction circuit, an input end of the voltage reduction circuit is connected to the switch circuit, and an output end of the voltage reduction circuit is connected to the fault detection circuit. The voltage reduction circuit comprises two DC-DC voltage reduction branches and three LDO voltage reduction branches, the two DC-DC voltage reduction branches are connected in parallel, the three LDO voltage reduction branches are connected in parallel, and output ends of the two DC-DC voltage reduction branches are connected to input ends of the three LDO voltage reduction branches.

10. The controllable power panel for a drone of claim 1, wherein, The controllable distribution board further comprises a pre-charge independent switch circuit, and the pre-charge independent switch circuit is connected to the pre-charge circuit.

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