An asymmetric half-bridge flyback converter light load control strategy optimization method

Abstract

The application discloses a kind of asymmetric half-bridge flyback converter light load control strategy optimization method in the technical field of flyback converter, including obtaining the input voltage of the input end of the asymmetric half-bridge flyback converter, obtaining first dead time and second dead time, obtain excitation current peak value;The excitation current valley value of the first switch tube zero-voltage opening in the asymmetric half-bridge flyback converter under the voltage and second dead time is calculated, and the excitation current valley value is set as the excitation current valley value when the asymmetric half-bridge flyback converter is steady-state.The application optimizes the cross-cycle mode control strategy, forms enhanced cross-cycle mode, so that the asymmetric half-bridge flyback converter in cross-cycle mode can quickly enter steady state, and the enhanced cross-cycle mode is used, which can reduce the additional excitation current circulation under light load working condition, improve the efficiency of the converter and form enhanced cross-cycle mode.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of flyback converter, and particularly relates to a light load control strategy optimization method for asymmetric half-bridge flyback converter. BACKGROUND

[0002] Traditional small power switching converters often adopt flyback topology, which has the advantages of simple structure and low cost. However, the ordinary flyback topology belongs to hard switching, and cannot recover the leakage energy, which limits the efficiency improvement and volume reduction of small and medium power converters to some extent. In order to meet the trend of small, light and modular development of power converters, soft switching is currently used to reduce the volume of transformer and inductor. Compared with ordinary flyback converter, the asymmetric half-bridge flyback converter can realize zero-voltage turn-on of two switching tubes, recover leakage energy, easily realize self-driven synchronous rectification, effectively improve efficiency, and reduce the volume of transformer under the condition of similar number and complexity of devices.

[0003] The circuit diagram of a common asymmetric half-bridge flyback converter is shown in Figure 1a and 1b The working principle of the two circuits is the same, only the position of the resonant cavity is different. In the figure, Q1 and Q2 are two switching tubes of the half-bridge, and the switching tube of the resonant circuit composed of leakage inductance Lr, magnetizing inductance Lm, ideal transformer TR and resonant capacitor Cr is the second switching tube, and the other is the first switching tube. Specifically, in Figure 1a and Figure 1b , Q2 is the second switching tube, and Q1 is the first switching tube. Figure 1a and Figure 1b , Np and Ns are the number of turns of the primary winding and the secondary winding of the transformer respectively, C1 and C2 are the body capacitances of the first switching tube and the second switching tube respectively, Vin is the input voltage, D1 is the secondary diode, Vo is the output voltage, Co is the output filter capacitor, and Vgs1 and Vgs2 are the driving signals of the first switching tube and the second switching tube respectively.

[0004] Take Figure 1b for example, the working waveform under the continuous resonant mode (i.e. Q1 and Q2 complementary conduction) is as shown in Figure 2As shown, Vgs1 and Vgs2 are the driving signals of the first switch tube and the second switch tube respectively; iLm is the primary excitation current waveform, and iLr is the leakage inductance current, that is, the half-bridge primary current. In order to prevent the first switch tube Q1 and the second switch tube Q2 from being turned on at the same time to cause input short circuit, a certain dead time (such as td1 and td2) is required to be left between the driving voltage signals of the first switch tube Q1 and the second switch tube Q2. In a steady state, the working principle of the circuit is that the output voltage charges the excitation inductor, the leakage inductor and the resonant capacitor during the conduction period of the first switch tube. At this time, the leakage inductor current is equal to the excitation inductor current, and the secondary side diode bears the reverse voltage and is turned off. After the first switch tube is turned off, the forward half-bridge current pulls the second switch tube body diode, and then the second switch tube is turned on with zero voltage. The voltage on the resonant capacitor acts on the leakage inductor and the excitation inductor to make the secondary side diode conduct, and the energy transmission stage is entered. In this stage, the voltage across the excitation inductor is clamped at N*Vo (N=Np / Ns), the excitation current linearly decreases, and the leakage inductor and the resonant capacitor enter the resonance stage. Then there are two cases. In the first case, the resonance stage ends until the leakage inductor current is equal to the excitation current, the secondary side diode is turned off with zero current, the leakage inductor current is equal to the excitation current and continues to decrease under the action of the resonant capacitor voltage, and then the second switch tube is turned off. In the second case, the leakage inductor current has not resonated to be equal to the excitation current, and the second switch tube has been turned off. In this way, the resonance stage ends quickly, the leakage inductor current quickly rises to be equal to the excitation current, and the secondary side diode cannot be turned off with zero current in the second case. Figure 2 As shown in the first case, a control method of the asymmetric half-bridge flyback converter is a pulse width modulation method. This method adjusts the duty cycle of the first switch tube based on the error amount of the output voltage and the reference value to realize voltage stabilization. This method is most difficult to realize soft switching in a full load working condition. If soft switching is realized in a full load working condition through parameter design, the primary excitation current valley value decreases with the decrease of the output current. In this way, the converter drives a large part of negative excitation current value in a light load or no load, and this part of current completely exists in the primary side in the form of circulating current, resulting in additional loss and reducing the light load efficiency of the converter.

[0005] Another type of control method for the existing asymmetric half-bridge flyback converter is the peak current control method, which turns off the first switch when the leakage inductance current reaches the set peak value after the first switch is turned on, and then turns on the second switch after a dead time, and turns off the second switch when the magnetizing current reaches the threshold value through a series of methods (such as current detection, integral value judgment method, etc.). This method can control the energy transmitted in each cycle by adjusting the peak current set value to achieve voltage stabilization. The threshold value of the magnetizing current when the second switch is turned off is the current value that can achieve zero voltage turn-on of the first switch at the beginning of the next cycle. The threshold value is negative and its size depends on the input voltage, dead time, and the size of the first and second switch body capacitance. The above-mentioned peak current control method can achieve soft switching of the converter and control the magnetizing current valley to avoid the negative circulating current problem that occurs in the pulse width modulation mode. However, this method reduces the peak current set value as the output current decreases, which in turn causes the switching frequency to rise. High switching frequency at light load or no load will increase the drive loss and switching loss, thereby reducing the efficiency of the converter.

[0006] It can be seen that the above two types of existing asymmetric half-bridge flyback converter control methods have the problem of low efficiency at light load. Currently, there is a light load control method for asymmetric half-bridge flyback converters, which turns on the converter for a certain number of cycles, keeps the switching frequency and magnetizing current peak unchanged for a certain number of cycles, and then adds an interval time without driving. The converter is in a free oscillation state to solve the problem of low efficiency caused by high switching frequency at light load under peak current control. This method is referred to as the cross-cycle mode in this paper.

[0007] The cross-cycle mode has certain technical defects, which will be explained below with reference to Figure 3 Figure 3 Vgs1 and Vgs2 are the driving signals of the first switch and the second switch, iLm is the primary side magnetizing current waveform, and I_p is the peak value of the magnetizing current. Figure 3 ​The waveforms of the first two switching periods T_first and T_second in the cross-period mode are shown in FIG. 2. It should be noted that the period length of T_first and T_second is the same, and the peak value of the magnetizing current is also the same. Before T_first, the converter is in a free oscillation state, and the magnetizing current can be regarded as 0. Therefore, when the first switch is turned on in T_first, iLm starts to increase from 0, and when iLm reaches I_p, the first switch is turned off. After a dead time td1, the second switch is turned on, and then the second switch is turned off at the end of T_first. After a dead time td2, T_second is entered. It should be noted that the valley value I_n_first of the magnetizing current at the end of T_first cannot be actively controlled and depends on the length of T_first. In order to achieve soft switching, I_n_first is usually less than zero and has an absolute value large enough to discharge the body capacitor of the first switch and charge the body capacitor of the second switch. This paper discusses this case. It can be seen that in T_first, iLm increases from 0 to I_p and then decreases to I_n_first, and then enters T_second. That is, at the beginning of T_second, unlike T_first, iLm starts to increase from I_n_first instead of 0. Therefore, the rising time of iLm in T_second is longer than that in T_first, and the period length of T_second and T_first is the same. Therefore, the falling time of iLm in T_second is shorter than that in T_first, which will cause the valley value I_n_second of the magnetizing current at the end of T_second to be greater than I_n_first. From the above analysis, it can be seen that the smaller I_n_first is, the larger I_n_second is. Therefore, I_n_first may be too small to achieve soft switching. By repeating the above analysis process, it can be found that in the cross-period mode, the valley value of the magnetizing current is unstable, that is, it is small at times and large at times. The converter cannot quickly enter a steady state. Although a too small valley value of the magnetizing current can achieve soft switching, it will cause additional circulating current loss. A too large magnetizing current will directly cause the converter to lose the soft switching condition.

[0008] In summary, although the existing cross-period mode can alleviate the problem of too high switching frequency and too large negative circulating current of the asymmetric half-bridge flyback converter under light load conditions to a certain extent, it will cause the problem of unstable valley value of the magnetizing current, and the converter cannot quickly enter a steady state. On the other hand, although a too small valley value of the magnetizing current can achieve soft switching, it will cause additional circulating current loss. A too large magnetizing current will directly cause the converter to lose the soft switching condition. SUMMARY

[0009] The purpose of the present application is to provide a kind of asymmetric half-bridge flyback converter light load control strategy optimization method, solve asymmetric half-bridge flyback converter pulse width modulation method in light load negative circulation, peak current control method in light load switching frequency is too high, and the problem that converter cannot quickly enter steady state in cross-cycle mode.

[0010] To achieve the above object, the present application provides the following technical solutions:

[0011] A kind of asymmetric half-bridge flyback converter light load control strategy optimization method, including the asymmetric half-bridge flyback converter includes low side resonant asymmetric half-bridge flyback converter and high side resonant asymmetric half-bridge flyback converter, the method comprises:

[0012] Obtain the input voltage Vin of the input end of the asymmetric half-bridge flyback converter, obtain the first dead time td1 and the second dead time td2, obtain the excitation current peak value;

[0013] The excitation current valley value of the first switch tube zero voltage opening in asymmetric half-bridge flyback converter under the voltage Vin and the second dead time td2 is calculated, and the excitation current valley value is set as the excitation current valley value when the asymmetric half-bridge flyback converter is in steady state;

[0014] Based on the excitation current valley value I_n and the excitation current peak value I_p, the corresponding switching frequency under the input voltage Vin and the output voltage Vo of asymmetric half-bridge flyback converter is calculated, wherein the switching frequency is the switching frequency Fsw of the second and subsequent periods in enhanced cross-cycle mode;

[0015] The switching frequency of the first switching period in control Tp is the switching frequency Fsw_first of the first switching period, and the switching frequency of subsequent switching periods is the switching frequency Fsw of subsequent switching periods in enhanced cross-cycle mode, so that the converter enters steady state and eliminates additional excitation current circulation and hard switching loss.

[0016] As a further scheme of the present application: the excitation current valley value of the first switch tube zero voltage opening in asymmetric half-bridge flyback converter under the voltage Vin and the second dead time td2 is calculated, comprising:

[0017] Adopt formula:

[0018] I_n=-(C1+C2)*Vin / td2 calculates excitation current valley value, wherein I_n is excitation current valley value, C1 is the body capacitance value of the first switch tube in asymmetric half-bridge flyback converter, C2 is the body capacitance value of the second switch tube in asymmetric half-bridge flyback converter, Vin is input voltage value, and td2 is the second dead time.

[0019] As a further scheme of the present application, the calculating the corresponding switching frequency under the conditions of the input voltage Vin and the output voltage Vo of the asymmetric half-bridge flyback converter comprises:

[0020] The switching frequency is calculated by using the formula:

[0021] The switching frequency is calculated by using the formula:

[0022] The switching frequency of the first switching cycle in the enhanced cross-cycle mode is calculated based on the switching frequency Fsw of the subsequent switching cycles in the enhanced cross-cycle mode.

[0023] As a further scheme of the present application, the calculating the corresponding switching frequency under the conditions of the input voltage Vin and the output voltage Vo of the asymmetric half-bridge flyback converter comprises:

[0024] The switching frequency of the first switching cycle in the enhanced cross-cycle mode is calculated by using the formula:

[0025] The switching frequency of the first switching cycle in the enhanced cross-cycle mode is calculated by using the formula:

[0026] As a further scheme of the present application, the calculating the corresponding switching frequency under the conditions of the input voltage Vin and the output voltage Vo of the asymmetric half-bridge flyback converter comprises:

[0027] The first switch is turned on at the beginning of an enhanced cross-cycle mode cycle Tp, and the first switch is turned off when the current value iLm of the magnetizing inductor rises to the peak value I_p of the magnetizing current;

[0028] The second switch is turned on after a first dead time tdl, and the second switch is turned off at the end of the first switching cycle; when the time length of turning off the second switch reaches a td2 time, the second switching cycle in the enhanced cross-cycle mode cycle Tp is entered;

[0029] The multiple switching cycles are repeatedly obtained.

[0030] As a further scheme of the present application, the switching frequency of the first switching cycle is recorded as the switching frequency Fsw_first of the first switching cycle in the enhanced cross-cycle mode, and the switching frequency of the subsequent switching cycles is recorded as the switching frequency Fsw of the subsequent switching cycles in the enhanced cross-cycle mode.

[0031] As a further scheme of the present application, the method further comprises an implementation approach, which comprises:

[0032] The output voltage sample value and the output voltage reference value are obtained, an error value of the voltage sample value and the output voltage reference value is extracted and output to a PI controller, and the PI controller is used to adjust the length of the enhanced cross-cycle mode cycle Tp;

[0033] A first input end of an or gate is generated with an indication pulse when the enhanced cross-cycle mode cycle Tp starts; whether the current cycle is the first switching cycle within Tp is determined according to a first switching counter, if yes, a current cycle end signal is generated based on Fsw_first and output to a second input end of the or gate, otherwise, a current cycle end signal is generated according to Fsw and also output to the second input end of the or gate;

[0034] The output end of the or gate outputs a logical determination result to the input end of a flip-flop, the first output end of the flip-flop is connected to a dead zone setting module, the output end of the dead zone setting module is connected to a first switch tube drive, and the second output end of the flip-flop is connected to another dead zone setting module, the output end of the other dead zone setting module is connected to a second switch tube drive;

[0035] The second input end of the flip-flop is connected to the output end of a comparator, the non-inverting input end of the comparator is connected to a leakage inductance current sample value, and the inverting input end of the comparator is connected to an excitation current peak value setting value.

[0036] As a further scheme of the present application, the implementation approach further comprises:

[0037] When the output voltage sample value is lower than the output voltage reference value, the length of the enhanced cross-cycle mode cycle Tp is reduced;

[0038] When the output voltage sample value is not lower than the output voltage reference value, the length of the enhanced cross-cycle mode cycle Tp is increased.

[0039] As a further scheme of the present application, the implementation approach further comprises:

[0040] The value of the number of switching cycles N within the enhanced cross-cycle mode cycle Tp is determined, when the enhanced cross-cycle mode cycle Tp starts, a driving indication pulse is driven to enter an RS flip-flop through an or gate to turn on a first switch tube, and drive the leakage inductance current to rise;

[0041] When the leakage inductance current rises to the excitation current peak value I_p, the comparator outputs a pulse and turns off the first switch tube through the RS flip-flop and turns on a second switch tube;

[0042] A cycle end indication pulse is generated and input to the asymmetric half-bridge flyback converter.

[0043] As a further scheme of the present application: the generation period end indication pulse comprises:

[0044] The first switch period counter is used to determine whether the current period is the first period in the enhanced cross-period mode period Tp, if yes, the current period length is 1 / Fsw_first, wherein Fsw_first is the numerical value of the switching frequency of the first switch period in the enhanced cross-period mode;

[0045] If no, the current period length is 1 / Fsw, wherein Fsw is the numerical value of the switching frequency of the subsequent switch period in the enhanced cross-period mode.

[0046] Compared with the prior art, the present application has the beneficial effects that:

[0047] The present application optimizes the cross-period mode control strategy, forms the enhanced cross-period mode, so that the asymmetric half-bridge flyback converter in the cross-period mode can quickly enter the steady state, and at the same time, the enhanced cross-period mode can reduce the additional excitation current circulation under light load working condition, improve the efficiency of the converter and form the enhanced cross-period mode. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1a It is the high-side resonant asymmetric half-bridge flyback converter circuit diagram of the present application;

[0049] Figure 1b It is the low-side resonant asymmetric half-bridge flyback converter circuit diagram of the present application;

[0050] Figure 2 It is the waveform diagram of the asymmetric half-bridge flyback converter in the continuous resonant mode;

[0051] Figure 3 It is the waveform diagram of the asymmetric half-bridge flyback converter in the cross-period mode;

[0052] Figure 4 It is the enhanced cross-period mode waveform diagram of the present application;

[0053] Figure 5 It is the control structure module diagram of the present application;

[0054] Figure 6 It is the circuit structure diagram of the embodiment of the present application. DETAILED DESCRIPTION

[0055] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0056] Embodiment:

[0057] Please refer to Figures 1a-6 In the embodiments of the present application, a light load control strategy optimization method of an asymmetric half-bridge flyback converter includes a low-side resonant asymmetric half-bridge flyback converter and a high-side resonant asymmetric half-bridge flyback converter, wherein the high-side resonant asymmetric half-bridge flyback converter is as shown in Figure 1a , and the low-side resonant asymmetric half-bridge flyback converter is as shown in Figure 1b , wherein Vin is an input voltage, Lm is a transformer excitation inductance, Lr is a transformer primary side leakage inductance, Cr is a resonant capacitor, Np and Ns are the number of turns of the primary winding and the secondary winding respectively, TR is an ideal transformer, D1 is a secondary diode, Vo is an output voltage, and Co is an output filter capacitor. Figure 1a and Figure 1b respectively show two structures of the asymmetric half-bridge flyback converter, the main difference being the position of the resonant cavity on the half-bridge structure, Figure 1a is high-side resonant, Figure 1b is low-side resonant. In Figure 1a and Figure 1b , Q1 is a first switch tube, Q2 is a second switch tube, C1 and C2 are the body capacitances of the first switch tube and the second switch tube respectively. The working principles of the converter are consistent in the high-side resonant and low-side resonant cases, so subsequent related analysis is carried out on the structure as shown in Figure 1b .

[0058] The optimization method in the embodiments reduces the period length of T_first in Figure 3 , so that I_n_first in Figure 3 increases and is equal to the excitation current valley value in the steady state of the converter, and then the converter directly enters the steady state in the subsequent period, and the excitation current valley value is maintained constant.

[0059] This is shown in Figure 4 , that is, Fsw_first (the switching frequency of the first switching period in the enhanced cross-period mode) is greater than Fsw, and Fsw_first is calculated by Fsw.

[0060] A light load control strategy optimization method of an asymmetric half-bridge flyback converter includes the following steps:

[0061] S1: obtaining an input voltage Vin of an asymmetric half-bridge flyback converter, obtaining a first dead time td1 and a second dead time td2, and obtaining a peak value of an excitation current;

[0062] S2: calculating a valley value of the excitation current of the asymmetric half-bridge flyback converter under the voltage Vin and the second dead time td2, and setting the valley value of the excitation current as a valley value of the excitation current in a steady state of the asymmetric half-bridge flyback converter;

[0063] S3: calculating a corresponding switching frequency under the input voltage Vin and an output voltage Vo of the asymmetric half-bridge flyback converter based on the valley value of the excitation current I_n and the peak value of the excitation current I_p, wherein the switching frequency is a switching frequency Fsw of a second and subsequent switching period in an enhanced cross-cycle mode;

[0064] S4: controlling the switching frequency of a first switching period in Tp as a switching frequency Fsw_first of the first switching period, and controlling the switching frequency of subsequent switching periods as the switching frequency Fsw of the subsequent switching periods in the enhanced cross-cycle mode, so that the converter enters a steady state to eliminate an additional excitation current circulation and a hard switching loss.

[0065] In the embodiment, when the number of switching periods n in Tp is constant, Tp is longer, Tdelay is longer, and vice versa. According to the length of Tp, a very short indication pulse can be generated at the beginning of each Tp period by means of carrier comparison.

[0066] Preferably, the valley value of the excitation current of the asymmetric half-bridge flyback converter under the voltage Vin and the second dead time td2 is calculated, and the calculation includes:

[0067] The formula is:

[0068] I_n=-(C1+C2)*Vin / td2, wherein I_n is the valley value of the excitation current, C1 is a bulk capacitance value of a first switching tube in the asymmetric half-bridge flyback converter, C2 is a bulk capacitance value of a second switching tube in the asymmetric half-bridge flyback converter, Vin is an input voltage value, and td2 is the second dead time.

[0069] Preferably, the corresponding switching frequency under the input voltage Vin and the output voltage Vo of the asymmetric half-bridge flyback converter is calculated, and the calculation includes:

[0070] The formula is:

[0071] The switching frequency is calculated, wherein Np and Ns are the number of turns of the primary winding and the secondary winding respectively, Vin is the voltage value of the input voltage, Vo is the voltage value of the output voltage, I_n is the excitation current valley value, I_p is the excitation current peak value, Lr is the inductance value of the leakage inductance, and Lm is the inductance value of the excitation inductance.

[0072] The switching frequency of the first switching period in the enhanced cross-cycle mode is calculated based on the switching frequency Fsw of the subsequent switching period in the enhanced cross-cycle mode.

[0073] Preferably, the switching frequency of the first switching period in the enhanced cross-cycle mode is calculated based on the switching frequency Fsw of the subsequent switching period in the enhanced cross-cycle mode, including:

[0074] The formula is adopted:

[0075] The switching frequency of the first switching period in the enhanced cross-cycle mode is calculated.

[0076] Preferably, the switching frequency of the first switching period in the control Tp is the switching frequency Fsw_first of the first switching period, and the switching frequency of the subsequent switching period is the switching frequency Fsw of the subsequent switching period in the enhanced cross-cycle mode, including:

[0077] The first switch is turned on at the beginning of an enhanced cross-cycle mode period Tp, and the first switch is turned off when the current value iLm of the excitation inductance rises to the excitation current peak value I_p.

[0078] The second switch is turned on after the first dead time td1, and the second switch is turned off at the end of the first switching period. When the duration of turning off the second switch reaches the td2 time, the second switching period in the enhanced cross-cycle mode period Tp is entered.

[0079] The multiple switching periods are repeatedly obtained.

[0080] Preferably, the switching frequency of the first switching period is recorded as the switching frequency Fsw_first of the first switching period in the enhanced cross-cycle mode, and the switching frequency of the subsequent switching period is the switching frequency Fsw of the subsequent switching period in the enhanced cross-cycle mode.

[0081] Preferably, the method further includes an implementation approach, and the implementation approach includes:

[0082] The output voltage sample value and the output voltage reference value are obtained, the error value of the voltage sample value and the output voltage reference value is extracted and output to a PI controller, and the length of the enhanced cross-cycle mode period Tp is adjusted by using the PI controller.

[0083] a first input end of the or gate is produced with an indication pulse when the enhanced cross-cycle mode cycle Tp starts; according to the first switch counter, it is judged whether the current cycle is the first switch cycle within Tp, if yes, a current cycle end signal is produced based on Fsw_first and output to the second input end of the or gate, otherwise, a current cycle end signal is produced based on Fsw and output to the second input end of the or gate as well;

[0084] the output end of the or gate outputs the logical judgment result to the input end of the flip-flop, the first output end of the flip-flop is connected with a dead zone setting module, the output end of the dead zone setting module is connected with the first switch tube drive, the second output end of the flip-flop is connected with another dead zone setting module, and the output end of the other dead zone setting module is connected with the second switch tube drive;

[0085] the second input end of the flip-flop is connected with the output end of the comparator 1, and the non-inverted input end of the comparator 1 is connected with the leakage current sampling value, and the inverted input end of the comparator 1 is connected with the excitation current peak value setting value.

[0086] Preferably, the implementation approach further comprises:

[0087] when the output voltage sampling value is lower than the output voltage reference value, the length of the enhanced cross-cycle mode cycle Tp is reduced;

[0088] when the output voltage sampling value is not lower than the output voltage reference value, the length of the enhanced cross-cycle mode cycle Tp is increased.

[0089] Preferably, the implementation approach further comprises:

[0090] the value of the number of switch cycles N within the enhanced cross-cycle mode cycle Tp is determined, when the enhanced cross-cycle mode cycle Tp starts, the indication pulse is driven to pass through the or gate and enter the RS flip-flop to open the first switch tube, and the leakage current is driven to rise;

[0091] when the leakage current rises to the excitation current peak value I_p, the comparator outputs a pulse and turns off the first switch tube through the RS flip-flop and turns on the second switch tube;

[0092] a cycle end indication pulse is produced, and the cycle end indication pulse is input to the asymmetric half-bridge flyback converter.

[0093] Preferably, the production of the cycle end indication pulse comprises:

[0094] a first switch cycle counter is used to judge whether the current cycle is the first cycle within the enhanced cross-cycle mode cycle Tp, if yes, the length of the current cycle is 1 / Fsw_first, wherein Fsw_first is the value of the switching frequency of the first switch cycle in the enhanced cross-cycle mode;

[0095] If the answer is no, the current cycle length is 1 / Fsw, where Fsw is the value of the switching frequency of the subsequent switching cycle in the enhanced cross-cycle mode.

[0096] In this embodiment, whether the first switching cycle counter judges the current cycle as the first cycle in the enhanced cross-cycle mode cycle Tp or not, a cycle end indication pulse is output at the end of the cycle, which enters the RS flip-flop through the OR gate, turns on the first switch and turns off the second switch, and then enters the next cycle, and the control mode repeats the above steps.

[0097] As shown in Figure 4 is the enhanced cross-cycle mode waveform proposed by the method, Figure 4 Vgs1 and Vgs2 are the driving signals of the first switch and the second switch, iLm is the excitation current waveform, I_p is the excitation current peak value, I_n is the excitation current valley value. The first dead time td1 is the dead time between the turn-off of the first switch and the turn-on of the second switch, and the second dead time td2 is the dead time between the turn-off of the second switch and the turn-on of the first switch. Fsw_first is the switching frequency of the first switching cycle in the enhanced cross-cycle mode, Fsw is the switching frequency of the subsequent switching cycle in the enhanced cross-cycle mode. Tp is the length of an enhanced cross-cycle mode cycle, and N is the number of switching cycles in a Tp, that is, a Tp contains N switching cycles and a first interval time Tdelay, where N is an integer greater than or equal to 2, Figure 4 In the case of N=3, the length of Tdelay can be adjusted.

[0098] In this embodiment, in the enhanced cross-cycle mode, the frequency Fsw_first of the first switching cycle in Tp is increased, so that the excitation current valley value reaches a steady state at the end of the first switching cycle, and then the excitation current valley value in the switching cycle is stabilized at a value that can just realize soft switching of the first switch. On the basis of realizing soft switching, additional circulating loss is avoided. In addition, the enhanced cross-cycle mode contains a first interval time Tdelay, and by adjusting the value of Tdelay, the problem of excessive driving loss caused by excessively high switching frequency can be avoided.

[0099] In this embodiment, as shown in Figure 6 In addition to the devices shown in Figure 1b , the current sampling resistor Rc, the output voltage dividing resistors R3 and R4, the isolation feedback unit, the enhanced cross-cycle mode main control unit, and the driving unit are also included. The enhanced cross-cycle mode main control unit internally performs Figure 5The isolation feedback unit sends the output voltage sampling value to the enhanced cross-cycle mode master unit in an isolated manner, and the enhanced cross-cycle mode master unit also receives the leakage inductance current sampling signal generated by the sampling resistor Rc. The output of the enhanced cross-cycle mode master unit is the driving signal of the first switch tube and the second switch tube, and the driving signal controls the conduction or turn-off of the first switch tube and the second switch tube through the driving unit.

[0100] In the embodiment, the isolation feedback unit can be implemented by using an optical coupling isolator, but is not limited thereto.

[0101] In the embodiment, the driving unit can be implemented by using various half-bridge driving chips, but is not limited thereto.

[0102] In the embodiment, the current sampling can be implemented by using a sampling resistor Rc and a current transformer, but is not limited thereto.

[0103] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can make equivalent replacements or changes to the technical solution and the inventive concept of the present application within the technical range disclosed by the present application, which should be covered by the protection scope of the present application.

Claims

1. An asymmetric half-bridge flyback converter light load control strategy optimization method, characterized in that, The asymmetric half-bridge flyback converter includes a low-side resonant asymmetric half-bridge flyback converter and a high-side resonant asymmetric half-bridge flyback converter, and the method includes: obtaining an input voltage Vin of an input end of the asymmetric half-bridge flyback converter, obtaining a first dead time td1 and a second dead time td2, and obtaining a peak value of an excitation current; calculating a valley value of the excitation current at which the first switch tube of the asymmetric half-bridge flyback converter is turned on at zero voltage under the voltage Vin and the second dead time td2, and setting the valley value of the excitation current as a valley value of the excitation current in a steady state of the asymmetric half-bridge flyback converter; based on the valley value I_n and the peak value I_p of the excitation current, calculating a corresponding switching frequency under the input voltage Vin and an output voltage Vo of the asymmetric half-bridge flyback converter, wherein the switching frequency is a switching frequency Fsw of a second and subsequent switching period in an enhanced cross-period mode; controlling the switching frequency of a first switching period in Tp to be a switching frequency Fsw_first of the first switching period, and controlling the switching frequency of a subsequent switching period to be a switching frequency Fsw of the subsequent switching period in the enhanced cross-period mode, so that the converter enters a steady state to eliminate an additional excitation current circulation and hard switching loss.

2. The method of claim 1, wherein: The calculation of the valley value of the excitation current at which the first switch tube of the asymmetric half-bridge flyback converter is turned on at zero voltage under the voltage Vin and the second dead time td2 includes: using a formula: I_n=-(C1+C2)*Vin / td2 to calculate the valley value of the excitation current, wherein I_n is the valley value of the excitation current, C1 is a body capacitance value of the first switch tube in the asymmetric half-bridge flyback converter, C2 is a body capacitance value of the second switch tube in the asymmetric half-bridge flyback converter, Vin is an input voltage value, and td2 is the second dead time. The calculation of the corresponding switching frequency under the input voltage Vin and the output voltage Vo of the asymmetric half-bridge flyback converter includes:

3. The method of claim 1, wherein: using a formula: Fsw=I_n / (C1+C2)*Vin / td2 to calculate the switching frequency under the input voltage Vin and the output voltage Vo of the asymmetric half-bridge flyback converter. The calculation of the switching frequency of the first switching period in the enhanced cross-period mode based on the switching frequency Fsw of the subsequent switching period in the enhanced cross-period mode includes: The switching frequency is calculated, wherein Np and Ns are the number of turns of the primary and secondary windings, Vin is the voltage value of the input voltage, Vo is the voltage value of the output voltage, I_n is the excitation current valley value, I_p is the excitation current peak value, Lr is the inductance value of the leakage inductance, and Lm is the inductance value of the excitation inductance. using a formula: Fsw_first=I_n / (C1+C2)*Vin / td2 to calculate the switching frequency of the first switching period in the enhanced cross-period mode.

4. The method of claim 3, wherein: The control of the switching frequency of the first switching period in Tp to be the switching frequency Fsw_first of the first switching period and the control of the switching frequency of the subsequent switching period to be the switching frequency Fsw of the subsequent switching period in the enhanced cross-period mode include: turning on the first switch tube at the beginning of an enhanced cross-period mode period Tp, and turning off the first switch tube when the current value iLm of the excitation inductance rises to the peak value I_p of the excitation current; The switching frequency of the first switching cycle in the enhanced cross-cycle mode is calculated.

5. The method of claim 1, wherein: turning on the second switch tube after the first dead time td1, and turning off the second switch tube at the end of the first switching period, and entering a second switching period in the enhanced cross-period mode period Tp after the time of turning off the second switch tube reaches the td2 time; repeating the obtaining of multiple switching periods. The method further includes an implementation approach, and the implementation approach includes: ​ 6. The method of claim 1, wherein, ​ The output voltage sample value and the output voltage reference value are obtained, and an error value of the voltage sample value and the output voltage reference value is output to a PI controller to adjust the length of an enhanced cross-cycle mode cycle Tp by using the PI controller; A first input end of an or gate is generated with an indication pulse when the enhanced cross-cycle mode cycle Tp starts; whether the current cycle is the first switching cycle in Tp is determined according to a first switching counter, if yes, a current cycle end signal is generated based on Fsw_first and output to a second input end of the or gate, otherwise, a current cycle end signal is generated based on Fsw and output to the second input end of the or gate; The output end of the or gate outputs a logical determination result to the input end of a flip-flop, the first output end of the flip-flop is connected to a dead zone setting module, the output end of the dead zone setting module is connected to a first switch tube drive, the second output end of the flip-flop is connected to another dead zone setting module, and the output end of the other dead zone setting module is connected to a second switch tube drive; The second input end of the flip-flop is connected to the output end of a comparator, the non-inverting input end of the comparator is connected to a leakage current sample value, and the inverting input end of the comparator is connected to an excitation current peak value setting value.

7. The method of claim 6, wherein, The implementation approach further includes: When the output voltage sample value is lower than the output voltage reference value, the length of the enhanced cross-cycle mode cycle Tp is reduced; When the output voltage sample value is not lower than the output voltage reference value, the length of the enhanced cross-cycle mode cycle Tp is increased.

8. The method of claim 7, wherein, The implementation approach further includes: The number of switching cycles N in the enhanced cross-cycle mode cycle Tp is determined, when the enhanced cross-cycle mode cycle Tp starts, a driving indication pulse is generated to pass through an or gate and enter an RS flip-flop to turn on a first switch tube, and the leakage current is driven to rise; When the leakage current rises to the excitation current peak value I_p, a comparator output pulse is generated to pass through an RS flip-flop to turn off the first switch tube and turn on a second switch tube; A cycle end indication pulse is generated and input to the asymmetric half-bridge flyback converter.

9. The method of claim 8, wherein: The generation of the cycle end indication pulse includes: A first switching cycle counter is used to determine whether the current cycle is the first cycle in the enhanced cross-cycle mode cycle Tp, if yes, the length of the current cycle is 1 / Fsw_first, where Fsw_first is the value of the switching frequency of the first switching cycle in the enhanced cross-cycle mode; If no, the length of the current cycle is 1 / Fsw, where Fsw is the value of the switching frequency of the subsequent switching cycle in the enhanced cross-cycle mode.

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