High bandwidth integrated high sensitivity photodiode amplifier circuit

Abstract

The application discloses a high-bandwidth integrated high-sensitivity photodiode amplifying circuit, which comprises a first-stage amplifying unit, a buffer isolation unit and a second-stage amplifying unit connected in sequence, the first-stage amplifying unit is provided with a transconductance operational amplifier, and the buffer isolation unit is provided with an operational amplifier; the first-stage amplifying unit is provided with a common-source and common-gate structure, the circuit gain is maintained stable, the buffer isolation unit connects the operational amplifier into a unit negative feedback structure to serve as a buffer, and a forward diode is connected at an output end to perform isolation, so that the influence of the output of the latter-stage amplification on the photodiode is prevented, and the reliability of the circuit is enhanced; the second-stage amplifying unit adopts a differential amplifying structure with a gate-drain terminal resistance, not only the output common mode point is determined, but also the gain and the bandwidth can be adjusted according to the resistance values of resistors R4 and R5, the bandwidth can be adjusted to be higher, the design flexibility is increased, and the differential structure also reduces the influence of temperature, power voltage and process angle on the output.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of switching power supply, and particularly relates to a high-bandwidth integrated high-sensitivity photodiode amplification circuit. BACKGROUND

[0002] The silicon-based photodiode amplification circuit is widely applied in the fields of photoelectric detection and optical communication, and with the development of photoelectric detection systems in the direction of miniaturization, high integration, high speed, high performance and low cost, the traditional detector, amplification circuit and other separate device board-level link solutions cannot meet the application requirements, so a new generation of monolithic integrated photodiode amplification structure has great competitive advantage and application prospect.

[0003] Therefore, how to provide a high-bandwidth integrated high-sensitivity photodiode amplification circuit is a problem to be solved by those skilled in the art. SUMMARY

[0004] In view of the above problems in the prior art, the high-bandwidth integrated high-sensitivity photodiode amplification circuit provided by the application realizes the high-bandwidth integrated high-sensitivity photodiode amplification circuit by using a relatively simple circuit, reduces the circuit size, reduces the cost, enhances the reliability of the circuit and has a high bandwidth, and solves the problem that the traditional amplification circuit cannot simultaneously meet the requirements of miniaturization, high performance and low cost.

[0005] In order to achieve the above-mentioned application purposes, the technical scheme adopted by the application is as follows: a high-bandwidth integrated high-sensitivity photodiode amplification circuit, comprising a first amplification unit, a buffer isolation unit and a second amplification unit connected in sequence, the first amplification unit is provided with a transconductance operational amplifier, and the buffer isolation unit is provided with an operational amplifier.

[0006] The noninverting input terminal of the transconductance operational amplifier is connected with a reference voltage, the inverting input terminal of the transconductance operational amplifier is connected with a photodiode PD1, the output terminal of the transconductance operational amplifier and the inverting input terminal of the operational amplifier, the inverting input terminal of the operational amplifier is connected with the output terminal of the operational amplifier and the inverting input terminal of the second amplification unit, and the noninverting input terminal of the second amplification unit is connected with the reference voltage.

[0007] Further, the first amplification unit further comprises a resistor R1 and a capacitor C1, and the transconductance operational amplifier comprises a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q6, a MOS tube M1, a MOS tube M2, a MOS tube M3, a MOS tube M4, a MOS tube M5, a MOS tube M6, a MOS tube M7 and a MOS tube M8.

[0008] The base of the triode Q1 is connected with the cathode of the photodiode PD1, one end of the resistor R1 and one end of the capacitor C1 respectively, and serves as the inverting input terminal of the transconductance operational amplifier, the collector of the triode Q1 is connected with the emitter of the triode Q3, the emitter of the triode Q1 is connected with the emitter of the triode Q2 and the drain of the MOS tube M3 respectively, the base of the triode Q2 is connected with the emitter of the triode Q5 and the drain of the MOS tube M7 respectively, and serves as the non-inverting input terminal of the transconductance operational amplifier, the collector of the triode Q2 is connected with the emitter of the triode Q4, the base of the triode Q3 is connected with the base of the triode Q4, the base of the triode Q5, the collector of the triode Q5 and the drain of the MOS tube M5 respectively, the collector of the triode Q3 is connected with the base of the triode Q6 and the drain of the MOS tube M1 respectively, the collector of the triode Q4 is connected with the gate of the MOS tube M1, the gate of the MOS tube M2 and the drain of the MOS tube M2 respectively, and the emitter of the triode Q6 is connected with the drain of the MOS tube M8, the other end of the resistor R1 and the other end of the capacitor C1 respectively, and serves as the output terminal of the transconductance operational amplifier;

[0009] The source of the MOS tube M1, the source of the MOS tube M2, the source of the MOS tube M4, the source of the MOS tube M5 and the collector of the triode Q6 are connected with the power supply, the gate of the MOS tube M3, the gate of the MOS tube M6, the gate of the MOS tube M7 and the gate of the MOS tube M8 are connected with the bias voltage, the source of the MOS tube M3, the source of the MOS tube M6, the source of the MOS tube M7 and the source of the MOS tube M8 are grounded, and the gate of the MOS tube M4 is connected with the drain of the MOS tube M4, the gate of the MOS tube M5 and the drain of the MOS tube M6 respectively.

[0010] Further, the buffer isolation unit further comprises a grounding resistor R3 and a diode D1, and the operational amplifier comprises a triode Q7, a triode Q8, a triode Q9, a triode Q10, a triode Q11, a MOS tube M9, a MOS tube M10, a MOS tube M11, a MOS tube M12, a MOS tube M13, a MOS tube M14, a MOS tube M15 and a MOS tube M16.

[0011] The base of the triode Q7 is connected with the emitter of the triode Q12, the anode of the diode D1 and the drain of the MOS tube M16 respectively, and serves as the inverting input terminal of the operational amplifier, the emitter of the triode Q7 is connected with the emitter of the triode Q8 and the drain of the MOS tube M11 respectively, the collector of the triode Q7 is connected with the emitter of the triode Q9, the base of the triode Q8 is connected with the emitter of the triode Q11 and the drain of the MOS tube M15 respectively, and serves as the non-inverting input terminal of the operational amplifier, the collector of the triode Q8 is connected with the emitter of the triode Q10, the base of the triode Q9 is connected with the base of the triode Q10, the base of the triode Q11, the collector of the triode Q11 and the drain of the MOS tube M13 respectively, the collector of the triode Q9 is connected with the drain of the MOS tube M9 and the base of the triode Q12 respectively, the collector of the triode Q10 is connected with the drain of the MOS tube M10, the gate of the MOS tube M10 and the gate of the MOS tube M9 respectively, and the emitter of the triode Q12 serves as the output terminal of the operational amplifier;

[0012] The source of the MOS tube M9, the source of the MOS tube M10, the source of the MOS tube M12, the source of the MOS tube M13 and the collector of the triode Q12 are connected with the power supply, the gate of the MOS tube M11, the gate of the MOS tube M14, the gate of the MOS tube M15 and the gate of the MOS tube M16 are connected with the bias voltage, the source of the MOS tube M11, the source of the MOS tube M14, the source of the MOS tube M15 and the source of the MOS tube M16 are grounded, the gate of the MOS tube M12 is connected with the drain of the MOS tube M12, the gate of the MOS tube M13 and the drain of the MOS tube M14 respectively, and the cathode of the diode D1 is connected with the grounding resistor R3.

[0013] Further, the secondary amplification unit comprises the triode Q13, the triode Q14, the MOS tube M17, the MOS tube M18, the MOS tube M19, the resistor R2, the resistor R4, the resistor R5, the resistor R6, the grounding resistor R7 and the diode D2;

[0014] One end of the resistor R2 is taken as the reverse input end of the second-stage amplification unit, the other end of the resistor R2 is connected with the base of the triode Q13, the emitter of the triode Q13 is connected with the drain of the MOS tube M19 and the emitter of the triode Q14 respectively, the source of the MOS tube M19 is grounded, the gate of the MOS tube M19 is connected with a bias voltage, the collector of the triode Q13 is connected with one end of the resistor R4 and the drain of the MOS tube M17 respectively, and taken as the output end of the second-stage amplification unit, the gate of the MOS tube M17 is connected with the other end of the resistor R4, the gate of the MOS tube M18 and one end of the resistor R5 respectively, the other end of the resistor R5 is connected with the drain of the MOS tube M18 and the collector of the triode Q14 respectively, the source of the MOS tube M17 and the source of the MOS tube M18 are connected with a power supply respectively, the base of the triode Q14 is connected with one end of the resistor R6, the other end of the resistor R6 is connected with the grounding resistor R7 and the cathode of the diode D2 respectively, and the anode of the diode D2 is taken as the non-inverting input end of the second-stage amplification unit.

[0015] The present application has the following advantages:

[0016] (1) The present application provides a high-bandwidth integrated high-sensitivity photodiode amplification circuit, the first-stage amplification unit is provided with a common-source common-gate structure, which can ensure that the triode Q1 and the triode Q2 both work in the saturation region, maintain the stability of the circuit gain, the source of the triode Q6 is biased to the diode through the negative feedback formed by the resistor R1 and the capacitor C1, and the biasing and the first-stage amplification share the same circuit structure, which reduces the circuit size; the buffer isolation unit connects the operational amplifier into a unit negative feedback structure to serve as a buffer, and connects a forward diode at the output end to isolate, which prevents the influence of the output of the subsequent amplification on the photodiode, and enhances the reliability of the circuit; the second-stage amplification unit adopts a differential amplification structure with gate-drain terminal resistance, which not only determines the output common mode point, but also makes the gain and bandwidth adjustable according to the resistance values of the resistors R4 and R5, and the bandwidth can be adjusted to a higher value, which increases the design flexibility, and the differential structure also reduces the influence of temperature, power voltage and process angle on the output.

[0017] (2) The present application realizes a high-bandwidth integrated high-sensitivity photodiode amplification circuit by using a relatively simple circuit, which has the advantages of small area, strong stability, high bandwidth and strong reliability compared with the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The present application is a high-bandwidth integrated high-sensitivity photodiode amplification circuit Figure One .

[0019] Figure 2 The present application is a high-bandwidth integrated high-sensitivity photodiode amplification circuit Figure Two . DETAILED DESCRIPTION

[0020] The specific embodiments of the present application are described below to enable those skilled in the art to understand the present application, but the present application is not limited to the specific embodiments described below, and all the changes that are obvious to those skilled in the art within the spirit and scope of the present application defined by the appended claims are intended to be covered.

[0021] As shown in the figure, in one embodiment of the present application, a high-bandwidth integrated high-sensitivity photodiode amplification circuit includes a first amplification unit, a buffer isolation unit and a second amplification unit connected in sequence, the first amplification unit is provided with a transconductance operational amplifier, and the buffer isolation unit is provided with an operational amplifier. Figure 1 The non-inverting input terminal of the transconductance operational amplifier is connected with a reference voltage, the inverting input terminal of the transconductance operational amplifier is connected with a photodiode PD1, the output terminal of the transconductance operational amplifier and the inverting input terminal of the operational amplifier respectively, the non-inverting input terminal of the operational amplifier is connected with the output terminal of the operational amplifier and the inverting input terminal of the second amplification unit respectively, and the inverting input terminal of the second amplification unit is connected with the reference voltage.

[0022] As shown in the figure, the first amplification unit further includes a resistor R1 and a capacitor C1, and the transconductance operational amplifier includes a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q6, a MOS tube M1, a MOS tube M2, a MOS tube M3, a MOS tube M4, a MOS tube M5, a MOS tube M6, a MOS tube M7 and a MOS tube M8.

[0023] Figure 2

[0024] ​​The base of the triode Q1 is connected with the cathode of the photodiode PD1, one end of the resistor R1 and one end of the capacitor C1 respectively, and serves as the inverting input terminal of the transconductance operational amplifier, the anode of the photodiode PD1 is grounded, the collector of the triode Q1 is connected with the emitter of the triode Q3, the emitter of the triode Q1 is connected with the emitter of the triode Q2 and the drain of the MOS tube M3 respectively, the base of the triode Q2 is connected with the emitter of the triode Q5 and the drain of the MOS tube M7 respectively, and serves as the non-inverting input terminal of the transconductance operational amplifier, the collector of the triode Q2 is connected with the emitter of the triode Q4, the base of the triode Q3 is connected with the base of the triode Q4, the base of the triode Q5, the collector of the triode Q5 and the drain of the MOS tube M5 respectively, the collector of the triode Q3 is connected with the base of the triode Q6 and the drain of the MOS tube M1 respectively, the collector of the triode Q4 is connected with the gate of the MOS tube M1, the gate of the MOS tube M2 and the drain of the MOS tube M2 respectively, the emitter of the triode Q6 is connected with the drain of the MOS tube M8, the other end of the resistor R1 and the other end of the capacitor C1 respectively, and serves as the output terminal of the transconductance operational amplifier;

[0025] The source of the MOS tube M1, the source of the MOS tube M2, the source of the MOS tube M4, the source of the MOS tube M5 and the collector of the triode Q6 are connected with the power supply, the gate of the MOS tube M3, the gate of the MOS tube M6, the gate of the MOS tube M7 and the gate of the MOS tube M8 are connected with the bias voltage, the source of the MOS tube M3, the source of the MOS tube M6, the source of the MOS tube M7 and the source of the MOS tube M8 are grounded, and the gate of the MOS tube M4 is connected with the drain of the MOS tube M4, the gate of the MOS tube M5 and the drain of the MOS tube M6 respectively.

[0026] As shown in Figure 2 In the embodiment, a common-source common-gate structure is arranged in the primary amplification unit, which is composed of the triode Q1, the triode Q2, the triode Q3 and the triode Q4, so that the triode Q1 and the triode Q2 can work in the saturation region, and the circuit gain is stable.

[0027] The buffer isolation unit further comprises a grounding resistor R3 and a diode D1, and the operational amplifier comprises a triode Q7, a triode Q8, a triode Q9, a triode Q10, a triode Q11, a MOS tube M9, a MOS tube M10, a MOS tube M11, a MOS tube M12, a MOS tube M13, a MOS tube M14, a MOS tube M15 and a MOS tube M16.

[0028] The base of the triode Q7 is connected with the emitter of the triode Q12, the anode of the diode D1 and the drain of the MOS transistor M16 respectively, and serves as the inverting input terminal of the operational amplifier, the emitter of the triode Q7 is connected with the emitter of the triode Q8 and the drain of the MOS transistor M11 respectively, the collector of the triode Q7 is connected with the emitter of the triode Q9, the base of the triode Q8 is connected with the emitter of the triode Q11 and the drain of the MOS transistor M15 respectively, and serves as the non-inverting input terminal of the operational amplifier, the collector of the triode Q8 is connected with the emitter of the triode Q10, the base of the triode Q9 is connected with the base of the triode Q10, the base of the triode Q11, the collector of the triode Q11 and the drain of the MOS transistor M13 respectively, the collector of the triode Q9 is connected with the drain of the MOS transistor M9 and the base of the triode Q12 respectively, the collector of the triode Q10 is connected with the drain of the MOS transistor M10, the gate of the MOS transistor M10 and the gate of the MOS transistor M9 respectively, and the emitter of the triode Q12 serves as the output terminal of the operational amplifier;

[0029] The source of the MOS transistor M9, the source of the MOS transistor M10, the source of the MOS transistor M12, the source of the MOS transistor M13 and the collector of the triode Q12 are connected with the power supply, the gate of the MOS transistor M11, the gate of the MOS transistor M14, the gate of the MOS transistor M15 and the gate of the MOS transistor M16 are connected with the bias voltage, the source of the MOS transistor M11, the source of the MOS transistor M14, the source of the MOS transistor M15 and the source of the MOS transistor M16 are grounded, the gate of the MOS transistor M12 is connected with the drain of the MOS transistor M12, the gate of the MOS transistor M13 and the drain of the MOS transistor M14 respectively, and the cathode of the diode D1 is connected with the grounding resistor R3.

[0030] The secondary amplification unit comprises the triode Q13, the triode Q14, the MOS transistor M17, the MOS transistor M18, the MOS transistor M19, the resistor R2, the resistor R4, the resistor R5, the resistor R6, the grounding resistor R7 and the diode D2.

[0031] One end of resistor R2 serves as the inverting input of the second-stage amplifier unit. The other end of resistor R2 is connected to the base of transistor Q13. The emitter of transistor Q13 is connected to the drain of MOSFET M19 and the emitter of transistor Q14, respectively. The source of MOSFET M19 is grounded, and the gate of MOSFET M19 is connected to the bias voltage. The collector of transistor Q13 is connected to one end of resistor R4 and the drain of MOSFET M17, serving as the output of the second-stage amplifier unit. The gate of MOSFET M17... The base of transistor Q14 is connected to the other end of resistor R4, the gate of MOSFET M18, and one end of resistor R5. The other end of resistor R5 is connected to the drain of MOSFET M18 and the collector of transistor Q14. The sources of MOSFET M17 and MOSFET M18 are both connected to the power supply. The base of transistor Q14 is connected to one end of resistor R6. The other end of resistor R6 is connected to grounding resistor R7 and the cathode of diode D2. The anode of diode D2 serves as the non-inverting input of the secondary amplifier unit.

[0032] The specific operation process of the high-bandwidth integrated high-sensitivity photodiode amplifier circuit of the present invention is as follows:

[0033] like Figure 1 As shown, the inverting input of the transconductance operational amplifier is connected to its output via resistor R1. The inverting input of the transconductance operational amplifier is also connected to photodiode PD1. Bias is achieved through a feedback network consisting of resistor R1 and capacitor C1 connected in parallel and series with the input resistance rbe1 of transistor Q1. This negative feedback extends bandwidth and suppresses distortion. In the absence of light, the current I1 in photodiode PD1 is 0. Due to the negative feedback, Vin1 ≈ Vin2 = VREF; Vo1 = Vin1 + I3 * R1. Since I3 is very small, Vo1 ≈ VREF.

[0034] The buffer isolation unit is an operational amplifier with its output terminal connected to its inverting input terminal. Therefore, Vo2≈Vo1≈VREF, Vin3=Vo2-VD1=VREF-VD1; similarly, Vin4=VREF-VD2≈Vin3. Thus, the output level when there is no light is approximately VOUT≈VDD-VGS17. When there is light, current flows through PD1, I3<I4, Vo1 output is high, and Vo2 output is also high. At this time, Vo2>VREF, so VOUT output is low.

[0035] The application has the advantages that the application provides a high-bandwidth integrated high-sensitivity photodiode amplification circuit, the first-stage amplification unit is provided with a common-source common-gate structure, which can ensure that the triode Q1 and the triode Q2 both work in a saturation region, maintain the stability of the circuit gain, the source of the triode Q6 is biased to the diode through the negative feedback formed by the resistor R1 and the capacitor C1, and the biasing and the first-stage amplification share the same circuit structure, thereby reducing the circuit size; the buffer isolation unit connects the operational amplifier into a unit negative feedback structure to make a buffer, and connects a forward diode at the output end to perform isolation, thereby preventing the influence of the output of the subsequent-stage amplification on the photodiode, and enhancing the reliability of the circuit; the second-stage amplification unit adopts a differential amplification structure with a gate-drain terminal resistor, which not only determines the output common-mode point, but also enables the gain and the bandwidth to be adjusted according to the resistance values of the resistors R4 and R5, and the bandwidth can be adjusted to be relatively high, thereby increasing the design flexibility, and the differential structure also reduces the influence of the temperature, the power supply voltage and the process angle on the output.

[0036] The application realizes the high-bandwidth integrated high-sensitivity photodiode amplification circuit by using a relatively simple circuit, and has the advantages of small area, strong stability, high bandwidth and strong reliability compared with the prior art.

[0037] In the description of the application, it should be understood that the orientations or positional relationships indicated by the terms "center", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inner", "outer", "radial" and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. Therefore, the features limited by "first", "second", "third" can explicitly or implicitly include one or more of the features.

Claims

1. A high bandwidth integrated high sensitivity photodiode amplifier circuit, characterized by, The first amplification unit is provided with a transconductance operational amplifier, and the buffer isolation unit is provided with an operational amplifier; The non-inverting input terminal of the transconductance operational amplifier is connected with a reference voltage, the inverting input terminal of the transconductance operational amplifier is connected with a photodiode PD1, the output terminal of the transconductance operational amplifier and the inverting input terminal of the operational amplifier respectively, the non-inverting input terminal of the operational amplifier is connected with the output terminal of the operational amplifier and the inverting input terminal of the second amplification unit respectively, and the inverting input terminal of the second amplification unit is connected with the reference voltage; The second amplification unit comprises a transistor Q13, a transistor Q14, a MOS transistor M17, a MOS transistor M18, a MOS transistor M19, a resistor R2, a resistor R4, a resistor R5, a resistor R6, a grounding resistor R7 and a diode D2. One end of the resistor R2 serves as the inverting input terminal of the second amplification unit, the other end of the resistor R2 is connected with the base of the transistor Q13, the emitter of the transistor Q13 is connected with the drain of the MOS transistor M19 and the emitter of the transistor Q14 respectively, the source of the MOS transistor M19 is grounded, the gate of the MOS transistor M19 is connected with a bias voltage, the collector of the transistor Q13 is connected with one end of the resistor R4 and the drain of the MOS transistor M17 respectively, and serves as the output terminal of the second amplification unit, the gate of the MOS transistor M17 is connected with the other end of the resistor R4, the gate of the MOS transistor M18 and one end of the resistor R5 respectively, the other end of the resistor R5 is connected with the drain of the MOS transistor M18 and the collector of the transistor Q14 respectively, the source of the MOS transistor M17 and the source of the MOS transistor M18 are connected with a power supply respectively, the base of the transistor Q14 is connected with one end of the resistor R6, the other end of the resistor R6 is connected with the grounding resistor R7 and the cathode of the diode D2 respectively, and the anode of the diode D2 serves as the non-inverting input terminal of the second amplification unit.

2. The high bandwidth integrated high sensitivity photodiode amplifying circuit according to claim 1, wherein, The first amplification unit further comprises a resistor R1 and a capacitor C1, and the transconductance operational amplifier comprises a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q6, a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a MOS transistor M7 and a MOS transistor M8. The base of the triode Q1 is connected with the cathode of the photodiode PD1, one end of the resistor R1 and one end of the capacitor C1 respectively, and serves as the inverting input terminal of the transconductance operational amplifier, the collector of the triode Q1 is connected with the emitter of the triode Q3, the emitter of the triode Q1 is connected with the emitter of the triode Q2 and the drain of the MOS tube M3 respectively, the base of the triode Q2 is connected with the emitter of the triode Q5 and the drain of the MOS tube M7 respectively, and serves as the non-inverting input terminal of the transconductance operational amplifier, the collector of the triode Q2 is connected with the emitter of the triode Q4, the base of the triode Q3 is connected with the base of the triode Q4, the base of the triode Q5, the collector of the triode Q5 and the drain of the MOS tube M5 respectively, the collector of the triode Q3 is connected with the base of the triode Q6 and the drain of the MOS tube M1 respectively, the collector of the triode Q4 is connected with the gate of the MOS tube M1, the gate of the MOS tube M2 and the drain of the MOS tube M2 respectively, and the emitter of the triode Q6 is connected with the drain of the MOS tube M8, the other end of the resistor R1 and the other end of the capacitor C1 respectively, and serves as the output terminal of the transconductance operational amplifier; The source of the MOS tube M1, the source of the MOS tube M2, the source of the MOS tube M4, the source of the MOS tube M5 and the collector of the triode Q6 are connected with the power supply, the gate of the MOS tube M3, the gate of the MOS tube M6, the gate of the MOS tube M7 and the gate of the MOS tube M8 are connected with the bias voltage, the source of the MOS tube M3, the source of the MOS tube M6, the source of the MOS tube M7 and the source of the MOS tube M8 are grounded, and the gate of the MOS tube M4 is connected with the drain of the MOS tube M4, the gate of the MOS tube M5 and the drain of the MOS tube M6 respectively.

3. The high bandwidth integrated high sensitivity photodiode amplifying circuit of claim 1, wherein, The buffer isolation unit further comprises a grounding resistor R3 and a diode D1, and the operational amplifier comprises a triode Q7, a triode Q8, a triode Q9, a triode Q10, a triode Q11, a MOS tube M9, a MOS tube M10, a MOS tube M11, a MOS tube M12, a MOS tube M13, a MOS tube M14, a MOS tube M15 and a MOS tube M16. The base of the triode Q7 is connected with the emitter of the triode Q12, the anode of the diode D1 and the drain of the MOS transistor M16 respectively, and serves as the inverting input terminal of the operational amplifier, the emitter of the triode Q7 is connected with the emitter of the triode Q8 and the drain of the MOS transistor M11 respectively, the collector of the triode Q7 is connected with the emitter of the triode Q9, the base of the triode Q8 is connected with the emitter of the triode Q11 and the drain of the MOS transistor M15 respectively, and serves as the non-inverting input terminal of the operational amplifier, the collector of the triode Q8 is connected with the emitter of the triode Q10, the base of the triode Q9 is connected with the base of the triode Q10, the base of the triode Q11, the collector of the triode Q11 and the drain of the MOS transistor M13 respectively, the collector of the triode Q9 is connected with the drain of the MOS transistor M9 and the base of the triode Q12 respectively, the collector of the triode Q10 is connected with the drain of the MOS transistor M10, the gate of the MOS transistor M10 and the gate of the MOS transistor M9 respectively, and the emitter of the triode Q12 serves as the output terminal of the operational amplifier; The source of the MOS transistor M9, the source of the MOS transistor M10, the source of the MOS transistor M12, the source of the MOS transistor M13 and the collector of the triode Q12 are connected with the power supply, the gate of the MOS transistor M11, the gate of the MOS transistor M14, the gate of the MOS transistor M15 and the gate of the MOS transistor M16 are connected with the bias voltage, the source of the MOS transistor M11, the source of the MOS transistor M14, the source of the MOS transistor M15 and the source of the MOS transistor M16 are grounded, the gate of the MOS transistor M12 is connected with the drain of the MOS transistor M12, the gate of the MOS transistor M13 and the drain of the MOS transistor M14 respectively, and the cathode of the diode D1 is connected with the grounding resistor R3.

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