Programmable gain amplification circuit for flicker pulses

Abstract

The present application relates to the programmed gain amplification circuit of flicker pulse, belongs to electronic circuit technical field, including one level analog switch, one level amplifier, two level analog switch, two level amplifier, three level analog switch, three level amplifier, noise suppression switch and digital attenuator, one level analog switch, two level analog switch, three level analog switch and noise suppression switch are single pole double throw analog switch;The common end of one level analog switch is connected with signal input terminal, and the two prongs thereof are connected with one level amplifier and digital attenuator respectively;The common end of two level analog switch is connected with one level amplifier, and the two prongs thereof are connected with two level amplifier and digital attenuator respectively;The common end of three level analog switch is connected with two level amplifier, and the two prongs thereof are connected with three level amplifier and digital attenuator respectively.The present application realizes the precise pulse signal gain regulation of wide range.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a programmable gain amplifier circuit for scintillation pulses. Background Technology

[0002] Due to the influence of particle energy, detection materials, and detector efficiency, the amplitude of scintillation pulse signals can vary over a wide range. Meanwhile, data acquisition systems typically have a fixed range. If the scintillation pulse signal is not amplified or attenuated accordingly, the acquisition accuracy will decrease when acquiring signals with small amplitudes, and truncation or cutoff may occur when acquiring signals with large amplitudes, potentially damaging the acquisition system.

[0003] Discrete component amplifier circuits: These circuits are built using discrete components such as resistors, capacitors, and transistors. Gain can be adjusted by changing component parameters (such as resistor values). While this type of circuit can achieve gain adjustment within a certain range, the large number of components and high circuit complexity lead to poor circuit stability, large size, and high cost. Furthermore, the parameters of discrete components are not very consistent, making it difficult to achieve high-precision gain adjustment, and the adjustment process is cumbersome, usually requiring manual component replacement or parameter adjustment.

[0004] Integrated amplifier circuits: With the development of integrated circuit technology, many integrated amplifier circuit chips have emerged, such as operational amplifiers (Op-Amp) and programmable gain amplifiers (PGA). These integrated amplifier circuits have advantages such as small size, stable performance, and low cost. However, most integrated amplifier circuits have limited gain adjustment range and insufficient adjustment accuracy and flexibility, making it difficult to meet the high gain adjustment requirements of some special application scenarios.

[0005] In the current technology, the mainstream approach in the field of electronic circuits is to select integrated circuit components with multiple functions to implement specific functions for different application requirements. At the same time, there are other programmable gain amplifier design schemes that operate at high frequencies, such as a very high frequency programmable gain amplifier based on MMIC proposed by LI Xunshuan, ZHOU Shuang and others.

[0006] Adjusting the gain of a fixed-gain amplifier circuit, whether composed of discrete components or a single integrated amplifier circuit, often requires changing the value of the feedback resistor, making flexible adjustment without modifying the circuit itself impossible. Programmable gain amplifiers (PGAs) offered by some manufacturers cannot support input signals with a wide amplitude range, and their gain adjustment range is also limited. Using analog or digital potentiometers as feedback resistors for gain adjustment results in inaccurate gain control and a small gain adjustment range.

[0007] Existing technologies use integrated circuit components with multiple functions to build programmable gain amplifier circuits. However, since programmable gain amplifiers (PGAs) or digital potentiometers are used as part of the circuit design, problems such as small input signal range, small gain adjustment range, and inaccurate gain control will occur.

[0008] For a very high frequency programmable gain amplifier based on MMIC, the following problems exist:

[0009] 1. The gain control of the variable gain amplifier VCA824 is controlled by analog voltage, which makes the gain control inaccurate.

[0010] 2. The input signal must pass through the preamplifier, which limits the input signal range of the preamplifier and requires it to be lower than the maximum input voltage of the preamplifier.

[0011] 3. The minimum step of the digital attenuator is 1dB, which makes the adjustable gain step of the overall gain amplifier only 1dB.

[0012] 4. The gain adjustment range is relatively small, only from -19dB to 52dB. Summary of the Invention

[0013] To address the aforementioned problems in the prior art, this invention provides a programmable gain amplifier circuit for flicker pulses, enabling the input signal amplitude to range from 2mV to 10V, the gain adjustment range to -30dB to 60dB, and the gain adjustment step size to be 0.25dB. Furthermore, it can be program-controlled by devices such as microcontrollers or FPGAs.

[0014] The programmable gain amplifier circuit for flicker pulses includes a first-stage analog switch, a first-stage amplifier, a second-stage analog switch, a second-stage amplifier, a third-stage analog switch, a third-stage amplifier, a noise suppression switch, and a digital attenuator. The first-stage analog switch, second-stage analog switch, third-stage analog switch, and noise suppression switch are all single-pole double-throw analog switches. The common terminal of the first-stage analog switch is connected to the signal input terminal, and its two throw terminals are connected to the first-stage amplifier and the digital attenuator, respectively. The common terminal of the second-stage analog switch is connected to the first-stage amplifier, and its two throw terminals are connected to the second-stage amplifier and the digital attenuator, respectively. The common terminal of the third-stage analog switch is connected to the second-stage amplifier, and its two throw terminals are connected to the third-stage amplifier and the digital attenuator, respectively. The common terminal of the noise suppression switch is connected to the third-stage amplifier, and its two throw terminals are connected to resistor R1 and the digital attenuator, respectively. Resistor R1 is grounded.

[0015] Furthermore, the first-stage amplifier, second-stage amplifier, and third-stage amplifier are all fixed-gain amplifiers, implemented using the high-speed operational amplifier OPA354 chip, with a gain-bandwidth product of 250MHz, providing a stable 20dB gain.

[0016] Furthermore, the digital attenuator uses the PE43711 chip, providing precise attenuation from -32dB to 0dB, with an attenuation step value of 0.25dB.

[0017] Furthermore, the first-level analog switch, the second-level analog switch, and the third-level analog switch use the PE42520 chip, with an operating frequency of 9KHz to 13GHz.

[0018] Furthermore, the PE42520 chip grounds the LS pin and controls the signal flow of the analog switch chip by controlling the high and low levels of the CTRL pin.

[0019] Furthermore, the PE43711 chip can control the attenuation of the digital attenuator chip by using the SI, CLK, and LE pins for serial communication.

[0020] The beneficial effects of this invention are as follows: This invention utilizes a multi-stage analog switch to control the number of amplifier stages through which the signal passes, thereby achieving a wide range of gain adjustment; it utilizes a digital attenuator to control the attenuation magnitude of the attenuator, thereby achieving precise gain adjustment; and it utilizes a digital signal to control the circuit operation, thereby improving control accuracy. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the programmable gain amplifier circuit of the present invention.

[0022] Figure 2 This is the circuit schematic for the analog switch section.

[0023] Figure 3 This is the circuit schematic of the amplifier section.

[0024] Figure 4 This is the circuit diagram of the digital attenuator section. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the figures. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] In this embodiment, as Figure 1As shown, the programmable gain amplifier circuit for flicker pulses includes a first-stage analog switch S1, a first-stage amplifier OPA1, a second-stage analog switch S2, a second-stage amplifier OPA2, a third-stage analog switch S3, a third-stage amplifier OPA3, a digital attenuator AT1, and a noise suppression switch S4. The common terminal of the first-stage analog switch S1 is connected to the signal input terminal SIGIN, and its two throw terminals are connected to the first-stage amplifier OPA1 and the digital attenuator AT1, respectively. The common terminal of the second-stage analog switch S1 is connected to the first-stage amplifier OPA1, and its two throw terminals are connected to the second-stage amplifier OPA2 and the digital attenuator AT1, respectively. The common terminal of the three-stage analog switch S3 is connected to the two-stage amplifier OPA2, and its two throw terminals are connected to the three-stage amplifier OPA3 and the digital attenuator AT1, respectively. The common terminal of the noise suppression switch S4 is connected to the three-stage amplifier OPA3, and its two throw terminals are connected to the resistor R1 and the digital attenuator AT1, respectively. The resistor R1 is grounded. In actual circuits, analog switches are not completely ideally isolated, and noise signals will enter the operational amplifier circuit through the switches. In order to prevent noise amplified by multiple operational amplifiers from mixing into the signal, the noise suppression switch S4 is set to introduce the noise into the ground plane through high impedance to dissipate it.

[0027] The first-stage analog switch S1, the second-stage analog switch S2, and the third-stage analog switch S3 are used to control the number of amplifier stages through which the input signal passes, so that the signal obtains a gain that gradually increases according to the number of stages when it enters the digital attenuator AT1. The following is an explanation with specific data and examples.

[0028] like Figure 2 As shown, the PE42520 analog switch chip is selected to implement the first, second, and third stage analog switching circuits, with an operating frequency of 9kHz to 13GHz, an insertion loss of 0.4dB, and an isolation of 65dB. Figure 3 As shown, the high-speed operational amplifier OPA354 chip is selected to implement the first, second, and third stage fixed-gain amplifier circuits. The gain-bandwidth product is 250MHz, which can stably provide a 20dB gain at high frequencies. Figure 4 As shown, the PE43711 digital attenuator chip is selected to achieve precise attenuation. It operates at frequencies from 9kHz to 6GHz, with an attenuation range of -32dB to 0dB and a minimum step of 0.25dB. It can be controlled in both serial and parallel modes.

[0029] Each analog switch provides a 20dB gain, allowing the signal to achieve gains of 0dB, 20dB, 40dB, or 60dB when entering the digital attenuator AT1. The digital attenuator AT1 provides precise attenuation from -32dB to 0dB in 0.25dB steps. The signal gain is precisely controlled by the digital attenuator AT1, ultimately achieving precise gain adjustment from -32dB to 60dB in 0.25dB steps.

[0030] In terms of the specific signal flow of an input signal in the circuit: The signal first enters the first-stage analog switch S1. If a 0dB gain is desired when the signal enters the digital attenuator AT1, the signal flow is directly controlled by the first-stage analog switch S1 to the digital attenuator AT1. If a 20dB gain is desired, the first-stage analog switch S1 controls the signal to be sent to the first-stage amplifier OPA1. The signal outputs from the first-stage amplifier OPA1 with a 20dB gain and is then directly input to the second-stage analog switch S2. Similar to the first-stage analog switch S1, it can be selected to allow the signal to flow to either the digital attenuator AT1 or the second-stage amplifier OPA2 to obtain another 20dB gain. The third-stage analog switch S3 and the third-stage amplifier OPA3 are the same as the second stage, allowing the signal to flow to either the digital attenuator AT1 or the third-stage amplifier OPA3 to obtain another 20dB gain. The signal enters the digital attenuator AT1 with a gain of 0dB, where precise attenuation is provided, resulting in a final output signal gain range of -32dB to 0dB; the signal enters the digital attenuator AT1 with a gain of 20dB, where precise attenuation is provided, resulting in a final output signal gain range of 0dB to 20dB; the signal enters the digital attenuator AT1 with a gain of 40dB, where precise attenuation is provided, resulting in a final output signal gain range of 20dB to 40dB; the signal enters the digital attenuator AT1 with a gain of 60dB, where precise attenuation is provided, resulting in a final output signal gain range of 40dB to 60dB.

[0031] In terms of program control: This invention grounds the LS pin of the PE42520 chip, and controls the signal flow of the analog switch chip by controlling the high and low levels of the CTRL pin. The SI, CLK, and LE pins of the PE43711 chip are used for serial communication to control the attenuation of the digital attenuator chip. The program control adopts a modular programming approach, consisting of a main program and several program modules. The main program controls the signal flow of each stage of the PE42520 chip according to the target gain, while simultaneously changing the serial communication data of the PE43711 chip to adjust the attenuation, achieving signal amplification or attenuation at a specific gain. It also includes a serial communication module for communication with the PE43711 chip; and a control word module for converting the user-inputted actual gain into the circuit's control word.

[0032] In the description of embodiments of the present invention, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0033] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A programmed gain amplification circuit for flicker pulses, characterized by The application relates to a signal processing circuit, which comprises a first analog switch, a first amplifier, a second analog switch, a second amplifier, a third analog switch, a third amplifier, a noise suppression switch and a digital attenuator, wherein the first analog switch, the second analog switch, the third analog switch and the noise suppression switch are single-pole double-throw analog switches; the common terminal of the first analog switch is connected with a signal input terminal, and the two throw terminals are respectively connected with the first amplifier and the digital attenuator; the common terminal of the second analog switch is connected with the first amplifier, and the two throw terminals are respectively connected with the second amplifier and the digital attenuator; the common terminal of the third analog switch is connected with the second amplifier, and the two throw terminals are respectively connected with the third amplifier and the digital attenuator; the common terminal of the noise suppression switch is connected with the third amplifier, and the two throw terminals are respectively connected with a resistor R1 and the digital attenuator, and the resistor R1 is grounded; the digital attenuator adopts a PE43711 chip, provides accurate attenuation of -32dB to 0dB, and the attenuation step value is 0.25dB; the SI, CLK and LE pins of the PE43711 chip are used for serial communication, so as to control the attenuation size of the digital attenuator chip.

2. The programmed gain amplification circuit of flickering pulses according to claim 1, characterized in that, The first amplifier, the second amplifier and the third amplifier are fixed-gain amplifiers, which are realized by using high-speed operational amplifiers OPA354 chips, have a gain-bandwidth product of 250MHz, and provide stable 20dB gain.

3. The programmed gain amplification circuit of flickering pulses according to claim 1, characterized in that, The first analog switch, the second analog switch and the third analog switch adopt PE42520 chips, and the working frequency is 9KHz to 13GHz.

4. The programmed gain amplification circuit of flickering pulses according to claim 3, characterized in that, The LS pin of the PE42520 chip is grounded, and the signal flow direction of the analog switch chip is realized by controlling the high and low levels of the CTRL pin.

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