Leveling method and system for PCB processing in integrated circuits

Abstract

The application discloses a flattening method and system for PCB processing in integrated circuits, and relates to the field of printed circuits. The method comprises the following steps: collecting surface data of a PCB to be processed to obtain a topography data set, and establishing a three-dimensional topography model of the PCB to be processed based on the topography data set; identifying three-dimensional deviation areas of the PCB to be processed through the three-dimensional topography model; performing flattening analysis according to the mapping of the three-dimensional deviation areas to the integrated circuit, setting a flattening priority mapping diagram, dynamically planning the flattening based on the flattening priority mapping diagram, and generating a flattening path; performing flattening monitoring according to the flattening path, verifying the flattening degree according to multi-source monitoring data, obtaining flattening quality parameters, and iteratively updating the flattening path to adaptively flatten the PCB to be processed. The method solves the technical problems of insufficient adaptability and precision of existing PCB processing and flattening, and achieves the technical effect of high-precision adaptive flattening.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of printed circuit, in particular to a flattening method and system for PCB processing in integrated circuits. BACKGROUND

[0002] In the field of integrated circuit manufacturing, the flatness of the PCB plays a crucial role in circuit performance, component mounting reliability and overall product quality. Even slight deviations in flatness can cause signal interference, poor component contact and other serious problems, thereby affecting the normal operation and service life of the integrated circuit. Currently, mechanical flattening or hot air flattening methods are mainly used for appearance correction of PCBs before processing. However, these methods lack accurate identification and dynamic planning capabilities for three-dimensional surface topography, resulting in poor adaptability, insufficient precision and easy secondary deformation during flattening.

[0003] At present, in the related art, the flattening for PCB processing in integrated circuits has the technical problems of insufficient adaptability and precision. SUMMARY

[0004] The present application provides a flattening method and system for PCB processing in integrated circuits, which collects surface data of the PCB to be processed to form a topography data set, establishes a three-dimensional topography model based on the topography data set, identifies three-dimensional deviations using the three-dimensional topography model, finds out three-dimensional deviation areas such as warping and unevenness, maps the three-dimensional deviation areas to the integrated circuit for flattening analysis, sets a flattening priority mapping diagram, dynamically plans the flattening based on the flattening priority mapping diagram, generates a flattening path, monitors the flattening when executing the flattening path, verifies the flatness based on multi-source monitoring data, and iteratively updates the flattening quality parameters obtained from the flattening path. The technical means of adaptive flattening of the PCB to be processed is achieved, the technical problems of insufficient adaptability and precision of the existing flattening for PCB processing in integrated circuits are solved, and the technical effect of high-precision adaptive flattening is achieved.

[0005] The present application provides a flattening method for PCB processing in integrated circuits, comprising: collecting surface data of the PCB to be processed to obtain a topography data set, establishing a three-dimensional topography model of the PCB to be processed based on the topography data set; identifying three-dimensional deviations of the PCB to be processed through the three-dimensional topography model, extracting three-dimensional deviation areas, which include warping areas and uneven areas; mapping the three-dimensional deviation areas to the integrated circuit for flattening analysis, setting a flattening priority mapping diagram, dynamically planning the flattening based on the flattening priority mapping diagram, and generating a flattening path; monitoring the flattening by executing the flattening path, verifying the flatness based on multi-source monitoring data, obtaining flattening quality parameters, and iteratively updating the flattening path for adaptive flattening of the PCB to be processed.

[0006] In a possible implementation, the three-dimensional deviation identification is performed on the PCB to be processed by using the three-dimensional topographic model, and a three-dimensional deviation region is extracted. The following processing is performed: a plurality of feature points in a four-corner region of the PCB to be processed are selected as reference points, fitting is performed according to the reference points, and reference plane data is set; a vertical distance between a first grid node of the three-dimensional topographic model and the reference plane data is fitted, and a plurality of node deviation values are obtained; the node deviation values of the plurality of nodes are stored in association with coordinate positions of the reference plane data, and a deviation distribution map is generated; and the deviation distribution map is subjected to region identification, and the three-dimensional deviation region is extracted.

[0007] In a possible implementation, the deviation distribution map is subjected to region identification, and the three-dimensional deviation region is extracted. The following processing is performed: a positive and negative deviation threshold is set, a potential deviation point set is generated by determining and identifying based on the deviation distribution map in combination with the positive and negative deviation threshold; region growing analysis is performed based on the potential deviation point set, and adjacent potential deviation points in a spatial position are aggregated to construct a deviation continuous region; curvature calculation is performed on the deviation continuous region, and a warping region is determined according to region curvature; local roughness calculation is performed on the deviation continuous region, and an uneven region is determined according to region roughness; and the warping region and the uneven region are integrated to construct the three-dimensional deviation region.

[0008] In a possible implementation, flattening analysis is performed according to mapping of the three-dimensional deviation region to an integrated circuit, a flattening priority mapping map is set, dynamic flattening planning is performed based on the flattening priority mapping map, a flattening path is generated, and the following processing is performed: an integrated circuit layout map is called to identify key elements, and key circuit element coordinates are obtained; contour identification is performed on the three-dimensional deviation region, and region outer contour coordinates are extracted; the key circuit element coordinates and the region outer contour coordinates are subjected to spatial mapping to construct a region-circuit connection network map; circuit function influence analysis is performed according to the region-circuit connection network map, and a circuit function influence coefficient is obtained; region deviation influence analysis is performed according to the region-circuit connection network map, and a region deviation influence coefficient is obtained; flattening weight analysis is performed based on the circuit function influence coefficient and the region deviation influence coefficient, and a flattening priority is constructed; and the flattening priority is traced back to the three-dimensional deviation region for mapping and labeling according to the flattening priority, and the flattening priority mapping map is constructed.

[0009] In a possible implementation, the key circuit element coordinates are spatially mapped with the region outer contour coordinates to construct a region-circuit connection graph, and the following processing is performed: adjacent sorting is performed based on the region outer contour coordinates, a boundary point coordinate sequence is generated for geometric analysis, and geometric feature parameters are extracted; topography reading is performed on the region outer contour coordinates according to the boundary point coordinate sequence, and topographic feature parameters are generated; spatial region division is performed by traversing the three-dimensional topography model, and a plurality of spatial grid coding units are generated; the key circuit element coordinates are matched with the plurality of spatial grid codes, and the key circuit element coordinates are mapped to the plurality of spatial grid coding units according to the matching result to generate element spatial coding positions; spatial position mapping analysis is performed on the element spatial coding positions and the region outer contour coordinates according to the geometric feature parameters and the topographic feature parameters, and the region-circuit connection graph is constructed.

[0010] In a possible implementation, dynamic flattening planning is performed based on the flattening priority mapping graph to generate a flattening path, and the following processing is performed: the performance constraints and flattening process constraints of a flattening device are called, and a flattening path optimization target is established; a path starting point is determined by performing a maximum value search on the flattening priority mapping graph according to the flattening priority; a region access order is determined by performing a nearest neighbor search on the flattening priority mapping graph according to the path starting point; a to-be-flattened trajectory is generated by performing flattening planning on the flattening priority mapping graph based on the region access order; and the flattening path is constructed by performing real-time correction according to the flattening movement direction based on the to-be-flattened trajectory.

[0011] In a possible implementation, flattening monitoring is performed on the flattening path, flattening degree verification is performed based on multi-source monitoring data, flattening quality parameters are obtained, and the following processing is performed: the flattening path is controlled to move the flattening head according to the planned path to perform flattening monitoring on the to-be-processed PCB, and multi-source monitoring data is obtained; a plurality of surface topography data are obtained by performing interval collection based on the multi-source monitoring data; real-time flattening degree calculation is performed according to the plurality of surface topography data, and a real-time flattening degree index is set; flattening degree verification is performed on the multi-source monitoring data according to the real-time flattening degree index, and a flattening verification evaluation result is generated; surface flatness errors and local curling degrees are generated by performing flattening calculation based on the flattening verification evaluation result; first flattening quality parameters are obtained by performing surface roughness quality analysis based on the surface flatness errors; and second flattening quality parameters are obtained by performing flattening residual stress distribution quality analysis based on the local curling degrees.

[0012] In a possible implementation, according to the flatness verification evaluation result, surface flatness error and local curling degree are generated by performing the following processing: traversing the flatness verification evaluation result to extract a plurality of surface flattening points in the PCB to be processed that pass the verification; traversing the flatness verification evaluation result to perform local deformation identification and extract a plurality of local deformation regions; calculating the vertical distance between the plurality of surface flattening points and the reference plane data to generate deviation data; calculating the range value of the deviation data as the overall plane error value, performing local plane partition calculation according to the overall plane error value, and generating surface flatness error; performing curvature calculation based on the plurality of local deformation regions to obtain curvature variation characteristics, aggregating the plurality of local deformation regions according to the curvature variation characteristics, and generating continuous deformation regions; performing deformation calculation according to the continuous deformation regions to determine curling angle and warping height; and performing comprehensive identification based on the curling angle and the warping height to determine the local curling degree.

[0013] In a possible implementation, the flatness quality parameter is obtained and iteratively updated back to the flattening path, and adaptive flattening is performed on the PCB to be processed by performing the following processing: setting a plurality of quality tolerance thresholds, comparing and analyzing the flattening quality parameter and the plurality of quality tolerance thresholds to generate a flattening quality defect distribution map; determining the traversal order of the flattening path according to the flattening quality defect distribution map, associating and mapping the flattening path, determining the to-be-optimized flattening path parameter, and the to-be-optimized flattening path parameter includes a path optimization target; updating the flattening path according to the path optimization target to generate a flattening optimized path; constructing a virtual environment to perform feasibility simulation verification on the flattening optimized path, iteratively correcting the flattening optimized path according to the verification result, and formulating a flattening strategy to perform adaptive flattening on the PCB to be processed.

[0014] The application also provides a flattening system for PCB processing in an integrated circuit, comprising: a three-dimensional topography model establishing module, configured to collect surface data of a PCB to be processed, obtain a topography data set, and establish a three-dimensional topography model of the PCB to be processed based on the topography data set; a three-dimensional deviation identification module, configured to perform three-dimensional deviation identification on the PCB to be processed through the three-dimensional topography model, and extract a three-dimensional deviation region, the three-dimensional deviation region including a warping region and an uneven region; a dynamic flattening planning module, configured to perform flattening analysis according to the mapping of the three-dimensional deviation region to the integrated circuit, set a flattening priority mapping diagram, perform dynamic flattening planning based on the flattening priority mapping diagram, and generate a flattening path; and an adaptive flattening module, configured to perform flattening monitoring on the flattening path, perform flatness verification according to multi-source monitoring data, obtain a flattening quality parameter, iteratively update the flattening quality parameter back to the flattening path, and perform adaptive flattening on the PCB to be processed.

[0015] The leveling method and system for PCB processing in integrated circuits provided by the present application first collects surface data of the PCB to be processed to obtain a topographic data set, establishes a three-dimensional topographic model of the PCB to be processed based on the topographic data set, then performs three-dimensional deviation identification on the PCB to be processed through the three-dimensional topographic model, extracts a three-dimensional deviation area, and the three-dimensional deviation area includes a warping area and an uneven area. Then, the three-dimensional deviation area is mapped to the integrated circuit for leveling analysis, a leveling priority mapping diagram is set, dynamic leveling planning is performed based on the leveling priority mapping diagram, a leveling path is generated, and finally the leveling path is executed for leveling monitoring, the flatness is verified according to multi-source monitoring data, the leveling quality parameter is obtained, and the leveling path is iteratively updated for adaptive leveling of the PCB to be processed. The technical effect of high-precision adaptive leveling is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments of the present application will be briefly introduced below. The flowchart is used to illustrate the operations performed by the system according to the embodiments of the present application in the present application. It should be understood that the foregoing or the following operations are not necessarily performed in sequence. On the contrary, various steps can be processed in reverse order or simultaneously according to needs. At the same time, other operations can be added to these processes, or one or more steps of operations can be removed from these processes.

[0017] Figure 1 The flowchart of the leveling method for PCB processing in integrated circuits provided by the embodiments of the present application is shown.

[0018] Figure 2 The structural diagram of the leveling system for PCB processing in integrated circuits provided by the embodiments of the present application is shown.

[0019] Explanation of reference signs: three-dimensional topographic model establishment module 10, three-dimensional deviation identification module 20, dynamic leveling planning module 30, and adaptive leveling module 40. DETAILED DESCRIPTION

[0020] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described below.

[0021] In order to make the purposes, technical solutions and advantages of the present application clearer, the following will make further detailed description to the present application in conjunction with the drawings, and the described embodiments should not be regarded as limitation to the present application, all other embodiments obtained by those skilled in the art without creative labor shall belong to the protection scope of the present application.

[0022] In the following description, "some embodiments" are referred to, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict, and the term "first\second" referred to only distinguishes similar objects, and does not represent a specific order of the objects. The terms "include" and "have" and any variations, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or server including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or modules not clearly listed or inherent to these processes, methods, products or devices. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by those skilled in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application.

[0023] The embodiments of the present application provide a flattening method for PCB processing in integrated circuits, as shown in Figure 1 The method comprises the following steps:

[0024] In step S100, surface data of a PCB to be processed is collected to obtain a topography data set, and a three-dimensional topography model of the PCB to be processed is established based on the topography data set.

[0025] Specifically, a three-dimensional scanner or a laser range finder is used to non-contact scan the surface of the PCB to be processed, and three-dimensional coordinate data of each point on the surface is obtained. For example, the three-dimensional scanner emits a laser beam and receives the reflected signal, and determines the distance of each point on the surface by calculating the round-trip time of the signal, thereby obtaining the three-dimensional coordinate data. These data constitute a topography data set, which contains the height, concave-convex and other topography information of the surface of the PCB. The collected topography data set is imported into a computer-aided design software or a three-dimensional modeling software, and a three-dimensional topography model of the PCB to be processed is generated through data processing.

[0026] In step S200, three-dimensional deviation identification is performed on the PCB to be processed through the three-dimensional topography model, and a three-dimensional deviation region is extracted, which includes a warping region and an uneven region.

[0027] Specifically, the three-dimensional topography model is analyzed by using image processing techniques to identify the areas deviating from the ideal flat surface. These deviations are manifested as height differences, curvature changes, etc. According to the identification results, the areas deviating by more than a preset threshold are extracted as three-dimensional deviation areas. These areas include warped areas and uneven areas, such as areas where the edges or part of the PCB surface are warped due to stress, temperature, etc., areas where the PCB surface has uneven phenomena such as protrusions, depressions, etc.

[0028] In one possible implementation, the three-dimensional deviation identification of the PCB to be processed is performed by the three-dimensional topography model, and the three-dimensional deviation areas are extracted. Step S200 further includes step S210 of selecting a plurality of feature points in the four corner regions of the PCB to be processed as reference points, fitting according to the reference points, and setting reference plane data. Specifically, in the four corner regions of the PCB to be processed, a plurality of representative feature points are selected by using image recognition techniques or by a pre-set marker positioning method. These feature points have obvious geometric features, such as corner points, edge intersection points, etc. For example, on the four corners of the PCB, two obvious intersection points of each corner edge are selected as feature points, and a total of 8 feature points are selected in the four corners.

[0029] A mathematical fitting algorithm such as the least squares method is used to fit the selected plurality of feature points. The least squares method finds the best function match of the data by minimizing the sum of squares of errors, i.e., finds a plane closest to these feature points. Through calculation, the equation parameters of this fitting plane are determined, thereby setting the reference plane data, which contains the position, normal vector, etc. of the reference plane, representing the flat plane that the PCB should theoretically be in, for comparison with the actual surface of the PCB.

[0030] Step S220, fitting the vertical distance between the first grid node of the three-dimensional topography model and the reference plane data to obtain the deviation degree values of a plurality of nodes. Specifically, the three-dimensional topography model of the PCB to be processed is subjected to grid processing to form a plurality of small grid cells, and the vertices of each grid cell are grid nodes. A programming algorithm is used to traverse these grid nodes, for example, a double loop structure is used to access each grid node in turn in the order of rows and columns. For each grid node, the vertical distance from the node to the reference plane is calculated according to its three-dimensional coordinates and the equation of the reference plane data. This can be calculated by vector operation or the distance formula from a point to a plane. The calculated vertical distance is taken as the deviation degree value of the grid node, which reflects the deviation degree of the point relative to the reference plane.

[0031] Step S230, store the deviation value of each node in association with the coordinate position of the reference plane data, and generate a deviation distribution map. Specifically, a data structure is established, for example, an array or a dictionary, to store the deviation value of each grid node in association with its coordinate position in the reference plane coordinate system, so that the deviation value of the corresponding node can be quickly queried according to the coordinate position. Using a graphics drawing library or a visualization tool, the distribution of the deviation on the surface of the PCB board is displayed in a graphical manner according to the associated stored data. Different colors or gray scales can be used to represent different deviation value ranges, for example, green is used to represent areas with smaller deviation, and red is used to represent areas with larger deviation, thereby generating a deviation distribution map.

[0032] Step S240, regionally identify the deviation distribution map to extract the three-dimensional deviation region. Specifically, an image segmentation algorithm is used, for example, a threshold-based segmentation method, a region growing algorithm, or an edge detection algorithm, etc., to process the deviation distribution map. Taking the threshold-based segmentation method as an example, a deviation threshold is set to identify the region with a deviation value greater than the threshold as a whole region. This threshold can be determined according to the processing accuracy requirement of the PCB board and actual production experience. According to the region identification result, the identified region is positioned and marked in the three-dimensional topographic model to extract the corresponding three-dimensional deviation region. These regions are the regions that need to be flattened.

[0033] In one possible implementation, the deviation distribution map is regionally identified to extract the three-dimensional deviation region, and step S240 further includes step S241 of setting positive and negative deviation threshold values, determining and identifying based on the deviation distribution map in combination with the positive and negative deviation threshold values, and generating a set of potential deviation points. Specifically, according to the processing accuracy requirement of the PCB board and actual production experience, a positive deviation threshold value and a negative deviation threshold value are set. The positive deviation threshold value is used to identify the abnormal region of the PCB board surface higher than the reference plane, and the negative deviation threshold value is used to identify the abnormal region of the surface lower than the reference plane. Each point in the deviation distribution map is traversed, and its deviation value is compared with the set positive and negative deviation threshold values. If the deviation value is greater than the positive deviation threshold value or less than the negative deviation threshold value, the point is marked as a potential deviation point, and its coordinate and deviation value are recorded. All data marked as potential deviation points are stored in a data structure, for example, an array or a linked list, to form a set of potential deviation points.

[0034] Step S242, based on the set of potential deviation points, region growing analysis is performed to extract potential deviation points that are adjacent in spatial position and aggregate them to construct a deviation continuous region. Specifically, a region growing algorithm is selected, for example, a seed point region growing algorithm based on neighborhood. The algorithm starts from a seed point and gradually merges points adjacent to the seed point and satisfying certain conditions into the current region. A point is randomly selected from the set of potential deviation points as a seed point. For each neighborhood point of the seed point, it is checked whether the neighborhood point is also in the set of potential deviation points. If yes, the neighborhood point is merged into the current region and used as a new seed point to continue the region growing. The above process is repeated until no new neighborhood point can be merged into the current region, at which time a deviation continuous region is constructed. Then, a seed point is again selected from the remaining potential deviation points and the above steps are repeated to construct other deviation continuous regions.

[0035] Step S243, curvature calculation is performed on the deviation continuous regions to determine a warping region according to the region curvature. Specifically, for each deviation continuous region, a curvature calculation algorithm is used, for example, a method based on differential geometry, to calculate the curvature of each point in the region. Curvature reflects the degree of bending of the surface at the point. For a discrete three-dimensional point set, a differential approximation method can be used to calculate the curvature. A curvature threshold is set. If the curvature of most points in a deviation continuous region is greater than the threshold, the region is determined as a warping region. The warping region represents a large local bending of the PCB surface.

[0036] Step S244, local roughness calculation is performed on the deviation continuous regions to determine an uneven region according to the region roughness. Specifically, for each deviation continuous region, a local roughness calculation algorithm is used, for example, the arithmetic mean deviation Ra calculation method in the surface roughness evaluation parameters. A local region of a certain size is selected within the deviation continuous region, and the average of the absolute values of the distances of all points in the region to the reference plane is calculated as the roughness value of the local region. A roughness threshold is set. If the roughness value of a deviation continuous region is greater than the threshold, the region is determined as an uneven region. The uneven region represents a rough and uneven local surface of the PCB.

[0037] Step S245, the warping region and the uneven region are integrated to construct the three-dimensional deviation region. Specifically, the warping region and the flat region are merged to form a complete three-dimensional deviation region. Set operation methods can be used, for example, union operation, to merge all points in the two regions into a new region. The integrated region is positioned and marked in the three-dimensional topography model to construct a three-dimensional deviation region. This region contains all areas of the PCB surface that need to be flattened.

[0038] Step S300, flattening analysis is performed according to the mapping of the three-dimensional deviation region to the integrated circuit, a flattening priority mapping diagram is set, dynamic flattening planning is performed based on the flattening priority mapping diagram, and a flattening path is generated.

[0039] Specifically, the position information of the identified three-dimensional deviation region in the three-dimensional topographic model is mapped to the actual integrated circuit layout, and it is determined which region has the greatest impact on the performance and reliability of the integrated circuit. According to the mapping result and the design requirements of the integrated circuit, a flattening priority mapping diagram is set. The diagram determines the flattening order and priority of each three-dimensional deviation region. Using a path planning algorithm, a flattening path is generated according to the flattening priority mapping diagram.

[0040] In one possible implementation, flattening analysis is performed according to the mapping of the three-dimensional deviation region to the integrated circuit, a flattening priority mapping diagram is set, dynamic flattening planning is performed based on the flattening priority mapping diagram, and a flattening path is generated, and step S300 further includes step S310 of calling an integrated circuit layout to identify key elements and obtain key circuit element coordinates. Specifically, the layout of the integrated circuit is called from the PCB board design file or the related database. The layout records the position, size and other information of each element in the integrated circuit on the PCB board. According to the function and performance requirements of the integrated circuit, the determination rules of the key elements are formulated. For example, for high-speed signal transmission circuits, high-speed signal pins, high-frequency filter capacitors and other elements are regarded as key elements; for power supply circuits, power supply chips, large-capacity capacitors and other elements are key elements. Using image recognition or data analysis technology, the key elements are identified in the integrated circuit layout according to the determined key element rules. Then, by analyzing the coordinate information in the layout, the center coordinates or other representative coordinate points of each key element are obtained and recorded in a data structure, such as an array or a dictionary.

[0041] Step S320, contour identification is performed on the three-dimensional deviation region, and the outer contour coordinates are extracted. Specifically, the relevant information in the three-dimensional deviation region data is read, and a contour identification algorithm is selected, such as an edge detection-based algorithm or a region growing-based contour extraction algorithm. The selected algorithm is used to identify the contour of the three-dimensional deviation region, and then the coordinates of the outer contour are extracted. The extracted outer contour coordinates are stored in a data structure, such as a linked list or an array.

[0042] Step S330, spatially map the key circuit element coordinates with the region outer contour coordinates to construct a region-circuit association graph. Specifically, use coordinate conversion and spatial relationship judgment methods to map the key circuit element coordinates and the region outer contour coordinates into the same three-dimensional space coordinate system. Coordinate conversion can be performed using methods such as homogeneous coordinate transformation to ensure consistency of the two coordinate systems. Determine the spatial relationship between the key circuit element and the three-dimensional deviated region, such as whether the element is located within the deviated region, the distance from the deviated region, etc. According to these relationships, construct an association matrix or graph structure. Use graph structure in graph theory to represent the association relationship between the region and the circuit element. Take the three-dimensional deviated region and the key circuit element as nodes in the graph, add edges according to their association relationship, and construct a region-circuit association graph.

[0043] Step S340, perform circuit function impact analysis according to the region-circuit association graph to obtain a circuit function impact coefficient. Specifically, establish a circuit function model according to the design documents and functional description of the integrated circuit. This model can be a circuit simulation model or a rule-based functional model, which is used to describe the functional relationship and signal transmission path between elements in the circuit. Analyze the impact of the three-dimensional deviated region on the function of the key circuit element. For example, for elements on the signal transmission path, if the deviated region causes the element position to change or the performance to decline, it will affect the transmission quality of the signal; for elements in the power supply circuit, the deviated region will affect the stability and voltage accuracy of the power supply. According to the results of the impact analysis, calculate the circuit function impact coefficient. This coefficient can be a numerical value ranging from 0 to 1, indicating the degree of influence of the deviated region on the circuit function, 0 indicating no influence and 1 indicating severe influence.

[0044] Step S350, perform region deviation impact analysis according to the region-circuit association graph to obtain a region deviation impact coefficient. Specifically, determine indicators for evaluating the degree of deviation of the three-dimensional deviated region, such as deviation height, deviation area, deviation curvature, etc. These indicators can reflect the geometric characteristics of the deviated region and the impact on the overall flatness of the PCB board. Link the deviation degree evaluation indicators with the impact on the performance of the PCB board. For example, the greater the deviation height, the greater the gap that will occur in the assembly process of the PCB board, affecting the mechanical stability; the greater the deviation area, the greater the impact on signal transmission and heat dissipation performance. According to the impact analysis and the geometric characteristics of the three-dimensional deviated region, calculate the region deviation impact coefficient. This coefficient is also a numerical value ranging from 0 to 1, indicating the degree of influence of the deviated region on the performance of the PCB board.

[0045] Step S360, based on the circuit function influence coefficient, the area deviation influence coefficient, the flattening weight analysis is carried out, and the flattening priority is constructed. Specifically, according to the importance of the circuit function and the severity of the area deviation, the analytic hierarchy process or expert scoring method and other methods are used to assign weights to the circuit function influence coefficient and the area deviation influence coefficient. For example, if the circuit function is crucial to the performance of the entire system, the weight of the circuit function influence coefficient can be set to be higher. According to the assigned weight, the flattening weight of each three-dimensional deviation area is calculated. The flattening weight can be calculated by weighted summation, that is, flattening weight = circuit function influence coefficient x circuit function weight + area deviation influence coefficient x area deviation weight. According to the size of the flattening weight, the three-dimensional deviation area is sorted, and the flattening priority is determined. The larger the flattening weight, the higher the flattening priority.

[0046] Step S370, according to the flattening priority, the mapping label is performed on the three-dimensional deviation area model or image, and the flattening priority mapping diagram is constructed. Specifically, according to the flattening priority, the three-dimensional deviation area model or image is labeled. Different colors, symbols or labels can be used to represent different flattening priorities. For example, red represents high priority, yellow represents medium priority, and green represents low priority. The labeled three-dimensional deviation area model or image is integrated together to construct the flattening priority mapping diagram.

[0047] In one possible implementation, the key circuit element coordinates and the area outer contour coordinates are spatially mapped to construct a region-circuit connection graph, and step S330 further includes step S331 of performing adjacent sorting based on the area outer contour coordinates, generating a boundary point coordinate sequence for geometric analysis, and extracting geometric feature parameters. Specifically, a distance-based adjacent sorting algorithm is used. For the outer contour coordinate point set of the three-dimensional deviation area, the distance between each point and other points is calculated, and the adjacent points of each point are determined according to the distance from small to large. For example, for point P i , the n closest points to P i are found as its adjacent points, and then these adjacent points are sorted according to certain rules, such as clockwise or counterclockwise direction, to generate a boundary point coordinate sequence.

[0048] The generated boundary point coordinate sequence is subjected to geometric analysis, and geometric feature parameters are extracted, including contour curvature, contour length, contour area, etc. For the contour curvature, the curvature of the curve formed by the adjacent three points in the boundary point coordinate sequence can be calculated; for the contour length, the distance between adjacent points can be accumulated; for the contour area, the polygon area calculation formula can be used.

[0049] Step S332, according to the sequence of boundary point coordinates, the profile coordinates outside the region are read to generate the profile feature parameters. Specifically, according to the sequence of boundary point coordinates, the profile coordinates outside the region are interpolated or fitted to more accurately describe the profile of the outer contour. Linear interpolation, cubic spline interpolation and other methods can be used to interpolate the coordinates between the boundary points to obtain a more dense set of coordinate points, thereby more accurately reflecting the profile of the outer contour. The set of coordinate points after interpolation or fitting is analyzed for profile to generate profile feature parameters, including surface roughness, surface roughness, etc. For surface roughness, the standard deviation of the height difference between adjacent points in the coordinate point set can be calculated; for surface roughness, the height difference between the highest point and the lowest point in the coordinate point set can be calculated.

[0050] Step S333, traverse the three-dimensional profile model to divide the space region and generate a plurality of space grid coding units. Specifically, a uniform grid division method is used to divide the space region of the three-dimensional profile model. First, the size of the grid is determined, then the number of grids is calculated according to the size of the grid and the range of the three-dimensional profile model, and each grid is assigned a unique code. According to the calculated number of grids and the coding rule, a plurality of space grid coding units are generated. Each space grid coding unit corresponds to a specific space region in the three-dimensional profile model.

[0051] Step S334, match the key circuit element coordinates with the plurality of space grid codes, and map the key circuit element coordinates to the plurality of space grid coding units according to the matching result to generate element space coding position. Specifically, for each key circuit element coordinate, according to its coordinate value, the space grid coding unit to which it belongs is determined. The specific method is to divide the value of the key circuit element coordinate by the size of the grid in the corresponding direction respectively, and then take the integer part to obtain the grid number of the coordinate in three directions, so as to determine the space grid coding unit to which it belongs. Map the key circuit element coordinates to the matching space grid coding unit, record the position information of the element in the space grid coding unit, and generate the element space coding position. The element space coding position can be represented as a data structure containing the element coordinates and the grid code to which it belongs.

[0052] Step S335, according to the geometric feature parameters and the topographic feature parameters, performing spatial position mapping analysis on the element space coding position and the region outer contour coordinates, and constructing a region-circuit connection graph. Specifically, the spatial position relationship between the element space coding position and the region outer contour coordinates is analyzed by comprehensively considering the geometric feature parameters and the topographic feature parameters. For example, the distance between the element coordinates and the region outer contour coordinates is calculated, and in combination with parameters such as contour curvature and surface roughness, it is determined whether the element is located in the deviation region or has a close spatial correlation with the deviation region. The graph structure in graph theory is used to represent the correlation relationship between the region and the circuit element. The three-dimensional deviation region and the key circuit element are respectively taken as nodes in the graph, and according to the result of the spatial position mapping analysis, edges are added between the nodes, and the weight of the edge can be determined according to the closeness of the spatial position relationship, so as to construct the region-circuit connection graph.

[0053] In a possible implementation, based on the flattening priority mapping, a dynamic flattening plan is generated, and a flattening path is generated. Step S300 further includes step S380 of retrieving performance constraints of the flattening device and flattening process constraints, and establishing a flattening path optimization target. Specifically, the performance parameters of the device are obtained from the database or configuration file of the device, including maximum moving speed, maximum acceleration, maximum flattening pressure, etc. These parameters reflect the running limitations of the device at the physical level, for example, the maximum moving speed determines the maximum distance that the device can move in a unit of time, and the maximum acceleration limits the speed change rate of the device during start and stop. The relevant specifications and standards of the flattening process are consulted to obtain process constraints, such as flattening temperature range, flattening time interval, flattening frequency limit, etc. These conditions are set to ensure the flattening quality, for example, the flattening temperature range can ensure that the material is flattened at an appropriate temperature to avoid changes in material performance due to excessively high or low temperature.

[0054] The flattening path optimization target is established, the minimum total flattening time is set as the primary optimization target, and the shortest flattening head moving path length is set as the secondary optimization target. A shorter moving path can reduce the energy consumption and mechanical wear of the device, and also improve the flattening efficiency. The flattening quality uniformity requirement is set as a constraint condition to ensure consistent flattening effect in different regions and avoid local over-flattening or under-flattening. At the same time, the device energy consumption constraint and mechanical wear constraint are added to avoid frequent acceleration and deceleration in path planning, so as to reduce energy consumption and mechanical wear.

[0055] Step S390, according to the flattening priority, the flattening priority map is traversed to search for the maximum value, and the path starting point is determined. Specifically, a depth-first search or breadth-first search algorithm is used to traverse the flattening priority map. The depth-first search starts from the starting node, searches as deeply as possible along a path, and stops until a leaf node is reached or a specific condition is met; the breadth-first search starts from the starting node and searches adjacent nodes layer by layer. During the traversal process, the flattening priority value of each node is compared, and the node with the highest priority is recorded as the path starting point. A variable can be used to store the maximum priority value found so far, and the variable is updated during the traversal process.

[0056] Step S3100, according to the path starting point, the nearest neighbor search is performed on the flattening priority map to determine the region access order. Specifically, starting from the path starting point, the Euclidean distance or other distance measurement method is used to calculate the distance between the starting point and the surrounding nodes. The node closest to the starting point is selected as the next access node, and then the node is used as the new starting point to repeat the above process until all nodes are accessed. The nearest neighbor nodes selected each time are recorded in the access order to form the region access order. A list or array can be used to store this order.

[0057] Step S3110, based on the region access order, the flattening priority map is traversed to plan the flattening, and the to-be-flattened trajectory is generated. Specifically, according to the region access order, the dwell time and flattening parameters of the flattening head in each region are determined, such as flattening pressure, flattening time, etc. These parameters are set according to the flattening process constraints and the performance constraints of the equipment. The movement path and dwell time of the flattening head in each region are combined to form the to-be-flattened trajectory. Coordinate points can be used to represent the position of the flattening head, and time parameters can be used to represent the dwell time.

[0058] Step S3120, according to the to-be-flattened trajectory, real-time correction is performed in the flattening direction to construct the flattening path. Specifically, during the flattening process, the position and movement direction of the flattening head are monitored in real time using sensors. If it is found that the actual movement direction of the flattening head deviates from the direction set in the to-be-flattened trajectory, the movement direction of the flattening head is adjusted through the control equipment to return to the correct trajectory. The movement path of the flattening head after real-time correction is recorded to construct the final flattening path. A series of consecutive coordinate points can be used to represent the flattening path.

[0059] Step S400, the flattening path is executed for flattening monitoring, the flatness is verified according to the multi-source monitoring data, the flattening quality parameter is obtained, the flattening path is iteratively updated, and the to-be-processed PCB board processing is adaptively flattened.

[0060] Specifically, the flattening device processes the PCB board according to the generated flattening path, and flattens the three-dimensional deviation area by mechanical pressure, heat treatment and the like. In the flattening process, the sensor is used to monitor the motion state and processing effect of the flattening device in real time, and to obtain multi-source monitoring data. According to the multi-source monitoring data, the flatness of the flattened PCB board is verified, and whether the flattening quality meets the preset standard is evaluated. The flatness verification result is fed back, the flattening path is iteratively updated according to the flattening quality parameter, the flattening process is optimized, and adaptive flattening is realized.

[0061] In a possible implementation, the flattening path is executed for flattening monitoring, the flatness verification is performed according to the multi-source monitoring data, the flattening quality parameter is obtained, and step S400 further includes step S410. The flattening head is controlled to move according to the planned path to monitor the flattening of the PCB board to be processed, and the multi-source monitoring data is obtained. Specifically, the pre-planned flattening path is input into the device through the control system of the flattening device. The control system controls the movement of the flattening head according to the path information, including the movement direction, speed and acceleration and the like, to ensure that the flattening head moves on the PCB board to be processed according to the planned path. In the movement process of the flattening head, the multi-source monitoring system composed of multiple sensors is used to monitor the flattening process in real time. For example, a laser displacement sensor is used to measure the distance between the PCB board surface and the flattening head to obtain the surface height information; a pressure sensor is used to monitor the pressure applied by the flattening head to the PCB board to ensure that the pressure is within a suitable range; and a visual sensor can also be used to capture the image of the PCB board surface for topography analysis. These sensors work simultaneously, and the collected data is transmitted to the data processing unit to form multi-source monitoring data.

[0062] Step S420, interval collection based on the multi-source monitoring data is performed to obtain a plurality of surface topography data. Specifically, the collection interval is set. For example, according to the movement speed of the flattening head and the size of the PCB board, it is determined to collect data once every certain distance or time. When collecting, the information related to the surface topography is extracted from the multi-source monitoring data, such as the distance data measured by the laser displacement sensor and the image data captured by the visual sensor. The collected distance data and image data are processed and analyzed to generate data capable of describing the surface topography of the PCB board. For the distance data, noise interference can be removed by data filtering and fitting to obtain the surface height profile; for the image data, the geometric features and texture information of the surface can be obtained by using image processing algorithms such as edge detection, feature extraction and the like. The processed distance data and image data are combined to form a plurality of surface topography data.

[0063] Step S430, real-time flatness calculation is performed according to the plurality of surface topography data, and a real-time flatness index is set. Specifically, the plurality of surface topography data is processed to calculate the flatness of the PCB surface. Methods that can be used include least squares fitting of a plane, calculation of surface roughness parameters, etc. For example, when using least squares fitting of a plane, a plurality of points in the surface topography data is fitted onto a plane, the distance of each point to the plane is calculated, and then the flatness of the surface is evaluated according to the statistical characteristics, such as the standard deviation, of these distances.

[0064] According to the requirements of the flattening process and the quality standards of the PCB, the real-time flatness index is set. These indexes can include the maximum allowable deviation of flatness, the upper limit of surface roughness, etc. The calculated flatness value is compared with the set index to determine whether the flatness of the current surface meets the requirements.

[0065] Step S440, according to the real-time flatness index, the flatness verification of the multi-source monitoring data is performed, and a flattening verification evaluation result is generated. Specifically, the real-time calculated flatness value is compared and analyzed with the set real-time flatness index. If the flatness value is within the range allowed by the index, it is considered that the flatness verification of the current area is passed; if the flatness value exceeds the index range, it is considered that the verification is not passed, and the position and degree of the out-of-tolerance are recorded. According to the results of the flatness verification, a flattening verification evaluation report is generated, including the number of areas that pass the verification, the position and out-of-tolerance of areas that do not pass the verification, the evaluation conclusion of the overall flatness, etc.

[0066] Step S450, according to the flattening verification evaluation result, flattening calculation is performed to generate surface flatness error and local curling degree. Specifically, according to the out-of-tolerance position and degree recorded in the flattening verification evaluation result, flattening calculation is performed. For the calculation of surface flatness error, three-dimensional coordinate measurement and fitting method can be used to determine the deviation between the actual surface and the ideal plane; for the calculation of local curling degree, the local height change and slope information in the surface topography data can be analyzed to determine the position and degree of curling. The calculated results are sorted and counted to generate specific values of surface flatness error and local curling degree.

[0067] Step S460, surface roughness quality analysis is performed based on the surface flatness error, and a first planarization quality parameter is obtained. Specifically, according to the size and distribution of the surface flatness error, in combination with relevant quality standards and specifications, the surface roughness quality is analyzed. Methods that can be used include calculating surface roughness parameters such as arithmetic average roughness, maximum profile height, etc., and comparing them with standard values. At the same time, the influence of the surface flatness error on the electrical and mechanical properties of the PCB board can also be analyzed, and the surface roughness quality is comprehensively evaluated. According to the results of the surface roughness quality analysis, the first planarization quality parameter is determined. This parameter can be a comprehensive score or a classification index such as pass, fail, excellent, etc., used to reflect the quality of the surface roughness.

[0068] Step S470, planarization residual stress distribution quality analysis is performed based on the local warping degree, and a second planarization quality parameter is obtained. Specifically, the local warping degree is related to the residual stress generated during the planarization process. By establishing a mathematical model between the local warping degree and the residual stress, and using finite element analysis and other methods, the distribution of the residual stress during the planarization process is simulated. According to the simulation results, the influence of the residual stress on the performance of the PCB board is analyzed, such as whether it will cause board deformation, cracking, etc., so as to evaluate the planarization residual stress distribution quality. According to the results of the planarization residual stress distribution quality analysis, the second planarization quality parameter is determined. This parameter is used to reflect the rationality of the residual stress distribution and the degree of influence on the quality of the PCB board, and can also be a comprehensive score or a classification index.

[0069] In one possible implementation, according to the planarization verification evaluation results, the surface flatness error and the local warping degree are generated, and step S450 further includes step S451, traversing the planarization verification evaluation results to extract a plurality of surface planarization points in the PCB board to be processed that pass the verification. Specifically, the planarization verification evaluation results are scanned row by row, column by column, or in a predetermined data structure order. The evaluation results contain information such as the verification status and position coordinates of each measurement point. The verification status of each point is checked, and when a point that passes the verification is found, the relevant information of the point is recorded. These points are the surface planarization points. The coordinate information of the extracted surface planarization points is stored in a data structure such as an array, a list, or a database table.

[0070] Step S452, traverse the flattening verification evaluation results to identify local deformation, and extract multiple local deformation regions. Specifically, a method based on image processing or geometric analysis is used to identify local deformation regions. For example, an edge detection algorithm can be used to detect edge changes in the PCB surface topography image, and regions with large edge mutations exist local deformation; or by calculating the local difference of the height data of the measurement points, when the difference value exceeds the set threshold, it is considered that the region exists local deformation. Once the position of the local deformation is identified, according to the distribution of the deformation points, the boundary of the local deformation region is determined. A clustering algorithm can be used to cluster adjacent deformation points together to form multiple local deformation regions, and the boundary coordinates or included point set of each region are recorded.

[0071] Step S453, calculate the vertical distance between the multiple surface flattening points and the reference plane data to generate deviation data. Specifically, for each surface flattening point, the vertical distance between the point and the reference plane is calculated using the point-to-plane distance formula. The calculated vertical distance between each surface flattening point and the reference plane is stored to form a deviation data set.

[0072] Step S454, calculate the range value of the deviation data as the overall plane error value, and perform local plane partition calculation according to the overall plane error value to generate surface flatness error. Specifically, the range value of the deviation data set refers to the difference between the maximum and minimum values in the data set. By calculating the range value, the overall deviation range of the surface flattening points relative to the reference plane can be determined. According to the overall plane error value, different partition thresholds are set to divide the PCB surface into multiple local plane regions. For example, the range value can be divided into three intervals, corresponding to different flatness level regions. For each local plane region, calculate the average value or standard deviation of the surface flattening point deviation in the region as a statistical quantity, as the surface flatness error indicator of the region. Comprehensive flatness error indicators of each local plane region, generate the flatness error description of the entire PCB surface, which can be a comprehensive score or a regional error report.

[0073] Step S455, curvature calculation is performed based on the plurality of local deformation regions to obtain curvature variation features, and the plurality of local deformation regions are aggregated according to the curvature variation features to generate continuous deformation regions. Specifically, for a point in each local deformation region, a curvature calculation formula in differential geometry is used to calculate the curvature. For example, for a point on a two-dimensional surface, the curvature of the surface can be described by calculating the normal curvature or the principal curvature at the point. In actual applications, an approximate calculation method can be used, such as locally fitting the points in the deformation region, and then calculating the curvature according to the parameters of the fitted surface. The distribution of the curvature in each local deformation region is analyzed, and the variation features of the curvature are extracted, such as the maximum value, the minimum value, the average value, and the rate of change of the curvature, which reflect the bending degree and the change trend of the local deformation region. According to the similarity of the curvature variation features, a clustering algorithm is used to aggregate adjacent local deformation regions together. A similarity threshold is set, and when the similarity of the curvature variation features of two local deformation regions exceeds the threshold, they are merged into a continuous deformation region.

[0074] Step S456, deformation calculation is performed according to the continuous deformation regions to determine the curling angle and the warping height. Specifically, for each continuous deformation region, a deformation calculation model is established. If the deformation region is small and the deformation degree is not large, it can be approximated as a simple geometric shape deformation, such as a triangular deformation or a quadrilateral deformation, and the curling angle and the warping height are calculated using geometric relationships; if the deformation region is large or the deformation is complex, a finite element analysis method can be used for accurate calculation. For the approximate geometric shape deformation region, the curling angle is determined by measuring the angle change of the related edges before and after deformation. For example, for a triangular deformation region, the angle between the two edges before and after deformation is measured, and the change amount is the curling angle. The highest point and the lowest point in the deformation region are determined, and the vertical distance between them is calculated as the warping height. In finite element analysis, the maximum displacement and the minimum displacement can be found by extracting the displacement information of the nodes after deformation, and thus the warping height can be calculated.

[0075] Step S457, comprehensive identification is performed based on the curling angle and the warping height to determine the local curling degree. Specifically, a weighted average or other comprehensive evaluation method is used to determine the local curling degree in combination with the curling angle and the warping height. Different weight coefficients can be set for the curling angle and the warping height according to actual application requirements. For example, if the curling angle is more sensitive, a larger weight can be given to the curling angle; if the warping height is more concerned, a larger weight can be given to the warping height. According to the calculated results, the local curling degree is determined according to the preset curling degree level standard. The level standard can be divided into different levels such as mild curling, moderate curling, and severe curling.

[0076] In a possible implementation, the flattening quality parameter is iteratively updated back to the flattening path for adaptive flattening of the PCB to be processed, and step S400 further includes step S480 of setting a plurality of quality tolerance thresholds, comparing and analyzing the flattening quality parameter with the plurality of quality tolerance thresholds, and generating a flattening quality defect distribution map. Specifically, in the flattening quality evaluation system, a plurality of quality tolerance thresholds of different levels are set in advance according to the application scenarios, performance requirements, and industry standards of the PCB, and the like. For example, for the PCB in an electronic device with high precision requirements, quality tolerance thresholds of different strictness levels such as level one, level two, and level three are set. The level one threshold is the most strict, representing an extremely high flattening quality standard, and is suitable for core circuit boards with extremely high requirements on signal transmission stability and component mounting precision; the level two threshold is relatively loose, and is used for PCBs with general performance requirements; and the level three threshold is the most basic quality requirement, and meets the requirements of some simple circuit boards with low requirements on flattening quality.

[0077] The flattening quality parameter is compared and analyzed with the plurality of quality tolerance thresholds set above, to determine the level of the flattening quality and the gap with each threshold. Based on the comparison and analysis result, a flattening quality defect distribution map is generated. The map is presented in a graphical manner, for example, a two-dimensional or three-dimensional coordinate graph, and different colors or marks represent different levels of quality defect areas.

[0078] Step S490 is performed to determine the traversal order of the flattening path according to the flattening quality defect distribution map, to associate and map the flattening path, and to determine the flattening path parameter to be optimized, which includes a path optimization target. Specifically, according to the generated flattening quality defect distribution map, the traversal order of the flattening path is determined according to certain logical rules. For example, the most serious quality defect area is processed first to ensure the flattening quality of the key part, or the traversal is performed in the order from the edge to the center and from the simple area to the complex area. The determined traversal order is associated and mapped with the original flattening path, and each point or line segment on the flattening path is given new processing priority and order information. On the basis of the association and mapping, the flattening path parameter to be optimized is analyzed and determined, including a path optimization target, for example, adjusting the bending degree of the path to better adapt to the shape of the quality defect area, optimizing the spacing of the path to ensure the uniformity of the flattening, or changing the direction of the path to improve the flattening efficiency, and the like.

[0079] Step S4100, update the flattening path according to the path optimization target to generate a flattening optimization path. Specifically, according to the flattening path parameters to be optimized and the optimization target determined in step S490, perform a substantial update operation on the original flattening path, including re-running the path planning algorithm, using new parameter input, generating a new flattening path through computer-aided design software or a special path planning tool. After the update operation, the final flattening optimization path is obtained.

[0080] Step S4110, construct a virtual environment to simulate and verify the feasibility of the flattening optimization path, and according to the verification result, iteratively correct the flattening optimization path, and develop a flattening strategy for adaptive flattening of the PCB to be processed. Specifically, a virtual environment similar to the actual processing environment is constructed using computer simulation technology. In this virtual environment, the generated flattening optimization path is imported into the corresponding simulation model to simulate the entire process of flattening the PCB to be processed by the flattening device according to the path. Through simulation, various phenomena in the flattening process can be observed, such as the distribution of flattening force, material deformation, flattening time consumption, etc., so as to evaluate the feasibility of the flattening optimization path in actual application. If some problems are found in the simulation verification process, such as excessive flattening force in some areas causing PCB damage, or excessive flattening time affecting production efficiency, etc., the flattening optimization path is iteratively corrected according to these verification results. Iterative correction is a process of continuous optimization and improvement, through multiple adjustments of path parameters and re-simulation verification, gradually eliminating problems in the path, making the flattening optimization path more perfect. After multiple iterations and corrections, the final flattening optimization path is determined, and a flattening strategy is developed based on it. In actual processing, the flattening device performs adaptive flattening of the PCB to be processed according to the developed flattening strategy, dynamically adjusts the flattening parameters according to the real-time quality feedback of the PCB, and ensures that the final flattening effect is of high quality.

[0081] The embodiment of the present application collects surface data of the PCB to be processed to form a topographic data set, establishes a three-dimensional topographic model therefrom, uses the three-dimensional topographic model for three-dimensional deviation identification, finds out three-dimensional deviation regions such as warping and unevenness, maps the three-dimensional deviation regions to integrated circuits for flattening analysis, sets a flattening priority mapping diagram, performs dynamic flattening planning and generates a flattening path according to the flattening priority mapping diagram, performs flattening monitoring when executing the flattening path, verifies the flatness according to multi-source monitoring data, and traces the obtained flattening quality parameters back to the flattening path for iterative updating, thereby realizing adaptive flattening of the PCB to be processed and other technical means, solving the technical problems of insufficient adaptability and precision of existing flattening for PCB processing in integrated circuits, and achieving the technical effect of high-precision adaptive flattening.

[0082] In the foregoing, reference is made to Figure 1The leveling method for PCB processing in integrated circuits according to the embodiment of the present application is described in detail. Next, the leveling system for PCB processing in integrated circuits according to the embodiment of the present application will be described with reference to the accompanying drawings. Figure 2 The leveling system for PCB processing in integrated circuits according to the embodiment of the present application is described.

[0083] The leveling system for PCB processing in integrated circuits according to the embodiment of the present application is used to solve the technical problem of insufficient adaptability and precision of the existing leveling for PCB processing in integrated circuits, and achieves the technical effect of high-precision adaptive leveling. The leveling system for PCB processing in integrated circuits comprises a three-dimensional topography model establishing module 10, a three-dimensional deviation identifying module 20, a dynamic leveling planning module 30, and an adaptive leveling module 40.

[0084] The three-dimensional topography model establishing module 10 is used to collect surface data of a PCB to be processed, obtain a topography data set, and establish a three-dimensional topography model of the PCB to be processed based on the topography data set. The three-dimensional deviation identifying module 20 is used to identify three-dimensional deviations of the PCB to be processed through the three-dimensional topography model, and extract a three-dimensional deviation region, which includes a warping region and an uneven region. The dynamic leveling planning module 30 is used to analyze leveling according to the mapping of the three-dimensional deviation region to an integrated circuit, set a leveling priority mapping graph, perform dynamic leveling planning based on the leveling priority mapping graph, and generate a leveling path. The adaptive leveling module 40 is used to perform leveling monitoring according to the leveling path, verify flatness according to multi-source monitoring data, obtain leveling quality parameters, and iteratively update the leveling path for adaptive leveling of PCB processing.

[0085] The three-dimensional deviation identifying module 20 is further configured as follows: As described above, the three-dimensional deviation identifying module 20 can further comprise a reference plane data setting unit for selecting a plurality of feature points in a four-corner region of the PCB to be processed as reference points, fitting according to the reference points, and setting reference plane data; a deviation value obtaining unit for fitting the vertical distance between the first grid node of the three-dimensional topography model and the reference plane data, and obtaining deviation values of a plurality of nodes; a deviation distribution graph generating unit for associating and storing the deviation values of a plurality of nodes with the coordinate positions of the reference plane data, and generating a deviation distribution graph; and a region identifying unit for identifying regions of the deviation distribution graph, and extracting the three-dimensional deviation region.

[0086] The region identification unit can further include: a judgment identification subunit configured to set positive and negative deviation threshold values, perform judgment identification based on the deviation distribution map and the positive and negative deviation threshold values, and generate a set of potential deviation points; a region growth analysis subunit configured to perform region growth analysis based on the set of potential deviation points, aggregate spatially adjacent potential deviation points, and construct a deviation continuous region; a curvature calculation subunit configured to perform curvature calculation on the deviation continuous region, and determine a warping region according to region curvature; a local roughness calculation subunit configured to perform local roughness calculation on the deviation continuous region, and determine an uneven region according to region roughness; and a region integration subunit configured to integrate the warping region and the uneven region, and construct the three-dimensional deviation region.

[0087] The dynamic planarization planning module 30 can further include: a key element identification unit configured to call an integrated circuit layout map to identify key elements, and obtain key circuit element coordinates; a contour identification unit configured to traverse the three-dimensional deviation region to identify a contour, and extract an out-of-region contour coordinate; a spatial mapping unit configured to perform spatial mapping on the key circuit element coordinates and the out-of-region contour coordinate, and construct a region-circuit connection graph; a circuit function influence analysis unit configured to perform circuit function influence analysis according to the region-circuit connection graph, and obtain a circuit function influence coefficient; a region deviation influence analysis unit configured to perform region deviation influence analysis according to the region-circuit connection graph, and obtain a region deviation influence coefficient; a planarization weight analysis unit configured to perform planarization weight analysis based on the circuit function influence coefficient and the region deviation influence coefficient, and construct a planarization priority; and a mapping annotation unit configured to perform mapping annotation on the three-dimensional deviation region according to the planarization priority, and construct the planarization priority mapping graph.

[0088] The key circuit element coordinates are spatially mapped with the region outer contour coordinates to construct a region-circuit connection graph. The spatial mapping unit can further include: an adjacent ordering subunit for adjacent ordering based on the region outer contour coordinates, generating a boundary point coordinate sequence for geometric analysis, and extracting geometric feature parameters; a topography reading subunit for topography reading of the region outer contour coordinates according to the boundary point coordinate sequence, generating topography feature parameters; a spatial region division subunit for traversing the three-dimensional topography model to perform spatial region division, generating a plurality of spatial grid coding units; an element spatial coding position generation subunit for matching the key circuit element coordinates with the plurality of spatial grid codes, mapping the key circuit element coordinates to the plurality of spatial grid coding units according to the matching result, and generating element spatial coding positions; and a spatial position mapping analysis subunit for spatial position mapping analysis of the element spatial coding positions and the region outer contour coordinates according to the geometric feature parameters and the topography feature parameters, and constructing the region-circuit connection graph.

[0089] The dynamic flattening planning module 30 can further include: a constraint condition calling unit for calling performance constraints and flattening process constraints of a flattening device, and establishing a flattening path optimization target; a maximum value searching unit for maximum value searching of the flattening priority mapping graph according to the flattening priority, and determining a path starting point; a nearest neighbor searching unit for nearest neighbor searching of the flattening priority mapping graph according to the path starting point, and determining a region access order; a flattening planning unit for flattening planning of the flattening priority mapping graph based on the region access order, and generating a to-be-flattened trajectory; and a real-time correction unit for real-time correction according to the to-be-flattened trajectory in a flattening movement direction, and constructing the flattening path.

[0090] The adaptive flattening module 40 is configured as follows: as described above, the flattening path is executed to monitor the flattening, the flatness is verified according to the multi-source monitoring data, the flattening quality parameters are obtained, and the adaptive flattening module 40 can further include: a flattening monitoring unit for executing the flattening path to control the flattening head to move according to the planned path to monitor the flattening of the PCB to be processed, and obtain multi-source monitoring data; an interval acquisition unit for interval acquisition based on the multi-source monitoring data, and obtain multiple surface topography data; a real-time flatness calculation unit for real-time flatness calculation according to the multiple surface topography data, and set a real-time flatness index; a flatness verification unit for flatness verification of the multi-source monitoring data according to the real-time flatness index, and generate a flattening verification evaluation result; a flattening calculation unit for flattening calculation according to the flattening verification evaluation result, and generate surface flatness error and local curling degree; a surface roughness quality analysis unit for surface roughness quality analysis based on the surface flatness error, and obtain a first flattening quality parameter; and a flattening residual stress distribution quality analysis unit for flattening residual stress distribution quality analysis based on the local curling degree, and obtain a second flattening quality parameter.

[0091] In the flattening calculation according to the flattening verification evaluation result, the surface flatness error and the local curling degree are generated, and the flattening calculation unit can further include: a surface flattening point extraction subunit for traversing the flattening verification evaluation result to extract multiple surface flattening points in the PCB to be processed that pass the verification; a local deformation recognition subunit for traversing the flattening verification evaluation result to recognize local deformation, and extract multiple local deformation areas; a vertical distance calculation subunit for calculating the vertical distance between the multiple surface flattening points and the reference plane data to generate deviation amount data; a local plane partition calculation subunit for calculating the range value of the deviation amount data as an overall plane error value, performing local plane partition calculation according to the overall plane error value, and generating surface flatness error; a curvature calculation subunit for curvature calculation based on the multiple local deformation areas, obtaining curvature variation characteristics, and aggregating the multiple local deformation areas according to the curvature variation characteristics to generate continuous deformation areas; a deformation calculation subunit for deformation calculation according to the continuous deformation areas, determining curling angle and warping height; and a comprehensive recognition subunit for comprehensive recognition based on the curling angle and the warping height, and determining the local curling degree.

[0092] The flattening quality parameter is iteratively updated back to the flattening path, and adaptive flattening is performed on the PCB to be processed. The adaptive flattening module 40 can further include: a comparison and analysis unit configured to set a plurality of quality tolerance thresholds, compare and analyze the flattening quality parameter with the plurality of quality tolerance thresholds, and generate a flattening quality defect distribution map; a correlation mapping unit configured to determine a traversal order of the flattening path according to the flattening quality defect distribution map, correlate and map the flattening path, determine a flattening path parameter to be optimized, and the flattening path parameter to be optimized includes a path optimization target; a flattening path updating unit configured to update the flattening path according to the path optimization target, and generate a flattening optimized path; and a feasibility simulation verification unit configured to construct a virtual environment to perform feasibility simulation verification on the flattening optimized path, iteratively correct the flattening optimized path according to a verification result, and develop a flattening strategy to perform adaptive flattening on the PCB to be processed.

[0093] The flattening system for PCB processing in integrated circuits provided in the embodiments of the present application can perform the flattening method for PCB processing in integrated circuits provided in any of the embodiments of the present application, and has the corresponding function modules and beneficial effects of the execution method.

[0094] Although the present application makes various references to certain modules in the system according to the embodiments of the present application, however, any number of different modules can be used and run on the user terminal and / or server, and the various units and modules are only divided according to the functional logic, but are not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific names of the functional units are only for easy mutual differentiation, and do not limit the protection scope of the present application.

[0095] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application. In some cases, the actions or steps described in the present application can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are possible or can be advantageous.

Claims

1. A planarization method for PCB board processing in an integrated circuit, characterized by, The method comprises: Collecting surface data of the PCB to be processed to obtain a topographic data set, and establishing a three-dimensional topographic model of the PCB to be processed based on the topographic data set; Performing three-dimensional deviation identification on the PCB to be processed through the three-dimensional topographic model, extracting a three-dimensional deviation region, and the three-dimensional deviation region including a warping region and an uneven region; Performing flattening analysis on the integrated circuit according to the mapping of the three-dimensional deviation region, setting a flattening priority mapping graph, performing dynamic flattening planning based on the flattening priority mapping graph, and generating a flattening path; Performing flattening monitoring according to the flattening path, verifying the flatness according to multi-source monitoring data, obtaining flattening quality parameters, and iteratively updating the flattening path to perform adaptive flattening on the PCB to be processed; According to the three-dimensional deviation region mapping to the integrated circuit for flattening analysis, setting a flattening priority mapping graph, performing dynamic flattening planning based on the flattening priority mapping graph, and generating a flattening path, comprising: Calling an integrated circuit layout map to identify key components and obtain key circuit component coordinates; Iterating through the three-dimensional deviation region to identify the contour and extract the region contour coordinates; Spatially mapping the key circuit component coordinates and the region contour coordinates to construct a region-circuit connection graph; Performing circuit function influence analysis according to the region-circuit connection graph to obtain a circuit function influence coefficient; Performing region deviation influence analysis according to the region-circuit connection graph to obtain a region deviation influence coefficient; Performing flattening weight analysis based on the circuit function influence coefficient and the region deviation influence coefficient to construct a flattening priority; Mapping and labeling according to the flattening priority back to the three-dimensional deviation region to construct the flattening priority mapping graph; According to the flattening path, the flattening head moves according to the planning path to monitor the flattening of the PCB to be processed, and multi-source monitoring data is obtained; Based on the multi-source monitoring data, multiple surface topography data are obtained by interval collection; According to the multiple surface topography data, real-time flatness is calculated, and a real-time flatness index is set; According to the real-time flatness index, the multi-source monitoring data is verified for flatness, and a flattening verification evaluation result is generated; According to the flattening verification evaluation result, surface flatness error and local curling degree are calculated; Based on the surface flatness error, surface roughness quality analysis is performed to obtain a first flattening quality parameter; Based on the local curling degree, flattening residual stress distribution quality analysis is performed to obtain a second flattening quality parameter; According to the flattening quality parameters, the flattening path is iteratively updated, and adaptive flattening is performed on the PCB to be processed, comprising: Setting multi-level quality tolerance thresholds, comparing and analyzing the flattening quality parameters with the multi-level quality tolerance thresholds, and generating a flattening quality defect distribution map; ​ The traversal order of the flattening path is associated with the flattening quality defect distribution map, and parameters of the flattening path to be optimized are determined, wherein the parameters of the flattening path to be optimized include a path optimization target; The flattening path is updated according to the path optimization target, and a flattening optimized path is generated; A virtual environment is constructed to perform feasibility simulation verification on the flattening optimized path, and the flattening optimized path is iteratively corrected according to a verification result, and a flattening strategy is formulated to perform adaptive flattening on a PCB to be processed.

2. The planarization method for PCB processing in an integrated circuit according to claim 1, wherein, Three-dimensional deviation identification is performed on the PCB to be processed by using the three-dimensional topographic model, and a three-dimensional deviation region is extracted, and the method comprises the following steps: A plurality of feature points in a four-corner region of the PCB to be processed are selected as reference points, the reference points are fitted, and reference plane data is set; The vertical distance between the first grid node of the three-dimensional topographic model and the reference plane data is fitted, and the deviation degree values of a plurality of nodes are obtained; The deviation degree values of the plurality of nodes are associated with the coordinate positions of the reference plane data and are stored, and a deviation degree distribution map is generated; The deviation degree distribution map is subjected to region identification, and the three-dimensional deviation region is extracted.

3. The planarization method for PCB processing in an integrated circuit according to claim 2, wherein, The deviation degree distribution map is subjected to region identification, and the three-dimensional deviation region is extracted, and the method comprises the following steps: A positive and negative deviation degree threshold is set, the deviation degree distribution map is combined with the positive and negative deviation degree threshold to perform judgment and identification, and a set of potential deviation points is generated; Region growing analysis is performed based on the set of potential deviation points, and adjacent potential deviation points in a spatial position are aggregated, and a deviation continuous region is constructed; Curvature calculation is performed on the deviation continuous region, and a warping region is determined according to the region curvature; Local roughness calculation is performed on the deviation continuous region, and an uneven region is determined according to the region roughness; The warping region and the uneven region are integrated, and the three-dimensional deviation region is constructed.

4. The planarization method for PCB processing in an integrated circuit according to claim 1, wherein, The key circuit element coordinates and the region outer contour coordinates are subjected to spatial mapping, and a region-circuit connection graph is constructed, and the method comprises the following steps: Adjacent sorting is performed based on the region outer contour coordinates, a boundary point coordinate sequence is generated, geometric analysis is performed, and geometric feature parameters are extracted; Topographic reading is performed on the region outer contour coordinates according to the boundary point coordinate sequence, and topographic feature parameters are generated; Spatial region division is performed on the three-dimensional topographic model, and a plurality of spatial grid coding units are generated; The key circuit element coordinates are matched with the plurality of spatial grid codes, the key circuit element coordinates are mapped to the plurality of spatial grid coding units according to a matching result, and element spatial coding positions are generated; Spatial position mapping analysis is performed on the element spatial coding positions and the region outer contour coordinates according to the geometric feature parameters and the topographic feature parameters, and the region-circuit connection graph is constructed.

5. The planarization method for PCB processing in an integrated circuit according to claim 1, wherein, Dynamic flattening planning is performed based on the flattening priority mapping graph, and a flattening path is generated, and the method comprises the following steps: Performance constraint conditions and flattening process constraint conditions of a flattening device are called, and a flattening path optimization target is established; The flattening priority mapping graph is traversed according to the flattening priority, and a maximum value is searched, and a path starting point is determined; A nearest neighbor search is performed on the flattening priority map according to the path starting point to determine a region access order; A flattening plan is generated based on the region access order by traversing the flattening priority map to generate a flattening trajectory; The flattening trajectory is corrected in real time according to the flattening movement direction to construct the flattening path.

6. The planarization method for PCB processing in an integrated circuit according to claim 2, wherein, According to the flattening verification evaluation result, a surface flatness error and a local curling degree are generated, and the method comprises: A plurality of surface flattening points that pass the verification in the PCB to be processed are extracted by traversing the flattening verification evaluation result; Local deformation areas are identified by traversing the flattening verification evaluation result, and a plurality of local deformation areas are extracted; A perpendicular distance between the plurality of surface flattening points and the reference plane data is calculated to generate deviation data; A range value of the deviation data is calculated as a whole plane error value, and a local plane partition calculation is performed according to the whole plane error value to generate a surface flatness error; Based on the plurality of local deformation areas, a curvature calculation is performed to obtain a curvature change characteristic, and the plurality of local deformation areas are aggregated according to the curvature change characteristic to generate a continuous deformation area; According to the continuous deformation area, a deformation calculation is performed to determine a curling angle and a warping height; Based on the curling angle and the warping height, a comprehensive identification is performed to determine the local curling degree.

7. A planarization system for PCB processing in integrated circuits, characterized by The system is used to implement the flattening method for PCB processing in an integrated circuit according to any one of claims 1-6, and the system comprises: A three-dimensional topographic model establishment module is configured to collect surface data of a PCB to be processed to obtain a topographic data set, and establish a three-dimensional topographic model of the PCB to be processed based on the topographic data set; A three-dimensional deviation identification module is configured to perform three-dimensional deviation identification on the PCB to be processed through the three-dimensional topographic model, and extract a three-dimensional deviation area, wherein the three-dimensional deviation area includes a warping area and an uneven area; A dynamic flattening planning module is configured to perform flattening analysis on the three-dimensional deviation area mapped to an integrated circuit, set a flattening priority map, and perform dynamic flattening planning based on the flattening priority map to generate a flattening path; An adaptive flattening module is configured to perform flattening monitoring according to the flattening path, perform flatness verification according to multi-source monitoring data, obtain flattening quality parameter backtracking, and iteratively update the flattening path to perform adaptive flattening on the PCB to be processed.

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