Method for controlling warping of semiconductor test printed circuit board

Abstract

The invention relates to the technical field of printed circuit manufacturing, and discloses a semiconductor test printed circuit board warping control method, which comprises the following steps of: firstly, establishing a symmetric stress substrate through inner layer residual copper rate control and symmetric lamination; then, the plate is placed in the middle layer during pressing, and a uniform heat transfer path is constructed through the teflon base plates arranged up and down; and finally, long-time cold pressing is performed after hot pressing to neutralize internal stress, through the synergistic process combination, warping control of the super-multilayer thick plate is converted from dependence on later physical correction into the technological process that high flatness can be achieved in an endogenous mode in the pressing and curing stage, and the technological process is simplified. Therefore, interlayer stress generated by accumulation due to material thermal expansion difference and uneven thermal field is inhibited, and a yield-controllable engineering path is provided for reliable manufacturing of high-density and high-thickness semiconductor test boards.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor test printed circuit board warpage control method, belonging to the technical field of printed circuit manufacturing. BACKGROUND

[0002] At present, the production of multilayer boards generally adopts a vacuum hot pressing process to combine the inner layer core board and prepreg to form an overall structure. This process usually combines symmetric layer design and graphic residual copper rate balancing means to control the flatness of the finished board. With the continuous improvement of the signal routing capability requirements of semiconductor test equipment on circuit boards, the number of layers and the thickness of the finished product of the ATE (automatic test equipment) test board are increasing. In this case, the inherent coefficient of thermal expansion difference between the copper foil and the prepreg of the base material that constitutes the board, and the physical effects generated by it, are accumulated with the number of layers, resulting in total interlayer stress generated during the pressing process, which exceeds the range that can be controlled by conventional process means.

[0003] For such thick boards, adjusting the heating curve or pressure parameters of the pressing equipment cannot solve the temperature gradient that exists when heat is transferred from the outside to the inside of the board. The temperature rise process of the core area of the board and the surface layer is inconsistent, which can cause uneven resin curing, and further cause interlayer stress to solidify and form warping in the board. Specifically, the prior art mainly has the following deficiencies: 1. During the pressing process, the physical deformation of the materials in the board caused by the different thermal expansion coefficients cannot be synchronized, and with the increase in the number of layers, the interlayer stress accumulated by this asynchronization exceeds the adjustment range of conventional process control means; 2. The way of transferring heat energy from the pressing steel plate to the board is relatively direct, and there is no effective buffering and homogenization treatment before the heat energy reaches the surface of the board, resulting in temperature differences in the thickness direction of the board, which is a direct cause of inducing and solidifying interlayer stress. Therefore, how to regulate the heat transferred to the board during the pressing process to form a uniform heat distribution, and thereby inhibit the generation and accumulation of interlayer stress, has become a technical problem to be solved by the present application. SUMMARY

[0004] The present application provides a semiconductor test printed circuit board warpage control method, which mainly aims to solve the problem of how to build a uniform and controllable heat curing environment to inhibit the interlayer stress accumulated due to the difference in material thermal expansion and uneven heat field during the pressing process of ultra-multilayer thick boards.

[0005] To achieve the above-mentioned purpose, the present application provides a semiconductor test printed circuit board warpage control method, which is applied to a semiconductor test printed circuit board with a number of layers greater than or equal to twenty and a finished product thickness greater than or equal to 6 millimeters, and comprises: Step one, establishing symmetric stress base, designing the pattern of each inner core board of the semiconductor test printed circuit board so that the copper residual rate difference of the two sides of the same inner core board is less than or equal to 10%, and based on this, the inner core board and the prepreg are symmetrically distributed with respect to the intermediate layer when laminating; Step two, constructing uniform heat transfer path, placing the semiconductor test printed circuit board in the middle layer when pressing the plate, and setting a Teflon pad with a thickness of 3 mm on the upper and lower parts of the semiconductor test printed circuit board, the plane size of the Teflon pad is larger than the semiconductor test printed circuit board and ensures that the semiconductor test printed circuit board is located within its orthographic projection; Step three, performing stress neutralization timing, after completing the hot pressing, performing a cold pressing step with a duration of 60 to 120 minutes.

[0006] Preferably, in step two, a PIN-LAM metal plate with a thickness of 10 mm and a steel plate are further provided outside the Teflon pad, and the PIN-LAM metal plate, the steel plate and the kraft paper together constitute a multi-stage heat conduction buffer medium.

[0007] Preferably, the plane size of the Teflon pad satisfies the following relationship: mm, wherein, is the width of the Teflon pad in any direction, is the width of the semiconductor test printed circuit board in the same direction.

[0008] Preferably, the pattern design in step one includes laying copper dots in a cross manner in the process edge and the pattern open area of the inner core board.

[0009] Preferably, when pressing the plate, the specific stacking order of the semiconductor test printed circuit board, the Teflon pad, the PIN-LAM metal plate, the steel plate and the kraft paper is: taking a PIN-LAM metal plate as the bottom plate, on which is sequentially arranged the combination of kraft paper and steel plate and the Teflon pad, the semiconductor test printed circuit board is located in the middle layer of all the stacked materials, and the remaining plates and pads are stacked in a mirror-symmetric manner above the semiconductor test printed circuit board, and another PIN-LAM metal plate is taken as the cover plate.

[0010] Preferably, in step one, the cutting direction and the weft direction of the prepreg are consistent with the cutting direction and the weft direction of the inner core board.

[0011] Preferably, the method further comprises a copper-tin electroplating step after completing step three, and the copper-tin electroplating step adopts a preset small current value and a long time manufacturing method.

[0012] Preferably, the method further comprises a solder mask step after completing step three, and the process parameters of the solder mask step are controlled so that the height difference of the formed solder mask layer at any position is within 50 microns.

[0013] Preferably, before step one, the method further comprises a baking step for the inner core board, the baking step is set at a temperature of 150 degrees Celsius and a duration of 4 hours.

[0014] Preferably, the method further comprises a step of brown processing the inner core board after the etching step, the brown processing step is set at a conveying speed of 2.0 meters per minute.

[0015] Compared with the prior art, the present application has the following beneficial effects: 1. By pre-laying copper dots in the core board pattern empty area and maintaining the symmetry of the laminated structure, a relatively balanced physical substrate of internal stress is constructed from the source of material distribution before the circuit board enters the hot pressing process, which provides a stable premise for the uniform application and transmission of the thermal field in the subsequent pressing process, avoiding the generation of localized stress concentration points when heated due to the inherent differences in residual copper rate or structural asymmetry of the board.

[0016] 2. The method places the circuit board to be pressed in a specific hierarchical combination composed of Teflon pad steel plate and kraft paper, so that the heat transmitted by the external pressing platform does not directly act on the circuit board, but first passes through the regulation and conduction of the combination structure. The alternating arrangement of Teflon pad and steel plate forms a multi-level heat conduction buffer medium, which converts concentrated and rapid external heat flow into a gentle heat field, which is finally applied to the upper and lower surfaces of the circuit board through kraft paper. This heat transfer method changes the heating curve of the core material and prepreg during the curing process, allowing the board to expand and cure at a synchronized rate in the Z-axis direction, thereby suppressing the interlayer stress accumulated due to the difference in thermal expansion coefficient of each material.

[0017] 3. The design and pressing process work together to make the warping control of ultra-multilayer thick boards change from relying on post-processing correction or complex parameter compensation to a stable process flow that can achieve flatness during the pressing and curing stage. Since the board has high flatness after the core process, the machining reference consistency of subsequent processes such as drilling, plating, and pattern transfer is guaranteed, and the connection between processes is smoother, reducing the uncertainty of the impact of substrate deformation on subsequent processing accuracy. This increases the tolerance of the entire manufacturing process for board thickness, number of layers, and pattern complexity, providing a feasible engineering path for reliable manufacturing of high-density, high-thickness semiconductor test boards. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The figure is a schematic diagram of the laminated structure of the symmetric stress substrate of the present application. Figure 2 The figure is a schematic diagram of the cross-section of the symmetric laminated structure of the multi-layer board of the present application. Figure 3 Effect curve chart of the cold-press stress neutralization process of the present application; Figure 4 Overall process flow chart of the warpage control method of the present application. DETAILED DESCRIPTION

[0019] To make the technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described in detail below. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0020] The present application provides a semiconductor test printed circuit board warpage control method, which is applied to a printed circuit board with a number of layers greater than or equal to twenty and a finished product thickness greater than or equal to 6 mm, mainly including the following steps: establishing a symmetric stress base through inner layer residual copper rate control and symmetric lamination; constructing a uniform heat transfer path by using an auxiliary pad during pressing; and performing long-time cold pressing after hot pressing to neutralize internal stress, through the combination of the foregoing steps, the warpage deformation of the printed circuit board is controlled within a preset value; in the manufacture of the printed circuit board, due to the different thermal expansion coefficients of materials such as substrates, copper foils, and prepregs, the cumulative interlayer stress increases with the increase of the number of layers and the thickness, in order to suppress the formation of unbalanced stress, the first step of the method is to establish a symmetric stress base, this step adjusts the circuit pattern of each inner layer core plate during the graphic design stage, and copper dots are laid in a cross manner in the process edge and graphic empty area to compensate for the copper surface loss caused by uneven circuit patterns, the adjustment target is to make the residual copper rate difference of the two sides of the same inner layer core plate less than or equal to 10%; for example, the A-side circuit copper coverage of an inner layer core plate is 52%, the initial copper coverage of the B-side is 38%, the difference is 14%, then an array of copper dots is laid in the graphic empty area of the B-side until the total copper coverage of the B-side is increased to more than 43%, so that the residual copper rate difference of the two sides is less than or equal to 10%, in the pre-lamination operation, all inner layer core plates and prepregs are physically symmetrically distributed relative to the middle layer of the lamination structure, and the cutting direction and the weft direction of all prepregs are consistent with the cutting direction and the weft direction of the inner layer core plate, so that the board stack to be pressed has symmetry in material distribution and structure, which provides a homogenization basis for uniform heat application in the subsequent pressing process.

[0021] In view of the temperature gradient formed inside the thick plate by direct hot pressing, which causes uneven resin curing and curing stress, the next step of the method is to build a uniform heat transfer path. When pressing the plate, the printed circuit board with the previously established symmetric stress substrate is placed in the middle layer of the entire pressing stack, and a Teflon pad with a thickness of 3 mm is placed immediately above and below it. The Teflon pad serves as a heat buffer and homogenization medium, which can convert the concentrated heat flow from the external heating steel plate into a gentle and homogeneous heat field acting on the surface of the circuit board. To ensure complete coverage of the heat field, the planar size of the Teflon pad in any direction is greater than the corresponding size of the circuit board, and satisfies the relationship mm, where, is the width of the Teflon pad in any direction, is the width of the printed circuit board in the same direction. This size setting ensures that the edge area of the circuit board is also completely placed in the uniform heat field constructed by the pad; outside the Teflon pad, further PIN-LAM metal plates, steel plates, and kraft paper with a thickness of 10 mm are arranged to form a multi-level heat conduction buffer structure. The specific stacking order is as follows: a PIN-LAM metal plate as the bottom plate, followed by kraft paper, steel plate, kraft paper, steel plate, Teflon pad, steel plate, kraft paper, steel plate, and then the printed circuit board in the middle. The remaining boards and pads are stacked in a mirror-symmetric manner above the circuit board, and another PIN-LAM metal plate is used as the cover plate. The external heat is conducted and regulated by the multi-layer medium before reaching the circuit board, allowing the entire plate to expand and cure at a synchronized rate in the thickness direction, thereby suppressing the accumulation of interlayer stress.

[0022] To release the residual stress generated in the high-temperature curing and cooling process, the subsequent step of the method is to perform a stress neutralization timing. After the hot pressing process is completed, the laminated structure is executed without removing the pressure. A cold pressing step is performed for a duration of 60 minutes to 120 minutes. In a specific operation, the time is set to 90 minutes. The long-term slow cooling process provides time for the relaxation of the internal polymer chains of the board, allowing the internal stress accumulated at high temperature to be released, and stabilizing the shape of the board in a flat state. After this step is completed, the warpage of the board can be less than 0.1%, providing a flat processing reference for subsequent processes. Based on this reference, the subsequent electroplating copper and tin step can use a small current and long time production method to obtain a uniform plating layer. The parameters of the solder mask step can also be controlled so that the height difference of the solder mask layer formed at any position is within 50 microns, facilitating reliable contact of the final automatic test equipment probe. In addition, before executing the above process, a pre-treatment step can also be included, such as baking all the inner core boards at a temperature of 150 degrees Celsius for 4 hours to remove moisture and release part of the stress. After the inner layer pattern etching, the core board is subjected to a brown oxidation treatment, and the conveying speed is set to 2.0 meters per minute to form a uniform oxidation layer on the copper surface, enhancing its bonding force with the prepreg resin.

[0023] Embodiment 1: This embodiment is the application of the foregoing technical solution in a specific scenario, which involves the manufacturing of a 26-layer automatic test equipment (ATE) board. The finished board is 6.45 mm thick, the pressed board is 6.216 mm thick, the circuit pattern distribution of multiple core boards inside the board is uneven, and the finished product warpage is required to be less than 0.1%. When using the conventional pressing process to process this structure, the finished product warpage is more than 0.3%, and problems such as drilling position deviation and substrate exposure after grinding occur in subsequent processes, resulting in low finished product yield. For this 26-layer ATE board, first, the step of establishing a symmetric stress base is performed to compensate for the residual copper rate on both sides of the 6 inner layer core boards, and copper dots are laid in the pattern open area. The residual copper rate difference on both sides of these core boards is reduced from the initial maximum of 18% to within 8%, meeting the control requirement of less than 10%. Subsequently, all the pre-processed inner layer core boards and prepreg are stacked according to the principle of symmetric distribution relative to the middle layer to obtain the board stack to be pressed. This pre-constructed symmetric stress base provides a physical basis for stress homogenization in the subsequent heat treatment process. Without this step, the inherent unbalanced expansion moment due to uneven material distribution inside the board will still cause deformation when heated. Then, a uniform heat transfer path is constructed during the pressing of the board stack, and the ATE board is placed in the middle layer of a multi-stage heat conduction buffer medium composed of PIN-LAM metal plates, steel plates, kraft paper, and 3 mm thick Teflon pads. When the pressing machine is heated, the external heat is conducted and buffered by the steel plate and Teflon pad, the heating rate is slowed down, and is uniformly applied to the upper and lower surfaces of the ATE board. The uniform heat transfer path acts on the pre-constructed symmetric stress base, the former ensures the uniformity of the external input heat field, and the latter ensures the consistency of the board's response to the heat field. The combination of the two changes the process of generating and accumulating interlayer stress due to the coupling of uneven heat field and asymmetric structure in the conventional process.

[0024] After hot pressing is completed, the stress neutralization sequence is performed, and the entire stack is subjected to a 90-minute cold pressing process while maintaining the pressure. The long-term slow cooling provides time for the polymer chains inside the board to relax, releasing the residual stress formed during the hot pressing process, rather than fixing it in the board during rapid cooling. This method manages the thermodynamic environment and material structure symmetry throughout the entire pressing process, allowing the board to undergo significant warpage deformation during the shaping and curing stages. After the batch of 26-layer ATE boards completes all manufacturing processes, including small current long-time copper and tin plating and solder mask process with a height difference controlled within 50 microns, the finished product warpage is detected, and the result is 0.06%, which is lower than the required index of 0.1%. No quality problems caused by board deformation occur in subsequent processes.

[0025] Example 2: To verify the effect of each step in the method of the present application on warpage control, and the effectiveness of the specific process parameter range, a comparative test was conducted in this example, with the test object being a batch of 28-layer printed circuit boards, with a finished product thickness of 7.0 mm, a size of 400 mm x 500 mm, and containing an asymmetric large-area copper foil layer in the board. The test equipment included a standard vacuum pressing machine and a three-coordinate measuring instrument with a measurement accuracy of ±5 microns, used to measure the warpage of each sample board after the pressing process was completed. The warpage was expressed as the percentage of the maximum deformation of the board to the diagonal length of the board. Five sample groups were set up in this test, namely control group A, test group B, test group C, sample group D of the present application, and control group E. Control group A used the conventional pressing process, i.e. the inner core board was not compensated for the residual copper rate, and the iron fluoride rubber pad was not used when the pressing plate was arranged, and the cold pressing time after hot pressing was 15 minutes. Test group B introduced the step of establishing a symmetric stress base on the basis of control group A, i.e. the residual copper rate of the inner core board was compensated to make the difference between the two sides less than 10%. Test group C further introduced the step of constructing a uniform heat transfer path on the basis of test group B, i.e. a multi-stage heat conduction buffer medium containing a 3 mm thick iron fluoride rubber pad was used when the pressing plate was arranged, and the cold pressing time was still 15 minutes. Sample group D of the present application used the complete method claimed in the present application, including the steps of establishing a symmetric stress base, constructing a uniform heat transfer path, and performing a 90-minute stress neutralization timing. The process of control group E was basically the same as that of sample group D of the present application, but the cold pressing time in the stress neutralization timing was set to 30 minutes, which was shorter than the lower limit of 60 minutes required by the present application. The warpage data of the boards in each group after the pressing process was completed is shown in Table 1.

[0026] Table 1: Comparison of warpage data after pressing of each sample group.

[0027]

[0028] The test data show that the average warpage of the control group A is 0.35%; compared with the control group A, the average warpage of the test group B is reduced to 0.24%, indicating that the step of establishing a symmetric stress base reduces the warpage of the plate; compared with the test group B, the average warpage of the test group C is further reduced to 0.13%, indicating that the increase of the uniform heat transfer path enhances the warpage control effect; the average warpage of the sample group D of the application is 0.07%, which is further reduced compared with the test group C, indicating that the long-term stress neutralization timing has a significant effect on controlling the warpage within 0.1%; the average warpage of the control group E is 0.18%, which is higher than that of the sample group D of the application, indicating that the 30-minute cold pressing time is insufficient to neutralize the internal stress, and the data show that by combining the three steps of establishing a symmetric stress base, constructing a uniform heat transfer path and performing a long-term stress neutralization timing, and setting the process parameters within the range, the warpage of the 28-layer plate can be controlled within 0.1%.

[0029] To further verify the irreplaceability of the specific technical feature that the cold pressing step is performed without unloading the pressure in the stress neutralization timing of the application for finally achieving high flatness, whether other conventional stress release technologies that the person skilled in the art can adopt such as post-drawing baking can achieve the same technical effect, the following Comparative Example 1 is specially added.

[0030] Comparative Example 1: This comparative example aims to compare the sample group D in Example 2 of the application with a scheme adopting a conventional post-baking process for stress release; except for the stress release step, the test object, equipment, previous process steps and environmental conditions adopted by the comparative example are completely consistent with the sample group D in Example 2 of the application, specifically, the test object is also a 28-layer printed circuit board with a finished thickness of 7.0 millimeters and a size of 400 millimeters x 500 millimeters; the steps of establishing a symmetric stress base and constructing a uniform heat transfer path are also performed; after completing the hot pressing process, the comparative example does not perform the 90-minute cold pressing step under pressure as described in the sample group D of the application, but takes the laminated structure out of the pressing machine, and after naturally cooling at room temperature, places it in an industrial oven to perform a conventional baking program in the industry for relaxing stress, the specific parameters are: temperature 145±5 degrees Celsius, duration 120 minutes; after completing the baking and cooling process, the plate warpage of the sample group is measured by using the same measuring equipment and method as in Example 2; at the same time, in order to evaluate its real impact on the subsequent process, 50 finished plates are randomly selected for surface mount technology (SMT) simulation production test, and the tin paste printing deviation rate caused by substrate deformation is recorded, and the test results are shown in Table 2.

[0031] Table 2: Comparison table of key indicators of the sample group D of the application and Comparative Example 1.

[0032]

[0033] The test results show that the average warpage of the comparative example 1 using the conventional demolding and baking process is 0.53%, which is worse than the inventive example D (warpage 0.07%) using the method of the present application (warpage 0.07%), and fails to achieve the high precision control target of less than 0.1%, although it is worse than the test group C (warpage 0.13%) without stress optimization; the reason is that although the baking after demolding can make the high molecular chain inside the plate obtain energy for relaxation, the anisotropic material shrinkage and internal stress will be redistributed and freely released when cooling without external pressure constraint, resulting in uncontrollable secondary deformation of the plate; in the SMT simulation production, the 7.6% printing offset rate also proves that the warpage has a substantial impact on the yield of subsequent high-precision processing; this comparative example proves from another angle that the stress neutralization timing of not removing the pressure after hot pressing and performing cold pressing for 60 to 120 minutes is the key and indispensable technical link to suppress the warpage deformation of the super multi-layer thick plate.

[0034] Example 3: This example combines Figures 1 to 4 a semiconductor test printed circuit board warpage control method, as shown in Figure 1 , which shows the stacking mode of PP and core plate alternately arranged symmetrically above and below based on a core plate of an intermediate layer; as shown in Figure 2 , the structure takes the copper foil of the top layer and the bottom layer as the boundary, contains multiple core plate layers from L2 to L25 inside, and the PP arch surface is used as the prepreg for isolation and adhesion between each core plate, and all levels are symmetrically distributed relative to the physical center; as shown in Figure 3 , the abscissa represents the cold pressing time from 0 minutes to 150 minutes, the left ordinate represents the warpage from 0.00% to 0.40%, and the right ordinate represents the stress release rate from 0% to 100%, the solid line of the warpage change curve shows that as the cold pressing time increases, the warpage decreases and stabilizes below 0.1% after 60 minutes, and the stress release rate curve dotted line correspondingly stabilizes and rises, indicating that the internal stress is released; as shown in Figure 4 , the process starts with the inner core plate and prepreg in the raw material inventory, first enters the symmetric stress base establishment link and performs symmetric lamination to form the to-be-pressed plate stack, then in the pressing and uniform curing stage, the uniform heat transfer path configuration is performed according to the process specification and buffer medium, the cured plate is output and becomes the to-be-cold-pressed plate, and finally the high flatness finished product is obtained by performing the stress neutralization step and sent to the subsequent process workshop.

[0035] Example 4: This embodiment discloses a procedure for determining the specific process parameters in the method of the invention, when processing a brand new 32-layer printed circuit board with a finished thickness of 7.2 mm, the specific parameters in the lamination process need to be determined, the design of the board includes multiple asymmetric power layers and signal layers; in order to establish the symmetric stress base of the 32-layer board, one of the asymmetric inner core boards L15 / L16 needs to be compensated for residual copper rate, the initial state of the procedure is to input the circuit pattern data of L15 and L16 into the computer-aided manufacturing software with area calculation function; the first step of the procedure is quantification, the software measures that the copper coverage rate of L15 is 55.2%, the copper coverage rate of L16 is 38.5%, and the difference between the two is 16.7%, which is greater than the control threshold of 10%; the next step of the procedure is to perform compensation, according to the difference calculation, it is necessary to increase the copper foil corresponding to more than 6.7% of the total area in L16 layer, for this purpose, in the blank area of L16 layer, a copper dot array with a diameter of 0.3 mm is laid at an interval of 0.5 mm, after the operation is completed, quantification is performed again, and the copper coverage rate of L16 is measured to be 46.1%, at this time, the residual copper rate difference between the two layers is 9.1%, which is within the control range of 10%, through the steps of quantification, operation, and re-quantification, the equalization of residual copper rate is transformed into a repeatable process.

[0036] In the configuration of building a uniform heat transfer path, the thickness of the iron fluoride pad used affects the heat buffering effect and heat transfer efficiency, if the thickness of the pad is 1 mm, the thermal resistance is insufficient, which will cause the external heat to be transferred to the surface of the board too quickly, weakening the effect of heat field homogenization; if the thickness of the pad is 5 mm, the thermal resistance is too large, which will prolong the time required for the stack to reach the target curing temperature, which may cause the resin in the core area of the board to not be fully cured within the standard lamination cycle, for a board with a finished thickness of 6 mm or more, a 3 mm thick iron fluoride pad is selected to balance the heat buffering and transfer efficiency, which can slow down the heating rate and enable the core area of the board to reach the curing temperature within the standard lamination cycle, through the above procedure, specific process execution parameters can be determined for new board designs, thereby stably applying the method of the invention to the production of different products.

[0037] Example 5: When applying the method of the invention to the production of a 30-layer ATE board using a new type of high glass transition temperature substrate, a pre-lamination parameter calibration procedure needs to be performed to determine the process parameters suitable for the thermodynamic properties of the material, the procedure uses a test board identical in structure to the production board, and embeds thermocouples at the surface, quarter depth, and core positions of the test board, the test board is placed in a complete lamination stack containing an iron fluoride pad for test lamination, by monitoring and adjusting the temperature curve and pressure parameters of the laminator, until the thermocouple data shows that the temperature difference between the core and surface of the board is less than 1 and the time the core region remains above the glass transition temperature is in compliance with the resin cure requirements of the material supplier.

[0038] The specific set of temperature ramp and pressure parameters obtained through the above calibration procedure, which enables the uniform thermal path of the present invention to homogenize the thermal field and ensure that the subsequent stress neutralization sequence acts on a board that is already uniformly and fully cured, is recorded and set as the standard operating parameters for this model 30 layer ATE board on this lamination equipment, and this procedure enables the warpage control method of the present invention to be reproducible in terms of process results under different material systems and production equipment conditions.

[0039] Example 6: In the production of a 36 layer, 8.0 mm thick server backplane using a new high glass transition temperature substrate, in order to determine the applicable lamination process parameters, a pre-verification procedure is performed, which selects a process verification board with the same layer structure and size as the production board, and embeds armored thermocouples in the core layer, quarter depth and near-surface layer of the board; place this process verification board in the complete lamination stack containing a 3 mm thick Teflon pad, and perform a trial lamination using the initial standard lamination process parameters, in the process, record and analyze the data of each temperature measuring point in real time to determine whether the temperature ramp rate of the core region of the board is synchronized with that of the surface region, and whether the temperature difference between the two is controlled within 3 .

[0040] When the temperature difference data of the first trial lamination exceeds this control threshold, adjust the temperature ramp rate or segmented pressure holding time of the laminator according to the trend of the temperature difference curve; when the data shows that the core region temperature lags behind, appropriately extend the time of the low temperature preheating stage to obtain more sufficient heat penetration, and repeat the test procedure until the temperature difference data meets the control threshold, and finally obtain a set of lamination process parameters suitable for the specific material and equipment.

[0041] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0042] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present invention and are not limiting, and although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor test printed wiring board warpage control method, characterized by, The method is applied to a semiconductor test printed circuit board with a number of layers greater than or equal to twenty and a finished thickness greater than or equal to 6 mm, and comprises: Step one, establishing a symmetric stress base, performing graphic design on each inner core board of the semiconductor test printed circuit board, so that the copper residual rate difference of the two sides of the same inner core board is less than or equal to 10%, and based on this, the inner core board and the prepreg are symmetrically distributed with respect to the middle layer during lamination; Step two, constructing a uniform heat transfer path, placing the semiconductor test printed circuit board in the middle layer during pressing and arranging a Teflon pad with a thickness of 3 mm above and below it, the Teflon pad has a plane size greater than the semiconductor test printed circuit board and ensures that the semiconductor test printed circuit board is located within its orthographic projection; Step three, performing stress neutralization timing, after completing hot pressing, performing a cold pressing step with a duration of 60 to 120 minutes.

2. The semiconductor test printed wiring board warpage control method of claim 1 wherein, In step two, a PIN-LAM metal plate with a thickness of 10 mm and a steel plate are further arranged outside the Teflon pad, and the PIN-LAM metal plate, the steel plate and the kraft paper together constitute a multi-stage heat conduction buffer medium.

3. The semiconductor test printed wiring board warpage control method of claim 1 wherein, The planar dimensions of the ferrotron pad satisfy the following relationship: mm, wherein, W is the width of the ferrotron pad in either direction, W is the width of the semiconductor test printed wiring board in the same direction.

4. The method of claim 1, wherein the semiconductor test printed wiring board warpage control method is characterized by, The graphic design in step one includes laying copper dots in a cross manner in the process edge and graphic open area of the inner core board.

5. The method of claim 2, wherein the semiconductor test printed wiring board warpage control method is characterized by, During pressing, the specific stacking order of the semiconductor test printed circuit board, the Teflon pad, the PIN-LAM metal plate, the steel plate and the kraft paper is: a PIN-LAM metal plate as the bottom plate, on which is sequentially arranged the combination of kraft paper and steel plate and the Teflon pad, the semiconductor test printed circuit board is located in the middle layer of all stacked materials, and the remaining plates and pads are stacked in a mirror-symmetric manner above the semiconductor test printed circuit board, and another PIN-LAM metal plate is used as the cover plate.

6. The method of claim 1, wherein the semiconductor test printed wiring board warpage control method is characterized by, In step one, the cutting direction and the weft direction of the prepreg are consistent with the cutting direction and the weft direction of the inner core board.

7. The method of claim 1, wherein the semiconductor test printed wiring board warpage control method is characterized by, The method further comprises a copper-tin electroplating step after completing step three, which adopts a preset small current value and a long time production method.

8. The method of claim 1, wherein the semiconductor test printed wiring board warpage control method is characterized by, The method further comprises a solder mask step after completing step three, and the process parameters of the solder mask step are controlled so that the height difference of the formed solder mask layer at any position is within 50 microns.

9. The method of claim 1, wherein the semiconductor test printed wiring board warpage control method is characterized by, Before step one, it further comprises a baking step for the inner core board, and the baking step is set at a temperature of 150 degrees Celsius and a duration of 4 hours.

10. The method of claim 1, wherein the semiconductor test printed wiring board warpage control method is characterized by, The method further comprises a step of performing a brown oxidation treatment on the inner core board after the etching step, and the conveying speed of the brown oxidation treatment step is set to 2.0 meters per minute.

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