Semiconductor structure and manufacturing method thereof, semiconductor memory and electronic equipment
By introducing metal body lines to connect the transistor body region in the semiconductor structure and applying a body bias voltage, the charge loss problem of semiconductor transistors when shrinking in size is solved, and the stability and yield of the device are improved.
Patent Information
- Application Number
- CN202510926488.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-07
- Publication Date
- 2025-11-04
AI Technical Summary
During the shrinking of semiconductor transistors, mutual interference between adjacent devices leads to charge loss between the silicon substrate and the source/drain, resulting in performance degradation and yield deterioration.
Introducing metal body lines into semiconductor structures connects the body region of transistors to a fixed potential. By applying a body bias voltage at a specific location on the metal body line, the bias voltage can be efficiently and stably distributed to dense cells, suppressing the instability of the body potential of adjacent cells caused by bias fluctuations of surrounding components.
It effectively suppressed the performance degradation after device miniaturization, improved the yield, and ensured the stability and performance of high-density embedded component structures.
Smart Images
Figure CN120897446A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a semiconductor structure, a manufacturing method thereof, a semiconductor memory, and an electronic device. BACKGROUND
[0002] Dynamic Random Access Memory (DRAM) is a kind of semiconductor memory, a standard DRAM cell is composed of an access transistor and a storage capacitor, the capacitor is used to store electric charge (representing data bit 1 or 0), and the transistor is used as a switch to control the read and write access to the capacitor.
[0003] In the process of semiconductor transistor size miniaturization, as the cell spacing decreases, the mutual interference between adjacent devices intensifies, resulting in an increasingly prominent problem of charge loss between the silicon substrate and the source / drain. How to solve the performance degradation and yield deterioration problems encountered by semiconductor transistors in size reduction is a technical problem that needs to be solved in the field. SUMMARY
[0004] The purpose of the present disclosure is to provide a semiconductor structure, a manufacturing method thereof, a semiconductor memory, and an electronic device.
[0005] The first aspect of the present disclosure provides a semiconductor structure, comprising:
[0006] a semiconductor substrate comprising active regions spaced apart from each other;
[0007] a metal body line extending in a first direction is embedded under an isolation region between the active regions;
[0008] The metal body line is connected to the body region of the transistor, and is used to connect the body region of the transistor to a fixed potential.
[0009] In a possible implementation manner, the bottom of the metal body line is embedded in the semiconductor substrate below.
[0010] In a possible implementation manner, the manufacturing material of the metal body line comprises copper.
[0011] In a possible implementation manner, two gate structures are embedded in the active region.
[0012] In a possible implementation manner, at least one gate structure is embedded in the isolation region above the metal body line.
[0013] The second aspect of the present disclosure provides a manufacturing method of a semiconductor structure, comprising:
[0014] A semiconductor substrate is provided;
[0015] Active regions are formed on the substrate and spaced apart from each other;
[0016] A first trench extending in a first direction is formed between the active regions;
[0017] A second trench extending in the first direction is formed at the bottom of the first trench, and a width of the second trench is smaller than a width of the first trench;
[0018] A metal body line is formed in the second trench, and the metal body line is used to connect a body region of a transistor to a fixed potential;
[0019] An isolation region is formed in the first trench.
[0020] In one possible implementation, the active regions are formed on the substrate and spaced apart from each other by:
[0021] A sacrificial oxide film is formed on the substrate;
[0022] Different impurities are injected into specific regions of the substrate to form the active regions spaced apart from each other.
[0023] A semiconductor memory is provided in a third aspect of the present disclosure, comprising:
[0024] The semiconductor structure as described in the first aspect.
[0025] An electronic device is provided in a fourth aspect of the present disclosure, comprising:
[0026] The semiconductor memory as described in the third aspect.
[0027] Compared with the prior art, the present disclosure has the following advantages:
[0028] The semiconductor structure provided by the present disclosure has a metal body line buried under an isolation region between active regions, and the body region of a transistor is connected to a fixed potential through the metal body line. In a high-density embedded element structure, by integrating an embedded metal body line at the bottom of an element and applying a body bias voltage at a specific position of the metal body line, efficient and stable distribution of the bias voltage to the dense cells is achieved. This design can suppress the instability of the body potential of adjacent cells caused by the bias fluctuation of the surrounding elements, thereby preventing the performance degradation of the device after miniaturization, to improve the yield. BRIEF DESCRIPTION OF DRAWINGS
[0029] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The detailed description is made with reference to the accompanying drawings. The drawings are for purposes of illustration only and are not intended to be limiting in any respect. Moreover, the drawings are not necessarily drawn to scale and that like reference numerals can be used to denote like components across the various drawings. In the drawings:
[0030] Figure 1 A plan view schematic of an existing semiconductor structure is shown;
[0031] Figure 2 A plan view schematic of Figure 1 a semiconductor structure is shown;
[0032] Figure 3 A plan view schematic of a semiconductor structure provided by the present disclosure is shown;
[0033] Figure 4 A plan view schematic of Figure 3 a semiconductor structure is shown;
[0034] Figure 5 A cross-sectional schematic view of a specific semiconductor structure formed by the present disclosure is shown; Figure 4
[0035] Figure 6 A flowchart of a method of fabricating a semiconductor structure provided by the present disclosure is shown. DETAILED DESCRIPTION
[0036] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. Additionally, in the following detailed description, ordinal terms such as "first," "second," and "third," etc. are used merely for differentiating between similar entities or claim limitations and do not imply a creation of an ordinal rank based on the sequence of the descriptions of the features. Further, reference to prior art assemblies of features can be used to provide a more clear background and more substantive explanation of the current example embodiments. Moreover, example embodiments described in the "DETAILED DESCRIPTION," the Figures, and the claims are not intended to be limiting. Other embodiments and changes can be utilized, and not depart from the spirit or scope of the objectives presented herein. It should be readily understood that the aspects of the disclosure generally described herein, and illustrated in the drawings, can be arranged, substituted, combined, separated, and designed in various different configurations, all of which are implicitly contemplated herein.
[0037] Spatially relative terms, such as "beneath," "below," "lower," "above," "upper," "on," "over," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0038] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, regions, layers, and / or sections, which should not be limited to these terms. These terms may be used only to distinguish elements, components, regions, layers, or sections from one another. Unless the context clearly indicates otherwise, the terms such as “first,” “second,” and “third” used herein do not imply a sequence or order.
[0039] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain minor variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely or examples in which the event or situation occurred approximately.
[0040] In traditional processes, the bulk bias is connected to the transistor body region via substrate contact holes. However, the high resistance of these contact holes (especially in advanced processes) limits the effective transmission of the bias voltage. For example, when the bulk bias voltage needs to be dynamically adjusted, the high-resistance path can lead to response delays and bias non-uniformity. Therefore, the inventors discovered that one of the main reasons for the performance degradation and yield deterioration problems encountered by semiconductor transistors when shrinking in size is the fact that the bulk bias is connected to the transistor channel and source / drain regions via a high-resistance path, resulting in limited bias performance.
[0041] To address the problems existing in the prior art, this disclosure provides a semiconductor structure and its fabrication method, a semiconductor memory, and an electronic device, which will be described below in conjunction with the accompanying drawings.
[0042] Figure 1 A planar schematic diagram of an existing semiconductor structure is shown;
[0043] Figure 2 It shows Figure 1 The diagram shows a cross-sectional view of the semiconductor structure along line Aa.
[0044] Figure 3 A schematic planar view of a semiconductor structure provided in this disclosure is shown;
[0045] Figure 4 It shows Figure 3 The diagram shows a cross-sectional view of the semiconductor structure along line Bb.
[0046] Please refer to Figure 3 and Figure 4 The semiconductor structure provided in this disclosure includes: a semiconductor substrate 100, the semiconductor substrate 100 including active regions 110 spaced apart from each other.
[0047] The semiconductor substrate can be a P-type substrate or an N-type substrate formed from a silicon substrate, and this disclosure does not limit it.
[0048] Active Area refers to the area on the substrate used to manufacture active devices such as transistors, and its core functions include: carrier transport: in MOSFET, the active area contains the source, drain and channel, which is the path for current flow. Device isolation: blocking the conductive channel through shallow trench isolation (STI) or ion implantation technology to achieve electrical isolation between different devices.
[0049] Under the isolation area between the active areas 110, there is a metal body line 120 extending in the first direction, which is connected to the body region of the transistor, and is used to connect the body region of the transistor to a fixed potential.
[0050] As shown in Figure 3 , the first direction refers to the direction in which the metal body line 120 extends, and the angle between this direction and the direction in which each active area extends is the same.
[0051] MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is a basic semiconductor device, which is composed of source, gate, drain and body. The current-voltage characteristics of MOSFET can be described by different models, which take into account the working mode of the device, including the cutoff region, the linear region (also known as the variable resistance region) and the saturation region (also known as the active region). The body region of the transistor is one of the core structures, and its physical properties and electrical behavior directly affect the performance of the device. The body region is located between the source and drain of the transistor, adjacent to the area below the gate. Body bias refers to the voltage applied to the body region by an external circuit, which can be used to dynamically adjust the threshold voltage of the transistor in digital circuits, thereby reducing power consumption and improving speed.
[0052] Compared with the existing semiconductor structure as shown in Figure 1 and Figure 2 , the semiconductor structure provided by the present disclosure fills the metal body line under the isolation area between the active areas, and connects the body region of the transistor to a fixed potential through the metal body line. In high-density embedded element structures, by integrating an embedded metal body line at the bottom of the element and applying a body bias voltage at a specific position of the metal body line, efficient and stable distribution of the bias voltage to the dense cells is achieved. This design can suppress the instability of the body potential of adjacent cells caused by the bias fluctuation of the surrounding elements, thereby preventing performance degradation after device miniaturization and improving yield.
[0053] In some embodiments of the present disclosure, as shown in Figure 4As shown, the bottom of the metal body line 120 is embedded in the underlying semiconductor substrate 100, enabling connection between the metal body line and the body region of the transistor. Specifically, half the height of the metal body line 120 can be embedded in the underlying semiconductor substrate 100, or one-quarter of the height of the metal body line 120 can be embedded in the underlying semiconductor substrate 100, or three-quarters of the height of the metal body line 120 can be embedded in the underlying semiconductor substrate 100; this application does not limit this to any particular type.
[0054] In some embodiments of this disclosure, the metal body wire is made of copper. Copper (Cu) has become a mainstream material in semiconductor interconnect technology primarily due to its superior electrical properties, higher reliability, and compatibility with advanced processes.
[0055] Figure 5 This disclosure shows the provision in Figure 4 A schematic cross-sectional view of a specific semiconductor structure formed on this basis. For example... Figure 5 As shown, two gate structures are buried in the active region 110, and at least one gate structure is buried in the isolation region above the metal body line 120. Filling the blank area without transistors with dummy gates can balance the gate density distribution, thereby ensuring CMP / lithography uniformity, paving the way for nanoscale processes, reducing manufacturing defect rate, and improving wafer economic efficiency.
[0056] The gate structure includes a gate top insulating film, a gate side insulating film, and a gate. The gate top insulating film is located at the top of the gate, and the gate side insulating film is located on the side and bottom of the gate.
[0057] A buried-gate transistor (BGT) is a special type of transistor that mainly consists of a source, drain, gate, and substrate. The gate is "buried" in a channel, a structure that gives BGTs higher performance and lower power consumption. When a voltage is applied to the gate, a conductive channel is formed between the source and drain. This channel allows current to flow from the source to the drain. By changing the gate voltage, the conductivity of the channel can be controlled, thereby controlling the current between the source and drain. This controllable current characteristic makes BGTs play a crucial role in electronic devices.
[0058] Buried-gate transistors (BGTs) possess characteristics such as high mobility, low threshold voltage, and good subthreshold swing. These properties make them widely used in high-speed, low-power, and highly integrated circuits. For example, in portable devices such as mobile phones and computers, BGTs are widely used in key components such as processors and memory to improve device performance and battery life.
[0059] This disclosure also provides a method for fabricating a semiconductor structure, used to prepare the semiconductor structure as described in the above embodiments. Figure 6As shown, the manufacturing method comprises the following steps:
[0060] S101, providing a semiconductor substrate;
[0061] A single crystal silicon substrate (such as a silicon wafer) is selected, cleaned, polished, and pre-processed to ensure surface flatness and cleanliness, laying a foundation for subsequent processes.
[0062] S102, forming active regions spaced apart from each other on the substrate;
[0063] Specifically, the step of forming active regions spaced apart from each other on the substrate comprises the following steps: forming a sacrificial oxide film on the substrate; and injecting different impurities into a specific region of the substrate to form active regions spaced apart from each other.
[0064] A thin oxide film (such as SiO) is formed on the surface of the substrate by thermal oxidation or chemical vapor deposition (CVD) to protect the surface of the substrate or as a buffer layer for subsequent processes. Different types of impurities (such as phosphorus and boron) are injected into the target region (such as the transistor active region) of the substrate by ion implantation process to form N-type or P-type semiconductor regions, defining the electrical properties of the device.
[0065] S103, forming a first trench extending in a first direction between the active regions;
[0066] S104, forming a second trench extending in the first direction at the bottom of the first trench, the width of the second trench being smaller than the width of the first trench;
[0067] S105, forming a metal body line in the second trench, the metal body line being used to connect the body region of the transistor to a fixed potential;
[0068] S106, forming an isolation region in the first trench.
[0069] The following are the steps of creating a trench pattern and depositing metal to form a metal body line:
[0070] A multi-layer material structure (such as a combination of SiO / SiN / metal layer) is deposited on a substrate as a mask for subsequent etching. The multi-layer structure can improve the etching resistance and pattern accuracy of the mask. A photoresist is spin-coated on the mask layer, and a predetermined pattern (including longitudinal, transverse, diagonal, or recessed structures) is formed on the photoresist through an exposure and development process. The photoresist pattern is used as a mask to remove the unprotected mask layer material through dry etching (such as reactive ion etching, RIE), forming a mask pattern consistent with the photoresist. The silicon substrate is etched to a depth using the mask pattern as a mask, forming a trench. The trench is arranged along the insulating separation region between the transistor active region and other active regions, and the direction is linear or diagonal to meet the device isolation or wiring requirements. Metal 1 (such as tungsten) is filled in the trench through physical vapor deposition (PVD) or chemical vapor deposition (CVD), forming a shape conjugate to the inner surface of the trench to ensure uniform coverage of the trench bottom and sidewall. A layer of metal 2 (such as copper) is deposited on the metal 1, further filling the trench or forming a composite metal layer. Excess metal is removed by etch back to leave only the metal layer in the trench, forming a metal body wire. A layer of insulating material (such as SiO or SiN) with a predetermined thickness is deposited on the metal layer to isolate the metal layer from subsequent processes. The subsequent processes are implemented using related technologies, which are not described in detail in this disclosure.
[0071] The semiconductor structure produced by the above method has a metal body wire buried under the isolation region between the active regions, which connects the body region of the transistor to a fixed potential. In a high-density embedded element structure, by integrating an embedded metal body wire at the bottom of the element and applying a body bias voltage at a specific position of the metal body wire, efficient and stable distribution of the bias voltage to the dense cells is achieved. This design can suppress the instability of the body potential of adjacent cells caused by the bias fluctuation of the surrounding elements, thereby preventing performance degradation after device miniaturization and improving yield.
[0072] The embodiments of the present disclosure also provide a semiconductor memory including the semiconductor structure in the above embodiments. The semiconductor memory may, for example, be a DRAM.
[0073] For reference Figure 3 and Figure 4 The semiconductor structure provided by the present disclosure includes a semiconductor substrate 100 including active regions 110 spaced apart from each other. The semiconductor substrate can be a P-type substrate or an N-type substrate formed by a silicon substrate, which is not limited in the present disclosure.
[0074] A metal body wire 120 extending in a first direction is buried under the isolation region between the active regions 110, and the metal body wire 120 is connected to the body region of the transistor for connecting the body region of the transistor to a fixed potential.
[0075] like Figure 3 As shown, the first direction refers to the direction in which the metal body line 120 extends, and this direction has the same angle as the extension direction of each active region.
[0076] In some embodiments of this disclosure, such as Figure 4 As shown, the bottom of the metal body line 120 is embedded in the underlying semiconductor substrate 100, enabling connection between the metal body line and the body region of the transistor. Specifically, half the height of the metal body line 120 can be embedded in the underlying semiconductor substrate 100, or one-quarter of the height of the metal body line 120 can be embedded in the underlying semiconductor substrate 100, or three-quarters of the height of the metal body line 120 can be embedded in the underlying semiconductor substrate 100; this application does not limit this to any particular type.
[0077] In some embodiments of this disclosure, the metallic body wire is made of copper. Copper has become a mainstream material in semiconductor interconnect technology primarily due to its superior electrical properties, higher reliability, and compatibility with advanced manufacturing processes.
[0078] Figure 5 This disclosure shows the provision in Figure 4 A schematic cross-sectional view of a specific semiconductor structure formed on this basis. For example... Figure 5 As shown, two gate structures are buried in the active region 110, and at least one gate structure is buried in the isolation region above the metal body line 120. Filling the blank area without transistors with dummy gates can balance the gate density distribution, thereby ensuring CMP / lithography uniformity, paving the way for nanoscale processes, reducing manufacturing defect rate, and improving wafer economic efficiency.
[0079] Compared to existing semiconductor structures, the semiconductor structure disclosed herein includes a metal body line buried beneath the isolation region between active regions, through which the body region of the transistor is connected to a fixed potential. In this high-density embedded device structure, by integrating the embedded metal body line at the bottom of the device and applying a body bias voltage at a specific location on the metal body line, efficient and stable distribution of the bias voltage to the dense cells is achieved. This design can suppress the instability of the body potential of adjacent cells caused by bias fluctuations of surrounding components, thereby preventing performance degradation after device miniaturization and improving yield.
[0080] This disclosure also provides an electronic device that includes the semiconductor memory described in the above embodiments. The electronic device includes smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, power banks, etc.
[0081] It should be noted that:
[0082] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order not to obscure the understanding of this description.
[0083] Similarly, it is to be understood that the embodiments of the present application can be used in the exact form disclosed herein, or with minor modifications, and the present application is not limited to the exact form disclosed herein but is only limited by the claims. Similarly, it should be apparent that ones skilled in the art, upon possessing the teachings of the embodiments of the present application as set forth in the descriptions herein, can affect the disclosure of the application with minor modifications necessary to implement the present application in its various embodiments, none of which depart from the spirit of the application as recited in the claims.
[0084] Those skilled in the art can appreciate that modules in the apparatus in the embodiments can be adaptably changed and disposed in one or more apparatuses other than the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and furthermore can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination of all features disclosed in the specification (including the accompanying claims, abstract and drawings), and all processes or units of any method or apparatus disclosed thus can be adopted. Unless explicitly stated otherwise, each feature disclosed in the specification (including the accompanying claims, abstract and drawings) can be replaced by an alternative feature providing the same, equivalent or similar purpose.
[0085] Furthermore, those skilled in the art can appreciate that although some embodiments described herein include certain features of other embodiments but not others, combinations of the features of the different embodiments are meant to be within the scope of the present application and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.
[0086] It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of elements or steps other than those listed in a claim. The word 'a' or 'an' preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of both hardware and software, and any combination thereof. In a unitary claim, several devices or sub-claims can be joined by means of the expression 'and / or'. The use of the term 'at least' followed by a list of one or more items does not exclude additional such items. The use of the term 'one' or 'another' preceding the use of a list of elements or items does not exclude the presence of more than one of such element or item. The use of the term 'first','second' and 'third', etc. does not limit the number of these elements or items, which can be more than one. The use of the terms 'first','second', 'third', and the like, when used in the description or claims, might not imply an ordering but rather serve as identifiers, i.e. names, for distinguishing between two entities that might have same properties unless otherwise stated. The application is not limited to the embodiments described above, which can be modified in various ways within the scope of the inventive concept disclosed in the application.
[0087] The preferred embodiments of the application are described above, and the patent protection scope of the application is not limited by the above description, and any equivalent structural transformation made according to the content of the description and drawings of the application, or direct / indirect application in other related technical fields within the concept of the application are included in the patent protection scope of the application.
Claims
1. A semiconductor structure, characterized in that, include: A semiconductor substrate, including active regions spaced apart from each other; A metal body line extending in a first direction is buried below the isolation zone between the active regions; The metal body line is connected to the body region of the transistor to connect the body region of the transistor to a fixed potential.
2. The semiconductor structure according to claim 1, characterized in that, The bottom of the metal body wire is embedded in the underlying semiconductor substrate.
3. The semiconductor structure according to claim 1, characterized in that, The metal wire is made of copper.
4. The semiconductor structure according to claim 1, characterized in that, The active region contains two gate structures.
5. The semiconductor structure according to claim 4, characterized in that, At least one gate structure is embedded in the isolation region above the metal body line.
6. A method for fabricating a semiconductor structure, characterized in that, include: Provide semiconductor substrates; Active regions spaced apart from each other are formed on the substrate; A first trench extending in a first direction is formed between the active regions; A second groove extending in a first direction is formed at the bottom of the first groove, and the width of the second groove is smaller than the width of the first groove. A metal body line is formed in the second trench, the metal body line being used to connect the body region of the transistor to a fixed potential; An isolation zone is formed in the first trench.
7. The manufacturing method according to claim 6, characterized in that, The formation of spaced-apart active regions on the substrate includes: A sacrificial oxide film is formed on the substrate; Different impurities are injected into specific regions of the substrate to form active regions spaced apart from each other.
8. A semiconductor memory, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 5.
9. An electronic device, characterized in that, include: The semiconductor memory as described in claim 8.
10. The electronic device according to claim 9, including a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, and power bank.