Memory cell of non-volatile memory

Abstract

The invention discloses a memory cell of a non-volatile memory. The memory cell comprises an N-type region, an N-type well region, a P-type well region, a first p-type doped region, a second p-type doped region and a first n-type doped region, the N-type well region and the P-type well region are formed in the N-type region. The first p-type doped region and the second p-type doped region are located on the surface of the N-type well region. The gate layer is located above the surface of the N-type well region between the first p-type doped region and a second p-type doped region. The first n-type doped region is located on the surface of the P-type well region. The gate layer extends to the P-type well region, and a first side of the gate layer is adjacent to the first n-type doped region.

Description

[0001] This application is a divisional application of a Chinese patent application for invention (Application No. 202110930150.2, Application Date: August 13, 2021, Invention Name: Storage Cell of Non-volatile Memory). TECHNICAL FIELD

[0002] The present application relates to a memory, and in particular to a storage cell of a non-volatile memory. BACKGROUND

[0003] It is well known that a non-volatile memory can still save its data content after power off. Generally, when the non-volatile memory is manufactured and shipped, a user can program the non-volatile memory to record data in the non-volatile memory.

[0004] Please refer to Figure 1 which is shown as a schematic diagram of an array of storage cells of a prior art non-volatile memory. The array of storage cells 100 includes m x n storage cells c11~cmn, and the array of storage cells 100 is connected to m word lines WL1~WLm, n bit lines BL1~BLn, and m control lines CL1~CLm. In addition, each of the storage cells c11~cmn includes a floating gate transistor. The floating gate transistor is an n-type dual gate floating gate transistor, which includes a control gate terminal, a floating gate, a first source / drain terminal, and a second source / drain terminal. The floating gate is in a floating state and is not connected to any terminal.

[0005] In the n storage cells c11~c1n of the first column, the control gate terminals of the floating gate transistors are connected to the word line WL1, the first source / drain terminals of the floating gate transistors are connected to the control line CL1, and the second source / drain terminals of the floating gate transistors are connected to the corresponding n bit lines BL1~BLn. In the n storage cells c21~c2n of the second column, the control gate terminals of the floating gate transistors are connected to the word line WL2, the first source / drain terminals of the floating gate transistors are connected to the control line CL2, and the second source / drain terminals of the floating gate transistors are connected to the corresponding n bit lines BL1~BLn. Similarly, in the n storage cells cm1~cmn of the mth column, the control gate terminals of the floating gate transistors are connected to the word line WLm, the first source / drain terminals of the floating gate transistors are connected to the control line CLm, and the second source / drain terminals of the floating gate transistors are connected to the corresponding n bit lines BL1~BLn.

[0006] Basically, by providing appropriate bias to the word lines WL1~WLm, the bit lines BL1~BLn, and the control lines CL1~CLm, the memory cells c11~cmn in the memory cell array 100 can be subjected to a programming operation, an erasing operation, or a reading operation. For example, an activated voltage is provided to the word line WL1, and an inactivated voltage is provided to the other word lines WL2~WLm, so that the first column connected to the word line WL1 is a selected column, and the n memory cells c11~c1n in the selected column can be subjected to a programming operation, an erasing operation, or a reading operation.

[0007] Further, Figure 1 The memory cell array 100 in the above embodiment is described by taking an n-type double-gate floating gate transistor as an example. In fact, a p-type double-gate floating gate transistor can also be used to form a memory cell, and a memory cell array of a non-volatile memory. SUMMARY

[0008] The main purpose of the present application is to provide a memory cell of a non-volatile memory. In the memory cell, the transistor is a single-gate floating gate transistor. Further, by providing appropriate bias, the memory cell can normally perform a programming operation, an erasing operation, or a reading operation. Similarly, by providing appropriate bias, the memory cell array can also normally perform a programming operation, an erasing operation, or a reading operation.

[0009] The present application is a memory cell of a non-volatile memory, comprising: an N-type region; an N-type well region and a P-type well region formed in the N-type region; a first P-type doped region and a second P-type doped region located on the surface of the N-type well region; a gate layer located above the surface of the N-type well region between the first P-type doped region and the second P-type doped region, and the gate layer extends from the N-type well region to the P-type well region; and a first N-type doped region located on the surface of the P-type well region, and the first N-type doped region is adjacent to a first side of the gate layer; wherein the gate layer, the N-type well region, the first P-type doped region, and the second P-type doped region form a P-type transistor; the gate layer, the P-type well region, and the first N-type doped region form a transistor capacitor, the transistor capacitor and the P-type transistor share the gate layer; and the N-type region and the P-type well region form a diode; wherein a first drain / source terminal of the P-type transistor is connected to a bit line, a second drain / source terminal of the P-type transistor is connected to a source line, and the P-type well region and the first N-type doped region are connected to a word line.

[0010] The application is a storage unit of a non-volatile memory, comprising: an N-type region; an N-type well region and a P-type well region formed in the N-type region; a first P-type doped region and a second P-type doped region located on the surface of the N-type well region; a gate layer located above the surface of the N-type well region between the first P-type doped region and the second P-type doped region; and a first N-type doped region located on the surface of the P-type well region, wherein the gate layer extends to the P-type well region, the gate layer is located above the first N-type doped region, and the gate layer above the P-type well region is a comb-shaped gate layer; wherein the gate layer, the N-type well region, the first P-type doped region and the second P-type doped region form a P-type transistor; the gate layer, the P-type well region and the first N-type doped region form a transistor capacitor, the transistor capacitor and the P-type transistor share the gate layer, and the N-type region and the P-type well region form a diode; wherein a first drain / source terminal of the P-type transistor is connected to a bit line, a second drain / source terminal of the P-type transistor is connected to a source line, and the first N-type doped region is connected to a word line.

[0011] For a better understanding of the above and other aspects of the application, a preferred embodiment is described below in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 A schematic diagram of an array of storage units of a prior art non-volatile memory;

[0013] Figures 2A-2N A flowchart of the fabrication process of an array of storage units of the first embodiment of the application and a cross-sectional view along the ab dashed line in each fabrication process;

[0014] Figures 3A-3C A cross-sectional view, an equivalent circuit and a schematic diagram of an array of storage units of the first embodiment of the application;

[0015] Figure 4 A schematic diagram of a storage unit of the second embodiment of the application;

[0016] Figures 5A-5D A bias voltage schematic diagram of various actions performed by the storage unit of the first embodiment of the application;

[0017] Figures 6A-6H A flowchart of the fabrication process of a storage unit of the third embodiment of the application and a cross-sectional view along the ef dashed line in each fabrication process; and

[0018] Figure 7A And Figure 7B A cross-sectional view and an equivalent circuit schematic diagram of a storage unit of the third embodiment of the application.

[0019] SYMBOL DESCRIPTION

[0020] 100: memory cell array

[0021] 110, 610: isolation structure

[0022] 111, 112, 121, 122, 611: gate layer

[0023] 115: gate oxide layer

[0024] 131, 132, 133, 134, 135, 136, 141, 142, 143, 144, 631, 632: p-type doped region

[0025] 141, 152, 633: n-type doped region

[0026] 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 661, 662, 663: metal wire DETAILED DESCRIPTION

[0027] Reference is made to Figures 2A-2N which shows a flow chart of the fabrication of a memory cell array of a first embodiment of the present application and a cross-sectional view along the ab imaginary line in each fabrication step. Furthermore, the following is explained with a memory cell array of a non-volatile memory composed of 2x2 memory cells. Of course, the present application is not limited thereto, and those skilled in the art can form a memory cell array of a non-volatile memory composed of mxn memory cells according to the content of the present application.

[0028] As shown in Figure 2A and Figure 2B , a deep N well (DNW) is formed on a p-type semiconductor substrate (p_sub).

[0029] As shown in Figure 2C and Figure 2D , an isolation structure formation step is performed. As shown in Figure 2C , after the isolation structure 110 is formed on the deep N well DNW, the isolation structure 110 defines an A region, a B region, a C1 region and a C2 region on the surface of the deep N well DNW.

[0030] As shown in Figure 2E and Figure 2FAs shown, a well region formation step is performed. A mask is designed to expose only the B region, and a P-type well region PW formation step is performed on the B region. After that, a P-type well region PW is formed under the surface of the B region. Further, a mask is designed to expose only the C1 region and the C2 region, and an N-type well region NW1, NW2 formation step is performed on the C1 region and the C2 region. After that, an N-type well region NW1 and NW2 is formed under the surface of the C1 region and the C2 region, respectively. The N-type well region NW1, NW2 and the P-type well region PW are formed in a deep N-type well region DNW, and the deep N-type well region DNW, the N-type well region NW1 and NW2 are of the same N-type.

[0031] As shown, Figure 2G As shown, Figure 2H As shown, a gate structure formation step is performed, and gate layers 111, 112, 121, 122 are formed. The gate layers 111, 112, 121, 122 are polysilicon gate layers. As shown, Figure 2G The gate layer 111 and the gate layer 112 cover the surface of the N-type well region NW1, and divide the N-type well region NW1 into three parts. The gate layer 111 and the gate layer 112 extend to the P-type well region PW and cover the P-type well region PW. Similarly, the gate layer 121 and the gate layer 122 cover the surface of the N-type well region NW2, and divide the N-type well region NW2 into three parts. The gate layer 121 and the gate layer 122 extend to the P-type well region PW and cover the P-type well region PW. Further, as shown, Figure 2H As shown, the gate structure includes a gate oxide layer 115 under the gate layer 111, in addition to the gate layer 111. Similarly, there is a gate oxide layer under the other gate layers 112, 121, 122.

[0032] As shown, Figure 2I As shown, Figure 2J As shown, a p-type doped region formation step is performed. A mask with cross-hatching is designed to expose the N-type well regions NW1, NW2 and to expose part of the P-type well region PW. Then, ion implantation is performed, and the p-type doped region formation step is completed. Thus, the part of the N-type well region NW1 that is not covered by the two gate layers 111 and 112 forms p-type doped regions (p+) 131, 132, 133; the part of the N-type well region NW2 that is not covered by the two gate layers 121 and 122 forms p-type doped regions (p+) 134, 135, 136; and the part of the P-type well region PW that is not covered by the mask and the four gate layers 111, 112, 121, 122 forms p-type doped regions (p+) 141, 142, 143, 144.

[0033] In addition, as shown in Fig. 1 IB, the gate layer 111 adjacent to the p-type doped region (p+) 142 on the P-well PW forms a p-type gate layer (p+), and the gate layer 111 adjacent to the n-type doped region (n+) 152 on the P-well PW forms an n-type gate layer (n+). Figure 2J In addition, as shown in Fig. 1 IB, the gate layer 111 adjacent to the p-type doped region (p+) 142 on the P-well PW forms a p-type gate layer (p+), and the gate layer 111 adjacent to the n-type doped region (n+) 152 on the P-well PW forms an n-type gate layer (n+).

[0034] As shown in Fig. 1 ID, the n-type doped region formation step is performed. A mask with cross-hatching is designed to expose the A region (i.e., the deep N-well DNW) and to expose part of the P-well PW. Then, ion implantation is performed, and the n-type doped region formation step is completed. Thus, the n-type doped region (n+) 151 is formed in the deep N-well DNW, and the n-type doped region (n+) 152 is formed in the P-well PW that is not covered by the mask and the four gate layers 111, 112, 121, and 122, so that the P-well PW contains the p-type doped regions (p+) 141-144 and the n-type doped region (n+) 152. Figure 2K Figure 2L As shown in Fig. 1 ID, the n-type doped region formation step is performed. A mask with cross-hatching is designed to expose the A region (i.e., the deep N-well DNW) and to expose part of the P-well PW. Then, ion implantation is performed, and the n-type doped region formation step is completed. Thus, the n-type doped region (n+) 151 is formed in the deep N-well DNW, and the n-type doped region (n+) 152 is formed in the P-well PW that is not covered by the mask and the four gate layers 111, 112, 121, and 122, so that the P-well PW contains the p-type doped regions (p+) 141-144 and the n-type doped region (n+) 152.

[0035] In addition, as shown in Fig. 1 IB, the gate layer 111 adjacent to the p-type doped region (p+) 142 on the P-well PW forms a p-type gate layer (p+), and the gate layer 111 adjacent to the n-type doped region (n+) 152 on the P-well PW forms an n-type gate layer (n+). Figure 2L In other words, the gate layer 111 of the storage cell of the first embodiment includes a p-type gate layer (p+) and an n-type gate layer (n+), i.e., the gate layer 111 on the N-well NW1 contains a p-type gate layer (p+), the gate layer 111 on the P-well PW contains a p-type gate layer (p+) and an n-type gate layer (n+), and the p-type gate layer (p+) of the gate layer 111 on the P-well PW is adjacent to the p-type doped region (p+) 142, and the n-type gate layer (n+) of the gate layer 111 on the P-well PW is adjacent to the n-type doped region (n+) 152.

[0036] As shown in Fig. 1 ID, the n-type doped region formation step is performed. A mask with cross-hatching is designed to expose the A region (i.e., the deep N-well DNW) and to expose part of the P-well PW. Then, ion implantation is performed, and the n-type doped region formation step is completed. Thus, the n-type doped region (n+) 151 is formed in the deep N-well DNW, and the n-type doped region (n+) 152 is formed in the P-well PW that is not covered by the mask and the four gate layers 111, 112, 121, and 122, so that the P-well PW contains the p-type doped regions (p+) 141-144 and the n-type doped region (n+) 152. Figure 2M Figure 2N As shown in Fig. 1 ID, the n-type doped region formation step is performed. A mask with cross-hatching is designed to expose the A region (i.e., the deep N-well DNW) and to expose part of the P-well PW. Then, ion implantation is performed, and the n-type doped region formation step is completed. Thus, the n-type doped region (n+) 151 is formed in the deep N-well DNW, and the n-type doped region (n+) 152 is formed in the P-well PW that is not covered by the mask and the four gate layers 111, 112, 121, and 122, so that the P-well PW contains the p-type doped regions (p+) 141-144 and the n-type doped region (n+) 152. Figure 2M As shown in Fig. 1 ID, the n-type doped region formation step is performed. A mask with cross-hatching is designed to expose the A region (i.e., the deep N-well DNW) and to expose part of the P-well PW. Then, ion implantation is performed, and the n-type doped region formation step is completed. Thus, the n-type doped region (n+) 151 is formed in the deep N-well DNW, and the n-type doped region (n+) 152 is formed in the P-well PW that is not covered by the mask and the four gate layers 111, 112, 121, and 122, so that the P-well PW contains the p-type doped regions (p+) 141-144 and the n-type doped region (n+) 152. Figure 2M ​​The storage unit array in the memory cell includes four storage units of the same structure, and Figure 2N is a cross-sectional view of one storage unit.

[0037] In Figure 2N , the metal wire 168 is designed to connect to the P-well PW via the p-type doped region (p+) 142. Since the P-well PW has a wide range, the four storage units share the P-well PW. In other embodiments, the metal wire can also be designed to connect to other p-type doped regions (p+). For example, the metal wire 170 is designed to connect to the P-well PW via the p-type doped region (p+) 141, which can replace the metal wire 168. Similarly, the metal wire 161 is designed to connect to the deep N-well DNW via the n-type doped region (n+) 151. Those skilled in the art can also design the metal wire to connect to the deep N-well DNW via the n-type doped region (n+) at other locations to replace the metal wire 161.

[0038] In other words, in Figure 2M , the storage unit along the bc dashed line cross-sectional view will be similar to Figure 2N , but lacks the n-type doped region (n+) 151 and the metal wires 168 and 161. In fact, Figure 2M , the four storage units share the same P-well PW and deep N-well DNW. Therefore, the metal wires 161 and 168 can be used to control the bias of the deep N-well DNW and the P-well PW.

[0039] Please refer to Figures 3A-3C , which shows a cross-sectional view of a storage cell, an equivalent circuit (the equivalent circuit of the diode formed by the junction between the deep N-well DNW and the p-type semiconductor substrate p_sub is omitted here) and a storage cell array of the first embodiment of the present application. As Figure 3A and Figure 3B shown, the storage cell includes a p-type transistor Mp, an n-type transistor Mn and a diode D, the p-type transistor Mp and the n-type transistor Mn share the gate layer 111. The n-type well NW1, the p-type doped region 131, the p-type doped region 132 and the gate layer 111 form the p-type transistor Mp, and the gate layer 111 is a floating gate layer, i.e. the p-type transistor Mp is a single-gate floating gate transistor. Furthermore, the metal wire 162 is connected to the p-type doped region 131, and the metal wire 162 serves as the bit line BL1; the metal wire 163 is connected to the p-type doped region 132, and the metal wire 163 serves as the source line SL1; the metal wire 161 is connected to the deep N-well DNW via the n-type doped region (n+) 151, and the metal wire 161 serves as the deep N-well terminal T DNWTherefore, the first drain / source terminal of the p-type transistor Mp is connected to the bit line BL1, the second drain / source terminal of the p-type transistor Mp is connected to the source line SL1, and the body terminal of the p-type transistor Mp is connected to the deep N-type well terminal T. DNW .

[0040] Furthermore, the P-type well region PW, the n-type doped region 152, and the gate layer 111 constitute an n-type transistor Mn. Metal wire 169 connects to the n-type doped region 152 and serves as the character line WL1; metal wire 168 connects to the P-type well region PW via the p-type doped region 142 and is also connected to the character line WL1. Therefore, in the n-type transistor Mn, the n-type doped region 152 can be considered as two merged n-type doped regions. Thus, the two drain / source terminals of the n-type transistor Mn are interconnected and connected to the character line WL1, and the body terminal of the n-type transistor Mn is also connected to the character line WL1. This connection relationship makes the n-type transistor Mn a transistor capacitor, meaning the memory cell includes a p-type transistor Mp, a transistor capacitor, and a diode D. The first end of the transistor capacitor is the gate layer 111, and the second end of the transistor capacitor (i.e., the p-type doped region 142 and the n-type doped region 152) is connected to the character line WL1.

[0041] Furthermore, the P-type well region PW and the deep N-type well region DNW form a pn junction, creating a diode D. That is, the anode of diode D is connected to the body terminal of the n-type transistor Mn, and the cathode of diode D is connected to the body terminal of the p-type transistor Mp. Further, the deep N-type well region DNW and the p-type semiconductor substrate p_sub also form a pn junction, creating another diode with a back-to-back connection to diode D.

[0042] like Figure 3C As shown, the memory cell array includes four identical memory cells c11, c12, c21, and c22. The memory cell array is connected to source lines SL1~SL2, bit lines BL1~BL4, and character line WL1.

[0043] Taking memory cell c11 as an example, the two drain / source terminals of transistor Mn are interconnected with the body terminal and connected to the character line WL1. Transistor Mp and the gate terminal 111 of transistor Mn are interconnected. The first drain / source terminal of p-type transistor Mp is connected to the bit line BL1, the second drain / source terminal of p-type transistor Mp is connected to the source line SL1, and the body terminal of p-type transistor Mp is connected to the deep N-type well terminal T. DNWThe anode of the diode D is connected to the bulk terminal of the n-type transistor Mn, and the cathode of the diode D is connected to the bulk terminal of the p-type transistor Mp.

[0044] Similarly, the storage cells c12, c21, and c22 have similar connection relationships, which are not described here. In addition, in the four storage cells, the bulk terminals of the p-type transistors Mp are all connected to the N-type well region terminal T DNW , and the bulk terminals of the p-type transistors Mp are all connected to the word line WL1. Furthermore, in the storage cell array of Figure 3C , the source lines SL1 and SL2 can be connected to each other. That is, the storage cell array of Figure 3C can share a source line.

[0045] Furthermore, the storage cell of the first embodiment is fabricated on a p-type semiconductor substrate (p_sub). Of course, the present application is not limited thereto, and the storage cell can also be fabricated on an n-type semiconductor substrate (n_sub). Please refer to Figure 4 , which illustrates the storage cell of the second embodiment of the present application. The difference between the storage cell of the first embodiment and the storage cell of the second embodiment is that the storage cell is directly formed on an n-type semiconductor substrate (n_sub). In addition, the storage cell structure of the first embodiment is similar to that of the second embodiment, and the storage cell of the first embodiment has the same equivalent circuit as that of the second embodiment.

[0046] Please refer to Figures 5A-5D , which illustrates the bias voltage diagrams of the storage cell of the first embodiment of the present application in various actions. Of course, the various bias voltages of the storage cell of the first embodiment are also applicable to the storage cell of the second embodiment.

[0047] As shown in Figure 5A , in the programming action, the word line WL and the deep N-type well region terminal T DNW receive a programming voltage Vpgm, that is, the bulk terminals of the p-type transistor Mp and the n-type transistor Mn both receive the programming voltage Vpgm. Furthermore, the source line SL receives a source line voltage V SL , and the bit line BL receives a ground voltage (0V). Among them, the programming voltage Vpgm is greater than the source line voltage V SL , and the source line voltage V SL is greater than the voltage received by the bit line BL (i.e., the ground voltage (0V)). For example, the programming voltage Vpgm is 9V, and the source line voltage V SL is 4V.

[0048] In the n-type transistor Mn, since the bit line WL receives the program voltage Vpgm of 9 V from the p-type well PW, the program voltage Vpgm is coupled to the gate layer 111, so that the voltage on the gate layer 111 is about 9 V of the program voltage Vpgm. Further, since the gate layer 111 is the program voltage Vpgm, the p-type transistor Mp is turned off. Since the bit line BL receives the ground voltage, the band-to-band induced hot electron injection (BBHE) effect occurs between the p-type doped region 131 and the gate layer 111, and electrons are injected from the p-type doped region 131 to the gate layer 111. Accordingly, the programming operation performed by the BBHE effect can cause the gate oxide layer 115 to be damaged to a lesser extent; and the p-type doped region (p+) 142 and the n-type doped region (n+) 152 included in the p-type well PW can provide sufficient capacitance in the programming operation to improve / maintain the coupling ratio of the charge, thereby increasing the electron injection efficiency and improving the programming efficiency.

[0049] Please refer to Figure 5B and Figure 5C , which is a schematic diagram of a read operation on a memory cell. In the read operation, the word line WL receives the word line voltage V WL , the deep n-type well end T DNW receives the deep n-type well voltage V DNW , the source line SL receives the read voltage Vr, and the bit line BL receives the ground voltage (0 V). Among them, the deep n-type well voltage V DNW is greater than or equal to the read voltage Vr, the read voltage Vr is greater than the word line voltage V WL , and the word line voltage V WL is greater than the ground voltage (0 V). For example, the deep n-type well voltage V DNW and the read voltage Vr are 2 V, and the word line voltage V WL is 1 V.

[0050] As Figure 5B shown, when the gate layer 111 stores electrons, the p-type transistor Mp is turned on, and a large read current Ir is generated between the source line SL and the bit line BL. As Figure 5CAs shown, when the gate layer 111 does not store electrons, the p-type transistor Mp is turned off, and a near-zero read current Ir is generated between the source line SL and the bit line BL. In other words, during a read operation, the storage state of the memory cell can be determined based on the magnitude of the read current Ir. For example, when the read current Ir is large, the memory cell is confirmed to be in the first storage state, where electrons are stored. When the read current Ir is very small, the memory cell is confirmed to be in the second storage state, where no electrons are stored.

[0051] like Figure 5D As shown, during the erase operation, the character line WL receives the character line voltage V. WL Deep N-type well region end T DNW The source line SL and the bit line BL receive the erase voltage V. ERS Among them, the erasure voltage V ERS Greater than the character line voltage V WL And the character line voltage V WL Less than the ground voltage (0V). For example, the erase voltage V ERS It is 9V, and the character line voltage is V. WL The voltage is -9V. At this time, FN tunneling occurs between the gate layer 111 and the channel of the p-type transistor Mp, and electrons are ejected from the gate layer 111 into the N-type well region NW1 of the p-type transistor Mp. Based on this, the p-type doped region (p+) 142 and the n-type doped region (n+) 152 contained in the p-type well region PW can provide sufficient capacitance during the erasure operation to improve the erasure efficiency. In one embodiment, the p-type semiconductor substrate p_sub can receive a substrate voltage during the erasure operation, and the substrate voltage is less than the erasure voltage V. ERS For example, the substrate voltage is -20V.

[0052] By using the bias voltage of the above actions, any memory cell in the memory cell array can be controlled, and programming, reading and erasing actions can be performed on the selected memory cell.

[0053] Please refer to Figures 6A-6H The diagram shown is a flowchart of the manufacturing process of the storage unit according to the third embodiment of the present invention, and a cross-sectional view along the dotted line ef in each manufacturing process.

[0054] The process steps of the storage unit of the second embodiment are similar to those of the first embodiment. First, a deep N-well DNW is formed on the p-type semiconductor substrate p_sub. Next, an isolation structure 610 is formed on the deep N-well DNW, and the isolation structure 610 divides the surface of the deep N-well DNW into two regions. Next, a second well formation step is performed to form a P-well PW and an N-well NW in the two regions, respectively.

[0055] As shown in FIG. 6B, a gate structure formation step is performed to form a gate layer 611. According to the third embodiment of the present application, the gate layer 611 is a comb gate layer, and the gate layer 611 is a polysilicon gate layer. The gate layer 611 covers the surface of the N-well NW, divides the N-well NW into two parts, extends to the P-well PW, and covers the P-well PW. In addition, the gate layer 611 covering the P-well PW includes a plurality of finger-shaped branches, and each of the finger-shaped branches has a space between them. In addition, the gate structure includes a gate oxide layer 615 under the gate layer 611. Figure 6A Figure 6B As shown in FIG. 6C, a p-type doped region formation step is performed. P-type doped regions (p+) 631, 632 are formed in the portions of the N-well NW not covered by the gate layer 611. In addition, as shown in FIG. 6D, the gate layer 611 between the two p-type doped regions (p+) 631, 632 also forms a p-type gate layer (p+).

[0056] As shown in FIG. 6E, an n-type doped region formation step is performed. N-type doped regions (n+) 633 are formed in the portions of the P-well PW not covered by the gate layer 611. Similarly, the gate layer 611 covering the P-well PW forms an n-type gate layer (n+). In other words, the gate layer 611 of the storage unit of the third embodiment includes a p-type gate layer (p+) and an n-type gate layer (n+). Figure 6C Figure 6D As shown in FIG. 6E, an n-type doped region formation step is performed. N-type doped regions (n+) 633 are formed in the portions of the P-well PW not covered by the gate layer 611. Similarly, the gate layer 611 covering the P-well PW forms an n-type gate layer (n+). In other words, the gate layer 611 of the storage unit of the third embodiment includes a p-type gate layer (p+) and an n-type gate layer (n+). Figure 6D According to the third embodiment of the present application, because the width of each finger-shaped branch of the gate layer 611 is very narrow, the n-type gate layers (n+) formed between the finger-shaped branches diffuse and overlap with each other, thereby forming a merged n-type doped region. That is, the n-type doped regions 633 are located under the finger-shaped branches of the gate layer 611 and under the surfaces between the finger-shaped branches.

[0057] Figure 6E According to the third embodiment of the present application, because the width of each finger-shaped branch of the gate layer 611 is very narrow, the n-type gate layers (n+) formed between the finger-shaped branches diffuse and overlap with each other, thereby forming a merged n-type doped region. That is, the n-type doped regions 633 are located under the finger-shaped branches of the gate layer 611 and under the surfaces between the finger-shaped branches. Figure 6F According to the third embodiment of the present application, because the width of each finger-shaped branch of the gate layer 611 is very narrow, the n-type gate layers (n+) formed between the finger-shaped branches diffuse and overlap with each other, thereby forming a merged n-type doped region. That is, the n-type doped regions 633 are located under the finger-shaped branches of the gate layer 611 and under the surfaces between the finger-shaped branches.

[0058] According to the third embodiment of the present application, because the width of each finger-shaped branch of the gate layer 611 is very narrow, the n-type gate layers (n+) formed between the finger-shaped branches diffuse and overlap with each other, thereby forming a merged n-type doped region. That is, the n-type doped regions 633 are located under the finger-shaped branches of the gate layer 611 and under the surfaces between the finger-shaped branches.

[0059] ​​​As Figure 6G With Figure 6H the metal contact step, the memory cell array of the present application is formed. As Figure 6G With Figure 6H metal lines 661 and 662 are formed to contact the p-type doped regions (p+) 631 and 632, respectively. A metal line 663 is formed to contact the n-type doped region (n+) 663.

[0060] In addition, Figures 6A-6H only the fabrication process of a single memory cell is shown. Of course, those skilled in the art can apply the fabrication process disclosed in the first embodiment to the third embodiment and fabricate the third embodiment memory cell as a memory cell array. Like the first embodiment memory cell, since the P-type well region PW has a wide range, the P-type well region PW can be connected to a metal line (not shown) via the p-type doped region (p+) and connected to the word line WL. Similarly, the deep N-type well region DNW can be connected to another metal line (not shown) via the n-type doped region (n+) as the deep N-type well region terminal T DNW .

[0061] Please refer to Figure 7A With Figure 7B , which is shown as a cross-sectional view of the third embodiment memory cell of the present application and the equivalent circuit (here, the equivalent circuit of the diode formed by the junction of the deep N-type well region DNW and the p-type semiconductor substrate p_sub is omitted). As Figure 7A shown, the memory cell includes a p-type transistor Mp and a transistor capacitor C. The N-type well region NW, the p-type doped region 631, the p-type doped region 632, and the gate layer 611 form the p-type transistor Mp, and the gate layer 611 is a floating gate layer, i.e., the p-type transistor Mp is a single-gate floating gate transistor. Furthermore, the metal line 661 is connected to the p-type doped region 631, and the metal line 661 serves as the bit line BL; the metal line 662 is connected to the p-type doped region 632, and the metal line 662 serves as the source line SL. Therefore, the first drain / source terminal of the p-type transistor Mp is connected to the bit line BL, and the second drain / source terminal of the p-type transistor Mp is connected to the source line SL. In addition, the body terminal of the p-type transistor Mp is connected to the deep N-type well region terminal T DNW .

[0062] In addition, the P-type well region PW, the n-type doped region 633 and the gate layer 611 form a transistor capacitor C, the first end of the transistor capacitor C is the gate layer 611, and the second end of the transistor capacitor C is the n-type doped region 633. The metal wire 663 is connected to the n-type doped region 633, and the metal wire 663 serves as a word line WL. Therefore, the second end of the transistor capacitor C is connected to the word line WL.

[0063] In addition, the P-type well region PW and the deep N-type well region DNW form a pn junction, thereby forming a diode D. That is, the anode of the diode D is connected to the body terminal of the n-type transistor Mn, and the cathode of the diode D is connected to the body terminal of the p-type transistor Mp.

[0064] Basically, in the third embodiment, since the gate layer 611 is a comb gate layer, the n-type doped region (n+) 633 can be formed in combination, and thus the n-type doped region (n+) 633 is also formed under the finger branches of the gate layer 611. In this way, the transistor capacitor C can have a sufficient effective capacitance value, and the coupling ratio of the charge can be improved, thereby facilitating the programming operation and the erasing operation. In addition, the equivalent circuit of the third embodiment is the same as that of the first embodiment, and thus the bias voltages for the programming operation, the reading operation and the erasing operation of the third embodiment are the same as those of the first embodiment. Therefore, the detailed description is omitted here.

[0065] Further, the memory cell of the third embodiment is formed on the p-type semiconductor substrate (p_sub). Of course, the present application is not limited to this, and the memory cell can be formed on the n-type semiconductor substrate (n_sub) as in the second embodiment.

[0066] In summary, although the present application is disclosed in combination with the above preferred embodiments, it is not intended to limit the present application. Those skilled in the art to which the present application pertains can make various modifications and decorations without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application should be defined by the appended claims.

Claims

1. A storage cell of a non-volatile memory, comprising: N-type region; N-type well regions and P-type well regions are formed in this N-type region; The first p-type doped region and the second p-type doped region are located on the surface of the N-type well region; A gate layer is located above the surface of the N-type well region between the first p-type doped region and the second p-type doped region; as well as A first n-type doped region is located on the surface of the P-type well region, wherein the gate layer extends to the P-type well region, the gate layer is located above the first n-type doped region, and the gate layer above the P-type well region is a comb-shaped gate layer. The gate layer, the N-type well region, the first p-type doped region, and the second p-type doped region form a p-type transistor; the gate layer, the P-type well region, and the first n-type doped region form a transistor capacitor, the transistor capacitor and the p-type transistor share the gate layer, and the N-type region and the P-type well region form a diode; The first drain / source terminal of the p-type transistor is connected to the bit line, the second drain / source terminal of the p-type transistor is connected to the source line, and the first n-type doped region is connected to the character line. The comb-shaped gate layer includes multiple finger branches, and the first n-type doped region is located below the finger branches and below the surface between the finger branches.

2. The storage cell of the non-volatile memory as claimed in claim 1, wherein during programming, the character line receives a programming voltage, the source line receives a source line voltage, the bit line receives a ground voltage, the body terminal of the p-type transistor receives the programming voltage, the first n-type doped region receives the programming voltage, the programming voltage is greater than the source line voltage, and the source line voltage is greater than the ground voltage.

3. The memory cell of the non-volatile memory as claimed in claim 2, wherein during the programming operation, a band-to-band tunneling induced thermal electron injection effect occurs between the second p-type doped region and the gate layer, and a plurality of electrons are injected into the gate layer from the first p-type doped region.

4. The storage cell of the non-volatile memory as claimed in claim 1, wherein during a read operation, the character line receives a character line voltage, the source line receives a read voltage, the bit line receives a ground voltage, the body terminal of the p-type transistor receives a deep N-type well voltage, the first n-type doped region receives the character line voltage, the deep N-type well voltage is greater than or equal to the read voltage, the read voltage is greater than the character line voltage, and the character line voltage is greater than the ground voltage.

5. The memory cell of the non-volatile memory as claimed in claim 4, wherein during the read operation, a read current is generated between the source line and the bit line; and the memory state of the memory cell is determined according to the magnitude of the read current.

6. The memory cell of the non-volatile memory as claimed in claim 1, wherein during the erase operation, the character line receives a character line voltage, the source line receives an erase voltage, the bit line receives the erase voltage, the body terminal of the p-type transistor receives the erase voltage, the first n-type doped region receives the character line voltage, the erase voltage is a positive voltage, and the character line voltage is a negative voltage.

7. The memory cell of the non-volatile memory as claimed in claim 6, wherein during the erase operation, an FN tunneling effect occurs between the gate layer and the channel of the p-type transistor, and multiple electrons exit from the gate layer into the N-type well region of the p-type transistor.

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