Device manufacturing process for improving metal overturning problem
By adding an edge etching process to the semiconductor manufacturing process, dry etching is used to remove metal residues at the wafer edges, solving the metal overturning problem and improving product yield.
Patent Information
- Application Number
- CN202511002346.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-18
- Publication Date
- 2025-11-04
AI Technical Summary
In semiconductor manufacturing, metal residues at the edges of wafers pose a risk of peeling off in subsequent processes, affecting product yield.
By adding an edge etching process after the chemical mechanical polishing process, dry etching is used to remove the residual gate metal material in the groove, ensuring complete removal of the metal material.
It effectively removes residual metal material from the wafer edge, avoids metal tipping issues, and improves product yield.
Smart Images
Figure CN120897495A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a device manufacturing process for improving metal tilting problems. BACKGROUND
[0002] For platform products, defect-related BIN failure is one of the important reasons affecting product yield. In actual production, there is the following defect: after the bevel at the edge of the wafer passes through the chemical mechanical polishing process of the insulating medium layer, pits appear on the substrate at the edge of the wafer due to excessive polishing, and the bottom substrate silicon is exposed, so that after the subsequent pseudo-polysilicon etching, metal gate deposition, and metal gate chemical mechanical polishing steps, the remaining gate metal material in the pits cannot be polished clean, and the gate metal material remains at the edge of the wafer. In the subsequent process, the above-mentioned gate metal material residues have a risk of peeling off, affecting product yield. SUMMARY
[0003] The present application provides a device manufacturing process for improving metal tilting problems, which can solve the problem of metal residue tilting at the edge of the wafer in the related art.
[0004] The present application provides a device manufacturing process for improving metal tilting problems, which can solve the problem of metal residue tilting at the edge of the wafer in the related art. S1: providing a wafer, the wafer comprising a substrate, a barrier layer and an interlayer dielectric layer formed on the substrate, and a groove formed at an edge position of the wafer, wherein the substrate at the bottom of the groove is exposed; S2: depositing a gate metal material, the gate metal material being used to form a metal gate, and the gate material filling the groove; S3: performing a chemical mechanical polishing process on the gate metal material, and stopping at the barrier layer, wherein the gate metal material remains in the groove; S4: performing edge etching on the wafer to etch and remove the gate metal material remaining in the groove.
[0005] In some embodiments, the gate metal material comprises aluminum.
[0006] In some embodiments, in the S4, a dry etching process is used to remove the gate metal material remaining in the groove.
[0007] In some embodiments, in the S4, the duration of etching is 25-35s.
[0008] In some embodiments, before the S1, the method further comprises: providing a wafer, the wafer comprising a substrate, and a barrier layer formed on the substrate; depositing an interlayer dielectric layer; performing a chemical mechanical polishing process on the interlayer dielectric layer; performing a pseudo-polysilicon removal process on the wafer, during which the recess is formed in the edge position of the wafer.
[0009] In some embodiments, before the S2, further comprising: depositing a TaN / Ta layer.
[0010] The technical solution of the present application has at least the following advantages: 1. By adding an edge etching process after the chemical mechanical polishing process on the gate metal material, the edge etching process can effectively remove the residual gate metal material in the edge of the wafer, and the etching amount of the substrate is very small, which can effectively avoid the metal overturning problem. BRIEF DESCRIPTION OF DRAWINGS
[0011] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.
[0012] Figure 1 is a flow chart of a device manufacturing process for improving the metal overturning problem provided by an exemplary embodiment of the present application; Figures 2-7 is a schematic diagram of the structure of the edge position of the wafer in the process of performing the device manufacturing process for improving the metal overturning problem provided by an exemplary embodiment of the present application.
[0013] Explanation of reference signs: 1, substrate; 2, barrier layer; 3, interlayer dielectric layer; 4, recess; 5, gate metal material. DETAILED DESCRIPTION
[0014] The technical solutions in the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0015] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0016] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0017] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0018] The present application provides a device manufacturing process for improving the metal tilting problem, referring to Figure 1 which comprises the following steps: S1: providing a wafer, the wafer comprising a substrate, a barrier layer and an interlayer dielectric layer formed on the substrate, a groove is formed at the edge position (low step area in the figure) of the wafer, and the substrate at the bottom of the groove is exposed.
[0019] For example, a wafer is provided, referring to Figure 4 which comprises a substrate 1, a barrier layer 2 and an interlayer dielectric layer 3 formed on the substrate 1. Figure 4 The schematic diagram of the edge portion of the wafer is shown in FIG. 1, a groove 4 is formed at the edge portion of the wafer, so that the substrate 1 at the bottom of the groove 4 is exposed and no longer protected by the barrier layer 2.
[0020] In the above embodiment, the substrate 1 can be a silicon substrate 1, and the material of the barrier layer 2 can be SiN.
[0021] Further, before this step, the following processing process can also be included: Providing a wafer, the wafer comprising a substrate, a barrier layer formed on the substrate.
[0022] For example, a barrier layer 2 is formed on the substrate 1.
[0023] Depositing an interlayer dielectric layer.
[0024] For example, an interlayer dielectric layer 3 is deposited on the wafer, for example, the material of the interlayer dielectric layer 3 can be SiO2, and the interlayer dielectric layer 3 can be deposited by a PECVD process. As shown in Figure 2 The barrier layer 2 at the edge of the wafer is also covered by the interlayer dielectric layer 3.
[0025] The interlayer dielectric layer is subjected to a chemical mechanical polishing process.
[0026] Further, the interlayer dielectric layer 3 is subjected to a chemical mechanical polishing process, as shown in Figure 3 After this step, the interlayer dielectric layer 3 at the edge of the wafer is removed, and at the same time, when over-polishing occurs, the barrier layer 2 on the substrate 1 at the edge of the wafer is also thinned or even removed.
[0027] The wafer is subjected to a dummy poly removal process, and in this process, a groove is formed at the edge of the wafer.
[0028] For example, in order to form a metal gate, the wafer is subjected to a dummy poly removal process. In this process, the exposed substrate 1 at the edge of the wafer is also etched, resulting in a groove 4 at the edge of the wafer.
[0029] S2: Depositing a gate metal material for forming a metal gate, and the gate metal material fills the groove.
[0030] For example, as shown in Figure 5 The gate metal material 5 for forming a metal gate is deposited, covering the surface of the entire wafer and filling the groove 4 at the edge of the wafer.
[0031] Further, the material of the gate metal material 5 is aluminum.
[0032] Further, the gate metal material 5 can be deposited by a physical vapor deposition process.
[0033] Further, before depositing the gate metal material, the following steps can also be included: Depositing a TaN / Ta layer.
[0034] For example, the deposited TaN / Ta layer can act as a diffusion barrier layer and an adhesion layer.
[0035] S3: Subjecting the gate metal material to a chemical mechanical polishing process and stopping at the barrier layer, with the gate metal material remaining in the groove.
[0036] For example, the gate metal material 5 in the specified area is subjected to a chemical mechanical polishing process, and the polishing is stopped at the surface of the barrier layer 2, as shown in Figure 6After this step, the excess gate metal material 5 on the wafer surface is removed, but there is still excess gate metal material 5 remaining in the groove 4.
[0037] S4: edge etching is performed on the wafer to etch and remove the gate metal material remaining in the groove.
[0038] For example, in order to avoid the above-mentioned gate metal material 5 remaining in the groove 4 from peeling off in the subsequent process, i.e., the metal tilting problem, in this step, edge etching is first performed on the wafer to remove the gate metal material 5 remaining in the groove 4, as shown in FIG. 4. Figure 7
[0039] Further, in this step, a dry etching process can be used to remove the gate metal material 5 remaining in the groove, and the etching time can be set to 25-35s.
[0040] The device manufacturing process for improving the metal tilting problem provided by the embodiments of the present application can effectively remove the gate metal material remaining on the edge of the wafer by adding an edge etching process after the chemical mechanical polishing process of the gate metal material. The etching amount of the substrate is very small, and compared with the scheme of increasing the thickness of the interlayer dielectric layer, the technical solution adopted by the present application can avoid the metal tilting problem from the root.
[0041] Obviously, the above-mentioned embodiments are only examples for clear illustration, and not a limitation on the embodiments. For those skilled in the art, other different forms of changes or variations can be made on the basis of the above-mentioned description. Here, it is not necessary and impossible to enumerate all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present application.
Claims
1. A device manufacturing process for improving the problem of metal tipping, characterized in that, include: S1: A wafer is provided, the wafer including a substrate, a barrier layer and an interlayer dielectric layer are formed on the substrate, a groove is formed at the edge of the wafer, and the substrate is exposed at the bottom of the groove; S2: Deposit gate metal material, the gate metal material being used to form a metal gate, and the gate material filling the groove; S3: Perform a chemical mechanical polishing process on the gate metal material and stop at the barrier layer, leaving gate metal material remaining in the groove; S4: Perform edge etching on the wafer to remove the gate metal material remaining in the groove.
2. The device manufacturing process for improving metal tipping problems according to claim 1, characterized in that, The gate metal material includes aluminum.
3. The device manufacturing process for improving metal tilting problems according to claim 1, characterized in that, In step S4, a dry etching process is used to remove the residual gate metal material in the groove.
4. The device manufacturing process for improving metal tipping problems according to claim 1, characterized in that, In S4, the etching duration is 25~35s.
5. The device manufacturing process for improving metal tipping problems according to claim 1, characterized in that, Prior to S1, the method further includes: A wafer is provided, the wafer including a substrate on which a barrier layer is formed; Interlayer medium layer; The interlayer dielectric layer is subjected to a chemical mechanical polishing process; The wafer undergoes a pseudo-polysilicon removal process, during which the groove appears at the edge of the wafer.
6. The device manufacturing process for improving metal tipping problems according to claim 1, characterized in that, Before S2, it also includes: Deposit TaN / Ta layers.