Technological method for improving performance of CMOS image sensor

Abstract

The invention discloses a process method for improving the performance of a CMOS image sensor, and the method at least comprises the following steps: S1, providing a substrate, and growing a first P-type epitaxial layer on the substrate at a first temperature; s2, growing an N-type epitaxial layer on the first P-type epitaxial layer at a second temperature; s3, growing a second P-type epitaxial layer on the N-type epitaxial layer at a third temperature; the first temperature > the second temperature > the third temperature. According to the process method, the growth temperatures of different epitaxial layers are optimized, and the growth temperatures of the epitaxial layers are gradually reduced along the growth direction, so that the concentration distribution of doped ions is more uniform, the full well capacity is improved, and the performance of the CMOS image sensor is remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of image sensors, in particular to a process method for improving the performance of CMOS image sensors. BACKGROUND

[0002] CMOS image sensor (CIS) is a kind of semiconductor device that converts optical image into electrical signal, which is widely used in digital cameras, smart phones, tablet computers, medical devices, unmanned aerial vehicles and other emerging market fields. CIS includes photodiode for light sensing and logic circuit for processing the sensed light into electrical signal. Photodiode is the most important electrical structure in CIS, and its performance directly affects the overall performance of CIS. Full well capacity (FWC) is one of the key parameters of photodiode, which represents the number of electrons after photoelectric conversion in photodiode. Generally, the more the number of electrons, the better, because higher full well capacity can improve the sensitivity and dynamic range of image sensor.

[0003] In the manufacturing technology of existing CMOS image sensors, the method for improving full well capacity usually includes implanting N-type impurities (such as As or P) with high energy and high dose in the photodiode region. However, this method has the following problems: 1) high energy and high dose ion implantation will significantly affect the production efficiency; 2) high energy ion implantation puts higher requirements on the thickness of photoresist, increasing the process difficulty; 3) high energy ion implantation may affect the quality of silicon surface, and thus affect the performance of photodiode.

[0004] In order to solve the above problems, researchers introduced N-type epitaxial layer to replace high energy and high dose ion implantation to reduce the side effects caused by ion implantation. However, there are still some problems in introducing N-type epitaxial layer. In the formed PNP structure, the diffusion of ions caused by the difference in ion concentration makes the ion concentration not well meet the actual demand. For example, the doping concentration of N-type epitaxial layer gradually decreases from the wafer surface to the substrate, i.e. the doping concentration decreases from top to bottom, which is not uniformly distributed, resulting in low full well capacity and affecting the performance of CMOS image sensor.

[0005] The statements herein only provide background technology related to the present application, and do not necessarily constitute prior art. SUMMARY

[0006] The purpose of the present application is a process method for improving the performance of CMOS image sensor, which can effectively improve the problem of uneven ion concentration distribution, improve the full well capacity, and thus improve the performance of CMOS image sensor, by optimizing the growth temperature of different epitaxial layers and gradually reducing the growth temperature of epitaxial layers along the growth direction (close to the substrate to far from the substrate).

[0007] In order to achieve the above object, the present application provides a process method for improving the performance of CMOS image sensor, comprising at least the following steps:

[0008] Step S1, providing a substrate, growing a first P-type epitaxial layer on the substrate at a first temperature;

[0009] Step S2, growing an N-type epitaxial layer on the first P-type epitaxial layer at a second temperature;

[0010] Step S3, growing a second P-type epitaxial layer on the N-type epitaxial layer at a third temperature;

[0011] The first temperature > the second temperature > the third temperature.

[0012] Optionally, the first temperature is 1050-1150℃.

[0013] Optionally, the third temperature is 850-950℃.

[0014] Optionally, the second temperature is 950-1050℃.

[0015] Optionally, the doping concentration of the N-type epitaxial layer is 0.8E16 atom / cm 3 ~2.2E16 atom / cm 3 .

[0016] Optionally, the total thickness of the first P-type epitaxial layer, the N-type epitaxial layer and the second P-type epitaxial layer is not more than 3μm.

[0017] Optionally, the N-type epitaxial layer comprises a first N-type epitaxial layer and a second N-type epitaxial layer, the first N-type epitaxial layer is close to the first P-type epitaxial layer, the second N-type epitaxial layer is close to the second P-type epitaxial layer, and the doping concentration of the first N-type epitaxial layer is greater than that of the second N-type epitaxial layer.

[0018] Optionally, the thickness of the first N-type epitaxial layer is less than that of the second N-type epitaxial layer.

[0019] Optionally, after step S1 and before step S2, it further comprises: growing an N-type epitaxial sacrificial layer on the first P-type epitaxial layer at a fourth temperature.

[0020] Optionally, the first temperature > the fourth temperature > the third temperature.

[0021] Optionally, the thickness of the N-type epitaxial sacrificial layer is less than that of the N-type epitaxial layer.

[0022] Optionally, after step S3, the method further includes: removing the substrate, the first P-type epitaxial layer, and the N-type epitaxial sacrificial layer.

[0023] Optionally, the method for removing the substrate, the first P-type epitaxial layer, and the N-type epitaxial sacrificial layer is chemical mechanical polishing.

[0024] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0025] This invention optimizes the growth temperature of different epitaxial layers. At a first temperature, a first P-type epitaxial layer is grown on the substrate; at a second temperature, an N-type epitaxial layer is grown on the first P-type epitaxial layer; and at a third temperature, a second P-type epitaxial layer is grown on the N-type epitaxial layer. The first temperature > the second temperature > the third temperature. During ion diffusion, the ion diffusion coefficient and temperature follow the formula D = D0·exp(-E). a The diffusion coefficient (D) is proportional to the temperature (T). When the first P-type epitaxial layer and the N-type epitaxial layer are grown at higher first and second temperatures respectively, the diffusion coefficient is larger, the diffusion ability of ions in the first P-type epitaxial layer and the N-type epitaxial layer is stronger, and the diffusion quickly reaches equilibrium, with the ion concentration distribution remaining essentially unchanged. When the second P-type epitaxial layer is grown at a lower third temperature, the diffusion coefficient is smaller, the diffusion ability of ions in the second P-type epitaxial layer is weaker, and ion diffusion is less. At the same time, at the lower third temperature, the ions in the first P-type epitaxial layer and the N-type epitaxial layer basically no longer diffuse, and the ion concentration distribution eventually reaches a stable state. By gradually decreasing the growth temperature of different epitaxial layers, the distribution of doped ion concentration can be made more uniform, the full-well capacity can be increased, and thus the performance of CMOS image sensors can be significantly improved. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the flat region and the gradually decreasing region of doping concentration in an N-type epitaxial layer; where a is the flat region and b is the gradually decreasing region.

[0027] Figure 2 This is a flowchart of the process method for improving the performance of a CMOS image sensor according to the present invention.

[0028] Figure 3 This is a schematic diagram of the structure of the present invention, which grows a first P-type epitaxial layer, an N-type epitaxial layer and a second P-type epitaxial layer on a substrate.

[0029] Figure 4 This is a schematic diagram of the structure of the present invention, which grows a first P-type epitaxial layer, a first N-type epitaxial layer, a second N-type epitaxial layer and a second P-type epitaxial layer on a substrate.

[0030] Figure 5A schematic diagram of a structure of growing a first P-type epitaxial layer, an N-type epitaxial sacrificial layer, an N-type epitaxial layer and a second P-type epitaxial layer on a substrate according to the present application.

[0031] Reference signs:

[0032] Substrate 10

[0033] First P-type epitaxial layer 20

[0034] N-type epitaxial layer 30

[0035] First N-type epitaxial layer 31

[0036] Second N-type epitaxial layer 32

[0037] N-type epitaxial sacrificial layer 33

[0038] Second P-type epitaxial layer 40. DETAILED DESCRIPTION

[0039] The process method for improving the performance of CMOS image sensors according to the present application is described in further detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will become more apparent from the following description taken in conjunction with the drawings. It is to be understood that the drawings are designed solely for purposes of illustration to facilitate the ease of understanding of the present application. In order to facilitate the ease of understanding of the present application, reference is made to the drawings. It is to be understood that the structures, proportions, sizes, etc. shown in the drawings are only to be used to facilitate the ease of understanding of the present application and are not to be used to limit the present application. Any modification, change or adjustment of the structures, proportions, sizes, etc. that do not affect the effects and purposes of the present application are to be considered within the scope of the present application.

[0040] As described in the background section, although the injection of N-type impurities with higher energy and dosage in the photodiode region can improve the full well capacity, it can reduce the production efficiency, increase the process difficulty and affect the performance of the photodiode. Therefore, the N-type epitaxial layer is introduced in the photodiode region instead of high-energy and high-dosage ion implantation. However, the doping concentration of the N-type epitaxial layer gradually increases from the wafer surface to the substrate (the depth gradually increases), which can appear a flat region (as shown in a of Figure 1 and a gradual decrease region (as shown in b of Figure 1 ). The gradual decrease region is about 1 μm, i.e. the doping concentration gradually decreases from top to bottom, which is not uniformly distributed, resulting in a lower full well capacity, thereby affecting the performance of the CMOS image sensor.

[0041] To solve the above problems, the present application optimizes the growth temperature of different epitaxial layers, first, a first P-type epitaxial layer is grown on the substrate surface at a first higher temperature, ions in the first P-type epitaxial layer diffuse rapidly; then, an N-type epitaxial layer is grown at a second temperature lower than the first temperature, ions in the first P-type epitaxial layer basically no longer diffuse, while ions in the N-type epitaxial layer diffuse and quickly reach equilibrium, at this time, the ion concentration distribution in the first P-type epitaxial layer and the N-type epitaxial layer basically no longer changes; finally, a second P-type epitaxial layer is grown at a third temperature lower than the second temperature, the ability of ion diffusion in the second P-type epitaxial layer is greatly reduced, and ion diffusion is less, and at the lower third temperature, ions in the first P-type epitaxial layer and the N-type epitaxial layer basically no longer diffuse. By gradually reducing the growth temperature of different epitaxial layers, the distribution of doping ion concentration can be made more uniform.

[0042] Specifically, as shown in Figures 2-3 The present application provides a process method for improving the performance of a CMOS image sensor, at least comprising the following steps:

[0043] Step S1, providing a substrate, and growing a first P-type epitaxial layer on the substrate at a first temperature.

[0044] The first P-type epitaxial layer 20 is grown on the substrate 10 at the first temperature.

[0045] In some embodiments, the first temperature is 1050-1150°C.

[0046] Step S2, growing an N-type epitaxial layer on the first P-type epitaxial layer at a second temperature.

[0047] The N-type epitaxial layer 30 is grown on the first P-type epitaxial layer 20 at the second temperature.

[0048] The second temperature is lower than the first temperature. In some embodiments, the second temperature is 950-1050°C.

[0049] In some embodiments, the doping concentration of the N-type epitaxial layer 30 is 0.8E16 atom / cm 3 ~2.2E16 atom / cm 3 The doping concentration of the N-type epitaxial layer 30 should not be too high, if it is too high, it will cause a larger electric field strength to be formed near the PN junction, the width of the space charge region becomes narrow, and electrons and holes are more likely to pass through the PN junction barrier through quantum tunneling effect. When the electric field strength exceeds a certain threshold, tunneling phenomenon may be triggered.

[0050] Step S3, growing a second P-type epitaxial layer on the N-type epitaxial layer at a third temperature, the first temperature > the second temperature > the third temperature.

[0051] A second P-type epitaxial layer 40 is grown on the N-type epitaxial layer 30 at a third temperature.

[0052] In some embodiments, the third temperature is 850-950℃.

[0053] In some embodiments, the total thickness of the first P-type epitaxial layer 20, the N-type epitaxial layer 30 and the second P-type epitaxial layer 40 is not more than 3 μm. The thickness of each of the first P-type epitaxial layer 20, the N-type epitaxial layer 30 and the second P-type epitaxial layer 40 is set according to the process requirement, and the present application does not limit the thickness of the first P-type epitaxial layer 20 and the second P-type epitaxial layer 40. However, it is worth noting that the thickness of the N-type epitaxial layer 30 should not be too thin. When the doping concentration is constant, the thinner the N-type epitaxial layer 30, the smaller the physical volume of charge storage, and the lower the full well capacity. Therefore, the thickness of the N-type epitaxial layer 30 needs to meet the requirement of full well capacity.

[0054] In the present embodiment, the first temperature > the second temperature > the third temperature. In the process of ion diffusion, the ion diffusion coefficient and the temperature follow the formula D=D0·exp(-E a / kT), where D represents the diffusion coefficient, indicating the diffusion ability of impurity atoms in semiconductor material; D0 represents the initial diffusion coefficient, related to the type of semiconductor material and impurity atoms; E a represents the activation energy, indicating the energy barrier to be overcome by impurity atoms in the semiconductor lattice; k represents the Boltzmann constant, used for energy conversion with temperature; T represents the temperature. In this formula, the diffusion coefficient (D) is proportional to the temperature (T), the higher the temperature, the larger the diffusion coefficient, and the lower the temperature, the smaller the diffusion coefficient. First, the first P-type epitaxial layer 20 is grown at a higher first temperature, the diffusion coefficient is large, and the ions in the first P-type epitaxial layer 20 diffuse quickly; then the N-type epitaxial layer 30 is grown at a second temperature lower than the first temperature, the ions in the first P-type epitaxial layer 20 do not diffuse substantially, while the ions in the N-type epitaxial layer 30 diffuse and quickly reach equilibrium, at which time the ion concentration distribution in the first P-type epitaxial layer 20 and the N-type epitaxial layer 30 does not change substantially; finally, the second P-type epitaxial layer 40 is grown at a third temperature lower than the second temperature, the diffusion coefficient is small, the diffusion ability of the ions in the second P-type epitaxial layer 40 is weak, and the ions diffuse less, while the ions in the first P-type epitaxial layer 20 and the N-type epitaxial layer 30 do not diffuse substantially at the third temperature, and the ion concentration distribution eventually presents a stable state. By gradually reducing the growth temperature of different epitaxial layers, the distribution of doping ion concentration can be made more uniform, the full well capacity is improved, and thus the performance of the CMOS image sensor is improved.

[0055] As Figure 4As shown, in some other embodiments of the present invention, the N-type epitaxial layer 30 includes a first N-type epitaxial layer 31 and a second N-type epitaxial layer 32. The first N-type epitaxial layer 31 is close to the first P-type epitaxial layer 20, and the second N-type epitaxial layer 32 is close to the second P-type epitaxial layer 40. The doping concentration of the first N-type epitaxial layer 31 is greater than the doping concentration of the second N-type epitaxial layer 32, and the thickness of the first N-type epitaxial layer 31 is less than the thickness of the second N-type epitaxial layer 32. Since the first N-type epitaxial layer 31 is close to the first P-type epitaxial layer 20, ions in the first N-type epitaxial layer 31 can easily diffuse to the first P-type epitaxial layer 20, which reduces the ion concentration in the first N-type epitaxial layer 31. When the doping concentration of the first N-type epitaxial layer 31 is high, it can compensate for the ions lost by the first N-type epitaxial layer 31. When the ion diffusion reaches equilibrium, the ion concentration in the first N-type epitaxial layer 31 is comparable to the ion concentration in the second N-type epitaxial layer 32, which is beneficial to the uniform distribution of ion concentration in the N-type epitaxial layer 30.

[0056] like Figure 5 As shown, in some other embodiments of the present invention, after step S1 and before step S2, the method further includes: growing an N-type epitaxial sacrificial layer 33 on the first P-type epitaxial layer 20 at a fourth temperature. The N-type epitaxial sacrificial layer 33 is used as the descent region mentioned in the background art (see...). Figure 1 b) in the above will be removed in subsequent processes, which is beneficial to the uniform distribution of ion concentration and improves the full-well capacity. In order to facilitate the rapid removal of the N-type epitaxial sacrificial layer 33 in the subsequent process, the thickness of the N-type epitaxial sacrificial layer 33 can be set to be less than the thickness of the N-type epitaxial layer 30.

[0057] In some embodiments, the first temperature > the fourth temperature > the third temperature. When the first P-type epitaxial layer 20 and the N-type epitaxial sacrificial layer 33 are grown at higher first and fourth temperatures, respectively, the diffusion coefficient is larger, the diffusion ability of ions in the first P-type epitaxial layer 20 and the N-type epitaxial sacrificial layer 33 is stronger, and the diffusion quickly reaches equilibrium, so the ion concentration distribution basically no longer changes. When the second P-type epitaxial layer 40 is grown at a lower third temperature, the diffusion coefficient is smaller, the diffusion ability of ions in the second P-type epitaxial layer 40 is weaker, the ion diffusion is less, and at the third temperature, the ions in the first P-type epitaxial layer 20 and the N-type epitaxial sacrificial layer 33 basically no longer diffuse.

[0058] Following step S3, the process further includes removing the substrate 10, the first P-type epitaxial layer 20, and the N-type epitaxial sacrificial layer 33 from the back side of the wafer to obtain a PN structure with a uniform ion concentration distribution. The method for removing the substrate 10, the first P-type epitaxial layer 20, and the N-type epitaxial sacrificial layer 33 is chemical mechanical polishing.

[0059] In summary, the process method for improving the performance of the CMOS image sensor provided by the application grows the first P-type epitaxial layer and the N-type epitaxial layer at a relatively high first temperature and a relatively high second temperature, respectively, the diffusion coefficient is relatively large, the diffusion ability of the ions in the first P-type epitaxial layer and the N-type epitaxial layer is relatively strong and the diffusion reaches equilibrium very quickly, and the ion concentration distribution basically no longer changes; the second P-type epitaxial layer is grown at a relatively low third temperature, the diffusion coefficient is relatively small, the diffusion ability of the ions in the second P-type epitaxial layer is relatively weak, and the ion diffusion is small, and meanwhile, the ions in the first P-type epitaxial layer and the N-type epitaxial layer basically no longer diffuse at the relatively low third temperature, and the ion concentration distribution finally presents a stable state. By gradually reducing the growth temperature of different epitaxial layers, the distribution of the doping ion concentration can be made more uniform, the full well capacity is improved, and thus the performance of the CMOS image sensor is significantly improved.

[0060] It should be noted that, in this document, the terms "comprise", "comprising", or any other variant thereof are intended to cover a non-exclusive inclusion, such that processes, methods, articles, or apparatuses that comprise a list of elements are not limited to those elements, but can also include other elements not expressly listed, or inherent to such processes, methods, articles, or apparatuses. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0061] In the present application, unless otherwise explicitly specified and limited, "on" or "under" of a first feature to a second feature can include that the first and second features are in direct contact, or can include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, "on", "above" and "over" of a first feature to a second feature includes that the first feature is directly above and obliquely above the second feature, or only means that the first feature is higher in horizontal height than the second feature. "Under", "below" and "underneath" of a first feature to a second feature includes that the first feature is directly below and obliquely below the second feature, or only means that the first feature is lower in horizontal height than the second feature.

[0062] Although the content of the present application has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present application. After reading the above content, various modifications and alternatives of the present application will be apparent to those skilled in the art. Therefore, the protection scope of the present application should be defined by the appended claims.

Claims

1. A process method for improving the performance of a CMOS image sensor, characterized in that, Include at least the following steps: Step S1: Provide a substrate, and grow a first P-type epitaxial layer on the substrate at a first temperature; Step S2: At the second temperature, an N-type epitaxial layer is grown on the first P-type epitaxial layer; Step S3: At the third temperature, a second P-type epitaxial layer is grown on the N-type epitaxial layer; The first temperature > the second temperature > the third temperature.

2. The method as described in claim 1, characterized in that, The first temperature is 1050℃-1150℃.

3. The method as described in claim 1, characterized in that, The third temperature is 850℃-950℃.

4. The method as described in claim 1, characterized in that, The second temperature is 950℃-1050℃.

5. The method as described in claim 1, characterized in that, The doping concentration of the N-type epitaxial layer is 0.8E16 atom / cm³. 3 ~2.2E16 atom / cm 3 .

6. The method as described in claim 1, characterized in that, The total thickness of the first P-type epitaxial layer, the N-type epitaxial layer, and the second P-type epitaxial layer does not exceed 3 μm.

7. The method as described in claim 1, characterized in that, The N-type epitaxial layer includes a first N-type epitaxial layer and a second N-type epitaxial layer. The first N-type epitaxial layer is close to the first P-type epitaxial layer, and the second N-type epitaxial layer is close to the second P-type epitaxial layer. The doping concentration of the first N-type epitaxial layer is greater than the doping concentration of the second N-type epitaxial layer.

8. The method as described in claim 7, characterized in that, The thickness of the first N-type epitaxial layer is less than the thickness of the second N-type epitaxial layer.

9. The method as described in claim 1, characterized in that, After step S1 and before step S2, the process further includes: growing an N-type epitaxial sacrificial layer on the first P-type epitaxial layer at a fourth temperature.

10. The method as described in claim 9, characterized in that, The first temperature > the fourth temperature > the third temperature.

11. The method as described in claim 9, characterized in that, The thickness of the N-type epitaxial sacrificial layer is less than the thickness of the N-type epitaxial layer.

12. The method as described in claim 9, characterized in that, After step S3, the process further includes: removing the substrate, the first P-type epitaxial layer, and the N-type epitaxial sacrificial layer.

13. The method as described in claim 12, characterized in that, The method for removing the substrate, the first P-type epitaxial layer, and the N-type epitaxial sacrificial layer is chemical mechanical polishing.

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