Chip package with glass interposer

Abstract

A chip package has a package substrate including a top surface. The first chip module and the second chip module are mounted over a top surface of the package substrate. The first interposer is disposed between the package substrate and the first and second chip modules, and includes a glass interposer. The first interposer couples the first chip module and the second chip module to the package substrate. An interconnect bridge is disposed in the cavity of the glass interposer. The interconnect bridge includes circuitry connecting the circuitry of the first chip module to the circuitry of the second chip module.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 463,259, filed May 1, 2023, which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] Examples of the present disclosure relate generally to chip packages, and in particular to chip packages having integrated circuit (IC) dies disposed on a glass interposer. BACKGROUND

[0004] Electronic devices such as tablets, computers, copiers, digital cameras, smartphones, control systems, and automated teller machines, among others, often employ electronic components that utilize chip packages to increase functionality and improve component density. Conventional chip package solutions often utilize a package substrate (often in conjunction with a through-silicon via (TSV) interposer) to enable multiple integrated circuit (IC) dies to be mounted to a single package substrate. The IC dies can include memory, logic components, or other IC devices.

[0005] Wafer-level multi-chip package technology has been developed to combine multiple dies side-by-side on a silicon interposer in order to achieve better interconnect density and performance. The individual chips are bonded on the silicon interposer through micro-bumps, forming a chip-on-wafer (CoW). The CoW is then thinned, such that through-silicon vias are exposed. This is followed by C4 bump formation and singulation. The CoWoS package is completed by bonding to a package substrate. However, due to limitations of the reticle, wafer-based packages for large chip modules have limited scalability.

[0006] Accordingly, there is a need for an improved chip package that is scalable for larger chip modules. SUMMARY

[0007] A chip package has a first chip module and a second chip module mounted over a top surface of a package substrate. A first interposer is disposed between the package substrate and the first chip module and the second chip module and includes a glass interposer. The first interposer couples the first chip module and the second chip module to the package substrate. An interconnect bridge is disposed in a cavity of the glass interposer. The interconnect bridge includes circuitry that connects circuitry of the first chip module to circuitry of the second chip module. In one example, the first interposer includes an interconnect wiring structure disposed on a top surface of the glass interposer and located under the first chip module and the second chip module. The interconnect wiring structure can include one or more redistribution layers having circuitry that connects circuitry of the interconnect bridge to circuitry of the first chip module and the second chip module. The one or more redistribution layers also include circuitry that connects circuitry of the first chip module and the second chip module to circuitry of the package substrate.

[0008] In another example, a method for manufacturing a chip package is provided that includes mounting an interconnect bridge in a cavity of a first interposer having a glass interposer. At least one integrated circuit die is mounted to a second interposer to form a first integrated circuit chip module. For example, the first chip module can include a first circuit die and a second circuit die mounted to the second interposer. Similarly, at least one integrated circuit die is mounted to a third interposer to form a second integrated circuit chip module. For example, the second chip module can include a third circuit die and a fourth circuit die mounted to the second interposer. The first chip module and the second chip module are mounted on the first interposer. Circuitry of the interconnect bridge connects circuitry of the first chip module to circuitry of the second chip module. The first chip module and the second chip module and the first interposer are mounted on a package substrate. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order that the manner in which the above-recited features can be understood, a more particular description can be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings show only typical example implementations and are therefore not to be considered limiting of its scope.

[0010] Figure 1 is a schematic cross-sectional view of a chip package having an interposer made of glass and an interconnect bridge disposed in the interposer.

[0011] Figure 2 is Figure 1 is a schematic partial view of a portion of the chip package of

[0012] Figure 3is a flowchart of a method for manufacturing a chip package having a chip package having a glass interposer and an interconnect bridge coupling a first chip module to a second chip module.

[0013] For ease of understanding, the same reference numbers will be used in different drawings to designate the same elements. An element of one example can be advantageously incorporated into other examples. DETAILED DESCRIPTION

[0014] An improved chip package and method for manufacturing the same are described herein. The improved chip package uses a glass interposer to utilize the geometry of a glass panel for chip packaging. Two chip modules are mounted on the glass interposer, each chip module including a plurality of dies. The glass interposer is then mounted on a package substrate. The two chip modules are coupled via an interconnect bridge disposed in the glass interposer. In some embodiments, a photonic connector is mounted on the glass interposer.

[0015] Turning now to Figure 1 , Figure 1 is a schematic cross-sectional view of a chip package 100 having a first chip module 102 and a second chip module 104, a first interposer 150, and a package substrate 108. The first chip module 102 and the second chip module 104 are disposed laterally on a top surface 172 of the first interposer 150. In one embodiment, the first interposer 150 includes a glass interposer 405. The first interposer 150 is disposed above the package substrate 108. In one embodiment, the glass interposer 405 can be manufactured from a glass panel. The glass interposer 405 can have a thickness in the range of 200 pm to 1500 pm, such as 300 pm to 400 pm or 800 pm to 1200 pm.

[0016] In Figure 1In the depicted example, the first chip module 102 includes a first IC die 201, a second IC die 202, and a third IC die 203 laterally disposed on a second interposer 208. The second chip module 104 includes a fourth IC die 204 and a fifth IC die 205 laterally disposed on a third interposer 209. In this example, the first IC die 201 and the fourth IC die 204 can be core dies (e.g., logic or processor dies, such as field programmable gate arrays, application specific integrated circuits ASICs, or other digital signal processing chips). The second IC die 202, the third IC die 203, and the fifth IC die 205 can be memory devices, such as high bandwidth memory (“HBM”). However, it is contemplated that the IC dies 201-205 can be any suitable combination of logic and memory devices, such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), memory devices such as high bandwidth memory (HBM), optical devices, processors, or other IC logic or memory structures. One or more of the IC dies 206 can optionally include optical devices, such as photodetectors, lasers, light sources, etc.

[0017] The second interposer 208 and the third interposer 209 can be silicon interposers, organic interposers, ceramic interposers, glass interposers, or suitable material stacks through which interconnect routing can be disposed. The bottom surface of the second interposer 208 and the bottom surface of the third interposer 209 face the top surface 172 of the first interposer 150.

[0018] Although Figure 1 Although five IC dies 201-205 are shown, the total number of IC dies disposed on the second interposer 208 and the third interposer 209 can range from two to as many as can fit within the chip modules 102, 104. Additionally, one or more dies can be stacked directly on one or more of the IC dies 201-205. Filler material 168 can be disposed between the IC dies 201-205 and the second interposer 208 and the third interposer 209 to provide structural integrity to the chip modules 102, 104.

[0019] Each of the IC dies 201-205 includes internal functional circuitry 221-225 coupled to contact pads (not shown) exposed on the bottom surface of the IC dies 201-205 by internal wiring 231-235. The contact pads exposed on the bottom surface of the IC dies 201-205 are coupled to the internal wiring 252, 256 of the internal circuitry 238 of their respective interposers 208, 209 by interconnects 262 (e.g., solder micro-bumps). The internal wiring 252 provides communication between the IC dies 201-205, for example, between the first IC die 201 and the second IC die 202 or between the fourth IC die 204 and the fifth IC die 205. The internal wiring 256 provides communication between the IC dies 201-205 and the first interposer 150, for example, between the first IC die 201 and the first interposer 150 or between the fourth IC die 204 and the first interposer 150. The interconnects 262 provide mechanical and electrical connections between the IC dies 201-205 and the first interposer 208 and the second interposer 209. The fill material 169 can be disposed between the chip modules 102, 104 and the first interposer 150 to provide structural integrity.

[0020] The bottom surfaces of the second interposer 208 and the third interposer 209 face and overlap the top surface 172 of the first interposer 150. Interconnects 240, which can be, for example, controllable collapse chip connections (C4 balls), couple a portion of the internal wiring 256 of the second interposer 208 and the third interposer 209 to circuitry 236 formed through the first interposer 150. The interconnects 240 provide mechanical and electrical connections between the second interposer 208 and the third interposer 209 and the first interposer 150. In one embodiment, the circuitry 236 of the first interposer 150 includes circuitry through one or more redistribution layers 270 and a glass interposer 405 of the first interposer 150. In one example, two redistribution layers 270 are formed on the top surface 407 of the glass interposer 405. The redistribution layers 270 can be used to expand the pitch of the interconnects 240.

[0021] In one embodiment, a portion of the internal wiring 256 of the second interposer 208 and the third interposer 209 is connected to an interconnect bridge 180 disposed in the first interposer 150. The interconnect bridge 180 provides communication between the first chip module 102 and the second chip module 104. In one example, the interconnect bridge 180 is an embedded multi-die interconnect bridge (EMIB) with high density wiring. In another example, the interconnect bridge 180 is a silicon-based integrated circuit die with internal high density solid state wiring to provide communication between the first chip module 102 and the second chip module 104. In some examples, the interconnect bridge 180 configured as a silicon-based integrated circuit die has only solid state wiring without active circuit elements such as transistors, etc.

[0022] A bottom surface 409 of the first interposer 150 faces and overlaps the top surface 124 of the package substrate 108. Interconnects 110, which can be, for example, controlled collapse chip connections (C4 balls), couple a portion of the circuitry 236 of the first interposer 150 to the circuitry 136 formed through the package substrate 108. The interconnects 110 provide mechanical and electrical connections between the package substrate 108 and the first interposer 150.

[0023] Some of the circuitry in the circuitry 136 formed in the package substrate 108 terminates at contact pads (not shown) exposed on a bottom surface 126 of the package substrate 108 facing away from the first interposer 150. Solder balls 116, for example, a ball grid array (BGA), are disposed on the contact pads exposed on the bottom surface 126 of the package substrate 108. The solder balls 116 are used to couple the chip package 100 to a printed circuit board 118 (shown in dashed lines) to form an electronic device.

[0024] In one embodiment, the chip package 100 includes a photonic connector 310 attached to the first interposer 150. The photonic connector 310 includes a fiber optic cable 312 for connecting to an optical device. A bottom surface of the photonic connector 310 faces and overlaps the top surface 172 of the first interposer 150. Interconnects 240 couple circuitry of the photonic connector 310 to the circuitry 236 formed through the first interposer 150. The interconnects 240 provide mechanical and electrical connections between the photonic connector 310 and the first interposer 150. In one embodiment, an electronic integrated circuit (EIC) 315 disposed in the first interposer 150 provides communication between the second chip module 104 and the photonic connector 310. The EIC 315 can function as an electro-optical converter. In some embodiments, a co-packaged cable 313 is mounted on the first interposer 150.

[0025] In one embodiment, the first interposer 150 and the chip modules 102, 104 can be fabricated separately and then assembled together to form the chip package 100. Figure 2 An enlarged partial view of an exemplary embodiment of the first interposer 150 is illustrated. The first interposer 150 includes a glass interposer 405 provided with a plurality of vias 410. In some examples, the vias 410 are formed through the glass interposer 405, which can have a thickness of about 300 pm to about 400 pm. Pads 412 are formed on the top and bottom surfaces of the glass interposer 405. An interconnect bridge 180 is disposed in a cavity 415 formed in the glass interposer 405. In one example, the interconnect bridge 180 is an embedded multi-die interconnect bridge (EMIB) with high density wiring. The interconnect bridge 180 can be attached to the glass interposer 405 using any suitable mechanism, such as a die attach tape 183.

[0026] An interconnect wiring structure is formed on the exposed surfaces of the glass interposer 405. In this example, the interconnect wiring structure is embodied as one or more redistribution layers, such as a first redistribution layer 421 and a second redistribution layer 431. Each of the redistribution layers 421, 431 can include three or more patterned metal layers disposed between dielectric layers. In one example, the metal layers are copper plated, and the dielectric layers are oxides. The patterned metal layers are used to form pads 423, 433 and lines, which are interconnected by vias to form electrical routing circuitry through the redistribution layers 421, 431. The electrical routing circuitry through the redistribution layers 421, 431 connects the functional circuitry 236 of the first interposer 150 to the internal wiring 256 of the first and second chip modules 102, 104. For example, one pad 433 of the routing circuitry of the second redistribution layer 431 terminates at a solder interconnect 240, while the routing circuitry of the second redistribution layer 431 connects the pad 433 to a pad 423 of the first redistribution layer 421. In turn, the routing circuitry of the first redistribution layer 421 connects the pad 423 to a pad 412 of the glass interposer 405. The redistribution layers 421, 431 also connect the internal wiring 256 of the first and second chip modules 102, 104 to the functional circuitry of the interconnect bridge 180. In this way, the redistribution layers 421, 431 can be formed directly on the exposed top surface of the glass interposer 405 without any intervening solder connections. The solder interconnect 240 is plated or otherwise formed on the pad 433 of the second redistribution layer 431.

[0027] Figure 3 is a flowchart of a method 500 for fabricating a chip package having a glass interposer and an interconnect bridge coupling a first chip module and a second chip module. The method 500 can be used to fabricate the chip package 100 described above or other similar chip packages.

[0028] The method 500 begins at operation 502, in which an interconnect bridge 180 is mounted in a cavity 415 of a first interposer 150. In this example, the first interposer 150 comprises a glass interposer 405. The interconnect bridge 180 is an embedded multi-die interconnect bridge (EMIB) having high density wiring. In this example, the interconnect bridge 180 is disposed in a cavity formed in the glass interposer 405. The glass interposer 405 can have a thickness of about 300 pm to about 400 pm, and a plurality of vias 410 formed through the glass interposer 405. In some embodiments, interconnect wiring structures are formed on exposed surfaces of the glass interposer 405 and connected to the vias 410. In this example, the interconnect wiring structures are embodied as one or more redistribution layers, such as two redistribution layers 421, 431. In some embodiments, the glass interposer 405 can have a thickness of about 800 pm to 1200 pm. For these thicker glass interposers, a plurality of pillar vias are formed in the glass interposer 405 to a desired depth, rather than through the glass interposer 405.

[0029] At operation 504, a first integrated circuit (IC) die 201 and a second integrated circuit die 202 are mounted to the second interposer 208 via the interconnects 262 to form the first chip module 102. At operation 504, a fill material 168 can also be disposed on the second interposer 208 to fill the inter-die gap laterally defined between the IC dies 201, 202. In some embodiments, three or more dies (e.g., a third IC die 203) can be mounted to the second interposer 208.

[0030] At operation 506, a fourth integrated circuit (IC) die 204 and a fifth integrated circuit die 205 are mounted to the second interposer 208 via the interconnects 262 to form the second chip module 104. At operation 506, a fill material 168 can also be disposed on the third interposer 209 to fill the inter-die gap laterally defined between the IC dies 204, 205. In some embodiments, three or more dies can be mounted to the third interposer 209. It is contemplated that operations 504 and 506 can be performed prior to operation 502.

[0031] At operation 508, the first chip module 102 and the second chip module 104 are mounted on the first interposer 150. At operation 508, the solder interconnects 240 electrically and mechanically couple the first chip module 102 and the second chip module 104 to the first interposer 150. In this example, the first chip module 102 and the second chip module 104 are mounted over the interconnect wiring structures of the first interposer 150, for example, over the two redistribution layers 421, 431. The first chip module 102 and the second chip module 104 are electrically connected to the circuitry of the interconnect bridge 180. The interconnect bridge 180 provides communication between the first chip module 102 and the second chip module 104. In embodiments where the glass interposer 405 includes a post via instead of a glass via, a grinding process can be performed on the glass interposer 405 to expose the post via for connection to the package substrate 108.

[0032] At operation 510, the first chip module 102 and the second chip module 104 and the first interposer 150 are mounted on the package substrate 108. At operation 510, the interconnects 110 electrically and mechanically couple the first chip module 102 and the second chip module 104 and the first interposer 150 to the package substrate 108. In one embodiment, the solder balls 116 are disposed on the bottom surface 126 of the package substrate 108 to form the chip package 100. The solder balls 116 can be used to electrically and mechanically couple the chip package 100 to the printed circuit board 118.

[0033] At operation 512, optionally, the photonic connector 310 is mounted to the top surface of the first interposer 150. At operation 512, the electronic integrated circuit 315 is disposed in the glass interposer 405 of the first interposer 150. The electronic integrated circuit 315 couples the photonic connector 310 to the second chip module 104. The photonic connector 310 can include a fiber optic cable 312 for connection to an optical device. It should be noted that operation 512 can be performed prior to operations 508 or 510.

[0034] An improved chip package and method for manufacturing the same has been described that provides a chip package that includes a first interposer made of glass. In this regard, the glass interposer can be manufactured from a glass panel that advantageously provides a scalable solution for large mask module based on the geometry of the glass panel (e.g., rectangular, including square). The chip package described above advantageously enables a photonic connector to be included in the chip package and an electronic integrated circuit die to be embedded in the glass interposer.

[0035] While the foregoing is directed to particular examples, other and additional examples can be devised without departing from the basic scope of the application, and the scope of the application is determined by the following claims.

Claims

1. A chip package, the chip package comprising: A packaging substrate having a top surface; A first chip module is mounted above the top surface of the packaging substrate; The second chip module is mounted above the top surface of the packaging substrate; A first interposer layer is disposed between the packaging substrate and the first chip module and the second chip module, and includes a glass interposer layer, wherein the first interposer layer connects the first chip module and the second chip module to the packaging substrate; and An interconnect bridge is disposed in the cavity of the glass interposer, and the interconnect bridge has circuitry for connecting the circuitry of the first chip module to the circuitry of the second chip module.

2. The chip package according to claim 1, wherein, The first interposer layer further includes an interconnect wiring structure disposed on the top surface of the glass interposer layer and located below the first chip module and the second chip module.

3. The chip package according to claim 2, wherein, The interconnect wiring structure includes one or more redistribution layers, the one or more redistribution layers having circuitry that connects the circuitry of the interconnect bridge to the circuitry of the first chip module and the second chip module.

4. The chip package according to claim 2, wherein, The interconnect wiring structure includes one or more redistribution layers having circuitry that connects the circuitry of the first chip module and the second chip module to the circuitry of the packaging substrate.

5. The chip package according to claim 1, wherein the chip package further comprises a photonic connector mounted on the top surface of the first interposer layer.

6. The chip package according to claim 5, further comprising an electronic integrated circuit disposed in the first interposer layer, the electronic integrated circuit providing communication between the second chip module and the photonic connector.

7. The chip package according to claim 5, wherein, The photonic connector includes an optical fiber cable.

8. The chip package according to claim 1, wherein, The first chip module includes a first die mounted to a second interposer layer, and the second chip module includes a second die mounted to a third interposer layer.

9. The chip package according to claim 8, wherein, The first chip module further includes a third die mounted to the second interposer layer, and the second chip module further includes a fourth die mounted to the third interposer layer.

10. The chip package according to claim 1, wherein, The interconnect bridge includes high-density cabling.

11. A chip package, the chip package comprising: A packaging substrate having a top surface; A first chip module is mounted above the top surface of the packaging substrate; The second chip module is mounted above the top surface of the packaging substrate; A first interposer layer is disposed between the packaging substrate and the first chip module and the second chip module, and includes a glass interposer layer, wherein the first interposer layer connects the first chip module and the second chip module to the packaging substrate; A photonic connector, wherein the photonic connector is mounted on the top surface of the first interposer layer; and An electronic integrated circuit is disposed in the first interposer layer, and the electronic integrated circuit provides communication between the second chip module and the photonic connector.

12. The chip package of claim 11, further comprising an interconnect bridge disposed in the glass interposer, the interconnect bridge having circuitry for connecting the circuitry of the first chip module to the circuitry of the second chip module.

13. The chip package according to claim 12, wherein, The first interposer layer further includes a redistribution layer disposed on the top surface of the glass interposer layer and located below the first chip module and the second chip module. The redistribution layer includes circuitry for connecting the circuitry of the interconnect bridge to the circuitry of the first chip module and the second chip module.

14. A method for manufacturing a chip package, the method comprising: The interconnect bridge is installed in the cavity of the first interposer layer, which has a glass interposer layer; A first integrated circuit (IC) die and a second integrated circuit die are mounted onto a second interposer layer to form a first chip module; The third integrated circuit (IC) die and the fourth integrated circuit die are mounted onto the third interposer layer to form the second chip module; The first chip module and the second chip module are mounted on the first intermediary layer; The circuitry of the first chip module is connected to the circuitry of the second chip module using the interconnect bridge circuitry. as well as The first chip module, the second chip module, and the first interposer are mounted on the packaging substrate.

15. The method of claim 14, further comprising mounting a photonic connector to the first interposer layer.

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