Grating-like microstructure and preparation method thereof
By using a low-temperature dry etching process to generate a SiOxFy passivation layer with SF6 and O2 gases, combined with low bias power and plasma etching, the problems of nanoscale narrow linewidth and sidewall perpendicularity in silicon etching are solved, realizing high-precision nanostructure processing, which is suitable for MEMS and silicon photonic devices.
Patent Information
- Application Number
- CN202511086856.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-04
- Publication Date
- 2025-11-07
AI Technical Summary
Existing silicon etching techniques struggle to achieve nanoscale narrow linewidths with good sidewall perpendicularity, especially at low temperatures where it is difficult to control sidewall roughness and perpendicularity during the etching process, affecting the electrical/optical performance of devices.
A low-temperature dry etching process is adopted, using a mixture of SF6 and O2 gases to control the etching temperature to no higher than -50℃. Combined with low bias power and plasma etching to remove the mask, a dense SiOxFy passivation layer is generated, achieving vertical etching and suppressing sidewall damage.
The etching morphology with high aspect ratio and sub-nanometer surface roughness was achieved under low temperature conditions, ensuring the processing quality of high-precision nanostructures, which is suitable for the fabrication of MEMS and silicon photonic devices.
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Figure CN120903433A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of micro-nano manufacturing, and particularly relates to a kind of grating-like microstructure and its preparation method. BACKGROUND
[0002] High-precision patterning of silicon microstructure has important applications in micro-electro-mechanical system (MEMS), silicon-based optoelectronic devices, advanced packaging and many other fields. With the development of devices towards miniaturization, complex structure and high integration, higher requirements are put forward for silicon etching process, especially in terms of perpendicularity, aspect ratio and roughness.
[0003] Traditional silicon etching methods mainly include wet etching and dry etching. Among them, although the wet etching process is simple and low in cost, its anisotropy is poor, and it is difficult to achieve nanoscale narrow line width and good sidewall perpendicularity etching morphology, especially for nanoscale structure control, which is prone to problems such as undercutting and structure deformation. In addition, the roughness of the groove surface during etching process is difficult to achieve sub-nanometer level fine control, which is not suitable for precision machining of nanoscale narrow line width vertical structure. In the existing dry etching process, in order to achieve nanoscale narrow line width and sidewall vertical etching morphology, it is often necessary to increase the proportion of physical ion bombardment, but excessive bombardment caused by this method can increase the roughness of the groove surface after etching, which ultimately affects the electrical / optical performance of the device, and it is difficult to meet the high-precision requirements of silicon microstructure. SUMMARY
[0004] The purpose of the present application is to provide a kind of grating-like microstructure and its preparation method.
[0005] In order to achieve the above purpose, the present application provides the following technical scheme:
[0006] The present application provides a kind of grating-like microstructure and its preparation method, which comprises the following steps: after setting a mask plate on the surface of a silicon substrate, low-temperature dry etching and removing the mask plate are carried out in sequence to obtain the grating-like microstructure.
[0007] The conditions of the low-temperature dry etching include: the etching temperature is not higher than-50℃, the working gas includes SF6 and O2, and the bias power is 10-50W.
[0008] Preferably, the etching temperature is-50 to-150℃.
[0009] Preferably, the chamber pressure of the low-temperature dry etching is 5-15mTorr.
[0010] Preferably, the ICP power of the low-temperature dry etching is 200-450W.
[0011] Preferably, the flow rate of SF6 is 20-60sccm, and the flow rate of O2 is 1-8sccm.
[0012] Preferably, the flow rate ratio of SF6 to O2 is not less than 5:2.
[0013] Preferably, the mask plate comprises a hard mask plate or a soft mask plate.
[0014] The material of the hard mask plate comprises at least one of metal, amorphous carbon, oxide and nitride.
[0015] The material of the soft mask plate comprises any one of electron beam glue, fluorine-containing polymer, photoresist and polystyrene.
[0016] Preferably, the thickness of the hard mask plate is 10-100nm.
[0017] The thickness of the soft mask plate is 90-130nm.
[0018] Preferably, the method for removing the soft mask plate is plasma etching.
[0019] The conditions of the plasma etching comprise: using oxygen as the reaction gas, the flow rate of the reaction gas is 50-100sccm, the gas pressure is 5-15Pa, and the power is 150-250W.
[0020] The application further provides a class grating microstructure prepared by the preparation method.
[0021] The depth of a single groove is 1000-2000nm, and the depth-width ratio of a single groove is 1:2-5:1.
[0022] The number of the grooves is not less than two.
[0023] Compared with the prior art, the application has the following beneficial effects:
[0024] (1) The etching gas used in the application is a mixed gas of sulfur hexafluoride (SF6) and oxygen (O2), wherein SF6 provides fluorine radicals (F*) required for etching, and O2 introduces oxygen radicals (O*) which, in the etching process, react with silicon atoms to generate a non-volatile passivation layer SiO x F y In particular, under low temperature conditions, due to the reduced activity of free radicals, SiO x F yThe deposition is more stable and dense, and effectively inhibits lateral etching. The present application is based on the dry etching mechanism of SF6 and O2 mixed synergy under low temperature conditions, strictly controls the flow ratio between SF6 and O2, generates non-volatile amorphous SiO x F y The passivation layer effectively protects and controls the nanometer structure sidewall. The passivation layer is mainly generated by the reaction of Si, SF6 and O2, and preferentially deposits on the inner wall of the trench to form a continuous and dense protective film; at the same time, the low-temperature environment significantly improves the density and stability of SiO x F y The density and stability of SiO, so it is not easy to decompose or desorb due to thermal diffusion, thereby maintaining good passivation effect during the entire etching process. At the same time, due to the reduction of plasma electron temperature at low temperature, the dissociation of free radicals caused by high-energy electrons is reduced, so that the concentration of fluorine radicals (F*) will increase, which can occur faster spontaneous reaction with surface silicon atoms, generating volatile silicon tetrafluoride (SiF4), promoting the directional etching in the vertical direction, thereby realizing the processing of highly anisotropic structure.
[0025] (2) The present application controls the bias power, and the ion physical bombardment energy generated at low bias power is appropriate and directional, mainly concentrating on the bottom groove to remove the surface passivation film, and having little effect on the sidewall passivation layer and the surface of the mask plate. This selective removal mechanism of the passivation layer makes the etching occur only in the vertical direction, and the sidewall is completely preserved, thereby effectively inhibiting lateral etching and obtaining highly anisotropic etching profile, and significantly improving the verticality of the sidewall; at the same time, low temperature can also prevent the softening, flowing or deformation of the electron beam glue due to heat accumulation, avoiding pattern expansion or collapse. Especially in nanoscale line width structure, this process can keep the pattern edge clear and size stable, providing reliable guarantee for high-precision nanometer processing. Therefore, this process can realize nanometer structure etching with excellent sidewall verticality and accurate controllable morphology under low temperature conditions, and has excellent process advantages and application potential.
[0026] (3)In the normal temperature dry etching, the reaction by-products or intermediates are easy to re-deposit on the surface to form particles, deposition film or cross-linked polymer layer, thus causing surface contamination and roughness increase. In the low temperature etching process adopted by the present application, due to the reduced reaction activity and lower free radical energy, the side reaction rate is significantly slowed down, and the deposition of intermediate products is difficult to generate, thus effectively inhibiting the surface re-deposition and polymerization phenomenon, the etching process is cleaner, the particle adhesion is reduced, and the atomic level flatness of the etched surface is improved. In addition, the process also integrates the condition of relatively low bias power, the generated ion energy is low, which avoids the physical damage such as 'carbon pit effect', lattice defects and edge ablation that may be caused in the conventional high-energy etching. Therefore, the present application can achieve high anisotropic etching while obtaining extremely low surface roughness, and the precision of the etched silicon surface can reach sub-nanometer level, which meets the strict requirements of high-precision nanometer processing on surface quality.
[0027] (4)The method provided by the present application comprehensively inhibits the isotropic drilling effect of thermochemistry at low temperature, implements atomic layer level peeling by directional bombardment of low-energy ions, and inhibits side wall etching by more dense and stable in-situ plasma passivation film. Through the linkage of various control parameters in the reaction chamber to achieve dynamic balance, and with the help of faster reaction between high-concentration fluorine radicals and silicon at the bottom of the groove at low temperature, high aspect ratio (>10:1) silicon microstructure etching can be realized in one etching process, and the etching depth exceeds 1 micrometer. The method can realize excellent side wall perpendicularity and sub-nanometer level surface roughness of the etching morphology, thereby ensuring the morphology fidelity of high aspect ratio nanostructure, meeting the strict requirements of high-end devices on atomic level flat interface, and being beneficial to the significant improvement of subsequent structure quality and device performance. The high-quality, nanometer-level narrow-line-width grating-like microstructure obtained by the present application is suitable for manufacturing requirements in the fields of MEMS devices, silicon photonics devices and the like. The technical scheme of the present application breaks through the limitations of traditional silicon etching process in structure precision and process efficiency, and provides a new solution for the manufacturing of high-performance micro-nano devices. The method provided by the present application is especially suitable for the preparation scene of silicon microstructure array with high precision, high density and low damage, and has wide application prospect and industrial value. BRIEF DESCRIPTION OF DRAWINGS
[0028] Figure 1 It is a flowchart of the preparation method of the present application;
[0029] Figure 2 It is a scanning electron microscope image of the cross section of the grating-like microstructure obtained in Example 1;
[0030] Figure 3 It is an atomic force microscope scanning image of the grating-like microstructure obtained in Example 1;
[0031] Figure 4 It is a scanning electron microscope image of the cross section of the grating-like microstructure obtained in Example 2;
[0032] Figure 5 Atomic force microscope scanning diagram of the grating-like microstructure obtained in Example 2;
[0033] Figure 6 Scanning electron microscope diagram of the cross section of the grating-like microstructure obtained in Comparative Example 1;
[0034] Figure 7 Scanning electron microscope diagram of the cross section of the grating-like microstructure obtained in Comparative Example 2. DETAILED DESCRIPTION
[0035] The application provides a preparation method of a grating-like microstructure, comprising the following steps: after a mask plate is arranged on the surface of a silicon substrate, sequentially performing low-temperature dry etching and removing the mask plate to obtain the grating-like microstructure.
[0036] The conditions of the low-temperature dry etching comprise that the etching temperature is not higher than-50 DEG C, and the working gas comprises SF6 and O2; the bias power is 10-50 W.
[0037] Figure 1 The application provides a flowchart of the preparation method, and the preparation method is described in detail below. Figure 1
[0038] In the application, the silicon substrate is preferably a P<100> type silicon substrate.
[0039] In the application, before the mask plate is arranged, the silicon substrate is preferably subjected to pretreatment, and the pretreatment preferably comprises sequentially performing cleaning and drying, the cleaning is preferably ultrasonic cleaning by using acetone and IPA, and the drying mode is preferably nitrogen blowing.
[0040] In the application, the mask plate preferably comprises a hard mask plate or a soft mask plate; the material of the hard mask plate preferably comprises at least one of metal, amorphous carbon, oxide and nitride; the metal comprises Cr, Ti or W; and the thickness of the hard mask plate is preferably 10-100 nm.
[0041] In the application, the material of the soft mask plate preferably comprises any one of electron beam glue, fluorine-containing polymer, photoresist and polystyrene; and the thickness of the soft mask plate is preferably 90-130 nm, and specifically can be 90 nm, 100 nm, 110 nm, 120 nm or 130 nm. When the soft mask plate is electron beam glue, the application does not have special limitation on the type of the electron beam glue, and any electron beam glue known by those skilled in the art can be used. In the specific embodiment of the application, the model of the electron beam glue is ZEP 520A.
[0042] The electron beam glue is used as a mask plate, which has higher chemical inertness, thereby facilitating the improvement of etching selectivity. Compared with normal temperature or high temperature dry etching, the pyrolysis, ablation and carbonization of the electron beam glue under plasma action can be effectively inhibited in a low temperature environment, the chain breaking rate is reduced, the decomposition reaction is delayed, and the etching resistance and stability of the electron beam glue are significantly improved. In addition, under the condition of relatively low bias power, the ion bombardment energy is low, the physical damage of the plasma to the electron beam glue is significantly reduced, and the problems of surface erosion, peeling or mask degradation commonly occurring in traditional etching are avoided. Therefore, the process can realize high anisotropic etching while only relying on the electron beam glue with a thickness of hundreds of nanometers as a mask material, greatly simplifies the process flow, reduces the manufacturing cost, reduces the influence of subsequent mask plate removal on the surface quality of the unetched area of the silicon substrate, and is particularly suitable for the low-loss processing demand of high-resolution nano structures.
[0043] The process of setting the mask plate is not particularly limited in the present application, and can be known to those skilled in the art. In the present application, when the mask plate is electron beam glue, the process of setting the mask plate preferably comprises: coating electron beam glue on the surface of the silicon substrate by spin coating, sequentially performing baking, exposure, development and fixing, and then forming a specific pattern with micro-nano scale on the surface of the silicon substrate. The pattern area is not covered by the electron beam glue, and the remaining part is covered by the electron beam glue, forming a mask plate. In the present application, the exposure is preferably electron beam exposure. In the present application, during the fixing process of electron beam exposure, the electron beam glue inside the pattern is removed by the developer, the surface of the silicon substrate is exposed, and the electron beam glue outside the pattern still covers the surface of the silicon substrate. After the pattern is formed, the area of the silicon substrate surface covered by the electron beam glue does not undergo etching, and the area not covered by the electron beam glue undergoes etching.
[0044] In the present application, the etching temperature is preferably -50 to -150℃, and can be specifically -50℃, -60℃, -70℃, -80℃, -90℃, -100℃, -110℃, -120℃, -130℃, -140℃ or -150℃. In the present application, the chamber pressure of the dry etching is preferably 5 to 15 mTorr, and can be specifically 5 mTorr, 6 mTorr, 7 mTorr, 8 mTorr, 9 mTorr, 10 mTorr, 11 mTorr, 12 mTorr, 13 mTorr, 14 mTorr or 15 mTorr. In the present application, the ICP power of the low-temperature dry etching is preferably 200 to 450 W, and can be specifically 200 W, 220 W, 250 W, 280 W, 300 W, 320 W, 350 W, 380 W, 400 W, 420 W or 450 W. In the present application, the bias power is 10 to 50 W, and can be specifically 10 W, 20 W, 30 W, 40 W or 50 W.
[0045] In the present application, the flow rate of SF6 is preferably 20-60 sccm, and can be specifically 20 sccm, 30 sccm, 40 sccm, 50 sccm or 60 sccm; the flow rate of O2 is preferably 1-8 sccm, and can be specifically 1 sccm, 2 sccm, 3 sccm, 4 sccm, 5 sccm, 6 sccm, 7 sccm or 8 sccm; and the flow rate ratio of SF6 to O2 is preferably no less than 5:2, and can be specifically 10:1 or 15:2.
[0046] In the present application, the low-temperature dry etching is preferably performed by using an Oxford PlasmaPro 100Cobra dry etching machine.
[0047] In the present application, the method for removing the soft mask plate is preferably plasma etching; and the conditions of the plasma etching preferably include: using oxygen as the reaction gas, the flow rate of the reaction gas being 50-100 sccm, and can be specifically 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm or 100 sccm; the gas pressure being 5-15 Pa, and can be specifically 5 Pa, 10 Pa or 15 Pa; and the power being 150-250 W, and can be specifically 150 W, 200 W or 250 W.
[0048] The present application also provides a kind of grating-like microstructure prepared by the preparation method described in the above technical solutions, which comprises a plurality of parallel arranged grooves, the width of the interval gate between adjacent grooves is 40-130 nm, and can be specifically 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm or 130 nm; the aspect ratio of the interval gate is preferably greater than 10:1, and can be specifically 13:1 or 14:1.In the present application, the depth of the groove is the depth of the interval gate.
[0049] In the present application, the depth of a single groove is preferably 1000-2000 nm, and the aspect ratio of a single groove is preferably 1:2-5:1; and the number of grooves is preferably no less than two.
[0050] In the present application, the surface roughness Ra of the inner wall of the groove is preferably <0.5 nm.
[0051] In the present application, the surface roughness Ra of the upper surface of the interval gate is preferably 0.1-0.5 nm.
[0052] Unless otherwise specified, the materials and equipment used in the present application are commercially available in the art.
[0053] The technical solutions in the present application will be clearly and completely described below in combination with the embodiments in the present application. Apparently, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the protection scope of the present application.
[0054] Embodiment 1
[0055] The P<100> type silicon substrate was cleaned by ultrasonic cleaning using acetone and IPA, and the silicon substrate was dried by blowing nitrogen to obtain a pretreated silicon substrate;
[0056] An electron beam glue (model ZEP 520A, thickness about 100 nm) was deposited on the surface of the pretreated silicon substrate by a spin coating method, the electron beam glue completely covered the surface of the silicon substrate, and after baking, exposure, development and fixing in turn, a specific pattern with micro-nano scale was formed, the pattern area was not covered by the electron beam glue, and the remaining part was covered by the electron beam glue to form a mask plate;
[0057] The silicon substrate obtained above was subjected to low-temperature dry etching, and an Oxford PlasmaPro 100Cobra dry etching machine was adopted, and the conditions of the low-temperature dry etching were as follows: the temperature of the reaction chamber was-110℃, the working gas was SF6 (30 sccm) and O2 (3 sccm), the flow ratio of SF6 and O2 was 10:1, the chamber pressure was 8 mTorr, the ICP power was 280 W, and the bias power was 30 W.
[0058] After the etching was completed, the mask plate was removed by plasma etching, and the conditions of the plasma etching were as follows: oxygen was used as the reaction gas, the flow rate of the reaction gas was 80 sccm, the gas pressure was 10 Pa, and the power was 200 W, so that a wide-period narrow-line-width grating-like microstructure was formed on the surface of the silicon substrate, and the obtained grating-like microstructure included parallelly arranged grooves.
[0059] The scanning electron microscope (SEM) image of the cross section of the grating-like microstructure prepared by the above method is shown in Figure 2 From Figure 2 It can be seen that the inner wall of the groove has a smooth morphology, the depth of a single groove is 1440 nm, and the depth-width ratio of a single groove is 1.6:1.
[0060] The interval gate width between adjacent grooves is 100.5 nm, and the depth-width ratio is 14:1.
[0061] The roughness of the inner wall of the groove was characterized by an atomic force microscope (AFM), and the obtained AFM image is shown in Figure 3 It can be seen that the roughness Ra of the bottom of the groove is 0.471 nm, and the surface roughness Ra of the upper surface of the interval gate is 0.267 nm.
[0062] Example 2
[0063] Using acetone and IPA to treat P <100> The silicon substrate is ultrasonically cleaned and then dried with nitrogen to obtain a pretreated silicon substrate.
[0064] Electron beam resist (model ZEP 520A, thickness approximately 100nm) is deposited on the surface of a pretreated silicon substrate using spin coating. The electron beam resist completely covers the surface of the silicon substrate. After baking, exposure, development, and fixing, a specific pattern with micro-nano scale precision is formed. The patterned area is not covered by the electron beam resist, while the rest of the area is covered by the electron beam resist to form a mask.
[0065] The silicon substrate obtained above was subjected to low-temperature dry etching using an Oxford PlasmaPro 100Cobra dry etching machine. The conditions for low-temperature dry etching were: reaction chamber temperature -110℃, working gas SF6 (30 sccm) and O2 (4 sccm), SF6 to O2 flow ratio of 15:2, chamber pressure of 8 mTorr, ICP power of 280W, and bias power of 40W.
[0066] After etching is completed, the mask is removed in accordance with the method of Example 1, that is, a grating-like microstructure with a wide period and narrow linewidth is formed on the surface of the silicon substrate. The resulting grating-like microstructure includes trenches arranged in parallel.
[0067] A cross-sectional image of the scanning electron microscope (SEM) showing the grating-like microstructure prepared by the above method is shown below. Figure 4 As shown, from Figure 4 It can be seen that the inner wall of the trench has a smooth morphology, the depth of a single trench is 971.4 nm, and the aspect ratio of a single trench is 1.1:1;
[0068] The spacing between adjacent trenches is 70 nm, and the aspect ratio is 13.9:1;
[0069] The roughness of the inner wall of the groove was characterized using atomic force microscopy, and the resulting atomic force microscopy image is shown below. Figure 3 As shown, the surface roughness Ra at the bottom of the trench is 0.378 nm, and the surface roughness Ra of the upper surface of the spacer is 0.241 nm.
[0070] Comparative Example 1
[0071] The grating-like structure was obtained in accordance with Example 1, except that the etching temperature was set to 21.3°C (room temperature).
[0072] Comparative Example 2
[0073] A grating-like structure was obtained in the same manner as in Example 2, except that the bias power was 60 W.
[0074] Based on the above examples and comparative examples, Figure 6 The scanning electron microscope image of the cross section of the grating-like microstructure obtained in Comparative Example 1 is shown in Figure 2, and the scanning electron microscope image of the cross section of the grating-like microstructure obtained in Example 1 is shown in Figure 3. Figure 2 Compared with (Example 1), no grating-like structure was observed between the etching grooves when room temperature was used instead of low temperature etching environment, and obvious etching pits appeared on the sidewall. The above results show that the isotropic chemical drilling effect is obvious under the condition of room temperature etching, and the grating-like structure is completely etched.
[0075] Figure 7 The scanning electron microscope image of the cross section of the grating-like microstructure obtained in Comparative Example 2 is shown in Figure 4, and the scanning electron microscope image of the cross section of the grating-like microstructure obtained in Example 2 is shown in Figure 5. Figure 4 Compared with (Example 2), straight grating-like structures were observed between the etching grooves when a higher bias power was used, but the etching rate of the middle region of the etching groove bottom was obviously higher than that of the root of the Si grating structure, which caused obvious uneven etching pits on the groove bottom. The above results show that under the condition of higher bias power assistance, the excessive ion bombardment increases the roughness of the etched groove surface, and even destroys the consistency of the grating structure. At the same time, the increase of the bias power will intensify the ion bombardment on the electron beam glue surface, which may eventually lead to the local or overall failure of the soft mask.
[0076] Although the above examples have made a detailed description of the present application, it is only a part of the embodiments of the present application, but not all the embodiments, and other embodiments can be obtained according to the present embodiments without creativity, which all belong to the protection scope of the present application.
Claims
1. A method for fabricating a photonic-like grating microstructure, characterized by, The method comprises the following steps: After a mask plate is arranged on the surface of a silicon substrate, low-temperature dry etching and removal of the mask plate are sequentially performed to obtain the microstructure similar to a grating; The conditions of the low-temperature dry etching include: an etching temperature of not higher than-50 DEG C, working gas including SF6 and O2, and a bias power of 10-50 W.
2. The production method according to claim 1, characterized by, The etching temperature is-50 DEG C to-150 DEG C.
3. The preparation method according to claim 1, characterized in that, The chamber pressure of the low-temperature dry etching is 5-15 mTorr.
4. The method of claim 1, wherein, The ICP power of the low-temperature dry etching is 200-450 W.
5. The preparation method according to claim 1, characterized in that, The flow rate of the SF6 is 20-60 sccm, and the flow rate of the O2 is 1-8 sccm.
6. The production method according to claim 1 or 5, characterized by, The flow rate ratio of the SF6 to the O2 is not less than 5:
2.
7. The preparation method according to claim 1, characterized in that, The mask plate includes a hard mask plate or a soft mask plate. The material of the hard mask plate includes at least one of metal, amorphous carbon, oxide and nitride. The material of the soft mask plate includes any one of electron beam glue, fluorine-containing polymer, photoresist and polystyrene.
8. The preparation method according to claim 7, characterized in that, The thickness of the hard mask plate is 10-100 nm. The thickness of the soft mask plate is 90-130 nm.
9. The preparation method according to claim 7, characterized in that, The method for removing the soft mask plate is plasma etching. The conditions of the plasma etching include: oxygen is used as a reaction gas, the flow rate of the reaction gas is 50-100 sccm, the gas pressure is 5-15 Pa, and the power is 150-250 W.
10. The optically similar microstructure produced by the method according to any one of claims 1 to 9, characterized in that The microstructure similar to a grating comprises a plurality of parallelly arranged grooves, and the width of a spacing gate between adjacent grooves is 40-130 nm; the depth-width ratio of the spacing gate is greater than 10:
1. The depth of a single groove is 1000-2000 nm, and the depth-width ratio of a single groove is 1:2-5:
1. The number of the grooves is not less than two.