Graph correction method, storage medium, terminal and semiconductor structure forming method

Abstract

The invention discloses a graph correction method, a storage medium, a terminal and a forming method of a semiconductor structure. The graph correction method comprises the following steps: providing a to-be-corrected layout; providing a plurality of correction models; verifying the correction capability of the plurality of correction models to obtain a target correction model; and performing optical proximity effect correction on the to-be-corrected layout according to the target correction model to obtain a corrected layout. The accuracy of the graph correction method is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a pattern correction method, a storage medium and a terminal, and a forming method of semiconductor structure. BACKGROUND

[0002] In semiconductor manufacturing, as the design size is continuously reduced, the design size is closer and closer to the limit of the lithography imaging system, and the diffraction effect of light becomes more and more obvious, resulting in optical image degradation of the final design pattern, and the actual lithography pattern is seriously distorted relative to the pattern on the mask, and the actual pattern formed on the silicon wafer after lithography is different from the design pattern, which is called optical proximity effect (OPE).

[0003] In order to correct the optical proximity effect, optical proximity correction (OPC) is generated. The core idea of optical proximity correction is to establish an optical proximity correction model based on the consideration of offsetting the optical proximity effect, and to design a photomask pattern according to the optical proximity correction model. Although the lithography pattern after lithography is relative to the photomask pattern, the optical proximity effect occurs, but since the photomask pattern is designed according to the optical proximity correction model, the offsetting of the phenomenon has been considered, and therefore the lithography pattern after lithography is close to the target pattern that the user actually wants to obtain.

[0004] Improvement of optical proximity effect correction is a continuous problem to be solved. SUMMARY

[0005] The technical problem solved by the present application is to provide a pattern correction method, a storage medium and a terminal, and a forming method of semiconductor structure, to improve the process of optical proximity effect correction.

[0006] To solve the above technical problem, the technical scheme of the present application provides a pattern correction method, comprising: providing a to-be-corrected layout; providing a plurality of correction models; verifying the correction ability of the plurality of correction models to obtain a target correction model; and performing optical proximity effect correction on the to-be-corrected layout according to the target correction model to obtain a corrected layout.

[0007] Optionally, verifying the plurality of correction models to obtain a target correction model comprises: providing a standard pattern and a standard correction pattern, the standard correction pattern being a pattern obtained by performing optical proximity effect correction on the standard pattern; performing optical proximity effect correction on the standard pattern using the correction model to obtain a verification correction pattern; and determining the correction model whose error between the verification correction pattern and the standard correction pattern satisfies a preset range as the target correction model.

[0008] Optionally, the determining that the error of the verification correction pattern and the standard correction pattern meets the preset range of correction model is a target correction model comprises: comparing the verification correction pattern and the standard correction pattern; if the error of the verification correction pattern and the standard correction pattern is within the preset range, obtaining the target correction model; if the error of the verification correction pattern and the standard correction pattern exceeds the preset range, replacing the correction model, and verifying the replaced correction model until the target correction model is obtained.

[0009] Optionally, the obtaining process of the preset range comprises: providing a design pattern and a plurality of test correction patterns, the test correction patterns being obtained based on the standard pattern after optical proximity effect correction; obtaining the preset range according to the design pattern, the test correction pattern and the standard correction pattern.

[0010] Optionally, the obtaining the preset range according to the design pattern, the test correction pattern and the standard correction pattern comprises: obtaining a standard target pattern on a wafer based on the standard correction pattern; obtaining a test target pattern on the wafer based on a plurality of test correction patterns; obtaining a plurality of first error ranges between the test target pattern and the design pattern; taking the test target pattern meeting the preset requirement; obtaining the error range between the corresponding plurality of test correction patterns and the standard correction pattern according to the plurality of test target patterns meeting the preset requirement, and obtaining the preset range.

[0011] Optionally, the obtaining the preset range according to the plurality of test target patterns meeting the preset requirement comprises: obtaining a plurality of test correction patterns corresponding to the plurality of test target patterns meeting the preset requirement; obtaining a plurality of size errors between the corresponding plurality of test correction patterns and the standard correction pattern; obtaining the maximum size error and the minimum size error according to the plurality of size errors, and obtaining the preset range.

[0012] Optionally, the plurality of correction models run on different processors respectively.

[0013] Optionally, before the optical proximity effect correction of the to-be-corrected layout according to the target correction model, the method further comprises: dividing the to-be-corrected layout into a plurality of to-be-corrected regions; and performing the optical proximity effect correction on the to-be-corrected layout according to the target correction model, comprising: simultaneously correcting the plurality of to-be-corrected regions according to the target correction model to obtain a corrected layout, the corrected layout comprising a plurality of corrected regions, and the plurality of corrected regions corresponding to the plurality of to-be-corrected regions one by one.

[0014] Optionally, the to-be-corrected area comprises verification modules, the patterns of the verification modules are identical, and the sizes of the verification modules are identical; the correction area comprises correction modules, and the correction modules correspond to the verification modules one by one.

[0015] Optionally, the pattern correction method further comprises: performing pattern uniformity verification on the corrected layout; the pattern uniformity verification on the corrected layout comprises: comparing the pattern shapes of the correction modules; if the pattern shape of any correction module is different from the pattern shapes of other correction modules, replacing the processor where the correction model is located, performing pattern uniformity verification on the corrected layout by using the replaced correction model, or adjusting the sizes of the to-be-corrected areas, and performing pattern uniformity verification on the to-be-corrected areas with the adjusted sizes again; if the pattern shapes of the correction modules are identical, the pattern uniformity of the corrected layout meets the requirements.

[0016] Optionally, the sizes of the to-be-corrected areas are identical.

[0017] Optionally, before performing the optical proximity effect correction on the to-be-corrected layout according to the target correction model, the method further comprises: compensating etching deviation of the target correction model.

[0018] Optionally, before performing the optical proximity effect correction on the to-be-corrected layout according to the target correction model, the method further comprises: generating an auxiliary pattern on the to-be-corrected layout.

[0019] Correspondingly, the technical scheme of the present application further provides a storage medium, which has computer instructions stored thereon, and the steps of the above method.

[0020] Correspondingly, the technical scheme of the present application further provides a storage terminal, which comprises a memory and a processor, and the memory has computer instructions stored thereon, which can be run on the processor, and the processor runs the computer instructions to perform the steps of the above method.

[0021] Correspondingly, the technical scheme of the present application further provides a forming method of a semiconductor structure, which comprises: providing a to-be-etched layer; forming a core material layer on the surface of the to-be-etched layer; forming a photoresist material layer on the core material layer; providing a mask plate, wherein the mask plate comprises a plurality of patterns, and the patterns are obtained by using the above method; transferring the patterns on the mask plate to the photoresist material layer based on the mask plate, to form a patterned photoresist layer on the core material layer; etching the core material layer by using the patterned photoresist layer as a mask, to form a plurality of discrete core layers on the surface of the to-be-etched layer; forming a first side wall on the side wall of the core layer; and after forming the first side wall, removing the core layer, to form a plurality of discrete first side walls on the surface of the to-be-etched layer.

[0022] Optionally, the method further comprises: forming a second side wall on the first side wall sidewall surface; after forming the second side wall, removing the first side wall to form a plurality of discrete second side walls on the surface of the layer to be etched; and etching the layer to be etched using the second side walls as a mask to form a semiconductor structure.

[0023] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0024] The graphic correction method of the present application verifies the correction ability of a plurality of correction models, so that the correction result of the target correction model with the required correction ability is more accurate, and the situation of misoperation in the correction process is avoided. In addition, the process of verifying the plurality of correction models does not need to consume too much time, and will not affect the efficiency of graphic correction.

[0025] Further, the plurality of correction models are verified using standard graphics and standard correction graphics. The standard correction graphics are graphics with accurate correction results verified in the early stage. The standard correction graphics are used as the control to judge whether the verified correction graphics of the correction models meet the standard. The correction model corresponding to the verified correction graphics meeting the standard is the model with the required correction ability, and the correction model corresponding to the verified correction graphics not meeting the standard is the model with abnormal correction ability.

[0026] Further, the graphic correction method further comprises verifying the graphic uniformity of the corrected layout, so that the correction result of the target correction model is more accurate and the uniformity is better, and the situation of misoperation in the correction process is avoided. In addition, the process of verifying the graphic uniformity of the corrected layout does not need to consume too much time, and will not affect the efficiency of graphic correction. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figures 1 to 4 is a schematic diagram of the graphic correction process in the embodiment of the present application;

[0028] Figure 5 and Figure 6 is a structural schematic diagram of the graphic correction process in the embodiment of the present application;

[0029] Figures 7 to 11 is a structural schematic diagram of the semiconductor structure formation process in the embodiment of the present application. DETAILED DESCRIPTION

[0030] As described in the background, improvement of optical proximity correction is a continuous problem to be solved. Specifically, a general optical proximity correction process includes: providing a to-be-corrected layout; providing a correction model; compensating for etching deviation of the target correction model or generating an auxiliary pattern on the to-be-corrected layout; performing optical proximity correction on the to-be-corrected layout using the correction model to obtain a corrected layout; and verifying the accuracy of the corrected layout.

[0031] However, for the same to-be-corrected layout, different corrected layouts are sometimes obtained. Therefore, it is necessary to check the accuracy of the optical proximity correction process to obtain an accurate pattern correction result.

[0032] To solve the above problems, the technical scheme of the present application provides a pattern correction method, a storage medium and a terminal, and a method for forming a semiconductor structure. By verifying the correction ability of a plurality of correction models, the correction result of the target correction model with the required correction ability is more accurate, and the situation of misoperation in the correction process is avoided. In addition, the process of verifying a plurality of correction models does not need to consume too much time, and will not affect the efficiency of pattern correction.

[0033] In order to make the above-mentioned objects, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0034] Figures 1 to 4 is a schematic diagram of a pattern correction process in an embodiment of the present application.

[0035] Figure 1 is a flowchart of a pattern correction method in an embodiment of the present application.

[0036] Referring to Figure 1 , the pattern correction method comprises:

[0037] Step S10: providing a to-be-corrected layout;

[0038] Step S20: providing a plurality of correction models;

[0039] Step S30: verifying the correction ability of a plurality of correction models to obtain a target correction model;

[0040] Step S40: performing optical proximity correction on the to-be-corrected layout according to the target correction model to obtain a corrected layout;

[0041] Step S50: verifying the pattern uniformity of the corrected layout.

[0042] In the embodiment, the pattern correction method further comprises performing pattern uniformity verification on the corrected pattern.

[0043] Next, each step is analyzed and described.

[0044] Please refer to Figure 5 and Figure 6 Continue to refer to Figure 1 , step S10 is performed: providing a to-be-corrected pattern 100.

[0045] The to-be-corrected pattern 100 is a pattern designed on a mask, and the to-be-corrected pattern 100 needs to be corrected by optical proximity effect correction before the pattern is transferred to the mask.

[0046] Please continue to refer to Figure 5 , the to-be-corrected pattern 100 is divided into a plurality of to-be-corrected regions 101.

[0047] In the embodiment, the to-be-corrected region 101 comprises a verification module 102, and the plurality of verification modules 102 have the same pattern and the same size.

[0048] The plurality of verification modules 102 have the same pattern, please continue to refer to Figure 6 , Figure 6 (a), (b), (c), and (d) shown in FIG. 1 are schematic diagrams of a pattern in one of the verification modules 102, Figure 6 The patterns in (a), (b), (c), and (d) shown in FIG. 1 can be formed by a self-aligned multiple exposure technology, such as a self-aligned double patterning (SADP) technology, a self-aligned quadruple patterning (SAQP) technology, etc.

[0049] Figure 6 The patterns in (a), (b), (c), and (d) shown in FIG. 1 can be formed by a self-aligned multiple exposure technology, so that the pattern can be repeated in each to-be-corrected region 101.

[0050] The plurality of verification modules 102 have the same size, i.e., the plurality of verification modules 102 have the same area, and the plurality of verification modules 102 have the same size in a first direction X and a second direction Y, the first direction X and the second direction Y are parallel to the surface of the to-be-corrected pattern 100 and perpendicular to each other.

[0051] In the embodiment, the sizes of the plurality of to-be-corrected regions 101 are the same. The sizes of the plurality of to-be-corrected regions 101 are the same, that is, the sizes of the plurality of to-be-corrected regions 101 in the first direction X and the second direction Y are the same.

[0052] In other embodiments, the sizes of the plurality of to-be-corrected regions can be different.

[0053] Please continue to refer to Figure 1 , execute step S20: provide a plurality of correction models.

[0054] The correction model is a model for performing optical proximity correction.

[0055] The plurality of correction models run on different processors respectively, that is, the plurality of correction models are supported by different devices. When performing optical proximity correction, multiple correction models are usually operated in parallel. Changes in device hardware conditions will affect the running results of the correction model software installed on the device, for example, changes in temperature and voltage of the device will affect the correction results of the correction model.

[0056] Please continue to refer to Figure 1 , execute step S30: verify the correction ability of the plurality of correction models, and obtain a target correction model.

[0057] In the embodiment, the target correction model is a model with a correction ability meeting the requirements.

[0058] Please refer to Figure 2 , in the embodiment, verifying the plurality of correction models to obtain a target correction model includes:

[0059] Step S301: provide a standard pattern and a standard correction pattern, the standard correction pattern being a pattern obtained by performing optical proximity correction on the standard pattern;

[0060] Step S302: perform optical proximity correction on the standard pattern using the correction model to obtain a verification correction pattern;

[0061] Step S303: determine that the correction model whose error between the verification correction pattern and the standard correction pattern meets a preset range is a target correction model. In the embodiment, the to-be-corrected layout includes the standard pattern. That is, the standard pattern is located in the to-be-corrected layout.

[0062] Please refer to Figure 3 , in the embodiment, determining that the correction model whose error between the verification correction pattern and the standard correction pattern meets a preset range is a target correction model includes:

[0063] Step S3031: compare the verification correction pattern with the standard correction pattern;

[0064] Step S3032: if the error of the verification correction pattern and the standard correction pattern is within the preset range, obtain the target correction model;

[0065] Step S3033: if the error of the verification correction pattern and the standard correction pattern exceeds the preset range, replace the correction model, and verify the replaced correction model until the target correction model is obtained.

[0066] The standard pattern and the standard correction pattern are used to verify a plurality of correction models. The standard correction pattern is a pattern with accurate correction result after preliminary verification. The standard correction pattern is used as a control to judge whether the verification correction pattern corrected by the correction model meets the standard. The correction model corresponding to the verification correction pattern meeting the standard is a model with required correction ability, and the correction model corresponding to the verification correction pattern not meeting the standard is a model with abnormal correction ability.

[0067] The correction ability of a plurality of correction models is verified, so that the correction result of the target correction model with required correction ability obtained is more accurate, and the situation of misoperation in the correction process is avoided. In addition, the process of verifying a plurality of correction models does not need to consume too much time, and will not affect the efficiency of pattern correction.

[0068] When the correction model with abnormal correction ability appears, a correction model is usually replaced for continuous use, or it is checked whether the hardware conditions of the equipment corresponding to the correction model with abnormal correction ability change, such as temperature, voltage, etc. The correction model with abnormal correction ability is verified after the hardware conditions of the equipment return to normal.

[0069] In the embodiment, the process of obtaining the preset range includes: providing a design pattern and a plurality of test correction patterns; obtaining the preset range according to the design pattern, the test correction pattern and the standard correction pattern.

[0070] In the embodiment, the obtaining of the preset range according to the design pattern, the test correction pattern and the standard correction pattern includes: obtaining a standard target pattern on a wafer based on the standard correction pattern; obtaining a test target pattern on the wafer based on a plurality of test correction patterns; obtaining a plurality of first error ranges between the test target pattern and the design pattern; taking the test target pattern satisfying the preset requirement; obtaining the error range between the corresponding test correction pattern and the standard correction pattern according to a plurality of test target patterns satisfying the preset requirement, and obtaining the preset range.

[0071] In the embodiment, the first error ranges between the test target pattern and the design pattern are obtained, and the second error range between the standard target pattern and the design pattern is also obtained, and the second error range meets the preset requirement.

[0072] The standard target pattern on the wafer is obtained based on the standard correction pattern, including: transferring the standard correction pattern to a mask, transferring the pattern on the mask to the wafer, and obtaining the standard target pattern.

[0073] The test target pattern on the wafer is obtained based on the test correction pattern, including: transferring the test correction pattern to a mask, transferring the pattern on the mask to the wafer, and obtaining the test target pattern.

[0074] In the embodiment, the test correction patterns are obtained based on the standard pattern after optical proximity effect correction, and the test correction patterns are obtained by using different correction conditions and parameters, and the correction conditions and parameters are exhaustive within the allowable range.

[0075] The design pattern is a pattern on a designed wafer. The error range between the test correction pattern and the standard correction pattern is obtained based on the test target pattern meeting the preset requirement, and the preset range is obtained, including: obtaining the test correction pattern corresponding to the test target pattern meeting the preset requirement; obtaining the size error between the test correction pattern and the standard correction pattern; obtaining the maximum size error and the minimum size error based on the size error, and obtaining the preset range.

[0076] If the error between the verification correction pattern and the standard correction pattern is within the preset range, the target correction model obtained is a model with correction capability meeting the requirement; if the error between the verification correction pattern and the standard correction pattern exceeds the preset range, the correction capability of the correction model is abnormal and does not meet the correction requirement.

[0077] In the embodiment, the pattern correction method further includes compensating the etching deviation of the target correction model. The compensation of the etching deviation of the target correction model can make the accuracy of the target correction model higher when the target correction model is corrected.

[0078] In other embodiments, the pattern correction method can not compensate the etching deviation of the target correction model.

[0079] In the embodiment, the pattern correction method further includes generating an auxiliary pattern on the to-be-corrected layout. The auxiliary pattern can improve the exposure amount of the pattern on the to-be-corrected layout, so that the profile of the pattern exposed on the to-be-corrected layout is clearer.

[0080] In other embodiments, the pattern correction method can not generate auxiliary patterns on the to-be-corrected layout.

[0081] Please continue to refer to Figure 1 , execute step S40: according to the target correction model, perform optical proximity correction on the to-be-corrected layout to obtain a corrected layout.

[0082] In this embodiment, the method for performing optical proximity correction on the to-be-corrected layout according to the target correction model to obtain a corrected layout includes: performing simulation exposure on the to-be-corrected layout to obtain a first simulation exposure layout; obtaining an edge placement error between the first simulation exposure layout and the target layout; if the edge placement error is within a preset range, obtaining the corrected layout; if the edge placement error does not satisfy the preset range, moving a line segment of the pattern of the to-be-corrected layout according to the edge placement error, and continuing to perform simulation exposure on the to-be-corrected layout after the line segment is moved until the obtained edge placement error is within the preset range, and obtaining the corrected layout.

[0083] In this embodiment, the to-be-corrected layout 100 includes a plurality of to-be-corrected regions 101. According to the target correction model, the plurality of to-be-corrected regions 101 are simultaneously corrected to obtain a corrected layout, and the corrected layout includes a plurality of corrected regions, and the plurality of corrected regions correspond one-to-one to the plurality of to-be-corrected regions.

[0084] In this embodiment, the target correction model for simultaneously correcting the plurality of to-be-corrected regions 101 respectively belongs to the same processor.

[0085] In this embodiment, the corrected region includes a correction module, and the plurality of correction modules correspond one-to-one to the plurality of verification modules 102.

[0086] Please continue to refer to Figure 1 , execute step S50: perform pattern uniformity verification on the corrected layout.

[0087] Please refer to Figure 4 In this embodiment, the pattern uniformity verification on the corrected layout includes:

[0088] Step S501: compare the pattern shapes of the plurality of correction modules;

[0089] Step S502: if the pattern shape of any correction module is different from the pattern shapes of other correction modules, replace the processor where the correction model is located, and use the replaced correction model to perform pattern uniformity verification on the corrected layout, or adjust the sizes of the plurality of to-be-corrected regions, and re-perform pattern uniformity verification on the to-be-corrected regions after the sizes are adjusted.

[0090] Step S503: If the graphic shapes of several of the correction modules are the same, then the graphic uniformity of the correction layout meets the requirements.

[0091] In this embodiment, the size of several regions 101 to be corrected is adjusted, that is, the size of the regions 101 to be corrected is adjusted along the first direction X and / or the second direction Y, so as to adjust the correction range.

[0092] The graphic correction method also includes verifying the graphic uniformity of the corrected layout, making the correction result of the target correction model more accurate and more uniform, and avoiding misoperation during the correction process; in addition, the process of verifying the graphic uniformity of the corrected layout does not take much time and will not affect the efficiency of graphic correction.

[0093] Accordingly, embodiments of the present invention also provide a storage medium storing computer instructions thereon, which are executed when the computer instructions are run. Figures 1 to 4 The steps of the method are described.

[0094] Accordingly, embodiments of the present invention also provide a storage terminal, including a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, and the processor executes the computer instructions. Figures 1 to 4 The steps of the method are described.

[0095] Figures 7 to 11 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0096] Please refer to Figure 7 The system provides a layer 200 to be etched; a core material layer 201 is formed on the surface of the layer 200; a photoresist material layer (not shown) is formed on the core material layer 201; and a photomask (not shown) is provided, the photomask including several patterns, the several patterns being formed using... Figures 1 to 4 The modified pattern obtained by the method described herein; based on the mask, several patterns on the mask are transferred to the photoresist material layer to form a patterned photoresist layer 202 on the core material layer 201.

[0097] Based on the mask, several patterns on the mask are transferred to the photoresist material layer to form a patterned photoresist layer 202 on the core material layer 201. That is, the photoresist material layer is exposed and developed using the mask as a mask to form the patterned photoresist layer 202.

[0098] use Figures 1 to 4 The modified pattern obtained by the method described herein forms several patterns on the mask, which have higher accuracy and better uniformity.

[0099] Please refer toFigure 8 Etching the core material layer 201 with the patterned photoresist layer 202 as a mask to form a plurality of discrete core layers 203 on the surface of the layer to be etched 200.

[0100] Please refer to Figure 9 Forming a first sidewall 204 on the sidewall of the core layer 203.

[0101] Please refer to Figure 10 After forming the first sidewall 204, removing the core layer 203 to form a plurality of discrete first sidewalls 204 on the surface of the layer to be etched 200; and forming a second sidewall 205 on the sidewall surface of the first sidewall 204.

[0102] Please refer to Figure 11 After forming the second sidewall 205, removing the first sidewall 204 to form a plurality of discrete second sidewalls 205 on the surface of the layer to be etched 200; and etching the layer to be etched 200 with the second sidewall 205 as a mask to form a semiconductor structure.

[0103] In the present embodiment, the semiconductor structure is formed by a self-aligned quadruple patterning (SAQP) technique.

[0104] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the scope of protection of the present application should be subject to the scope defined by the claims.

Claims

1. A method of graphic correction, characterized by, The method comprises the following steps: providing a to-be-corrected layout; providing a plurality of correction models; verifying correction capabilities of the plurality of correction models to obtain a target correction model; performing optical proximity correction on the to-be-corrected layout according to the target correction model to obtain a corrected layout.

2. The graphic correction method of claim 1, wherein The method of verifying the plurality of correction models to obtain a target correction model comprises the following steps: providing a standard pattern and a standard correction pattern, wherein the standard correction pattern is a pattern obtained by performing optical proximity correction on the standard pattern; performing optical proximity correction on the standard pattern by using the correction model to obtain a verification correction pattern; determining that the correction model, whose error between the verification correction pattern and the standard correction pattern meets a preset range, is the target correction model.

3. The graphic correction method of claim 2, wherein The method of determining that the correction model, whose error between the verification correction pattern and the standard correction pattern meets a preset range, is the target correction model comprises the following steps: comparing the verification correction pattern with the standard correction pattern; if the error between the verification correction pattern and the standard correction pattern is within the preset range, obtaining the target correction model; if the error between the verification correction pattern and the standard correction pattern exceeds the preset range, replacing the correction model and verifying the replaced correction model until the target correction model is obtained.

4. The graphic correction method of claim 2, wherein The method of obtaining the preset range comprises the following steps: providing a design pattern and a plurality of test correction patterns, wherein the test correction patterns are obtained based on the standard pattern after performing optical proximity correction thereon; obtaining the preset range based on the design pattern, the test correction patterns and the standard correction pattern.

5. The graphic correction method of claim 4, wherein The method of obtaining the preset range based on the design pattern, the test correction patterns and the standard correction pattern comprises the following steps: obtaining a standard target pattern on a wafer based on the standard correction pattern; obtaining test target patterns on the wafer based on the plurality of test correction patterns; obtaining a plurality of first error ranges between the test target patterns and the design pattern; obtaining test target patterns that meet a preset requirement in terms of first error range; obtaining error ranges between corresponding test correction patterns and the standard correction pattern based on the test target patterns that meet the preset requirement, and obtaining the preset range.

6. The graphic correction method of claim 5, wherein, The method of obtaining error ranges between corresponding test correction patterns and the standard correction pattern based on the test target patterns that meet the preset requirement, and obtaining the preset range comprises the following steps: obtaining corresponding test correction patterns based on the test target patterns that meet the preset requirement; obtaining a plurality of size errors between the corresponding test correction patterns and the standard correction pattern; obtaining a maximum size error and a minimum size error based on the plurality of size errors, and obtaining the preset range.

7. The graphic correction method of claim 1, wherein The plurality of correction models run on different processors respectively.

8. The graphic correction method of claim 1, wherein, Before performing optical proximity correction on the to-be-corrected layout according to the target correction model, the method further comprises the following step: dividing the to-be-corrected layout into a plurality of to-be-corrected regions. The method of performing optical proximity correction on the to-be-corrected layout according to the target correction model comprises the following steps: According to the target correction model, a plurality of to-be-corrected regions are simultaneously corrected to obtain a corrected layout, wherein the corrected layout comprises a plurality of correction regions, and the plurality of correction regions correspond to the plurality of to-be-corrected regions one by one.

9. The graphic correction method of claim 8, wherein, The to-be-corrected regions comprise verification modules, and the plurality of verification modules have the same pattern and the same size; the correction regions comprise correction modules, and the plurality of correction modules correspond to the plurality of verification modules one by one.

10. The graphic correction method of claim 9, wherein The pattern correction method further comprises: performing pattern uniformity verification on the corrected layout; the pattern uniformity verification on the corrected layout comprises: comparing the pattern shapes of the plurality of correction modules; if the pattern shape of any correction module is different from the pattern shapes of other correction modules, replacing the processor where the correction model is located, and using the replaced correction model to perform pattern uniformity verification on the corrected layout, or adjusting the sizes of the plurality of to-be-corrected regions, and re-performing pattern uniformity verification on the to-be-corrected regions with adjusted sizes; if the pattern shapes of the plurality of correction modules are the same, the pattern uniformity of the corrected layout meets the requirements.

11. The graphic correction method of claim 8, wherein, The plurality of to-be-corrected regions have the same size.

12. The graphic correction method of claim 1, wherein, Before performing optical proximity correction on the to-be-corrected layout according to the target correction model, the method further comprises: compensating etching deviation of the target correction model.

13. The method of claim 1, wherein the step of modifying the image is performed by a computer. Before performing optical proximity correction on the to-be-corrected layout according to the target correction model, the method further comprises: generating an auxiliary pattern on the to-be-corrected layout.

14. A storage medium having stored thereon computer instructions, characterized in that, The computer instructions perform the steps of the method of any one of claims 1-13 when executed.

15. A storage terminal comprising a memory and a processor, the memory having stored thereon computer instructions executable on the processor, wherein, The processor performs the steps of the method of any one of claims 1-13 when executing the computer instructions.

16. A method of forming a semiconductor structure, comprising: The method comprises: providing a to-be-etched layer; forming a core material layer on the surface of the to-be-etched layer; forming a photoresist material layer on the core material layer; providing a mask plate, wherein the mask plate comprises a plurality of patterns, and the plurality of patterns are patterns of a corrected layout obtained by the method of any one of claims 1-13; transferring the plurality of patterns on the mask plate to the photoresist material layer based on the mask plate to form a patterned photoresist layer on the core material layer; etching the core material layer using the patterned photoresist layer as a mask to form a plurality of discrete core layers on the surface of the to-be-etched layer; forming a first side wall on the sidewall of the core layer; after forming the first side wall, removing the core layer to form a plurality of discrete first side walls on the surface of the to-be-etched layer.

17. The method of forming a semiconductor structure of claim 16, wherein The method further comprises: forming a second side wall on the sidewall surface of the first side wall; after forming the second side wall, removing the first side wall to form a plurality of discrete second side walls on the surface of the to-be-etched layer; etching the to-be-etched layer using the second side wall as a mask to form a semiconductor structure.

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