Data migration method, system and equipment

Abstract

The invention discloses a data migration method, system and equipment in the technical field of computers. In the application, the target dynamic random storage area is taken as the extension of the host dynamic random storage area, and a two-stage cache structure is established for the host; and according to the data access popularity, the data can be moved from the storage disk to the target dynamic random storage area and moved from the target dynamic random storage area to the host dynamic random storage area, so that the data can be flexibly moved in different storage media in a fine-grained manner according to the granularity of the size of the storage block; the hit rate of host near-end storage is increased as much as possible; and the memory hit rate, the host access performance and the read-write efficiency of the migrated data can also be improved through the adjustment of the self-adaptive quasi-migration threshold, and the access delay of the extended memory is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a data migration method, system and device. BACKGROUND

[0002] At present, the host memory is not enough, and the host memory can be expanded. However, the access delay of the host expanded memory is much higher than that of the host memory, which will affect the efficiency of reading and writing data of the host. Therefore, how to improve the reading and writing efficiency of the host is a problem to be solved by the person skilled in the art. SUMMARY

[0003] Therefore, the purpose of the present application is to provide a data migration method, system, device, medium and program product to improve the reading and writing efficiency of the host.

[0004] In a first aspect, the present application provides a data migration method applied to a target device, the target device comprising a target dynamic random storage area and a storage disk, the method comprising: taking the target dynamic random storage area and the storage disk as scheduling objects; dividing the storage space of the scheduling objects into a plurality of storage blocks according to a preset division strategy; determining the first access heat of each storage block by using a first heat statistical method; and calculating the current threshold of migration destination according to the free capacity of the migration destination, the migration frequency of the migration destination and the historical threshold of migration of the migration destination; wherein the target device is connected with a host, the host comprising a host dynamic random storage area; the target dynamic random storage area is an expansion of the host dynamic random storage area; when the target dynamic random storage area is taken as the scheduling object, the migration destination is the host dynamic random storage area; when the storage disk is taken as the scheduling object, the migration destination is the target dynamic random storage area; and if the first access heat of any storage block is not less than the current threshold of migration, the data stored in the storage block is migrated to the migration destination.

[0005] In a second aspect, the present application provides a data migration system, comprising: a host and a target device connected to the host; the target device comprising: a first scheduler, a second scheduler, a target dynamic random access memory and a storage disk; the host comprising: a host dynamic random access memory; the target dynamic random access memory being an extension of the host dynamic random access memory; the first scheduler being configured to: divide the storage space of the target dynamic random access memory into a plurality of storage blocks according to a preset division strategy; determine a first access heat of each storage block by using a first heat statistical method; calculate a current threshold for migration of the host dynamic random access memory according to the free capacity of the host dynamic random access memory, the frequency of migration into the host dynamic random access memory and the historical threshold for migration of the host dynamic random access memory; if the first access heat of any storage block is not less than the current threshold for migration, migrate the data stored in the storage block to the host dynamic random access memory; the second scheduler being configured to: divide the storage space of the storage disk into a plurality of storage blocks according to a preset division strategy; determine a first access heat of each storage block by using a first heat statistical method; calculate a current threshold for migration of the target dynamic random access memory according to the free capacity of the target dynamic random access memory, the frequency of migration into the target dynamic random access memory and the historical threshold for migration of the target dynamic random access memory; if the first access heat of any storage block is not less than the current threshold for migration, migrate the data stored in the storage block to the target dynamic random access memory.

[0006] In a third aspect, the present application provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the data migration method disclosed above.

[0007] In a fourth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program is executed by a processor to implement the data migration method disclosed above.

[0008] In a fifth aspect, the present application provides a computer program product, comprising computer programs / instructions, which are executed by a processor to implement the steps of the data migration method disclosed above.

[0009] It can be seen that the application provides a data migration method, which is applied to a target device, the target device includes a target dynamic random storage area and a storage disk, and the method comprises the following steps: taking the target dynamic random storage area and the storage disk as scheduling objects; dividing the storage space of the scheduling objects into a plurality of storage blocks according to a preset division strategy; determining the first access heat of each storage block by using a first heat statistical method; and calculating the current threshold value of the migration destination according to the free capacity of the migration destination, the migration frequency of the migration destination and the historical threshold value of the migration destination. The target device is connected with a host computer, the host computer includes a host dynamic random storage area, the target dynamic random storage area is an extension of the host dynamic random storage area, when the target dynamic random storage area is taken as the scheduling object, the migration destination is the host dynamic random storage area, when the storage disk is taken as the scheduling object, the migration destination is the target dynamic random storage area, and if the first access heat of any storage block is not less than the current threshold value, the data stored in the storage block is migrated to the migration destination.

[0010] It can be seen that the application has the following beneficial effects: the target dynamic random storage area is an extension of the host dynamic random storage area, thereby building a two-level cache structure for the host computer; and the data can be migrated from the storage disk to the target dynamic random storage area and from the target dynamic random storage area to the host dynamic random storage area according to the data access heat, so that the migration of the data in different storage media can be realized in a flexible and fine-grained manner with the granularity of the storage block, the hit rate of the host near-end storage is improved as much as possible, the current threshold value of the migration destination is calculated according to the free capacity of the migration destination, the migration frequency of the migration destination and the historical threshold value of the migration destination, the adjustment of the threshold value can be realized in an adaptive manner, the memory hit rate of the migrated data can be improved, the access performance and the read-write efficiency of the host computer can be improved, the access delay of the extended memory can be reduced, and the memory access performance optimization is realized.

[0011] Correspondingly, the data migration system, the device, the medium and the program product provided by the application also have the above technical effects. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0013] Figure 1 A flow chart of a data migration method disclosed by the application; Figure 2 A schematic diagram of a data migration system disclosed by the application; Figure 3 Another data migration system disclosed in the present application; Figure 4 A structure diagram of a page hotness monitoring and hot page identification module disclosed in the present application; Figure 5 An access hotness calculation diagram disclosed in the present application; Figure 6 A cache controller structure diagram disclosed in the present application; Figure 7 A hot and cold page migration flow diagram disclosed in the present application; Figure 8 A server structure diagram provided in the present application; Figure 9 A terminal structure diagram provided in the present application. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0015] It should be noted that in the description of the present application, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the processes, methods, articles or devices comprising a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. The terms "first", "second" and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0016] In order to enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0017] At present, in the case of insufficient host memory, the host memory can be expanded, but the access delay of the host expanded memory is much higher than that of the host memory, which will affect the efficiency of host read and write data. Therefore, the present application provides a data migration scheme, which can flexibly and finely realize the migration of data in different storage media with the granularity of storage block size, and as much as possible to improve the hit rate of host near-end storage; adaptive adjustment of the threshold value can improve the memory hit rate of migrated data, improve the host access performance and read-write efficiency, reduce the access delay of the expanded memory, and realize the optimization of memory access performance.

[0018] Referring toFigure 1 As shown, the embodiment of the present application discloses a data migration method, applied to a target device, the target device comprising a target dynamic random storage area and a storage disk, comprising: S101, taking the target dynamic random storage area and the storage disk as scheduling objects.

[0019] In this embodiment, when the target dynamic random storage area is taken as a scheduling object, the migration destination is the host dynamic random storage area, that is, the data stored in each storage block obtained by dividing the target dynamic random storage area needs to be migrated to the host dynamic random storage area by the method of this embodiment, so that the data is migrated from the extended memory (i.e. the target dynamic random storage area) to the host memory (i.e. the host dynamic random storage area), improving the memory hit rate of the host read-write operation. When the storage disk is taken as a scheduling object, the migration destination is the target dynamic random storage area, that is, the data stored in each storage block obtained by dividing the storage disk needs to be migrated to the target dynamic random storage area by the method of this embodiment, so that the data is migrated from the underlying storage (i.e. the storage disk, such as SSD) to the host extended memory (i.e. the cache of the storage disk), improving the memory hit rate of the host read-write operation. The target dynamic random storage area and the host dynamic random storage area can be uniformly addressed by the host. The target device can be implemented based on FPGA and the like.

[0020] S102, dividing the storage space of the scheduling object into a plurality of storage blocks according to a preset division strategy.

[0021] The division strategy of the target dynamic random storage area and the storage disk can be different due to the difference of the storage medium, for example: the target dynamic random storage area is DRAM (Dynamic Random Access Memory), and the storage disk is SSD (Solid State Drives), then different preset division strategies can be set for DRAM and SSD based on the properties of DRAM and SSD storage particles. In one implementation, the storage space of the scheduling object is divided into a plurality of storage blocks according to the preset division strategy, comprising: when the target dynamic random storage area is taken as a scheduling object, the preset division strategy is a byte division strategy, the storage space of the target dynamic random storage area is divided into a plurality of storage blocks in byte units according to the byte division strategy, realizing byte granularity migration and addressing; when the storage disk is taken as a scheduling object, the preset division strategy is a minimum read-write amount division strategy, the storage space of the storage disk is divided into a plurality of storage blocks in minimum read-write amount (such as 4K) units according to the minimum read-write amount division strategy, realizing minimum read-write amount granularity migration and addressing.

[0022] Of course, the target dynamic random storage area and the storage disk can also have the same division strategy. In an embodiment, the storage space of the scheduling object is divided into a plurality of storage blocks according to a preset division strategy, comprising: dividing the storage space of the target dynamic random storage area and the storage space of the storage disk into a plurality of storage blocks respectively according to the same preset division strategy.

[0023] S103, determining the first access heat of each storage block by using the first heat statistical method.

[0024] In order to realize high-precision and low-overhead heat statistics, the same direction repeated moving of the same storage block is avoided. In an embodiment, the first access heat of each storage block is determined by using the first heat statistical method, comprising: performing hash operation on the address of each storage block respectively; determining the corresponding position mark of the corresponding storage block in the plurality of hash tables according to the hash operation result; determining the corresponding counter value of each position mark corresponding to the same storage block; selecting the minimum value from each counter value corresponding to the same storage block, and obtaining the target value by adding one to the minimum value, and taking the target value as the first access heat of the storage block. In order to realize the next cycle calculation, for the same storage block, if the counter value other than the target value in each counter value is less than the target value, the counter value is modified to the target value, and if the counter value other than the target value in each counter value is not less than the target value, the counter value is kept unchanged. In an embodiment, the corresponding counter value of each position mark corresponding to the same storage block is determined, comprising: if it is the first calculation for the corresponding storage block this time, the counter value corresponding to each position mark corresponding to the corresponding storage block is set to zero; if it is not the first calculation for the corresponding storage block this time, the current counter value corresponding to each position mark corresponding to the corresponding storage block is kept.

[0025] For example: using hash functions h1(.), h2(.), …, h d (.) to perform hash operation on the address of storage block i respectively, obtaining d hash values: h1(i), h2(i), …, h d (i), as the corresponding position mark in the d hash tables; each position mark corresponds to a counter value, and when the first access heat of the storage block i is counted for the first time, the counter value corresponding to each position mark is set to 0, then when the first access heat of the storage block i is counted for the first time, the corresponding counter value Ti h1(i) , Ti h2(i) , …, Ti hd(i) of each storage block can be recorded as: 0 h1(i) , 1 h2(i) , …, X hd(i)The minimum value among the counter values is selected, i.e. 0, and the target value is obtained by adding 1 to the minimum value, i.e. 1, which is taken as the first access hot degree of the storage block. In order to realize the calculation in the next cycle, the counter values less than 1 except 1 are modified to 1, and the counter values not less than 1 except 1 are unchanged, and then the counter values corresponding to the storage block i are updated to 0 h1(i) , 1 h2(i) , …, X hd(i) , 1 h1(i) , 0 h2(i) , …, X hd(i) . When the first access hot degree of the storage block i is counted for the second time, the corresponding counter values of the position markers corresponding to the storage block i are 1 h1(i) , 0 h2(i) , …, X hd(i) , and the determination of the first access hot degree is performed on the basis thereof. It can be seen that the counter values are updated in time with the hot degree counting.

[0026] In order to avoid repeated moving in the same direction of the same storage block, each counter value is provided with an indicator in the embodiment, 1 represents a hot indicator, and 0 represents a cold indicator. In one implementation, after the target value is taken as the first access hot degree of the storage block, the hot degree is not determined immediately, but it is detected whether the counter values corresponding to the storage block are marked with the hot indicator; if the counter values corresponding to the storage block are marked with the hot indicator, it indicates that the storage block has been determined to be a hot block that needs to be moved in the previous time, that is, the moving has been completed in the previous time, and then in order to avoid repeated moving, the step of detecting whether the first access hot degree of the corresponding storage block is not less than the current moving threshold is abandoned, and the flow is directly ended. If the counter values corresponding to the storage block are not marked with the hot indicator, it indicates that the storage block has not been determined to be a hot block that needs to be moved in the previous time, that is, the storage block has not been moved in the previous time, and then the first access hot degree of the corresponding storage block is detected to confirm whether the storage block needs to be moved; if the first access hot degree of the storage block is not less than the current moving threshold, it can be determined that the storage block is a hot block, and the data in the storage block needs to be moved to the corresponding upper layer cache, and then the counter values corresponding to the storage block are marked with the hot indicator; if it is less than the current moving threshold, it can be determined that the storage block is a cold block, and the data in the storage block does not need to be moved to the corresponding upper layer cache, and then the counter values corresponding to the storage block are marked with the cold indicator, and the flow is ended.

[0027] After the counter values corresponding to the storage block are marked with the hot indicator, a moving step can be performed, such as a step of moving the data stored in the storage block to a moving destination, and the moving process can be realized based on DMA (Data Memory Access).

[0028] S104, calculating a current threshold value of the migration destination according to a free capacity of the migration destination, a migration-in frequency of the migration destination, and a historical threshold value of the migration destination; wherein the target device is connected with a host, the host comprises a host dynamic random access memory, the target dynamic random access memory is an extension of the host dynamic random access memory; when the target dynamic random access memory is taken as a scheduling object, the migration destination is the host dynamic random access memory; when the storage disk is taken as the scheduling object, the migration destination is the target dynamic random access memory.

[0029] In an embodiment, the current threshold value of the migration destination is calculated according to the free capacity of the migration destination, the migration-in frequency of the migration destination, and the historical threshold value of the migration destination, and the method comprises: calculating a threshold value parameter Y of the current threshold value according to a first formula; calculating a difference value Q of 1-Y; taking a Q-th quantile of the first access hotness of each storage block as the current threshold value; wherein the first formula is Y=Y t-1 ×[(1+α) a / (1+β) b ]; α is the free capacity, β is the migration-in frequency, a is a first coefficient corresponding to the free capacity, and b is a second coefficient corresponding to the migration-in frequency; Y t-1 is a threshold value parameter of the historical threshold value, and Y t-1 is a set value at the beginning. The first formula is used to realize real-time updating and adjusting of the threshold value, and the data that needs to be migrated can be more accurately migrated, and the memory hit rate is improved. For example, five storage blocks p1, p2, p3, p4, and p5 have first access hotnesses of 2, 3, 4, 6, and 7 respectively. If Y=0.2 after the first access hotnesses are sorted from small to large, then the difference value Q of 1-Y=5×(1-0.2)=4, and the fourth quantile of the sorted first access hotnesses, i.e., 6, is taken as the current threshold value.

[0030] S105, if the first access hotness of any storage block is not less than the current threshold value, then the data stored in the storage block is migrated to the migration destination.

[0031] The embodiment based on the first hotness statistical manner realizes the moving up of data from the storage disk to the target dynamic random storage area and from the target dynamic random storage area to the host dynamic random storage area. The target dynamic random storage area is used as the extension of the host dynamic random storage area, thereby constructing a two-level cache structure for the host. In addition, the data can be moved from the storage disk to the target dynamic random storage area and from the target dynamic random storage area to the host dynamic random storage area according to the data access hotness. Therefore, the moving up of data in different storage media can be realized in a flexible and fine-grained manner with the granularity of a storage block, and the hit rate of the host near-end storage is improved as much as possible. The current threshold of the moving destination is calculated according to the free capacity of the moving destination, the moving-in frequency of the moving destination and the historical threshold of the moving destination, so that the adjustment of the threshold can be realized in an adaptive manner, the memory hit rate of the moved data can be improved, the access performance and the read-write efficiency of the host can be improved, the access delay of the extended memory can be reduced, and the memory access performance optimization is realized.

[0032] In order to make the cold data in the target dynamic random storage area be written to the storage disk in time, improve the utilization rate of the target dynamic random storage area and save the storage space thereof, the second hotness statistical manner can be used to quickly perform hotness statistics on the data in the target dynamic random storage area. Specifically, the second hotness statistical manner calculates the second access hotness of each data block in the target dynamic random storage area. The operation complexity of the second hotness statistical manner is lower than that of the first hotness statistical manner. If the second access hotness of any data block is lower than a preset moving-down threshold and the data block is not modified, the data block is deleted from the target dynamic random storage area. If the second access hotness of any data block is lower than the preset moving-down threshold and the data block is modified, the data block is moved from the target dynamic random storage area to the storage disk. In the target dynamic random storage area, a mapping relationship table can be constructed, which records the address mapping relationship between each data block and the storage disk, the second access hotness and the dirty bit field. If the dirty bit field corresponding to any data block is a first target value, it is confirmed that the data block is not modified. If the dirty bit field corresponding to any data block is a second target value, it is confirmed that the data block is modified.

[0033] In an embodiment, the second hotness statistical manner is used to calculate the second access hotness of each data block in the target dynamic random storage area, including: if the access frequency of any data block is incremented by one, the second access hotness of the data block is incremented by one. In order to update the preset moving-down threshold, the value of the preset moving-down threshold can be updated according to the remaining capacity of the target dynamic random storage area, the current threshold and the preset moving-down threshold.

[0034] Next, a data moving system provided by the embodiment of the application is introduced. The data moving system described below can be referred to the other embodiments described herein.

[0035] See Figure 2 As shown in the embodiments of the application, a data migration system is disclosed, comprising: a host and a target device connected with the host; the target device comprises: a first scheduler, a second scheduler, a target dynamic random storage area and a storage disk; the host comprises: a host dynamic random storage area; the target dynamic random storage area is an extension of the host dynamic random storage area.

[0036] The host and the target device are connected in a cache coherence protocol. The cache coherence protocol can adopt CXL (Compute Express Link), which is a high-speed interface protocol that can optimize the interaction between computing, storage and communication resources in a data center. CXL actually consists of three sub-protocols, namely CXL.io, CXL.cache and CXL.mem. CXL.io is used for initialization, linking, device identification and enumeration, and register access, providing a non-coherent load / store interface for devices. CXL.cache is used to access the cache, which can define the interaction between the processor and the device, allowing connected CXL devices to use request and response methods to efficiently cache the processor memory with extremely low latency. CXL.mem is used to access memory, providing processors with access to device-attached memory using load and store commands, where the processor acts as the master device and the CXL device acts as the slave device, supporting volatile and persistent memory architectures. After these protocols are dynamically multiplexed together, data transmission can be performed at a speed of 32GT / s through the standard PCIe 5.0 physical layer.

[0037] The first scheduler is configured to: divide the storage space of the target dynamic random storage area into a plurality of storage blocks according to a preset division strategy; determine a first access heat of each storage block by using a first heat statistical method; calculate a current threshold for moving data of the host dynamic random storage area according to the idle capacity of the host dynamic random storage area, the moving-in frequency of the host dynamic random storage area and the historical threshold for moving data of the host dynamic random storage area; and if the first access heat of any storage block is not less than the current threshold, move the data stored in the storage block to the host dynamic random storage area.

[0038] The second scheduler is configured to: divide the storage space of the storage disk into a plurality of storage blocks according to a preset division strategy; determine a first access heat of each storage block by using a first heat statistical method; calculate a current threshold for moving data of the target dynamic random storage area according to the idle capacity of the target dynamic random storage area, the moving-in frequency of the target dynamic random storage area and the historical threshold for moving data of the target dynamic random storage area; and if the first access heat of any storage block is not less than the current threshold, move the data stored in the storage block to the target dynamic random storage area.

[0039] In an embodiment, the target device further comprises a cache controller; the first scheduler and the second scheduler invoke the cache controller to implement data migration in a direct memory access technology. In an embodiment, the target device further comprises a cache coherence controller; the host connects the cache coherence controller, the cache coherence controller connects the cache controller, and the cache controller connects the first scheduler, the second scheduler, the target dynamic random storage area and the storage disk.

[0040] The embodiment uses two schedulers to respectively implement the upward migration of data from the storage disk to the target dynamic random storage area and the upward migration of data from the target dynamic random storage area to the host dynamic random storage area, which do not interfere with each other and can implement data migration in a double cache structure to improve the hit rate.

[0041] Please refer to Figure 3 , based on FPGA programmable hardware, a target device is implemented, which uses a high-performance DIMM (Dual-Inline-Memory-Modules) interface DRAM medium as the cache (i.e., the target dynamic random storage area) of the NVMe SSD, and designs a two-level heat dynamic scheduling strategy for data to effectively improve the access performance of the CXL memory expansion device, so that the device has high performance and large capacity characteristics. Specifically, the target device supports two types of interfaces: DIMM interface and NVMe interface, and accordingly, DRAM and flash SSD are selected as the two media for combination.

[0042] Figure 3 The CXL controller (cache coherence controller) in supports CXL.io protocol and CXL.mem protocol, mainly composed of physical layer, link layer and transaction layer, wherein the Flex bus physical layer is responsible for physical information exchange, interface initialization and maintenance, the data link layer is responsible for reliable data transmission service, including link state and management transactions such as flow control and credit, and the transaction layer handles transactions associated with each protocol, performs data packet encapsulation and parsing. The host sends a CXL request, and the CXL controller parses the request and reads data from the DRAM cache or NVMe SSD by the cache controller, and returns read / write response and results. The host can also send access and configuration to the two page heat monitoring and hot page identification modules through the CXL.io protocol. It should be noted that the two page heat monitoring and hot page identification modules A and B (corresponding to the first scheduler and the second scheduler) can flexibly set the data granularity monitored, and the data granularity is not necessarily the storage page of the physical medium, but also other artificially divided ones, such as the storage block granularity described in the foregoing embodiments.

[0043] The page hotness monitoring and hot page identification module can realize address access frequency statistics, dynamic threshold calculation and hot page determination and other functions. The model can monitor the access frequency as the page hotness, dynamically calculate the hotness threshold in combination with the moving frequency and the DRAM idle capacity; according to the threshold, the hot and cold pages are judged, the hotness indicator is updated, the new hot page is identified, and the data moving is realized. The module can effectively prevent repeated moving, avoid resource waste, and improve the data moving efficiency and system performance.

[0044] The cache controller is the core module in the device controller, mainly responsible for quickly responding to the memory access request submitted by the CXL controller, and its external interface supports two kinds of memory media, respectively corresponding to the DDR DRAM of the DIMM interface and the SSD of the NVMe interface. With this model, multiple DRAM subsystems can be used to provide sufficient cache space for the SSD, improving the access performance of the CXL SSD memory. The module internally realizes the access scheduling and hot and cold page moving of the DRAM subsystem and the SSD subsystem.

[0045] The NVMe SSD subsystem and the DRAM cache subsystem, the former contains the SSD read controller NVMe IP Core based on the PCIe Hard IP, and the latter contains the DDR4 DIMM and the corresponding controller. The NVMe SSD subsystem is responsible for serving as a large-capacity persistent storage medium and providing non-volatile data saving capability, and is the final destination address of data storage in the CXL SSD device. The DRAM cache subsystem acts as a cache for the SSD, temporarily stores hot data and frequently accessed pages, to reduce the direct access delay to the NVMe SSD and improve the response speed and performance of the overall system.

[0046] The internal structure of the single page hotness monitoring and hot page identification module can be seen from Figure 4 . Since the frequency of the host access request is different from the frequency of the page hotness monitoring, the page address is first put into the FIFO buffer for cross-clock domain data transmission. The address access frequency index and frequency value analysis module can use hardware counters and other methods to perform page access frequency statistics, and the host can access the analysis results and configure its registers, such as enabling registers, adjusting threshold parameters, etc. The dynamic hotness threshold calculation module dynamically adjusts the hotness threshold in combination with the address access frequency distribution and the current moving frequency, the new hot page judgment module judges the new hot page in combination with the frequency analysis result and the dynamic threshold, and needs to prevent the device resource waste caused by repeated judgment of the hot page. Then the new hot page address is put into the hot page buffer for hot page moving or data prefetching.

[0047] The following lists an embodiment of the address access frequency index and frequency value analysis module for calculating the first access hotness. As Figure 5As shown, d hash tables are created, each with w hash buckets (corresponding to Figure 5 The hash table includes various blocks, each hash bucket contains a counter value and a 1-bit hot indicator (i.e. hot bit), the hot indicator takes the value of 0 or 1. At the beginning of the analysis, all counter values T and hot indicators are set to 0. For the access address sequence P = {p1, p2, …, pn} arrived in a period of analysis, that is, all addresses of a monitoring granularity, such as all addresses of a physical page or all addresses of a memory block, then a set of hash functions h1(.), h2(.), …, hd(.) is used to calculate the hash of the address sequence, so that a unique hash bucket in each hash table can be determined, the IDi in the hash bucket is filled with the value of h1(.), h2(.), …, hd(.), for example: ID1 in hash table 1 = h1(.), then T1(ID1) = T1h1(.), where h1(.) represents the position of the hash bucket in hash table 1, which is the mark value of T1, and 1 in T1 is the mark of hash table 1. Specifically, d position marks can be calculated by the formula IDi = hi (p), i = 1, …, d, so as to determine d counter values T1(ID1), T2(ID2), …, Td(IDd). The minimum value Tmin is selected from T1(ID1), T2(ID2), …, Td(IDd) by the formula c(p) = min(T i (ID i ))+1, i = 1, …, d, and the counter of the minimum counter value is increased by 1 to obtain c, c is the access frequency of the monitoring granularity, that is, the first access hotness. Subsequently, the counter values are updated by the formula Ti(IDi) = max(Ti(IDi), c), i = 1, …, d, that is: if the value is less than c, set all their values to c, otherwise keep unchanged.

[0048] To avoid repeated sending of data to the hot page buffer, the hot page determination module first checks the hot page indicator in the d hash buckets corresponding to the address before moving, if all are 1, it means that the page has been recorded as a hot page before, so whether it is determined as a hot page or a cold page this time, it does not need to be moved this time; if there is any hash bucket indicator is 0, and c is greater than or equal to the hotness threshold θ (i.e. the current threshold for moving), it means that it is a newly monitored hot page, then set the indicator to 1, and then send the p page address to the hot page buffer. Specifically, if c is greater than or equal to the hotness threshold θ, it is a hot page, and the indicator is 1; if it is less than θ, it is a cold page, and the indicator is 0. It can be expressed by the formula: .

[0049] The current threshold of moving is set; the page hotness monitoring module can obtain the distribution of the page access frequency, and the (1-Y) quantile is taken as the threshold θ of hot page determination, that is, Y% of the data access frequency is higher than the threshold θ. The page hotness monitoring and hot page identification modules A and B can take different Y values and corresponding θ values. The Y value can be dynamically adjusted according to the DRAM cache free capacity ratio α, the current data moving frequency β (the number of times of moving per unit time). The greater the DRAM memory free capacity ratio α, the greater the Y value; the higher the current data moving frequency β, the smaller the Y value, that is: Y=Y0×[(1+α) a / (1+β) b ]. Where a and b are adjustable parameters. After the Y value is dynamically determined, the hotness threshold θ is obtained from the access frequency distribution. In this way, the data transmission ping-pong phenomenon caused by too frequent page moving or too low data moving hotness can be avoided, and the data moving overhead is controlled. Y0 is the threshold value obtained in the previous calculation.

[0050] Please refer to Figure 6 , the cache controller is the core module in the device controller, mainly responsible for quickly responding to the memory access request submitted by the CXL controller, and realizing the dynamic data scheduling between two memories.

[0051] Among them, the cache controller can include: an access control module. There is a cache mapping relationship table in the DRAM cache, and the data in the table mainly includes three contents: the mapping relationship between the page in the cache and the SSD physical address (the corresponding device physical address Addr field, 46 bits), the page access frequency (the Freq field, 17 bits, that is, the second access hotness) and the dirty bit (the Dirty bit, 1 bit). The mapping table retrieval engine of the access control module indexes according to the mapping relationship to judge whether the DRAM cache hits: if it hits, it reads or writes the cache line in units of 64 bytes, and maintains the page hotness and state information of the data; if it does not hit, and there is remaining space in the DRAM cache, a new cache line is allocated, and if the DRAM is full, the existing cache line is expelled to the NVMe SSD, and a new mapping relationship is established.

[0052] Regarding the dirty bit of the cache mapping relationship table, if it is a read operation, the dirty bit does not need to be changed; if it is a write operation, the dirty bit is changed to 1. When the DRAM cache has been completely occupied and new data needs to be written, if the dirty bit of the expelled cold data is 0, it means that there is metadata in the NVMe SSD and it is clean, and the DRAM cache line can be discarded directly; if the dirty bit of the expelled cold data is 1, it means that the cache line has been modified, and the NVMe SSD needs to be written back first, and then the new data is written. Therefore, with the help of the dirty bit, the data consistency of the DRAM cache and the NVMe SSD can be maintained.

[0053] The cache controller can further include a DRAM cold data monitoring module. Each time a DRAM cache line is read or written, the Freq field of the corresponding page entry in the cache mapping relationship table is increased by 1. Because the DRAM cache is generally less than 16 GB, the frequency counter cache of each 4 KB page occupies an overhead of 2B, and this counter mode occupies no more than 8 MB of memory, which can simply and conveniently realize the heat statistics. According to the Freq field, the data access frequency of the current analysis period can be analyzed. For data access lower than the threshold θc, it is determined as cold data, and if the dirty flag is 0, it is directly discarded; if it is 1, it is written back to the NVMe SSD by the cold and hot data scheduling module, and after completion, the dirty flag is set to 0. Similarly, the cold data judgment threshold (i.e., the preset downward threshold) can be set according to the dynamic setting method mentioned above.

[0054] The cache controller can further include a cold and hot page moving mechanism. The dynamic moving mechanism of the cold and hot page between the DRAM and the NVMe SSD is as follows: when the cache controller detects that the page moving condition is triggered, it sends a moving request to the DMA engine, and the DMA engine is responsible for moving the cold page from the DRAM to the low-speed NVMe SSD to release the DRAM cache resource; and moving the hot page from the NVMe SSD back to the high-speed DRAM to improve the cache hit rate.

[0055] Referring to Figure 7 , the cold page moving process includes: the cache controller detects that the number of cold pages meets the moving condition, initiates a cold page moving request to the DMA engine, including its register configuration information, such as the source address being the DRAM and the destination address being the NVMe SSD. The DMA engine notifies the DRAM controller to read the cold page data. The DRAM controller reads the cold page and returns the data. The DMA engine writes the data into the NVMe SSD through the NVMe controller. After confirming the writing is completed, the DMA engine is notified. The DMA engine sends an interrupt to notify the cache controller that the moving is completed. The cache controller updates the cache mapping table, clears the dirty bit, and releases the cache line resource.

[0056] The hot page moving process includes: the cache controller detects that the number of hot pages meets the moving condition, initiates a hot page moving request to the DMA engine, including its register configuration information, such as the source address being the NVMe SSD and the destination address being the DRAM. The DMA engine notifies the NVMe controller to read the hot page data. The NVMe controller reads the hot page and returns the data. The DMA engine writes the data into the DRAM cache through the DRAM controller. After confirming the writing is completed, the DMA engine is notified. The DMA engine interrupts to notify the cache controller that the moving is completed.

[0057] It should be noted that the CXL technology can enable the SSD storage device to expand the host memory in a low-cost and large-capacity manner. In the target device of the embodiment, the DDR DRAM memory is used as the cache of the NVMe SSD, the cache controller is designed to support fast reading and writing of data when the DRAM cache hits, and the hot and cold pages between the device internal NVMe SSD and the DRAM cache are supported. The main advantages are: (1) based on the CXL SSD medium, the memory capacity expansion is realized, the expansion capacity is strong, and the cost is low. At the same time, the cold and hot page scheduling between the internal DRAM cache and the NVMe SSD of the device and between the device and the host DRAM memory improves the device access performance. (2) The device hardware level monitors the page access frequency, and perceives the memory access heat with high precision and low cost. (3) The cache controller is designed to support the DDR DRAM memory as the cache of the SSD, realize the byte granularity addressing of the CXL SSD device, improve the bandwidth utilization efficiency of the CXL bus, and greatly reduce the access delay of the CXL SSD device under cache hit condition. (4) The page heat monitoring module A monitors, identifies and extracts the page heat of the DRAM cache miss and the NVMe SSD local address access, and pre-fetches the hot page to the DRAM cache through the cache controller, thereby improving the cache hit rate. (5) The page heat monitoring module B monitors, identifies and extracts the heat of the CXL SSD access address, supports the CPU access and control, realizes the hot page migration to the host DRAM, optimizes the resource utilization, reduces the application access memory delay, and reduces the access pressure of the CXL SSD. (6) The page heat threshold is dynamically set, which is dynamically related to the overall page heat, the current page migration frequency, the DRAM cache free capacity and the like, thereby avoiding the increase of migration overhead caused by too frequent migration.

[0058] Thus, the following is achieved: 1) Two-level hot page scheduling architecture, cold and hot page scheduling between DRAM cache and NVMe SSD in the device improves device access performance, hot page migration to host DRAM between device and host reduces system memory access delay, and memory access performance optimization is realized. 2) Hardware-level page heat monitoring and hot page identification module, high-precision low-cost frequency statistics are realized, and hot surface repeated migration is avoided based on hot position judgment. 3) Adaptive page heat threshold adjustment method, the threshold is dynamically calculated according to the DRAM free rate and the migration frequency, and the (1-Y) quantile method is used to determine the hot page standard. 4) Intelligent cache management mechanism, byte-addressing cache controller architecture design, integrated address mapping, cache access frequency counting and dirty bit management mapping table, and cold and hot page migration process of DMA engine cooperation.

[0059] The embodiment can be widely applied to edge computing devices and AI inference servers, especially in data-intensive and low-latency scenarios, to improve inference speed and response capability. Subsequently, the hot page identification module can be further improved based on machine learning or deep learning technology to achieve more accurate access pattern prediction and dynamic threshold adjustment, thereby making the hot page migration more intelligent.

[0060] An electronic device provided by an embodiment of the present application is described below. The electronic device described below can be mutually referred to with other embodiments described herein. The electronic device in the embodiment can be any device or functional module mentioned in the foregoing embodiments.

[0061] An electronic device is disclosed by an embodiment of the present application, which includes a memory for saving a computer program and a processor for executing the computer program to implement the method disclosed by any of the foregoing embodiments.

[0062] In the embodiment, when the processor executes the computer program saved in the memory, the following steps can be specifically implemented: taking the target dynamic random storage area and the storage disk as scheduling objects; dividing the storage space of the scheduling objects into a plurality of storage blocks according to a preset division strategy; determining the first access heat of each storage block by using a first heat statistical method; and calculating the current threshold value of the migration destination according to the free capacity of the migration destination, the migration frequency of the migration destination, and the historical threshold value of the migration destination; wherein the target device is connected with a host, the host includes a host dynamic random storage area; the target dynamic random storage area is an extension of the host dynamic random storage area; when the target dynamic random storage area is taken as the scheduling object, the migration destination is the host dynamic random storage area; when the storage disk is taken as the scheduling object, the migration destination is the target dynamic random storage area; and if the first access heat of any storage block is not less than the current threshold value, the data stored in the storage block is migrated to the migration destination.

[0063] In the embodiment, when the processor executes the computer program saved in the memory, the following steps can be specifically implemented: when the target dynamic random storage area is taken as the scheduling object, the preset division strategy is a byte division strategy, and the storage space of the target dynamic random storage area is divided into a plurality of storage blocks in byte units according to the byte division strategy; and when the storage disk is taken as the scheduling object, the preset division strategy is a minimum read-write amount division strategy, and the storage space of the storage disk is divided into a plurality of storage blocks in minimum read-write amount units according to the minimum read-write amount division strategy.

[0064] In the embodiment, when the processor executes the computer program saved in the memory, the following steps can be specifically implemented: the storage space of the target dynamic random storage area and the storage space of the storage disk are respectively divided into a plurality of storage blocks by using the same preset division strategy.

[0065] In the embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: performing hash operation on the address of each storage block respectively; determining the position markers corresponding to the respective storage block in the plurality of hash tables according to the hash operation results; determining the respective counter values for the position markers corresponding to the same storage block; selecting the minimum value from the respective counter values corresponding to the same storage block, and obtaining the target value by adding one to the minimum value, and taking the target value as the first access heat of the storage block.

[0066] In the embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: for the same storage block, if the counter value other than the target value in each counter value is less than the target value, the counter value is modified to the target value, and if the counter value other than the target value in each counter value is not less than the target value, the counter value is kept unchanged.

[0067] In the embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: detecting whether the counter values corresponding to the storage block have been marked with the hot indicator; if the counter values corresponding to the storage block have been marked with the hot indicator, the step of detecting whether the first access heat of the corresponding storage block is not less than the current quasi-moving threshold is abandoned, and the process ends; if the counter values corresponding to the storage block have not been marked with the hot indicator, the first access heat of the corresponding storage block is detected; if the first access heat is not less than the current quasi-moving threshold, the counter values corresponding to the storage block are marked with the hot indicator; if the first access heat is less than the current quasi-moving threshold, the counter values corresponding to the storage block are marked with the cold indicator, and the process ends.

[0068] In the embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: if this time is the first calculation for the corresponding storage block, the counter values corresponding to the position markers corresponding to the corresponding storage block are zero; if this time is not the first calculation for the corresponding storage block, the current counter values corresponding to the position markers corresponding to the corresponding storage block are retained.

[0069] In the embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: calculating the second access heat of each data block in the target dynamic random storage area by using the second heat statistical method; the operation complexity of the second heat statistical method is lower than that of the first heat statistical method; if the second access heat of any data block is lower than the preset moving down threshold and the data block is not modified, the data block is deleted from the target dynamic random storage area; if the second access heat of any data block is lower than the preset moving down threshold and the data block is modified, the data block is moved from the target dynamic random storage area to the storage disk.

[0070] In this embodiment, the processor executes the computer program stored in the memory, and the following steps can be specifically implemented: if the dirty bit field corresponding to any data block is the first target value, it is confirmed that the data block is not modified; if the dirty bit field corresponding to any data block is the second target value, it is confirmed that the data block is modified.

[0071] In this embodiment, the processor executes the computer program stored in the memory, and the following steps can be specifically implemented: if the access times of any data block is incremented by one, the second access heat of the data block is incremented by one.

[0072] In this embodiment, the processor executes the computer program stored in the memory, and the following steps can be specifically implemented: a mapping relationship table is constructed in the target dynamic random storage area, and the mapping relationship table records the address mapping relationship of each data block and the storage disk, the second access heat and the dirty bit field.

[0073] In this embodiment, the processor executes the computer program stored in the memory, and the following steps can be specifically implemented: according to the remaining capacity of the target dynamic random storage area, the current moving threshold and the preset moving threshold, the value of the preset moving threshold is updated.

[0074] Further, the embodiment of the present application also provides an electronic device. Wherein, the above-mentioned electronic device can be a server as shown in the Figure 8 , or a terminal as shown in the Figure 9 . Figure 8 and Figure 9 are structural diagrams of electronic devices according to an exemplary embodiment, and the contents in the diagrams cannot be considered as any limitation to the use range of the present application.

[0075] Figure 8 A structural diagram of a server provided by the embodiment of the present application. The server can specifically include: at least one processor, at least one memory, power supply, communication interface, input and output interface and communication bus. Wherein, the memory is used to store computer programs, the computer programs are loaded and executed by the processor to realize the related steps in the data moving disclosed in any of the preceding embodiments.

[0076] In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and the external device, and the communication protocol followed by the communication interface is any communication protocol applicable to the technical solution of the present application, which is not limited here; the input and output interface is used to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which is not limited here.

[0077] In addition, the memory as a carrier for storing resources can be a read-only memory, a random access memory, a magnetic disk, an optical disk, or the like, and the resources stored thereon include an operating system, a computer program, data, and the like, and the storage mode can be temporary storage or permanent storage.

[0078] The operating system is used to manage and control each hardware device on the server and the computer program, so as to realize the operation and processing of the processor on the data in the memory, and can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program capable of completing the data migration method disclosed in any of the preceding embodiments, the computer program can further include a computer program capable of completing other specific work. In addition to the data including the update information of the application program and the like, the data can also include the developer information of the application program and the like.

[0079] Figure 9 A structure schematic diagram of a terminal provided by the embodiment of the present application, which can specifically include but is not limited to a smart phone, a tablet computer, a notebook computer, a desktop computer, etc.

[0080] Generally, the terminal in the embodiment includes a processor and a memory.

[0081] The processor can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor can be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor can also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor can be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor can also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0082] The memory can include one or more computer non-volatile storage media, which can be non-transitory. The memory can also include a high-speed random access memory, and a non-volatile memory such as one or more disk storage devices, flash storage devices. In the embodiment, the memory is at least used to store the following computer program, wherein the computer program is loaded and executed by the processor, and can realize the related steps in the data migration method executed by the terminal side disclosed in any of the preceding embodiments. In addition, the resources stored by the memory can also include an operating system and data, and the storage mode can be temporary storage or permanent storage. The operating system can include Windows, Unix, Linux, etc. The data can include but is not limited to application update information.

[0083] In some embodiments, the terminal can also include a display screen, an input / output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0084] Those skilled in the art can understand that, Figure 9 The structure shown in the figure does not constitute a limitation on the terminal, and can include more or fewer components than the figure.

[0085] The non-volatile storage medium provided by the embodiment of the present application is introduced below, and the non-volatile storage medium described below can be referred to with other embodiments described herein.

[0086] A non-volatile storage medium for saving a computer program, wherein the computer program is executed by a processor to realize the data migration method disclosed in the preceding embodiments. The non-volatile storage medium is a computer-readable non-volatile storage medium, which is a carrier for storing resources, and can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc. The resources stored thereon include an operating system, a computer program and data, etc., and the storage mode can be temporary storage or permanent storage.

[0087] The computer program product provided by the embodiment of the present application is introduced below, and the computer program product described below can be referred to with other embodiments described herein.

[0088] A computer program product, comprising computer programs / instructions, which are executed by a processor to realize the steps of the data migration method disclosed above.

[0089] The embodiment of the present application also provides another computer program product, which includes a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium is used to store a computer program, and the computer program is executed by a processor to realize the steps in any of the preceding embodiments.

[0090] The various embodiments described in this specification are presented for the purpose of illustration and description. Each of the embodiments highlights different aspects of the application, and the same or similar elements in each embodiment are referred to by the same or similar reference numbers.

[0091] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in random access memory (RAM), flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of non-transitory storage medium known in the art. The term "non-transitory" simply means a computer-readable medium that does not include a transient signal.

[0092] The principles and implementations of the present application have been described in relation to specific examples, which are presented for the purpose of illustration and description. The above description of the embodiments is only intended to help understand the method and its core idea of the present application; for those skilled in the art, according to the idea of the present application, the specific implementation and application scope will be changed, and the above description of the embodiments should not be understood as limiting the present application.

Claims

1. A data migration method, characterized by, The application is applied to a target device, the target device comprising a target dynamic random area and a storage disk, comprising: taking the target dynamic random area and the storage disk as scheduling objects; dividing the storage space of the scheduling object into a plurality of storage blocks according to a preset division strategy; determining the first access heat of each storage block by using a first heat statistical method; calculating the current threshold of the migration destination according to the free capacity of the migration destination, the migration frequency of the migration destination and the historical threshold of the migration destination; wherein the target device is connected with a host, the host comprising a host dynamic random area; the target dynamic random area is an extension of the host dynamic random area; when the target dynamic random area is taken as the scheduling object, the migration destination is the host dynamic random area; when the storage disk is taken as the scheduling object, the migration destination is the target dynamic random area; if the first access heat of any storage block is not less than the current threshold, the data stored in the storage block is migrated to the migration destination.

2. The method of claim 1, wherein, dividing the storage space of the scheduling object into a plurality of storage blocks according to a preset division strategy, comprising: when the target dynamic random area is taken as the scheduling object, the preset division strategy is a byte division strategy, and the storage space of the target dynamic random area is divided into a plurality of storage blocks in byte units according to the byte division strategy; when the storage disk is taken as the scheduling object, the preset division strategy is a minimum read-write amount division strategy, and the storage space of the storage disk is divided into a plurality of storage blocks in minimum read-write amount units according to the minimum read-write amount division strategy.

3. The method of claim 1, wherein, dividing the storage space of the scheduling object into a plurality of storage blocks according to a preset division strategy, comprising: respectively dividing the storage space of the target dynamic random area and the storage space of the storage disk into a plurality of storage blocks by using the same preset division strategy.

4. The method of claim 1, wherein, determining the first access heat of each storage block by using a first heat statistical method, comprising: respectively performing hash operation on the addresses of each storage block; determining the position marks corresponding to the respective storage blocks in a plurality of hash tables according to the hash operation results; determining the corresponding counter values for each position mark corresponding to the same storage block; selecting the minimum value from the corresponding counter values of the same storage block, and obtaining a target value by adding one to the minimum value, wherein the target value is taken as the first access heat of the storage block.

5. The method of claim 4, wherein, further comprising: for the same storage block, if the counter values other than the target value are less than the target value, the counter values are modified to the target value; if the counter values other than the target value are not less than the target value, the counter values remain unchanged.

6. The method of claim 4, wherein, after taking the target value as the first access heat of the storage block, further comprising: detecting whether the corresponding counter values of the storage block have marked a hot indicator; if the corresponding counter values of the storage block have marked the hot indicator, the step of detecting whether the first access heat of the corresponding storage block is not less than the current threshold is abandoned, and the process ends. If the counter values corresponding to the storage block are not marked with the hot indicator, it is detected whether the first access hotness of the corresponding storage block is not less than the current threshold value of migration; if not less than, the counter values corresponding to the storage block are marked with the hot indicator; if less than, the counter values corresponding to the storage block are marked with the cold indicator, and the process ends.

7. The method of claim 6, wherein, After the counter values corresponding to the storage block are marked with the hot indicator, the step of migrating the data stored in the storage block to the migration destination is performed.

8. The method of claim 5, wherein, The corresponding counter values of each location mark corresponding to the same storage block are determined, including: If this is the first calculation for the corresponding storage block, the counter values corresponding to each location mark corresponding to the corresponding storage block are set to zero; If this is not the first calculation for the corresponding storage block, the current counter values corresponding to each location mark corresponding to the corresponding storage block are retained.

9. The method of claim 1, wherein, The current threshold value of migration of the migration destination is calculated according to the free capacity of the migration destination, the migration-in frequency of the migration destination, and the historical threshold value of migration of the migration destination, including: The threshold parameter Y of the current threshold value of migration is calculated according to a first formula; The difference Q of 1-Y is calculated; The Qth quantile of the first access hotness of each storage block is taken as the current threshold value of migration; The first formula is Y=Y t-1 ×[(1+α) a / (1+β) b ];α is the idle capacity, β is the moving-in frequency, a is a first coefficient corresponding to the idle capacity, b is a second coefficient corresponding to the moving-in frequency; Y t-1 is a threshold parameter of the historical threshold value, and Y t-1 is a set value at the beginning.

10. The method according to any one of claims 1 to 9, characterized in that, Further comprising: The second access hotness of each data block in the target dynamic random storage area is calculated by using a second hotness statistical method; the operation complexity of the second hotness statistical method is lower than that of the first hotness statistical method; If the second access hotness of any data block is lower than a preset downshift threshold value and the data block is not modified, the data block is deleted from the target dynamic random storage area; If the second access hotness of any data block is lower than a preset downshift threshold value and the data block is modified, the data block is migrated from the target dynamic random storage area to the storage disk.

11. The method of claim 10, wherein, Further comprising: If the dirty bit field corresponding to any data block is a first target value, it is confirmed that the data block is not modified; If the dirty bit field corresponding to any data block is a second target value, it is confirmed that the data block is modified.

12. The method of claim 10, wherein, The second access hotness of each data block in the target dynamic random storage area is calculated by using a second hotness statistical method, including: If the access frequency of any data block is incremented by one, the second access hotness of the data block is incremented by one.

13. The method of claim 10, wherein, Further comprising: A mapping relationship table is constructed in the target dynamic random storage area, and the mapping relationship table records the address mapping relationship between each data block and the storage disk, the second access hotness, and the dirty bit field.

14. A data migration system, comprising: Comprising: A host and a target device connected with the host; The target device comprises a first scheduler, a second scheduler, a target dynamic random storage area, and a storage disk; The host comprises a host dynamic random storage area; the target dynamic random storage area is an extension of the host dynamic random storage area; The first scheduler is configured to: divide the storage space of the target dynamic random storage area into a plurality of storage blocks according to a preset division strategy; determine a first access heat of each storage block by using a first heat statistical method; calculate a current threshold of migration of the host dynamic random storage area according to a free capacity of the host dynamic random storage area, a migration-in frequency of the host dynamic random storage area and a historical threshold of migration of the host dynamic random storage area; and if the first access heat of any storage block is not less than the current threshold of migration, move the data stored in the storage block to the host dynamic random storage area. The second scheduler is configured to: divide the storage space of the storage disk into a plurality of storage blocks according to a preset division strategy; determine a first access heat of each storage block by using a first heat statistical method; calculate a current threshold of migration of the target dynamic random storage area according to a free capacity of the target dynamic random storage area, a migration-in frequency of the target dynamic random storage area and a historical threshold of migration of the target dynamic random storage area; and if the first access heat of any storage block is not less than the current threshold of migration, move the data stored in the storage block to the target dynamic random storage area.

15. An electronic device, comprising: The computer program product comprises: a memory configured to store a computer program; a processor configured to execute the computer program to implement the method according to any one of claims 1 to 13.

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