Electronic equipment and control method

Abstract

The invention provides electronic equipment, which comprises a plurality of first processors, and the first processors are connected based on data channels capable of controlling communication disconnection; the second processor is used for controlling connection and disconnection of the data channels according to the number of the models and / or functions of the models; wherein the plurality of first processors communicated with the data channel are jointly used for supporting the model work based on the model data of the model. The invention further provides a control method applied to the second processor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of electronic devices, and more particularly, to an electronic device and a control method. BACKGROUND

[0002] With the rapid development of artificial intelligence technology, specific processors (such as neural network processing unit (NPU) cards) have become important hardware components for processing complex computing tasks, and can efficiently run various deep learning models to support image recognition, natural language processing and other applications. However, electronic devices can usually only run a single model on a single processor, and this configuration results in inefficient use of multi-processor resources. When there are multiple processors of the same type in a device, only a single model is often supported for running, and parallel processing of multiple models cannot be achieved. This limitation not only causes waste of processor resources, but also significantly reduces the overall performance and flexibility of the system. SUMMARY

[0003] Therefore, the present disclosure provides an electronic device and a control method.

[0004] One aspect of the present disclosure provides an electronic device, comprising: a plurality of first processors, each first processor being connected with each other through a data channel based on controllable communication disconnection; a second processor configured to control the connection and disconnection of the data channel according to the number of models and / or the functions of each model; wherein the plurality of first processors with connected data channels are collectively configured to support model work based on model data of the models.

[0005] According to an embodiment of the present disclosure, the electronic device further comprises: a plurality of memories configured to store model data of each model, the first processors being connected with the memories correspondingly, and the number of memories matching the number of first processors; and the second processor is further configured to control the activation state of the memories corresponding to the first processors according to the connection state of the data channel, and store different model data in different memories in the activation state.

[0006] Another aspect of the present disclosure provides a control method applied to a second processor, comprising: obtaining target data, the target data including model data of a plurality of models; controlling the communication disconnection or connection between a plurality of first processors according to the models, to form a plurality of processing units, each processing unit corresponding to one model, and each processing unit including at least one first processor; and controlling each processing unit to run the corresponding model based on the corresponding model data.

[0007] According to an embodiment of the present disclosure, the communication bandwidth of the processing unit has a corresponding relationship with the number of first processors included in the processing unit.

[0008] According to an embodiment of the present disclosure, the method for controlling the communication disconnection or connection between the plurality of first processors to form the plurality of processing units comprises: rounding down the number of the first processors relative to the number of the models to obtain a first target value; rounding up the number of the first processors relative to the number of the models to obtain a second target value; and controlling the communication disconnection or connection between the plurality of first processors to form the plurality of processing units, wherein the number of the first processors in each processing unit is the first target value or the second target value.

[0009] According to an embodiment of the present disclosure, the method for controlling further comprises: controlling the activation state of at least part of the memories according to the processing units, wherein the activated memories correspond one-to-one to the processors included in the processing units; controlling the storage of the model data corresponding to different models into different memories in the activated state, wherein the processors in the different memories are in different processing units; and controlling the running of the corresponding models by the processing units based on the corresponding model data, comprising: controlling the running of the corresponding models by the processing units based on the model data in the corresponding memories.

[0010] According to an embodiment of the present disclosure, the method for controlling the plurality of first processors to form the plurality of processing units comprises: identifying the functions of the models; and controlling the communication disconnection or connection between the plurality of first processors to form the plurality of processing units according to the functions of the models, so that the computing power of each processing unit matches the function of the corresponding model.

[0011] According to an embodiment of the present disclosure, the method for controlling further comprises: in response to the running of the models by the processing units, controlling the processing units to stop running the corresponding models when the load of the target task corresponding to the model is greater than or equal to a preset load threshold; controlling the communication disconnection or connection between the plurality of first processors to form the plurality of processing units again according to the load of the target task corresponding to each processing unit, so that the computing power of the reformed processing units matches the load of the target task corresponding to the models; and controlling the reformed processing units to run the corresponding models again to perform the target task corresponding to the models.

[0012] According to an embodiment of the present disclosure, the method for controlling the communication disconnection or connection between the plurality of first processors to form the plurality of processing units comprises: generating and sending first prompt information according to the models, wherein the first prompt information is used to indicate the number of the first processors and the candidate working modes of the models; and in response to receiving feedback information corresponding to the prompt information and the feedback information representing that the working modes of the models are multi-model parallel running, controlling the communication disconnection or connection between the plurality of first processors to form the plurality of processing units.

[0013] According to an embodiment of the present disclosure, the control method further includes: in response to the number of models being greater than the number of first processors, determining N target models from the M models, N being an integer greater than 1, M being an integer greater than 1, and the number of models being M; and controlling the plurality of first processors to form a plurality of processing units, including: controlling the communication between the first processors to be disconnected to form N processing units; and controlling each processing unit to run a corresponding model based on corresponding model data, including: controlling the N processing units to run the corresponding target models based on the model data of the target models.

[0014] Another aspect of the present disclosure provides a control device, including: a first acquisition module configured to acquire target data, the target data including model data of a plurality of models; a first control module configured to control the communication between a plurality of first processors to be disconnected or connected according to the models, to form a plurality of processing units, the processing units corresponding to the models one by one, and each processing unit including at least one first processor; and a second control module configured to control each processing unit to run a corresponding model based on corresponding model data.

[0015] According to an embodiment of the present disclosure, the electronic device further includes: a memory connected to the second processor; and wherein the memory stores instructions executable by the at least one second processor, and the instructions are executed by the at least one second processor to enable the at least one second processor to perform the control method of any one of the preceding embodiments.

[0016] Another aspect of the present disclosure provides a computer readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to perform the control method according to any one of the preceding embodiments.

[0017] Another aspect of the present disclosure provides a computer program product, including computer programs / instructions, characterized by the computer programs / instructions being executed by a processor to implement the operations of the control method of any one of the preceding embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A block diagram of an electronic device according to an embodiment of the present disclosure is schematically shown;

[0020] Figure 2 Another block diagram of an electronic device according to an embodiment of the present disclosure is schematically shown;

[0021] Figure 3 A flowchart of a control method according to an embodiment of the present disclosure is schematically shown;

[0022] Figure 4 a block diagram illustrating a disconnected data lane according to an embodiment of the disclosure is schematically shown;

[0023] Figure 5 a block diagram illustrating a connected data lane according to an embodiment of the disclosure is schematically shown;

[0024] Figure 6 a flow diagram illustrating forming a plurality of processing units in a control method according to an embodiment of the disclosure is schematically shown;

[0025] Figure 7 another flow diagram illustrating a control method according to an embodiment of the disclosure is schematically shown;

[0026] Figure 8 another flow diagram illustrating forming a plurality of processing units in a control method according to an embodiment of the disclosure is schematically shown;

[0027] Figure 9 another flow diagram illustrating forming a plurality of processing units in a control method according to an embodiment of the disclosure is schematically shown;

[0028] Figure 10 another flow diagram illustrating forming a plurality of processing units in a control method according to an embodiment of the disclosure is schematically shown;

[0029] Figure 11 another flow diagram illustrating a control method according to an embodiment of the disclosure is schematically shown;

[0030] Figure 12 a block diagram illustrating a control apparatus according to an embodiment of the disclosure is schematically shown; and

[0031] Figure 13 another block diagram illustrating an electronic device adapted to implement the above-described method according to an embodiment of the disclosure is schematically shown. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description which follows is merely illustrative and is not intended to limit the scope of the disclosure. In the following detailed description of embodiments of the disclosure, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. However, it will be apparent to one skilled in the art that one or more embodiments of the disclosure can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring aspects of the disclosure.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the terms "comprises", "comprising", "includes", "including" and the like are, where used, meant to be inclusive, but not limiting in any way.

[0034] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art unless otherwise defined herein. It should be noted that the terms used herein are defined as having meanings that are consistent with the context of the specification in which they are used, and should not be interpreted in an overly idealized or overly formal way.

[0035] In the case of using expressions similar to "at least one of A, B, and C, etc.", it should generally be interpreted to include any of them, singly or in combination. For example, "a system having at least one of A, B, and C" should be interpreted to include a system having A alone, a system having B alone, a system having C alone, a system having A and B together, a system having A and C together, a system having B and C together, and / or a system having A, B, and C together, etc.

[0036] In embodiments of the disclosure, the collection, updating, analysis, processing, use, transmission, provision, disclosure, storage, etc. of data (for example, including but not limited to user personal information) involved are in accordance with the provisions of relevant laws and regulations, are used for legal purposes, and do not violate public order and good customs. In particular, necessary measures are taken to prevent illegal access to user personal information data, to maintain the security of user personal information, network security and national security.

[0037] Embodiments of the disclosure provide an electronic device, comprising: a plurality of first processors, each first processor being connected through a data channel based on controllable communication disconnection; a second processor configured to control the connection and disconnection of the data channel according to the number of models and / or the functions of each model; wherein the plurality of first processors connected through the data channel are collectively configured to support model work based on model data of the model.

[0038] Figure 1 A block diagram of an electronic device according to embodiments of the disclosure is schematically shown.

[0039] As Figure 1As shown, the electronic device includes a plurality of first processors, which are connected via controllable communication-disconnection data channels. The first processors can be hardware acceleration units configured to perform specific types of computing tasks (e.g., neural network inference or training). Specifically, the first processors can be neural processing units (NPUs). Each first processor can be disposed on a separate board card, such as an M.2 interface card, to facilitate modular addition or removal.

[0040] For example, with reference to the accompanying drawings Figure 1 In an electronic device having four M.2 slots, four first processors each carrying an NPU are inserted into the slots. There are controllable data channels between the first processor 1 and the first processor 2, between the first processor 2 and the first processor 3, and between the first processor 3 and the first processor 4. When the first processor 1 and the first processor 2 need to work together, the data channel between them can be controlled to be in a connected state; when they need to work independently, the data channel can be controlled to be in a disconnected state. It should be noted that the above connection is a serial connection, and in other embodiments, the plurality of first processors are connected in parallel via a bus.

[0041] The data channel refers to a link, physically or logically, for transmitting data between two or more first processors, and the key feature is that the connection state of the link can be controlled by an external signal, i.e., the direct communication between the first processors can be established (connected) or disconnected (disconnected) as needed.

[0042] The data channel can be a physical line that can be controlled to be connected or disconnected, or a virtual line located on a bus that can be controlled to be connected or disconnected. The physical line can be a high-speed electronic switch or multiplexer preset on a circuit board carrying multiple first processors, which directly controls the conduction and cutoff of the physical signal path connecting adjacent first processors. The virtual line is usually based on a shared bus architecture, such as a PCIe (Peripheral Component Interconnect Express) bus. Under this architecture, multiple first processors are physically connected to a PCIe switch chip, and by configuring the switch chip, the aggregation or disassembly of multiple physical ports in logic can be achieved. For example, two independent PCIe channels with an x2 bandwidth are logically combined into an x4 channel, thereby forming a virtual, wider "connected" line; or vice versa, an x4 channel is disassembled into two independent x2 channels, forming a virtual "disconnection". It should be noted that the lines that can be controlled to be connected or disconnected between the first processors in the figure are only to illustrate their states, and those skilled in the art can select appropriate data channels according to actual conditions.

[0043] The electronic device includes a second processor configured to control the connection and disconnection of the data channel according to the number of models and / or the functions of the models. The multiple first processors connected by the data channel are collectively configured to support the operation of the models based on the model data of the models. The second processor is configured to first obtain information of one or more models to be processed, the information including at least the number of models. Subsequently, the second processor generates a control instruction to configure the connection and disconnection state of the data channel between the first processors based on the number information. When configured in the connected state, a processing cluster composed of multiple first processors is formed, and the cluster serves as a unified computing resource to jointly carry out the operation task of a single model. The dashed line in the figure represents the data channel and the control channel of the second controller.

[0044] When the data channel is a physical line, the second processor can write a preset control word into a register of a control register of the high-speed electronic switch or multiplexer through a dedicated control bus or a general input-output pin. For example, writing a control word "1" to close the switch to realize the connection of the physical line; writing a control word "0" to disconnect the switch to realize the disconnection of the physical line.

[0045] When the data channel is a virtual line (for example, based on PCIe bus connection), the second processor modifies the internal port configuration register of the PCIe switch chip by accessing the configuration space of the PCIe switch chip. For example, by writing instructions to a specific register, the switch chip is instructed to configure two independent downstream ports (connected to two first processors respectively) in a non-peer mode, logically isolating them from each other, achieving "disconnection"; or configure them in a peer mode and aggregate their bandwidth, enabling them to communicate directly and efficiently, achieving "connection".

[0046] When the device needs to run a single but computationally intensive large language model, the second processor (such as the master chip) determines that the number of models for the current task is 1, and sets the data channel between the multiple first processors involved in the calculation (for example, first processor 1 and first processor 2) to a "connected" state. In this way, first processor 1 and first processor 2 can perform efficient internal data exchange and task coordination, working together as an enhanced processor to perform inference operations for the large language model. Conversely, if the device needs to run two different models simultaneously (for example, one model for face recognition and another model for speech recognition), the second processor determines that the number of models is 2, and controls the data channel between first processor 1 and first processor 2 to be in a "disconnected" state, so that the two first processors become two independent computing units, each loading and running a different model to achieve parallel processing.

[0047] According to embodiments of the present disclosure, by setting a data channel that can be dynamically controlled to be connected or disconnected, and by the second processor flexibly configuring the channel according to the number of models to be run, dynamic aggregation and segmentation of processing resources is achieved. When processing a single complex model, the computing power of multiple processors can be pooled to meet the demand for high-performance computing; when processing multiple independent models, processor resources can be allocated to different tasks to achieve high-throughput parallel computing.

[0048] Figure 2 Another block diagram of an electronic device according to embodiments of the present disclosure is schematically shown.

[0049] As Figure 2As shown, the electronic device also includes multiple memories for storing model data for each model. A first processor is connected to each memory, and the number of memories matches the number of first processors. The "memory" can be volatile memory (such as DRAM) or non-volatile memory (such as NAND Flash), configured as a local data cache for the first processor, providing high-bandwidth, low-latency access to model data during computation. Each first processor has its own dedicated, physically or logically tightly coupled memory unit. For example, in an M.2 board design, the NPU chip (first processor) and the memory chip (memory) can be integrated onto the same board, forming a paired computing and storage unit.

[0050] Specifically, such as Figure 2 As shown, this electronic device includes multiple computing-storage units, each consisting of a first processor and a paired memory. When N first processors are installed in the device, N corresponding memories are also configured, forming a one-to-one correspondence architecture. Specifically, for example, in a device with four M.2 slots, if four M.2 cards integrating NPUs and memory chips are inserted, then the device will have four first processors and four corresponding memories.

[0051] The second processor is also used to control the activation state of the memory corresponding to the first processor according to the connectivity of the data channel, and to store different model data in different memories that are in the activation state.

[0052] The "enabled state" of a memory can refer to the memory being powered on and in a read / write operational state. The second processor determines which paired memories need to be activated to load model data based on its configuration of the data channel between the first processor (connected or disconnected).

[0053] Specifically, such as Figure 2 As shown, when the second processor controls the data channels between multiple first processors to collaboratively process a single model, the second processor only needs to utilize one or a portion of the memory in the collaborative processing cluster to store the model data for that model. However, when the second processor controls the data channels between the first processors to disconnect, enabling them to process multiple different models in parallel, the second processor will utilize the memory corresponding to each independently operating first processor and load the different model data into these utilized memories respectively. The dashed lines in the diagram represent the data channels and control channels of the second controller.

[0054] On the basis of the foregoing examples, when the two NPU cards (first processors 1 and 2) are configured in a single-thread mode (data channel connected) to jointly run a large model, the second processor sends a control signal to enable only the memory 1 corresponding to the first processor 1, while keeping the memory 2 in a disabled state. At this time, the model data of the large model will be entirely filled into the enabled memory 1. Conversely, when the two NPU cards are configured in a multi-thread mode (data channel disconnected) to run two different models respectively, the second processor enables the memory 1 and the memory 2 at the same time, and then fills the data of model A into the memory 1 and fills the data of model B into the memory 2.

[0055] According to embodiments of the present disclosure, by introducing a memory paired with the first processor and enabling the memory according to the cooperative or independent working mode of the processors (i.e., the connection status of the data channel) by the second processor, more refined resource management is achieved. On the one hand, when multiple processors work cooperatively, enabling only the necessary memory can avoid redundant storage of data in multiple memories, saving storage space and simplifying the complexity of data consistency management. On the other hand, this on-demand enabling method can significantly reduce the power consumption of the memory in a non-working state, thereby optimizing the energy efficiency ratio of the entire electronic device.

[0056] Figure 3 A flowchart of a control method according to an embodiment of the present disclosure is schematically shown. Figure 4 A block diagram of a disconnected data channel according to an embodiment of the present disclosure is schematically shown. Figure 5 A block diagram of a connected data channel according to an embodiment of the present disclosure is schematically shown.

[0057] As shown in Figure 3 The control method can at least include operations S310-S350. The control method can be performed by the second processor in the electronic device.

[0058] In operation S310, target data is obtained, the target data including model data of a plurality of models respectively. The second processor receives a computing task request from an upper-layer application or a user, the request containing information of one or more models that need to be run. The second processor parses the request to determine the specific number of models to be run and the model data (e.g., network structure, weight parameters, etc.) corresponding to each model.

[0059] For example, when the user needs to perform two tasks of face recognition and voice recognition at the same time, the second processor receives target data containing two different models (model A and model B) and their corresponding model data. Or, when the user needs to perform a complex natural language processing task, the target data received by the second processor can only contain a large language model (model C) and its model data.

[0060] In operation S320, according to the model, the communication between the plurality of first processors is controlled to be disconnected or connected, forming a plurality of processing units, the processing units corresponding to the models one by one, and the processing units at least including one first processor. The processing unit refers to a logical computing set composed of one or more first processors and used for performing a single model operation task. The second processor determines how to organize the available first processors according to the number of models obtained in operation S310.

[0061] The second processor generates and sends a control instruction according to the information of each model (such as the number of models) to configure the on-off state of the data channel connecting each first processor. If one model is obtained, the data channel between the plurality of first processors is controlled to be connected to each other, so as to be aggregated into one processing unit. If M models are obtained, the data channel between the first processors is controlled to form M independent processing units, and each processing unit can include one or more first processors.

[0062] For example, referring to Figure 4 In the scenario where the device has two first processors (NPU1, NPU2), if the number of models obtained is 2 (models A and B), the second processor controls the communication channel between NPU1 and NPU2 to be in a "disconnected" state, thereby forming two independent processing units, namely {NPU1} and {NPU2}, which are respectively used for corresponding models A and B.

[0063] For example, referring to Figure 5 In the scenario where the device has two first processors (NPU1, NPU2), if the number of models obtained is 1 (model C), the second processor controls the communication channel between NPU1 and NPU2 to be in a "connected" state, thereby forming a processing unit {NPU1, NPU2} including two NPUs and having stronger computing power, which is uniformly used for corresponding model C.

[0064] In operation S330, each processing unit is controlled to run the corresponding model based on the corresponding model data.

[0065] After the processing unit is constructed, the second processor distributes the model data required by each model to the corresponding processing unit, and issues an execution instruction to start the operation process of each processing unit.

[0066] For example, in the aforementioned scenario: for the case of forming two independent processing units {NPU1} and {NPU2}, the second processor loads the model data of model A to NPU1 and the model data of model B to NPU2, and then instructs the two processing units to start running respectively. For the case of forming one aggregated processing unit {NPU1, NPU2}, the second processor loads the model data of model C to the processing unit, and then instructs the aggregated unit to cooperatively perform the operation task of model C.

[0067] According to embodiments of the present disclosure, by first identifying model information, then controlling the inter-processor communication to form matched processing units accordingly, and finally performing operations, the physical flexibility (controllable data channels) of hardware is converted into actual application layer advantages. It enables the same set of hardware devices to seamlessly switch between the two working modes of "multi-task parallel processing" and "single-task intensive research", realizing efficient, intelligent and flexible scheduling and utilization of computing resources.

[0068] According to embodiments of the present disclosure, the communication bandwidth of a processing unit has a corresponding relationship with the number of first processors included in the processing unit. The communication bandwidth refers to the data transmission rate between the host (e.g., the source of model data) of the electronic device and each processing unit formed. The corresponding relationship refers to that the communication bandwidth allocated to a processing unit is adjusted according to the number of first processors contained in the processing unit, or according to the total number of processing units formed in the current system. The bandwidth is usually determined by the channel configuration of the underlying physical communication interface (such as PCIe bus). The corresponding relationship refers to that the communication bandwidth allocated to a processing unit is adjusted according to the number of first processors contained in the processing unit, or according to the total number of processing units formed in the current system.

[0069] The total communication bandwidth (e.g., the total number of PCIe channels) of the electronic device is a fixed value. When multiple first processors are controlled to form processing units, the total bandwidth is dynamically divided and allocated to each processing unit. Generally, when fewer first processors are combined into a processing unit, or when the system needs to support a larger number of independent processing units, the bandwidth allocated to each processing unit is relatively small. Conversely, when more first processors are aggregated to form a processing unit, a larger bandwidth is allocated to it to match its enhanced computing power.

[0070] Figure 6 A flowchart of forming multiple processing units in the control method according to embodiments of the present disclosure is schematically shown.

[0071] As Figure 6 shown, on the basis of the aforementioned embodiments, S320 can include operations S610-S630.

[0072] At operation S610, the number of first processors is rounded down relative to the multiple of the number of models as a first target value. After obtaining the total number N of first processors and the total number M of models to be run, the second processor calculates the ratio N / M, and performs a floor operation on the ratio, and the result is the first target value. This value represents the number of first processors that each processing unit can at least get when performing average allocation. For example, when there are 3 first processors (N=3) in the electronic device, and 2 different models (M=2) need to be run in parallel, the second processor calculates 3 / 2 = 1.5, and the first target value obtained after rounding down is 1.

[0073] At operation S620, the number of first processors is rounded up relative to the multiple of the number of models as a second target value. The second processor also performs a ceiling operation based on the ratio N / M, and the result is the second target value. The difference between the first target value and the second target value is usually 1, which represents the number of processors that some processing units can have more than other units when the number of processors cannot be divided by the number of models. Continuing with the above example, when N=3 and M=2, the second processor calculates 3 / 2 = 1.5, and the second target value obtained after rounding up is 2.

[0074] At operation S630, the communication between the plurality of first processors is controlled to be disconnected or connected, forming a plurality of processing units, and the number of first processors included in a processing unit is the first target value or the second target value. The physical processors are grouped according to the calculation result. The second processor allocates the total N first processors into M processing units, some of which contain the first target value of processors, and some of which contain the second target value of processors, finally ensuring that the total number of processors contained in all M processing units is exactly N.

[0075] Continuing with the above example, 2 processing units need to be formed, and each processing unit contains 1 (first target value) or 2 (second target value) processors. To use all 3 processors, the only allocation scheme is to form one processing unit containing 2 first processors, and one processing unit containing 1 first processor. To this end, the second processor controls the data channel between first processor 1 and first processor 2 to be connected, so that they are aggregated into one processing unit; at the same time, the data channel between first processor 2 and first processor 3 is controlled to be disconnected, so that first processor 3 becomes another processing unit independently.

[0076] According to an embodiment of the present disclosure, by calculating the target values of the down and up rounding, the method can ensure that all available first processors are included in the calculation, avoiding the idling of resources. At the same time, the processor resources are divided to different model tasks in a way as balanced as possible, thereby achieving efficient and sufficient use of computing resources.

[0077] Figure 7 Another flowchart of the control method according to an embodiment of the present disclosure is schematically shown.

[0078] As shown in the foregoing embodiments, the control method can further include operation S710. Figure 7

[0079] In operation S710, the activation state of at least part of the memory is controlled according to the processing unit. The activated memory corresponds to the first processor included in the processing unit one by one. After the formation of the processing unit in operation S320, the second processor will identify the set of first processors contained in each processing unit. Then, according to the set, the second processor sends a control instruction to the memory paired with these first processors to activate (i.e. set to the activated state) at least one of the memories. For the processing unit aggregated by multiple first processors, only the memory corresponding to one of the first processors can be activated as the main storage area shared by the processing unit.

[0080] For example, when two processing units are formed, one containing first processors 1 and 2 (PU_A) and the other containing first processor 3 (PU_B), the second processor will: enable memory 1 for PU_A, while keeping memory 2 in the non-activated state; and enable memory 3 for PU_B.

[0081] In other embodiments, the memory has an aggregation function, and accordingly, the memory corresponding to each first processor included in the processing unit can be aggregated into a whole storage space as the storage space of the processing unit.

[0082] ​At operation S720, the model data corresponding to different models is stored in different memories in an enabled state, and the processors corresponding to the different memories are in different processing units. The second processor controls the data input channel to route the model data of model A to an enabled memory belonging to processing unit A and to route the model data of model B to an enabled memory belonging to processing unit B, so as to ensure that the computing tasks of different models are isolated at the data level. Continuing with the above example, there are two models (model A and model B) to be run, and model A is assigned to PU_A and model B is assigned to PU_B. The second processor controls the model data of model A to be filled into enabled memory 1 (the processor 1 corresponding to the memory 1 belongs to PU_A) and the model data of model B to be filled into enabled memory 3 (the processor 3 corresponding to the memory 3 belongs to PU_B).

[0083] Operation S330 can include operation S730.

[0084] At operation S730, the corresponding model is controlled to be run by the processing unit based on the model data in the corresponding memory. After the model data is loaded, the second processor issues an execution instruction to each processing unit. After receiving the instruction, all first processors in the processing unit start reading instructions and data from the enabled memory corresponding to the model data to perform model computation. For a processing unit aggregated by multiple first processors, all member processors access the specified memory loaded with data through the internally connected data channel.

[0085] Continuing with the above example, after the second processor issues the execution instruction: the first processor 1 and the first processor 2 in the processing unit PU_A work together to access the model A data in the memory 1 to perform computation. At the same time, the first processor 3 in the processing unit PU_B works independently to access the model B data in the memory 3 to perform computation.

[0086] According to embodiments of the present disclosure, by further and jointly controlling the enabling state of the corresponding memory and the directional loading of the model data after forming the processing unit, on the one hand, the memory is enabled on demand, especially only part of the memory is enabled when multiple processors aggregate to process a single model, which significantly reduces the standby power consumption and data redundancy of the system and improves the energy efficiency. On the other hand, the model data is accurately loaded into the local memory of the specified processing unit, which ensures data locality and reduces the need for cross-unit data access, thereby effectively avoiding bus contention and data conflicts.

[0087] Figure 8 Another flowchart for forming multiple processing units in the control method according to embodiments of the present disclosure is schematically shown.

[0088] like Figure 8 As shown, based on the aforementioned embodiments, S320 may include operations S810 to S820.

[0089] When operating the S810, the functionality of the model is identified. Model functionality can refer to the inherent, static computational complexity of the model for performing a specific category of tasks. Before deploying the model, the second processor predicts the basic computational power requirements of different model functionalities by parsing the metadata accompanying the model file (e.g., tagged "video decoding," "text summarization," etc.) or by analyzing the model's own network structure (e.g., the number of parameters, the proportion of computationally intensive operators (such as convolution), etc.).

[0090] For example, when an electronic device needs to load a model (Model A) for processing video streams and a model (Model B) for processing text data, the second processor can determine, through identification, that Model A has a higher inherent computing power requirement due to its functional nature (processing high-dimensional, high-volume video signals), while Model B has a lower inherent computing power requirement due to its functional nature (processing relatively low-dimensional text sequences).

[0091] When operating the S820, communication between multiple first processors is controlled to either open or close based on the model's function, forming multiple processing units. This ensures that the computing power of each processing unit matches the corresponding model's function. The computing power of a processing unit is directly proportional to the number of first processors it contains. For models with higher inherent computing power requirements, a more powerful processing unit composed of a larger number of first processors is allocated; conversely, a less powerful processing unit composed of a smaller number of first processors is allocated.

[0092] For example, suppose the device has a total of four first processors (NPU cards). After identifying that model A, which processes video, requires more computing power, while model B, which processes text, requires less computing power, the second processor will perform the following control: it will connect the data channels between first processors 1, 2, and 3 to form a high-computing-power processing unit containing three NPU cards, and allocate this processing unit to model A; at the same time, it will keep first processor 4 independent, as a standard-computing-power processing unit containing only one NPU card, and allocate it to model B.

[0093] According to embodiments of this disclosure, by configuring computing resources that match the computational complexity of different functional models during the deployment phase, the computing power of the entire system can be utilized more rationally and efficiently, ensuring that computationally intensive functions receive sufficient performance support, while avoiding wasting valuable computing resources on functions with low computational requirements.

[0094] Figure 9Another flowchart of forming multiple processing units in the control method according to an embodiment of the disclosure is schematically shown.

[0095] As shown in the foregoing embodiments, the control method can further include operations S910-S930. Figure 9

[0096] At operation S910, in response to the processing unit running the model, if the load of the target task corresponding to the model is greater than or equal to a preset load threshold, the control processing unit stops running the corresponding model. The load of the target task refers to the real-time computing pressure generated by the model when processing specific input data, which is different from the inherent complexity of the model function (static attribute) and is a dynamic quantity. The preset load threshold can be a critical value of one or more performance indicators, such as processing delay, data volume processed per unit time, or utilization rate of the first processor in the processing unit, etc.

[0097] The second processor will continuously monitor the key performance indicators of each processing unit after starting to execute the task. Once it is detected that the performance indicators (such as processing delay) of a certain processing unit continuously exceed the preset threshold, it means that the computing power currently allocated to the processing unit cannot meet the real-time task load requirements. At this time, the second processor will send a pause or terminate instruction to the processing unit to prepare for resource reconstruction.

[0098] For example, following the foregoing embodiments, the initial allocation scheme is that processing unit A (containing 3 NPUs) runs a video model and processing unit B (containing 1 NPU) runs a text model. During the running process, processing unit B receives a target task of processing a million-word level text. The second processor monitors that the computing delay of processing unit B sharply rises and far exceeds the preset load threshold of “processing delay should not be higher than 500 ms”. In response, the second processor first controls processing units A and B to stop the current processing task.

[0099] At operation S920, according to the load of the target task executed by each processing unit, the communication between the multiple first processors is re-controlled to be disconnected or connected, and multiple processing units are formed, so that the computing power of the re-formed processing units matches the load of the target task corresponding to the model. After pausing the high-load task, the second processor will evaluate the real-time load of the current task. It may be found that the high-load task needs more resources, while the load of other tasks can be low and there is resource redundancy. Based on this evaluation, the second processor will develop a new processor allocation scheme that can better match the actual load of the current tasks, and re-control the connection and disconnection of the data channel between the first processors to form a new combination of processing units.

[0100] ​Continuing with the above example, while determining that processing unit B is overloaded, the second processor can find that processing unit A (video model) is currently only processing one low-resolution video stream, and its actual load is low, and the computing power of 3 NPUs is wasted. Therefore, the second processor decides to reassign resources: allocate one NPU from processing unit A to processing unit B. It will send a control instruction to split the original processing unit A ({NPU1, NPU2, NPU3}) and recombine with the original processing unit B ({NPU4}) to form a new processing unit A' ({NPU1, NPU2}) and a new processing unit B' ({NPU3, NPU4}).

[0101] At operation S930, the control re-forms each processing unit to re-run the corresponding model to perform the target task corresponding to the model. After the hardware resource reconstruction is completed, the second processor instructs the new processing unit to load or confirm the model data, and restarts or continues to perform the target task that was previously paused.

[0102] According to embodiments of the present disclosure, on the basis of static function allocation, a dynamic feedback adjustment mechanism based on real-time task load is introduced, so that resource allocation is no longer a one-time static configuration, but a closed-loop optimization process that can adapt to the dynamic changes of task demand. When the initial allocated computing power does not match the actual task load, it can automatically detect and perform "secondary allocation", dynamically migrating computing power resources from low-load tasks to high-load tasks. It realizes the continuous and optimal use of computing resources in complex and variable actual application scenarios.

[0103] Figure 10 Another flowchart of forming multiple processing units in the control method according to an embodiment of the present disclosure is schematically shown.

[0104] As Figure 10 shown, on the basis of the foregoing embodiments, S320 can include operations S1010-S1020.

[0105] At operation S1010, a first prompt information is generated and sent according to the model, and the first prompt information is used to indicate the number of first processors and the candidate working mode of the model. The "candidate working mode" refers to the running mode in which the model can be configured, such as "single model centralized running" or "multiple model parallel running". After obtaining the model information, the second processor will generate a prompt message in combination with the total number of available first processors in the device. The message is sent through a user interface or a communication interface with an external control system for a user or an upper management system to select a suitable running mode.

[0106] For example, when there are 4 first processors in the device, and it is detected that 2 models (model A and model B) need to be run, the first prompt information generated by the second processor can be: "the current available processor number is 4, the recommended working mode is: 1) single model centralized running (4 processors are allocated to 1 model); 2) multi-model parallel running (2 processors are allocated to model A, and 2 processors are allocated to model B). Please confirm the mode selection.

[0107] In operation S1020, in response to receiving the feedback information for the prompt information, and the feedback information representing the working mode of each model as multi-model parallel running, the communication between the plurality of first processors is disconnected or connected, forming a plurality of processing units. Multi-model parallel running refers to the simultaneous independent running of a plurality of models, and each model is executed by an independent processing unit. After receiving the feedback information, if the second processor confirms that the user selects the multi-model parallel running mode, the number of processors allocated to each model is calculated according to the number of models and the total number of first processors, and the on-off state of the data channel is controlled according to the number of processors allocated to each model, forming a plurality of independent processing units.

[0108] For example, continuing with the above example, the user returns feedback information through the interface, confirming the selection of the "multi-model parallel running" mode. After receiving the feedback, the second processor calculates that 2 models should each be allocated 2 processors (4 ÷ 2 = 2), and then controls the data channel between first processors 1 and 2 to be connected, forming a processing unit A ({NPU1, NPU2}) allocated to model A; at the same time, the data channel between first processors 3 and 4 is controlled to be connected, forming a processing unit B ({NPU3, NPU4}) allocated to model B.

[0109] According to embodiments of the present disclosure, by introducing an interactive prompt and feedback mechanism, the decision-making power of resource allocation is partially given to the user or external system, thereby enhancing the flexibility and controllability of the system. Compared with the fully automated allocation mode, this mode based on user confirmation can better adapt to the individual needs in specific scenarios.

[0110] Figure 11 Another flowchart of the control method according to an embodiment of the present disclosure is schematically shown.

[0111] As Figure 11 shown, on the basis of the foregoing embodiments, the control method can further include operation S1110.

[0112] In operation S1110, in response to the number of models being greater than the number of first processors, N target models are determined from the M models, N is an integer greater than 1, M is an integer greater than 1, and the number of models is M.

[0113] Operation S320 can include operation S1120.

[0114] In operation S1120, communication between the respective first processors is controlled to be disconnected to form N processing units.

[0115] Operation S330 can include operation S1130.

[0116] In operation S1130, the N processing units are controlled to run corresponding target models based on model data of the target models.

[0117] The total number of models to be run M exceeds the total number of first processors available in the current device N. In this case, the second processor needs to select N target models from the M models as priority running. For example, based on preset priority rules (such as task urgency, algorithm demand level) or user input, N target models are selected from M models. The remaining M-N models are temporarily shelved and processed after the resources are released.

[0118] For example, it is assumed that there are 3 first processors (N=3) in the device, and 4 models (M=4) need to be run. The second processor selects 3 target models (model A, model B, model C) from the 4 models (model A, model B, model C, model D) according to the task priority, and assigns model A to first processor 1, model B to first processor 2, and model C to first processor 3. Then, the data channels between the first processors 1, 2, and 3 are all disconnected, forming 3 independent processing units, respectively running corresponding target models, and model D is temporarily shelved and deployed after the resources are released.

[0119] Figure 12 A block diagram of a control device according to an embodiment of the present disclosure is schematically shown.

[0120] As shown in FIG. 12, the control device 1200 can include a first acquisition module 1210, a first control module 1220, and a second control module 1230. Figure 12 The first acquisition module 1210 is configured to acquire target data, the target data including model data of a plurality of models respectively. In some embodiments, the first acquisition module 1210 can be configured to perform operation S310 in the above control method, and details are not repeated here.

[0121] The first control module 1220 is configured to control communication between a plurality of first processors to be disconnected or connected according to the models, to form a plurality of processing units, the processing units corresponding to the models one by one, and the processing units including at least one first processor. In some embodiments, the first control module 1220 can be configured to perform operation S320 in the above control method, and details are not repeated here.

[0122]

[0123] ​The second control module 1230 is configured to control each processing unit to run a corresponding model based on corresponding model data. In some embodiments, the second control module 1230 can be configured to perform operation S330 in the control method described above, which will not be repeated here.

[0124] According to an embodiment of the present disclosure, the first control module can include a first calculation module, a second calculation module, and a first sub-control module.

[0125] The first calculation module is configured to round down a multiple of a number of the first processors relative to a number of the models as a first target value. In some embodiments, the first calculation module can be configured to perform operation S610 in the control method described above, which will not be repeated here.

[0126] The second calculation module is configured to round up the multiple of the number of the first processors relative to the number of the models as a second target value. In some embodiments, the second calculation module can be configured to perform operation S620 in the control method described above, which will not be repeated here.

[0127] The first sub-control module is configured to control communication between the plurality of first processors to be disconnected or connected, to form a plurality of processing units, and the number of the first processors included in each processing unit is the first target value or the second target value. In some embodiments, the first sub-control module can be configured to perform operation S630 in the control method described above, which will not be repeated here.

[0128] According to an embodiment of the present disclosure, the control device can further include a third control module and a fourth control module, and the second control module can include a second sub-control module.

[0129] The third control module is configured to control an enabled state of at least part of the memories according to the processing units, and the enabled memories correspond one-to-one to the processors included in the processing units. In some embodiments, the third control module can be configured to perform operation S710 in the control method described above, which will not be repeated here.

[0130] The fourth control module is configured to control model data corresponding to different models to be stored in different memories in an enabled state, and the different memories correspond to different processing units in which the processors are located. In some embodiments, the fourth control module can be configured to perform operation S720 in the control method described above, which will not be repeated here.

[0131] The second sub-control module is configured to control the processing units to run the corresponding models based on the model data in the corresponding memories. In some embodiments, the second sub-control module can be configured to perform operation S730 in the control method described above, which will not be repeated here.

[0132] According to an embodiment of the present disclosure, the first control module can include an identification module and a third sub-control module.

[0133] The identification module is configured to identify the functions of the models. In some embodiments, the identification module can be configured to perform operation S810 in the control method described above, which will not be repeated here.

[0134] The third sub-control module is configured to control the communication between the plurality of first processors to be disconnected or connected according to the functions of the models, to form a plurality of processing units, so that the computing power of each processing unit matches the function of the corresponding model. In some embodiments, the third sub-control module can be configured to perform operation S820 in the control method described above, which will not be repeated here.

[0135] According to embodiments of the present disclosure, the control device can include a fifth control module, a sixth control module, and a seventh control module.

[0136] The fifth control module is configured to, in response to the processing unit running the model, control the processing unit to stop running the corresponding model when the load of the target task corresponding to the model is greater than or equal to a preset load threshold. In some embodiments, the fifth control module can be configured to perform operation S910 in the control method described above, which will not be repeated here.

[0137] The sixth control module is configured to, according to the load of the target task executed by each processing unit, re-control the communication between the plurality of first processors to be disconnected or connected, to form a plurality of processing units, so that the computing power of the re-formed processing unit matches the load of the target task corresponding to the model. In some embodiments, the sixth control module can be configured to perform operation S920 in the control method described above, which will not be repeated here.

[0138] The seventh control module is configured to control the re-formed each processing unit to re-run the corresponding model to execute the target task corresponding to the model. In some embodiments, the seventh control module can be configured to perform operation S930 in the control method described above, which will not be repeated here.

[0139] According to embodiments of the present disclosure, the first control module can include a sending module and a fifth sub-control module.

[0140] The sending module is configured to generate and send first prompt information according to the models, the first prompt information being used to indicate the number of first processors and the candidate working modes of the models. In some embodiments, the sending module can be configured to perform operation S1010 in the control method described above, which will not be repeated here.

[0141] The fifth sub-control module is configured to, in response to receiving feedback information for the prompt information, and the feedback information indicating that the working mode of each model is multi-model parallel running, control the communication between the plurality of first processors to be disconnected or connected, to form a plurality of processing units. In some embodiments, the fifth sub-control module can be configured to perform operation S1020 in the control method described above, which will not be repeated here.

[0142] According to the embodiments of the present disclosure, the control device can comprise a determination module, the first control module can comprise a sixth sub-control module, and the second control module can comprise a seventh sub-control module.

[0143] The determination module is configured to determine N target models from the M models in response to the number of models being greater than the number of first processors, N is an integer greater than 1, M is an integer greater than 1, and the number of models is M. In some embodiments, the determination module can be configured to perform operation S1110 in the above control method, and details are not described herein.

[0144] The sixth sub-control module is configured to control the communication between the first processors to be disconnected to form N processing units. In some embodiments, the sixth sub-control module can be configured to perform operation S1120 in the above control method, and details are not described herein.

[0145] The seventh sub-control module is configured to control the N processing units to run the corresponding target models based on the model data of the target models. In some embodiments, the seventh sub-control module can be configured to perform operation S1130 in the above control method, and details are not described herein.

[0146] Any one or more of the modules, sub-modules, units, sub-units according to the embodiments of the present disclosure, or at least part of the functions of any one or more of the modules, sub-modules, units, sub-units, can be implemented in one module. Any one or more of the modules, sub-modules, units, sub-units according to the embodiments of the present disclosure can be split into multiple modules for implementation. Any one or more of the modules, sub-modules, units, sub-units according to the embodiments of the present disclosure can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or any other reasonable way of hardware or firmware through integration or packaging of circuits, or in any one of software, hardware and firmware or in an appropriate combination of any of the above. Alternatively, one or more of the modules, sub-modules, units, sub-units according to the embodiments of the present disclosure can be at least partially implemented as computer program modules that can perform corresponding functions when the computer program modules are run.

[0147] For example, any plurality of the first acquisition module 1210, the first control module 1220, and the second control module 1230 can be combined into one module / unit / subunit, or any one of these modules / units / subunits can be split into multiple modules / units / subunits. Alternatively, at least part of the functionality of one or more of these modules / units / subunits can be combined with at least part of the functionality of other modules / units / subunits and implemented in one module / unit / subunit. According to embodiments of this disclosure, at least one of the first acquisition module 1210, the first control module 1220, and the second control module 1230 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or any other reasonable means of integrating or packaging the circuitry, or implemented in software, hardware, or firmware, or in any suitable combination of any of these three implementation methods. Alternatively, at least one of the first acquisition module 1210, the first control module 1220, and the second control module 1230 may be implemented at least partially as a computer program module, which can perform corresponding functions when the computer program module is run.

[0148] It should be noted that the data processing system part in the embodiments of this disclosure corresponds to the data processing method part in the embodiments of this disclosure. The specific description of the data processing system part is referred to in the data processing method part, and will not be repeated here.

[0149] Figure 13 Another block diagram of an electronic device suitable for implementing the methods described above, according to embodiments of the present disclosure, is illustrated schematically. Figure 13 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0150] like Figure 13 As shown, an electronic device 1300 according to an embodiment of the present disclosure includes a processor 1301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1302 or a program loaded from a storage portion 1308 into a random access memory (RAM) 1303. The processor 1301 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 1301 may also include onboard memory for caching purposes. The processor 1301 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0151] It should be particularly pointed out that the electronic device 1300 further includes at least one first processor 1312 (only one is shown in the figure) Figure 13 , which serves as a core computing unit and can be regarded as a special-purpose processing resource working in cooperation with or under the control of the second processor 1301, and a plurality of memories (not separately identified in the figure) corresponding to the plurality of first processors. The first processor can be a hardware acceleration unit configured to perform a specific type of computing task (e.g., neural network inference or training), and specifically can be a neural processing unit (NPU). The plurality of first processors are connected through a data channel based on controllable communication connection. Figure 13

[0152] In the RAM 1303, various programs and data required for the operation of the electronic device 1300 are stored. The processor 1301, the ROM 1302, and the RAM 1303 are connected to each other through the bus 1304. The processor 1301 performs various operations of the method flow according to the embodiments of the present disclosure by executing the programs in the ROM 1302 and / or the RAM 1303. It should be noted that the programs can also be stored in one or more memories other than the ROM 1302 and the RAM 1303. The processor 1301 can also perform various operations of the method flow according to the embodiments of the present disclosure by executing the programs stored in the one or more memories.

[0153] According to embodiments of the present disclosure, the electronic device 1300 can further include an input / output (I / O) interface 1305, which is also connected to the bus 1304. The electronic device 1300 can further include one or more of the following components connected to the input / output (I / O) interface 1305: an input part 1306 including a keyboard, a mouse, etc.; an output part 1307 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage part 1308 including a hard disk, etc.; and a communication part 1309 including a network interface card such as a LAN card, a modem, etc. The communication part 1309 performs communication processing via a network such as the Internet. A drive 1310 is also connected to the input / output (I / O) interface 1305 as needed. A removable medium 1311 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is mounted on the drive 1310 as needed, so that a computer program read therefrom is installed in the storage part 1308 as needed.

[0154] ​According to an embodiment of the present disclosure, a method flow according to an embodiment of the present disclosure can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product including a computer program carried on a computer-readable storage medium, the computer program containing program code for executing the method shown in the flow chart. In such an embodiment, the computer program can be downloaded and installed from a network by the communication part 1309, and / or installed from the detachable medium 1311. When the computer program is executed by the processor 1301, the above-described functions defined in the system of the embodiment of the present disclosure are executed. According to an embodiment of the present disclosure, the system, device, apparatus, module, unit, etc. described above can be implemented by computer program modules.

[0155] The present disclosure also provides a computer-readable storage medium, which can be included in the device / apparatus / system described in the above embodiments, or can exist separately without being assembled into the device / apparatus / system. The above computer-readable storage medium carries one or more programs, which when executed, implement the method according to an embodiment of the present disclosure.

[0156] According to an embodiment of the present disclosure, the computer-readable storage medium can be a non-volatile computer-readable storage medium. For example, it can include but is not limited to a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any appropriate combination thereof. In the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.

[0157] For example, according to an embodiment of the present disclosure, the computer-readable storage medium can include one or more memories of the ROM 1302 and / or the RAM 1303 described above and / or one or more memories other than the ROM 1302 and the RAM 1303.

[0158] An embodiment of the present disclosure also includes a computer program product including a computer program containing program code for executing the method provided by an embodiment of the present disclosure, which program code is used to make the electronic device implement the control method provided by an embodiment of the present disclosure when the computer program product is run on the electronic device.

[0159] When the computer program is executed by the processor 1301, the above-described functions defined in the system / apparatus of the embodiment of the present disclosure are executed. According to an embodiment of the present disclosure, the system, apparatus, module, unit, etc. described above can be implemented by computer program modules.

[0160] In one embodiment, the computer program can be tangibly embodied in a non-transitory computer readable medium, such as a tangible memory device, a magnetic storage device, or the like. In another embodiment, the computer program can be tangibly embodied in a signal, such as a download signal, and be distributed over the Internet or other network. In either embodiment, the computer program can be downloaded and installed by the communication portion 1309 and / or installed from the removable media 1311. The computer program embodied in the computer program can be transmitted in any suitable form, including, but not limited to, radio frequency, electrical, optical, acoustic, or the like, or any suitable combination thereof. The program code embodied in the computer program can be executed by any suitable processing device, including, but not limited to, a microprocessor, a microcontroller, a microcomputer, a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like, or any suitable combination thereof. The program code embodied in the computer program can be written in any suitable programming language, including, but not limited to, a high-level procedural or object-oriented programming language, or the like, or any suitable combination thereof. The program code embodied in the computer program can be executed in whole or in part on a user computing device, on a remote computing device, or on a combination thereof.

[0161] The computer program can be tangibly embodied in a non-transitory computer readable medium, such as a tangible memory device, a magnetic storage device, or the like. In another embodiment, the computer program can be tangibly embodied in a signal, such as a download signal, and be distributed over the Internet or other network. In either embodiment, the computer program can be downloaded and installed by the communication portion 1309 and / or installed from the removable media 1311. The computer program embodied in the computer program can be transmitted in any suitable form, including, but not limited to, radio frequency, electrical, optical, acoustic, or the like, or any suitable combination thereof. The program code embodied in the computer program can be executed by any suitable processing device, including, but not limited to, a microprocessor, a microcontroller, a microcomputer, a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like, or any suitable combination thereof. The program code embodied in the computer program can be written in any suitable programming language, including, but not limited to, a high-level procedural or object-oriented programming language, or the like, or any suitable combination thereof. The program code embodied in the computer program can be executed in whole or in part on a user computing device, on a remote computing device, or on a combination thereof.

[0162] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Various alternatives and modifications can be made to the embodiments without departing from the scope of the present disclosure, and such alternatives and modifications shall fall within the scope of the present disclosure.

Claims

1. An electronic device comprising: a plurality of first processors, each of the first processors being connected with each other via a controllable communication disconnected data channel; a second processor configured to control the connection and disconnection of the data channel according to a number of models and / or a function of each of the models; wherein the plurality of the first processors connected via the data channel are collectively configured to support the operation of the models based on model data of the models. 2.The electronic device of claim 1, further comprising: a plurality of memories configured to store model data of each of the models, the first processors being connected with the memories correspondingly, and the number of the memories matching the number of the first processors; the second processor being further configured to control the activation state of the memories corresponding to the first processors according to the connection state of the data channel, and store different model data in different memories in the activation state. 3.A control method comprising: obtaining target data, the target data comprising model data of a plurality of models; controlling the disconnection or connection of communication between a plurality of first processors according to the models, to form a plurality of processing units, each of the processing units corresponding to one of the models, and each of the processing units comprising at least one of the first processors; controlling each of the processing units to run the corresponding model based on the corresponding model data. 4.The method of claim 3, wherein the communication bandwidth of each of the processing units has a corresponding relationship with the number of the first processors included in the processing unit. 5.The method of claim 3, wherein the controlling the disconnection or connection of communication between a plurality of first processors to form a plurality of processing units comprises: downward rounding the number of the first processors relative to the number of the models as a first target value; upward rounding the number of the first processors relative to the number of the models as a second target value; controlling the disconnection or connection of communication between a plurality of first processors to form a plurality of processing units, each of the processing units comprising the number of the first processors being the first target value or the second target value. 6.The method of claim 3, further comprising: controlling the activation state of at least part of the memories according to the processing units, each of the memories in the activation state corresponding to one of the processors included in the processing unit; controlling the storage of different model data corresponding to different models into different memories in the activation state, the processors corresponding to the different memories being in different processing units; the controlling each of the processing units to run the corresponding model based on the corresponding model data comprises: controlling each of the processing units to run the corresponding model based on the model data in the corresponding memory. 7.The method of claim 3, wherein the controlling a plurality of the first processors to form a plurality of processing units comprises: identifying the function of the models; controlling the disconnection or connection of communication between a plurality of first processors according to the function of the models to form a plurality of processing units, so that the computing power of each of the processing units matches the function of the corresponding model.

8. The method of claim 3, further comprising: in response to the processing unit running the model, if a load of a target task corresponding to the model executed by the processing unit is greater than or equal to a preset load threshold, controlling the processing unit to stop running the model corresponding thereto; re-controlling communication between the plurality of first processors to be disconnected or connected according to the load of the target task corresponding to each of the processing units, to form a plurality of processing units, so that the computing power of the re-formed processing units matches the load of the target task corresponding to the model; controlling each of the re-formed processing units to re-run the model corresponding thereto to execute the target task corresponding to the model.

9. The method of claim 3, wherein the re-controlling communication between the plurality of first processors to be disconnected or connected to form a plurality of processing units comprises: generating and sending first prompt information according to the model, the first prompt information being used to indicate the number of the first processors and candidate working modes of the model; in response to receiving feedback information corresponding to the prompt information, and the feedback information indicating that the working mode of each of the models is multi-model parallel running, controlling communication between a plurality of the first processors to be disconnected or connected to form a plurality of the processing units.

10. The method of claim 3, further comprising: in response to the number of the models being greater than the number of the first processors, determining N target models from M models, N being an integer greater than 1, M being an integer greater than 1, and the number of the models being M; the controlling the plurality of first processors to form a plurality of processing units comprises: controlling communication between each of the first processors to be disconnected to form N processing units; the controlling each of the processing units to run the model corresponding thereto based on the model data corresponding thereto comprises: controlling N processing units to run the target model corresponding thereto based on model data of the target model.

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