Detection method and device and electronic equipment

Abstract

The invention discloses a detection method and device and electronic equipment, and belongs to the technical field of electronics. In the application, the data caching module is associated with the target module, and the condition capable of causing the data caching module to fall into logic interlocking comprises the target condition. And when the data caching module meets the target condition, counting time to obtain a target count value, and determining whether the data caching module falls into long-time logic interlocking or not according to a relationship between the target count value and a target threshold value corresponding to the target condition. The target threshold value and the target count value correspond to the same condition, so that the target threshold value is matched with the target count value, and the accuracy is relatively high, so that whether the data caching module is subjected to long-time logic interlocking or not can be accurately determined according to the relationship between the target count value and the target threshold value, and the false detection rate is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronics, and in particular, to a detection method, device and electronic equipment. BACKGROUND

[0002] In the technical field of electronics, a data cache module associated with a target module can be logically interlocked due to the influence of the target module.

[0003] For example, when the data cache module outputs data to the target module, the state machine of the data cache module needs to be in a working state. However, when the state machine of the data cache module is in a broken chain state, the state machine of the data cache module can not be able to jump to the working state due to the influence of the target module, so that the data cache module cannot output data, and at this time, the data cache module is logically interlocked.

[0004] If the logical interlocking lasts for a long time, the performance of the electronic equipment will be affected. Therefore, there is an urgent need for a solution to detect whether the data cache module is logically interlocked for a long time. SUMMARY

[0005] The present application provides a detection method, device and electronic equipment, which can accurately determine whether the data cache module is logically interlocked for a long time and reduce the false detection rate. The technical solution includes the following contents.

[0006] In one aspect, a detection method is provided, and the method includes:

[0007] counting time to obtain a target count value when a data cache module meets a target condition, the data cache module being associated with a target module, and the target condition representing a condition that can cause the data cache module to be logically interlocked due to the target module;

[0008] obtaining a target threshold value corresponding to the target condition;

[0009] determining a target detection result according to a relationship between the target count value and the target threshold value, the target detection result representing whether the data cache module is logically interlocked for a long time.

[0010] In another aspect, a detection device is provided, and the device includes:

[0011] a condition checking and counting module configured to count time to obtain a target count value when a data cache module meets a target condition, the data cache module being associated with a target module, and the target condition representing a condition that can cause the data cache module to be logically interlocked due to the target module;

[0012] a threshold value calculation module, configured to obtain a target threshold value corresponding to the target condition;

[0013] a timeout checking module, configured to determine a target detection result according to a relationship between the target count value and the target threshold value, the target detection result representing whether the data caching module is in a long-time logical interlock.

[0014] In another aspect, an electronic device is provided, which includes a processor and a memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor to enable the electronic device to implement any of the detection methods described above.

[0015] In another aspect, a computer readable storage medium is also provided, which stores at least one computer program, the at least one computer program being loaded and executed by a processor to enable an electronic device to implement any of the detection methods described above.

[0016] The technical solutions provided in the present application bring at least the following beneficial effects:

[0017] In the technical solutions provided in the present application, when the data caching module meets the target condition, the time is counted to obtain a target count value, so that the target count value represents the time corresponding to the target condition. The target threshold value corresponding to the target condition is obtained, so that the target threshold value and the target count value correspond to the same condition, so that the target threshold value is a threshold value adapted to the target count value, which has high accuracy. Based on this, according to the relationship between the target count value and the target threshold value, it can be accurately determined whether the data caching module is in a long-time logical interlock, and the false detection rate of the long-time logical interlock is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0019] Figure 1 is a connection diagram of a detection device provided by an embodiment of the present application;

[0020] Figure 2 is a flowchart of a detection method provided by an embodiment of the present application;

[0021] Figure 3 is a connection diagram of another detection device provided by an embodiment of the present application;

[0022] Figure 4 is a detection schematic diagram provided by an embodiment of the present application;

[0023] Figure 5 is a structural schematic diagram of a detection device provided by an embodiment of the present application;

[0024] Figure 6 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the drawings.

[0026] It should be noted that the terms "first", "second", and the like in the present application are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0027] In the field of electronic technology, when a data cache module and a target module are associated with each other, the data cache module may be trapped in a logic interlock due to the influence of the target module, resulting in data being stranded in the data cache module. That is, the data cache module will not be able to normally output data due to being trapped in a logic interlock.

[0028] For example, when the data cache module outputs data to the target module, the state machine of the data cache module needs to be in a working state to control the data cache module to output data through the state machine of the data cache module. Assuming that the state machine of the data cache module is in a broken link state, the state machine of the data cache module needs to jump from the broken link state to the idle state and then to the working state. The state machine of the data cache module needs to jump from the broken link state to the idle state by the state machine of the target module jumping to the idle state. If the target module continuously outputs data, the state machine of the target module is always in a working state to control the target module to output data through the state machine of the target module. In this case, since the state machine of the target module is always in a working state and cannot jump to the idle state, the state machine of the data cache module cannot jump to the idle state, and the state machine of the data cache module is always in a broken link state, so that the state of the data cache module is locked and cannot output data to the target module.

[0029] From the above, the data cache module falls into logical interlocking, which means that the logic of the target module affects the logic of the data cache module, causing the data cache module to be locked due to the influence of the target module. If the data cache module falls into logical interlocking, the state of the data cache module will be locked, causing the data cache module to be unable to normally output data, resulting in data being stranded in the data cache module.

[0030] If the data cache module falls into logical interlocking for a short time, that is, when the data cache module meets certain conditions, it will exit the logical interlocking, at which time the data cache module can normally output data and does not affect the performance of the electronic device. If the data cache module falls into logical interlocking for a long time, it will cause the data cache module to be unable to normally output data for a long time, thereby affecting the performance of the electronic device. Based on this, it is crucial to detect whether the data cache module falls into long-time logical interlocking.

[0031] In related technologies, the data cache module generates a receiving timestamp when receiving data and generates a sending timestamp when sending data. According to the receiving timestamp and the sending timestamp, it is determined whether the data cache module falls into long-time logical interlocking. For example, if the time difference between the sending timestamp and the receiving timestamp is greater than a threshold, it means that the data is stranded in the data cache module for a long time, and in this case, it can be determined that the data cache module falls into long-time logical interlocking. However, some normal situations, such as data stranded in the data cache module due to network congestion, will also be detected as the data cache module falling into long-time logical interlocking, resulting in a high false detection rate.

[0032] To this end, the embodiments of the present application provide a detection method that can detect whether the data cache module falls into long-time logical interlocking in multiple scenarios, and can also reduce the false detection rate on the basis of rich detection scenarios.

[0033] The detection method provided by the embodiments of the present application is executed by a detection device. The content of the detection device is not limited here, and any circuit, chip or device that can execute the detection method provided by the embodiments of the present application can be used as the detection device.

[0034] Among them, the detection device is connected with the data cache module. The data cache module is a module that can cache data in a chip or device. For example, a memory, a field programmable gate array, an ASIC (Application Specific Integrated Circuit), a processor, a communication device, a controller, etc. all include a data cache module. The data cache module is associated with a target module, specifically, the logic of the target module affects the logic of the data cache module, and based on this, the data cache module is connected with the target module.

[0035] As Figure 1 shown, the data cache module 101 and the target module 102 are connected, and the detection apparatus 100 is connected with the data cache module 101. The connection mode among the detection apparatus 100, the data cache module 101 and the target module 102 is not limited here. Exemplarily, the three are directly connected through wires. Alternatively, the three are connected through interfaces and wires. For example, the detection apparatus 100 is integrated in one device, the data cache module 101 is integrated in another device, and the target module 102 is integrated in yet another device, and the three devices all include interfaces and are connected with each other through the interfaces and the wires.

[0036] The data cache module 101 and the target module 102 are associated, specifically, the logic of the target module 102 will affect the logic of the data cache module 101, and based on this, the data cache module 101 may be trapped in logical interlocking due to the influence of the target module 102. Based on this, the detection apparatus 100 is used to execute the detection method of the embodiments of the present application to detect whether the data cache module 101 is trapped in logical interlocking for a long time. Specifically, as Figure 2 shown, the detection method of the embodiments of the present application includes the following steps.

[0037] Step 201, when the data cache module meets a target condition, counting the time to obtain a target count value, the data cache module and the target module are associated, and the target condition represents a condition that can cause the data cache module to be trapped in logical interlocking due to the target module.

[0038] The data cache module 101 and the target module 102 are associated, specifically, the logic of the target module 102 affects the logic of the data cache module 101. Among them, the data cache module 101 has the functions of data receiving, storing and sending, and the function of the target module 102 is not limited here. That is to say, the target module 102 can be any circuit, chip or device that can affect the data cache module 101. Optionally, the data cache module 101 receives data sent by an upstream module and stores the data, and the target module 102 will affect whether the data cache module 101 can send the data. Among them, the data can be any type of request.

[0039] The detection apparatus 100 will detect whether the data cache module 101 meets the target condition. In actual application, there are at least two conditions that can cause the data cache module 101 to be trapped in logical interlocking, and for the convenience of description, these conditions are collectively referred to as candidate conditions. That is, there are at least two candidate conditions, and the target condition is any one of the candidate conditions.

[0040] When the detection apparatus 100 detects that the data buffer module 101 satisfies a certain candidate condition (i.e., a target condition), the time is counted. Optionally, starting from an initial counting value, the counting value is accumulated by 1 every counting unit, so as to constantly update the counting value and obtain a target counting value. Optionally, the initial counting value is 0, and one counting unit is equal to one clock period. In this case, the target counting value is equal to the number of elapsed clock periods.

[0041] In step 202, a target threshold corresponding to the target condition is obtained.

[0042] In the embodiments of the present application, there is a threshold corresponding to each candidate condition, and the thresholds corresponding to any two candidate conditions can be the same or different. The manner of obtaining the threshold corresponding to any candidate condition is not limited herein, for example, the threshold corresponding to a candidate condition can be a pre-configured value, or a value calculated based on data related to the candidate condition. When the detection apparatus 100 detects that the data buffer module 101 satisfies a certain candidate condition (i.e., a target condition), the threshold corresponding to the candidate condition is obtained, and a target threshold is obtained.

[0043] In step 203, a target detection result is determined according to the relationship between the target counting value and the target threshold, and the target detection result represents whether the data buffer module is in long-time logical interlocking.

[0044] The target threshold is a critical value for determining whether the data buffer module 101 is in long-time logical interlocking. Based on this, step 203 includes the following three cases.

[0045] In case 1, when the target counting value is greater than the target threshold, it is determined that the target detection result represents that the data buffer module is in long-time logical interlocking.

[0046] In case 2, when the target counting value is less than the target threshold, it is determined that the target detection result represents that the data buffer module is not in long-time logical interlocking.

[0047] In case 3, when the target counting value is equal to the target threshold, it is determined that the target detection result represents that the data buffer module is in or not in long-time logical interlocking.

[0048] Optionally, the target detection result is a first symbol or a second symbol. The first symbol and the second symbol are different symbols, for example, the first symbol is 0 and the second symbol is 1. If the target detection result is the first symbol, it represents that the data buffer module 101 is not in long-time logical interlocking. If the target detection result is the second symbol, it represents that the data buffer module 101 is in long-time logical interlocking.

[0049] As mentioned above, the data caching module 101 is used to receive, store, and send data. In practical applications, there are various data processing logics, and the data caching module 101 can employ at least one of them. These data processing logics include: 1. Optimal algorithm: The data caching module 101 determines the optimal data from the stored data. The optimal data may be the data to be used in the next clock cycle, and sends the optimal data. 2. Random algorithm: The data caching module 101 randomly determines data from the stored data and sends the determined data. 3. First-In-First-Out (FIFO) algorithm: The data caching module 101 determines the first received data from the stored data and sends the first received data. 4. Least Recently Used (LRU) algorithm: The data caching module 101 determines the least frequently used data from the stored data and sends the least frequently used data.

[0050] Furthermore, the target module 102 can be any module capable of influencing the data cache module 101. Optionally, the data cache module 101 can send data to the target module 102, and the target module 102 can receive, store, and send the data. That is, the target module 102 has the functions of data reception, data storage, and data transmission, which are the same as the functions of the data cache module 101. Based on this, the target module 102 can also employ at least one of the above-mentioned data processing logics. For ease of description, the following example, where both the data cache module 101 and the target module 102 use the FIFO algorithm, will further illustrate the detection method provided in this application embodiment.

[0051] To facilitate the distinction between the data buffer module 101 and the target module 102, the data buffer module 101 will also be referred to as the transmit FIFO module and the target module 102 as the receive FIFO module in the following text.

[0052] like Figure 3 As shown, the transmit FIFO module 301-1 is integrated into device 301, which includes multiple interfaces through which it connects to the detection device 300. It is understood that the number of interfaces in the transmit FIFO module 301-1 that connect to the detection device 300 is not limited here. Different interfaces can transmit different signals or data; for example, one interface of the transmit FIFO module 301-1 may be used to transmit a clock (Clk) signal, while another interface may be used to transmit a reset (rst) signal.

[0053] The sending FIFO module 301-1 processes data based on the FIFO algorithm, i.e., the sending FIFO module 301-1 sends the data received first each time. The sending FIFO module 301-1 includes N sending FIFO queues, where N is a positive integer. Each sending FIFO queue processes data based on the FIFO algorithm, i.e., when receiving data, the sending FIFO queue stores the received data at the tail of the queue, and when sending data, the sending FIFO queue sends the data stored at the head of the queue and pushes all the data in the sending FIFO queue towards the head of the queue. In this way, the data is stored in the order of reception, so that the data received first is stored at the head of the queue and the data received last is stored at the tail of the queue. For ease of description, the N sending FIFO queues are denoted as sending FIFO queue 1-1, sending FIFO queue 1-2, …, and sending FIFO queue 1-N in turn.

[0054] It can be understood that the device 301 can integrate other modules in addition to the sending FIFO module 301-1. For example, the device 301 also integrates a first state machine 301-2 and a first control unit 301-3. The first state machine 301-2 is used to control the sending FIFO module 301-1 to send data to the receiving FIFO module 302-1. The first control unit 301-3 is used to perform packet assembly or disassembly on data, control a signal to be at a high level or a low level, etc.

[0055] Similarly, the receiving FIFO module 302-1 is integrated in the device 302. The receiving FIFO module 302-1 also processes data based on the FIFO algorithm. The receiving FIFO module 302-1 includes N receiving FIFO queues, where N is a positive integer, and each receiving FIFO queue processes data based on the FIFO algorithm. For ease of description, the N receiving FIFO queues are denoted as receiving FIFO queue 1-1, receiving FIFO queue 1-2, …, and receiving FIFO queue 1-N in turn.

[0056] The device 302 can integrate other modules in addition to the receiving FIFO module 302-1. For example, the device 302 also integrates a second state machine 302-2 and a second control unit 302-3. The second state machine 302-2 is used to control the receiving FIFO module 302-1 to output data. The second control unit 302-3 is used to perform packet assembly or disassembly on data, control a signal to be at a high level or a low level, etc.

[0057] It can be understood that the number of sending FIFO queues in the sending FIFO module 301-1 is the same as the number of receiving FIFO queues in the receiving FIFO module 302-1. Each sending FIFO queue has a corresponding receiving FIFO queue, for example, the sending FIFO queue 1-i corresponds to the receiving FIFO queue 1-i, i is any positive integer from 1 to N. Based on this, the data sent by the sending FIFO queue can be stored in the corresponding receiving FIFO queue, and the data is sent to the downstream module by the receiving FIFO queue.

[0058] The device 301 is connected through the interface and the connection module 303, and the connection module 303 is connected through the interface and the device 302. The connection module 303 is a module for simulating PCS (Physical Coding Sublayer, physical coding sublayer) and PHY (Physical Medium Dependent Sublayer, physical medium dependent sublayer), which is used to connect the sending FIFO module 301-1 and the receiving FIFO module 302-1. The content of the connection module 303 is not limited here, and any circuit, chip or device with a connection function can be used as the connection module 303.

[0059] It has been mentioned above that the detection device 300 can detect whether the sending FIFO module 301-1 meets the target condition based on the signal or data transmitted by the interface of the sending FIFO module 301-1. When the sending FIFO module 301-1 meets the target condition, on the one hand, the time is counted to obtain a target count value, and on the other hand, a target threshold corresponding to the target condition is obtained. Then, according to the relationship between the target count value and the target threshold, a target detection result is determined. The target condition is any one of the candidate conditions, and the number and content of the candidate conditions are not limited here. Exemplarily, the candidate conditions include candidate conditions 1 to 5 as shown below.

[0060] The candidate condition 1 is that the target condition includes that the data transmission link between the data cache module and the target module is in a non-working state.

[0061] The data transmission link is a transmission channel of data. If the data transmission link is in a working state, it is equivalent to that the transmission channel of data is a passageway, so that the data stored in the sending FIFO module 301-1 can be transmitted from the sending FIFO module 301-1 to the receiving FIFO module 302-1. If the data transmission link is in a non-working state, it is equivalent to that the transmission channel of data is a break, so that the data stored in the sending FIFO module 301-1 cannot be transmitted from the sending FIFO module 301-1 to the receiving FIFO module 302-1.

[0062] Based on this, if the data transmission link is in a non-working state, it will cause: data to be stranded in the sending FIFO module 301-1, affecting the receiving, storing and sending of data by the receiving FIFO module 302-1. In this example, the sending FIFO module 301-1 falls into a logical interlock, which may cause the data transmission link to be in a non-working state. The data transmission link in a non-working state will cause the read enable condition of each sending FIFO queue of the sending FIFO module 301-1 to be unable to be met, thereby causing data to be stranded in each sending FIFO queue of the sending FIFO module 301-1, causing the sending FIFO module 301-1 to be unable to transmit data to the receiving FIFO module 302-1 through the data transmission link. Based on this, the candidate condition 1 can be the target condition that causes the sending FIFO module 301-1 to fall into a logical interlock.

[0063] If the target condition includes the candidate condition 1, then: step 201 includes counting the time when the sending FIFO module 301-1 meets the candidate condition 1 to obtain a target count value; step 202 includes determining a target threshold according to at least one of a first time parameter and a second time parameter, the first time parameter representing the time required to establish the data transmission link, and the second time parameter representing the time required to disconnect the data transmission link. Step 203 includes determining a target detection result according to the relationship between the target count value and the target threshold.

[0064] In this example, as shown in Figure 3 The sending FIFO module 301-1 can transmit a Link_active signal to the detection device 300 through an interface, and the Link_active signal is used to represent whether the data transmission link between the sending FIFO module 301-1 and the receiving FIFO module 302-1 is in a working state. Wherein, the Link_active signal is low, representing that the data transmission link is in a non-working state. The Link_active signal is high, representing that the data transmission link is in a working state.

[0065] The sending FIFO module 301-1 includes a first control unit 301-3, which can control the Link_active signal transmitted by the sending FIFO module 301-1 to be high or low through the first control unit 101-3. Wherein, the first control unit 101-3 is any circuit or device for controlling signals or data.

[0066] The detection apparatus 300 can receive the Link_active signal in real time. If it is determined that the data transmission link is in the non-working state based on the Link_active signal, the detection apparatus 300 adds 1 to the initial count value every other count unit to obtain a target count value. Alternatively, the initial count value link_cnt is 0, and link_cnt is added by 1 every other count unit, i.e., link_cnt++. In this way, link_cnt is constantly updated. The count unit is at least one clock period.

[0067] It can be understood that, in the process of counting time, if the sending FIFO module 301-1 does not satisfy the candidate condition 1, the counting of time is stopped. For example, it is determined that the data transmission link is in the working state based on the Link_active signal, and at this time, the sending FIFO module 301-1 does not satisfy the candidate condition 1, and the counting of time can be stopped. Finally, a target count value link_cnt can be obtained.

[0068] In addition, the detection apparatus 300 receives configuration information transmitted by the sending FIFO module 301-1 through the interface, or the detection apparatus 300 stores the configuration information. The configuration information includes at least one of a first time parameter and a second time parameter. The first time parameter represents the time required to establish the data transmission link, which can be represented by a parameter T1. The second time parameter represents the time required to disconnect the data transmission link. It can be understood that, both the establishment of the data transmission link and the disconnection of the data transmission link require a certain time, which is the time for hysteresis control of the establishment or disconnection of the data transmission link. That is, the data transmission link will not be immediately switched from the non-working state to the working state, but will be switched to the working state after a delay represented by the first time parameter. Similarly, the data transmission link will not be immediately switched from the working state to the non-working state, but will be switched to the non-working state after a delay represented by the second time parameter.

[0069] Alternatively, the second time parameter is the product of a first configuration parameter and a second configuration parameter. The first configuration parameter represents the number of count units that the data transmission link is switched from the working state to the non-working state (i.e., the data transmission link is disconnected) and the second configuration parameter represents the count unit. Usually, one count unit is equal to at least one clock period, for example, one count unit is 5 clock periods or 1 clock period. The first configuration parameter can be represented by a parameter LP_HYST, and the second configuration parameter can be represented by a parameter TIME_UNIT. Based on this, the second time parameter = LP_HYST x TIME_UNIT.

[0070] The detection apparatus 300 calculates the threshold corresponding to the candidate condition 1 according to at least one of the first time parameter or the second time parameter, and the calculation manner is not limited herein. For example, the first time parameter and the second time parameter are added, and the threshold corresponding to the candidate condition 1 is determined based on the addition result.

[0071] Optionally, the threshold Link_cnt_thred corresponding to the candidate condition 1 is calculated according to the formula Link_cnt_thred=K1×((LP_HYST×TIME_UNIT) / clk_period+T1). Wherein, K1 is a configured safety factor, and the value is not limited herein. Optionally, K1 is a multiple of the theoretical maximum delay for establishing or disconnecting the data transmission link, for example, K1=2. clk_period represents the clock period. Therefore, (LP_HYST×TIME_UNIT) / clk_period represents the number of clock periods for disconnecting the data transmission link, and T1 represents the number of clock periods for establishing the data transmission link.

[0072] The threshold corresponding to the candidate condition 1 is determined by the first time parameter and the second time parameter, which realizes determining the threshold according to the data related to the candidate condition 1, so that the target threshold and the target count value correspond to the same candidate condition, improves the accuracy of the target threshold, and thus improves the accuracy of the target detection result.

[0073] If the target count value link_cnt is greater than the target threshold Link_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 falls into long-time logical interlocking; if the target count value link_cnt is less than the target threshold Link_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 does not fall into long-time logical interlocking; if the target count value link_cnt is equal to the target threshold Link_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 falls into or does not fall into long-time logical interlocking.

[0074] It should be noted that after stopping counting the time to obtain the target count value link_cnt, on the one hand, the target detection result is determined based on the relationship between the target count value link_cnt and the target threshold Link_cnt_thred. On the other hand, the target count value link_cnt can be cleared, i.e. link_cnt=0, so as to facilitate subsequent detection.

[0075] The candidate condition 2 and the first state machine of the data buffer module are in a non-working state, and the first state machine is used to control the data buffer module to transmit data to the target module.

[0076] The state machine of the data buffering module is a model or logic for managing the behavior of the data buffering module. For example, the state machine can accurately determine whether the target module has sufficient storage space to store data, control the order and timing of data reading in the data buffering module, and so on. Based on this, the state machine needs to be in a working state during the process of the data buffering module sending data. If the state machine is in a non-working state, the data buffering module cannot send data.

[0077] As shown in Figure 3 The sending FIFO module 301-1 includes a first state machine 301-2. If the first state machine 301-2 is in a working state, the sending FIFO module 301-1 can send data. If the first state machine 301-2 is in a non-working state, the sending FIFO module 301-1 cannot send data.

[0078] When the first state machine 301-2 is in a non-working state, the sending FIFO module 301-1 cannot send data, causing data to be stranded in the sending FIFO module 301-1. As mentioned above, if the first state machine 301-2 is in a non-working state and cannot jump to a working state, data will be stranded in the sending FIFO module 301-1, causing the sending FIFO module 301-1 to be unable to transmit data to the receiving FIFO module 302-1. At this time, the sending FIFO module 301-1 falls into a logical interlock. Based on this, the candidate condition 2 can be a target condition that causes the sending FIFO module 301-1 to fall into a logical interlock.

[0079] If the target condition includes the candidate condition 2, step 201 includes counting the time when the sending FIFO module 301-1 satisfies the candidate condition 2 to obtain a target count value. Step 202 includes determining a target threshold value according to a third time parameter, which represents the time required for the first state machine to jump from a non-working state to a working state. Step 203 includes determining a target detection result according to the relationship between the target count value and the target threshold value.

[0080] In this example, as shown in Figure 3As shown, the sending FIFO module 301-1 can transmit other signals to the detection apparatus 300 through the interface, and the other signals include an FSM_active signal. The FSM_active signal is used to represent whether the first state machine 301-2 is in the working state. When the FSM_active signal is low, it represents that the first state machine 301-2 is in the non-working state. When the FSM_active signal is high, it represents that the first state machine 301-2 is in the working state. The FSM_active signal transmitted by the sending FIFO module 301-1 can be controlled to be high or low by the first control unit 101-3.

[0081] It should be noted that when the first state machine 301-2 is in the working state, the sending FIFO module 301-1 can transmit data to the receiving FIFO module 302-1, and when the first state machine 301-2 is in the non-working state, the sending FIFO module 301-1 cannot transmit data to the receiving FIFO module 302-1.

[0082] The detection apparatus 300 can receive the FSM_active signal in real time. If it is determined that the first state machine 301-2 is in the non-working state based on the FSM_active signal, the detection apparatus 300 adds 1 to the initial count value every other count unit to obtain a target count value. Alternatively, the initial count value Fsm_cnt is 0, and Fsm_cnt is added by 1 every other count unit, that is, Fsm_cnt++. In this way, Fsm_cnt is constantly updated.

[0083] In the process of counting time, if the sending FIFO module 301-1 does not satisfy the candidate condition 2, the counting of time is stopped. For example, when it is determined that the first state machine 301-2 is in the working state based on the FSM_active signal, the sending FIFO module 301-1 does not satisfy the candidate condition 2, and the counting of time can be stopped. Finally, a target count value Fsm_cnt can be obtained.

[0084] In addition, the detection apparatus 300 receives configuration information transmitted by the sending FIFO module 301-1 through the interface, or the detection apparatus 300 stores the configuration information. The configuration information includes a third time parameter. The third time parameter represents the time required for the first state machine 301-2 to jump from the non-working state to the working state, and the non-working state can be the disconnection state or the idle state, which can be represented by a parameter T2. The detection apparatus 300 calculates a threshold value corresponding to the candidate condition 2 according to the third time parameter, and the calculation manner is not limited herein. For example, the third time parameter is taken as the threshold value corresponding to the candidate condition 2.

[0085] Optionally, a threshold FSM_cnt_thred corresponding to the candidate condition 2 is calculated according to a formula FSM_cnt_thred=K2×(IDLE_TIME+T2). K2 is a configured safety coefficient, and its value is not limited herein. In the present example, K2 is a multiple of the theoretical maximum delay of the first state machine 301-2 from the disconnection state to the working state, for example, K2=2. IDLE_TIME represents the time of the first state machine 301-2 from the disconnection state to the idle state, and T2 represents the time of the first state machine 301-2 from the idle state to the working state.

[0086] The threshold corresponding to the candidate condition 2 is determined by the third time parameter, which realizes determining the threshold according to the data related to the candidate condition 2, so that the target threshold and the target count value correspond to the same candidate condition, improves the accuracy of the target threshold, and thus improves the accuracy of the target detection result.

[0087] If the target count value Fsm_cnt is greater than the target threshold FSM_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 falls into long-time logical interlocking; if the target count value Fsm_cnt is less than the target threshold FSM_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 does not fall into long-time logical interlocking; and if the target count value Fsm_cnt is equal to the target threshold FSM_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 falls into or does not fall into long-time logical interlocking.

[0088] It should be noted that after the target count value Fsm_cnt is obtained by stopping counting the time, on the one hand, the target detection result is determined based on the relationship between the target count value Fsm_cnt and the target threshold FSM_cnt_thred. On the other hand, the target count value Fsm_cnt can be cleared, i.e., Fsm_cnt=0, to facilitate subsequent detection.

[0089] The candidate condition 3 is that the data buffer module sends a transmission request and transmission data corresponding to the transmission request to the target module, and the target condition includes that the data buffer module does not store transmission data in the case of needing to send a transmission request.

[0090] The sending FIFO module 301-1 can store the transmission request and the transmission data requested by the transmission request, and send the transmission request and the transmission data to the receiving FIFO module 302-1. In one case, the transmission request carries the transmission data, that is, the transmission data and the transmission request are sent at the same time, and there is no delay phenomenon, and the receiving FIFO module 302-1 can determine the transmission data from the transmission request and store the transmission data. In another case, the transmission request does not carry the transmission data, and the transmission request is sent first, and then the transmission data is sent.

[0091] Generally, the upstream module can send the transmission request and the transmission data to the sending FIFO module 301-1 at the same time or in sequence, so that the sending FIFO module 301-1 stores the transmission request and the transmission data, and in this case, the sending FIFO module 301-1 can send the transmission request and the transmission data to the receiving FIFO module 302-1.

[0092] In the present example, if the sending FIFO module 301-1 needs to send the transmission request to the receiving FIFO module 302-1 without storing the transmission data, the read enable condition for reading the transmission request from the sending FIFO queue of the sending FIFO module 301-1 cannot be met due to the lack of transmission data, so that the transmission request is stranded in the sending FIFO module 301-1, and the transmission request cannot be sent to the receiving FIFO module 302-1, at this time, the sending FIFO module 301-1 falls into a logical interlock. Based on this, the candidate condition 3 can be the target condition that causes the sending FIFO module 301-1 to fall into a logical interlock.

[0093] If the target condition includes the candidate condition 3, step 201 includes counting the time when the sending FIFO module 301-1 meets the candidate condition 3 to obtain a target count value, and step 202 includes determining a target threshold according to a fourth time parameter, the fourth time parameter representing the maximum delay time allowed for the data buffering module to store no transmission data when it needs to send a transmission request. Step 203 includes determining a target detection result according to the relationship between the target count value and the target threshold.

[0094] As Figure 3As shown, the sending FIFO module 301-1 can transmit other signals to the detection device 300 through the interface, and the other signals include a Data_delay_vld signal. The Data_delay_vld signal is used to represent whether the sending FIFO module 301-1 stores transmission data in the case of needing to send a transmission request. When the Data_delay_vld signal is low, it represents that the sending FIFO module 301-1 stores transmission data in the case of needing to send a transmission request. When the Data_delay_vld signal is high, it represents that the sending FIFO module 301-1 does not store transmission data in the case of needing to send a transmission request. The Data_delay_vld signal transmitted by the sending FIFO module 301-1 can be controlled to be high or low by the first control unit 101-3.

[0095] The detection device 300 can receive the Data_delay_vld signal in real time. If it is determined based on the Data_delay_vld signal that the candidate condition 3 is met, that is, the sending FIFO module 301-1 does not store transmission data in the case of needing to send a transmission request, the detection device 300 adds 1 to the initial count value every other count unit to obtain a target count value. Alternatively, the initial count value Data_delay_cnt is 0, and Data_delay_cnt is added by 1 every other count unit, that is, Data_delay_cnt++. In this way, Data_delay_cnt is constantly updated.

[0096] Alternatively, the sending FIFO module 301-1 includes at least one sending FIFO queue, and the Data_delay_vld signal includes a first sub-signal of each sending FIFO queue. The first sub-signal of any sending FIFO queue is used to represent whether the sending FIFO queue stores transmission data in the case of needing to send a transmission request. When the first sub-signal is low, it represents that the sending FIFO queue stores transmission data in the case of needing to send a transmission request. When the first sub-signal is high, it represents that the sending FIFO queue does not store transmission data in the case of needing to send a transmission request. The candidate condition 3 includes that at least one sending FIFO queue does not store transmission data in the case of needing to send a transmission request.

[0097] If the sending FIFO module 301-1 does not satisfy the candidate condition 3 in the process of counting the time, the counting of the time is stopped. For example, based on the Data_delay_vld signal, it is determined that the sending FIFO module 301-1 stores the transmission data in the case where the transmission request needs to be sent, and then the sending FIFO module 301-1 does not satisfy the candidate condition 3, and the counting of the time can be stopped. Finally, the target count value Data_delay_cnt can be obtained.

[0098] In addition, the detection apparatus 300 receives the configuration information transmitted by the sending FIFO module 301-1 through the interface, or the detection apparatus 300 stores the configuration information. The configuration information includes a fourth time parameter. The fourth time parameter represents the maximum delay time of the data buffering module in the case where the transmission request needs to be sent without storing the transmission data, which can be represented by the parameter req_data_max_delay. The detection apparatus 300 calculates the threshold corresponding to the candidate condition 3 according to the fourth time parameter, and the calculation manner is not limited here. For example, the fourth time parameter is taken as the threshold corresponding to the candidate condition 3.

[0099] Alternatively, the threshold Data_delay_cnt_thred corresponding to the candidate condition 3 is calculated according to the formula Data_delay_cnt_thred=K3×req_data_max_delay. Wherein, K3 is a configured safety factor, and the value thereof is not limited here. Alternatively, K3 is a multiple of the theoretical maximum delay of the data buffering module in the case where the transmission request needs to be sent without storing the transmission data, for example, K3=2.

[0100] The threshold corresponding to the candidate condition 3 is determined by the fourth time parameter, which realizes the determination of the threshold according to the data related to the candidate condition 3, so that the target threshold and the target count value correspond to the same candidate condition, the accuracy of the target threshold is improved, and thus the accuracy of the target detection result is improved.

[0101] If the target count value Data_delay_cnt is greater than the target threshold Data_delay_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 falls into the long-time logical interlocking; if the target count value Data_delay_cnt is less than the target threshold Data_delay_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 does not fall into the long-time logical interlocking; if the target count value Data_delay_cnt is equal to the target threshold Data_delay_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 falls into or does not fall into the long-time logical interlocking.

[0102] It should be noted that after stopping counting time to obtain the target count value Data_delay_cnt, on the one hand, the target detection result is determined based on the relationship between the target count value Data_delay_cnt and the target threshold Data_delay_cnt_thred. On the other hand, the target count value Data_delay_cnt can be cleared, i.e., Data_delay_cnt = 0, to facilitate subsequent detection.

[0103] The candidate condition 4 is that the data cache module sends a first type request and a second type request to the target module, and the target condition includes that the first type request is blocked by the second type request.

[0104] The first type request is any type of request, and the second type request is any request different from the first type request. For ease of description, in the following, the first type request is taken as a read request, and the second type request is taken as a write request, and the embodiments of the present application are described. The read request can be denoted as a Non-posted request, and the write request can be denoted as a Posted request.

[0105] In the present example, the sending FIFO module 301-1 can have an ordering requirement when sending a request to the receiving FIFO module 302-1. The ordering requirement is a requirement for constraining the operation order of data, which needs to ensure that the data is processed or transmitted in a specific order. It is assumed that the upstream module sends M Non-posted requests and N Posted requests to the sending FIFO module 301-1 in sequence, M and N are both positive integers, and the Non-posted request and the Posted request can be sent in cross. Optionally, the Non-posted request and the Posted request are stored in the same sending FIFO queue or different sending FIFO queues in the sending FIFO module 301-1. For example, the Non-posted request is stored in the sending FIFO queue 1-1, and the Posted request is stored in the sending FIFO queue 1-2.

[0106] It can be understood that the time when the sending FIFO module 301-1 receives any one Non-posted request can be located before the receiving time of any one Posted request, or can be located after the receiving time of any one Posted request. For ease of description, in the following, the receiving time of the Non-posted request is taken as an example, and the embodiments of the present application are described.

[0107] In this example, since the sending FIFO module 301-1 receives the Non-posted request after receiving the Posted request, the ordering requirement is that the sending FIFO module 301-1 sends the Posted request before sending the Non-posted request. Assume that when the sending FIFO module 301-1 sends the Posted request, candidate condition 3 occurs, i.e., the data buffer module does not store the transmission data requested by the Posted request when the sending FIFO module 301-1 needs to send the Posted request, which causes the sending FIFO module 301-1 to fail to send the Posted request to the receiving FIFO module 302-1. In another possible case, the sending FIFO module 301-1 and the receiving FIFO module 302-1 transmit data based on a Credit mechanism. The Credit mechanism is a flow control mechanism. When the sending side needs to send data, it needs to check the credit status of the receiving side first. Only when the receiving side has enough credit, the sending side sends data to the receiving side and accordingly reduces the credit of the receiving side. After the receiving side receives the data, it sends an acknowledgement signal to the sending side. After the sending side receives the acknowledgement signal, it restores a certain amount of credit of the receiving side to further transmit data. Based on this, if the credit of the receiving FIFO module 302-1 is insufficient, the sending FIFO module 301-1 fails to send the Posted request to the receiving FIFO module 302-1.

[0108] If the sending FIFO module 301-1 fails to send the Posted request to the receiving FIFO module 302-1, the Posted request is stranded in the sending FIFO module 301-1. Since the ordering requirement is to send the Posted request before sending the Non-posted request, in the case where the Posted request cannot be sent, the Non-posted request with a receiving time later than the Posted request also cannot be sent, causing the Non-posted request to be stranded in the sending FIFO module 301-1.

[0109] In this example, the sending FIFO module 301-1 is in a logical interlock, which can cause the Posted request to fail to be sent, causing the Non-posted request with a receiving time later than the Posted request to also fail to be sent, and the Non-posted request being blocked by the Posted request. Based on this, candidate condition 4 can be a target condition that causes the sending FIFO module 301-1 to be in a logical interlock.

[0110] If the target condition includes candidate condition 4, then: Step 201 includes: when the FIFO module 301-1 satisfies candidate condition 4, counting the time to obtain the target count value; Step 202 includes: determining the configured value as the target threshold. Step 203 includes: determining the target detection result based on the relationship between the target count value and the target threshold.

[0111] like Figure 3 As shown, the transmitting FIFO module 301-1 can transmit other signals to the detection device 300 via an interface. These other signals include the Np_req_ordering signal. The Np_req_ordering signal is used to indicate whether a first type of request in the transmitting FIFO module 301-1 is blocked by a second type of request. Specifically, a low level Np_req_ordering signal indicates that a first type of request in the transmitting FIFO module 301-1 is blocked by a second type of request. A high level Np_req_ordering signal indicates that a first type of request is not blocked by a second type of request. The first control unit 101-3 can control the Np_req_ordering signal transmitted by the transmitting FIFO module 301-1 to be either high or low.

[0112] The detection device 300 can receive the Np_req_ordering signal in real time. If, based on the Np_req_ordering signal, it is determined that the first type of request in the sending FIFO module 301-1 is blocked by the second type of request, the detection device 300 increments the initial count value by 1 every counting unit to obtain the target count value. Optionally, the initial count value Np_req_ordering_cnt is 0, and Np_req_ordering_cnt is incremented by 1 every counting unit, i.e., Np_req_ordering_cnt++. In this way, Np_req_ordering_cnt is continuously updated.

[0113] Optionally, the transmit FIFO module 301-1 includes at least one transmit FIFO queue, and the Np_req_ordering signal includes a second sub-signal for each transmit FIFO queue. The second sub-signal of any transmit FIFO queue is used to characterize whether a first-type request in that transmit FIFO queue is blocked by a second-type request. Specifically, a low level second sub-signal indicates that a first-type request in the transmit FIFO queue is blocked by a second-type request. A high level first sub-signal indicates that a first-type request in the transmit FIFO queue is not blocked by a second-type request. Candidate condition 4 includes: at least one transmit FIFO queue has a first-type request blocked by a second-type request.

[0114] If the sending FIFO module 301-1 does not satisfy the candidate condition 4, the time counting is stopped. For example, based on the Np_req_ordering signal, it is determined that the first type of request is not blocked by the second type of request in the sending FIFO module 301-1, the sending FIFO module 301-1 does not satisfy the candidate condition 4, and the time counting can be stopped. Finally, the target counting value Np_req_ordering_cnt can be obtained.

[0115] In addition, the detection device 300 receives the configuration information transmitted by the sending FIFO module 301-1 through the interface, or the detection device 300 stores the configuration information. The configuration information includes a configured value, and the size of the value is not limited here. In this example, the configured value is used as the threshold value corresponding to the candidate condition 4. Alternatively, the threshold value Np_req_ordering_cnt_thred corresponding to the candidate condition 4 is calculated according to the formula Np_req_ordering_cnt_thred = 1000. In this example, the configured value is 1000.

[0116] In the candidate condition 4, the second type of request is stranded in the sending FIFO module 301-1, and due to the ordering requirement, the first type of request is blocked by the second type of request, so that the first type of request is also stranded in the sending FIFO module 301-1. Since the first type of request and the second type of request are stranded in the sending side, the receiving side cannot send an acknowledgement signal because it cannot receive the request, that is, the sending side cannot obtain the acknowledgement signal. Based on this, the configured value is used to determine the threshold value corresponding to the candidate condition 4, the characteristics based on the candidate condition 4 are realized, the experience value is determined as the target threshold value, the target threshold value and the target counting value correspond to the same candidate condition, the accuracy of the target threshold value is improved, and thus the accuracy of the target detection result is improved.

[0117] If the target counting value Np_req_ordering_cnt is greater than the target threshold value Np_req_ordering_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 falls into long-time logical interlocking; if the target counting value Np_req_ordering_cnt is less than the target threshold value Np_req_ordering_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 does not fall into long-time logical interlocking; and if the target counting value Np_req_ordering_cnt is equal to the target threshold value Np_req_ordering_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 falls into or does not fall into long-time logical interlocking.

[0118] It should be noted that after stopping counting the time to obtain the target count value Np_req_ordering_cnt, on the one hand, the target detection result is determined based on the relationship between the target count value Np_req_ordering_cnt and the target threshold Np_req_ordering_cnt_thred. On the other hand, the target count value Np_req_ordering_cnt can be cleared, i.e., Np_req_ordering_cnt = 0, to facilitate subsequent detection.

[0119] Candidate condition 5, unknown condition other than candidate conditions 1 to 4. That is, candidate conditions 1 to 4 are known conditions that can cause the sending FIFO module 301-1 to fall into logical interlocking, and in actual application, there are also some unknown conditions that can cause the sending FIFO module 301-1 to fall into logical interlocking. Since candidate condition 5 is an unknown condition other than candidate conditions 1 to 4, candidate condition 5 can include at least one of sub-conditions 1 to 4.

[0120] Sub-condition 1: The data transmission link between the data buffer module and the target module is in a working state.

[0121] Sub-condition 2: The first state machine of the data buffer module is in a working state, and the first state machine is used to control the data buffer module to transmit data to the target module.

[0122] Sub-condition 3: The data buffer module sends a transmission request and transmission data corresponding to the transmission request to the target module, and the target condition includes that the data buffer module has stored transmission data in the case of needing to send a transmission request.

[0123] Sub-condition 4: The data buffer module sends a first type of request and a second type of request to the target module, and the target condition includes that the first type of request is not blocked by the second type of request.

[0124] The above sub-conditions 1 to 4 can refer to the description of candidate conditions 1 to 4, which will not be repeated here. If the target condition includes candidate condition 5, step 201 includes counting the time to obtain a target count value when the sending FIFO module 301-1 meets candidate condition 5, and step 202 includes adjusting the configured value according to the historical detection result to obtain a target threshold, and the historical detection result represents the historical situation of the data buffer module falling into long-time logical interlocking. Step 203 includes determining a target detection result according to the relationship between the target count value and the target threshold.

[0125] In the present example, as Figure 3As shown, the sending FIFO module 301-1 can transmit at least one of the Link_active signal, the FSM_active signal, the Data_delay_vld signal, and the Np_req_ordering signal to the detecting device 300 through the interface.

[0126] The detecting device 300 can receive the signals transmitted by the sending FIFO module 301-1 in real time. If it is determined that the sub-condition 1 is satisfied based on the Link_active signal, i.e., it is determined that the data transmission link is in the working state based on the Link_active signal; it is determined that the sub-condition 2 is satisfied based on the FSM_active signal, i.e., the first state machine is in the working state; it is determined that the sub-condition 3 is satisfied based on the Data_delay_vld signal, i.e., the sending FIFO module 301-1 stores the transmission data in the case that the transmission request needs to be sent; it is determined that the sub-condition 4 is satisfied based on the Np_req_ordering signal, i.e., the first type of request is not blocked by the second type of request in the sending FIFO module 301-1. Then, the detecting device 300 adds 1 to the initial count value every one count unit to obtain a target count value. Alternatively, the initial count value Not_pop_cnt is 0, and Not_pop_cnt is added by 1 every one count unit, i.e., Not_pop_cnt++. In this way, Not_pop_cnt is constantly updated.

[0127] In the process of counting time, if the sending FIFO module 301-1 does not satisfy the candidate condition 5, the counting of time is stopped. For example, based on the Link_active signal, it is determined that the data transmission link is in the non-working state, and the sending FIFO module 301-1 does not satisfy the candidate condition 5, and the counting of time can be stopped. Finally, the target count value Not_pop_cnt can be obtained.

[0128] In addition, the detecting device 300 receives the configuration information transmitted by the sending FIFO module 301-1 through the interface, or the detecting device 300 stores the configuration information. The configuration information includes a configured value, and the value size is not limited herein. In this example, the value of the configuration is adjusted according to the historical detection result to obtain the threshold value corresponding to the candidate condition 5, and the adjustment manner is not limited herein. For example, according to the relationship between the historical count value corresponding to the historical detection result and the historical threshold value, the value of the configuration is adjusted, for example, the value of the configuration is 1000, if the historical count value is less than the historical threshold value, 1000 is reduced, and if the historical count value is equal to or greater than the historical threshold value, 1000 is maintained.

[0129] It can be understood that the detection method of the embodiments of the present application can be executed multiple times, and each execution of the detection method can obtain a target detection result, and the target detection results obtained by each execution before can be historical detection results. Each historical detection result can be obtained on the basis of the adjusted value of the configuration, and the value of the configuration can be adjusted according to the historical detection result. In this way, the value of the configuration is continuously adjusted to obtain the threshold Not_pop_cnt_thred corresponding to the candidate condition 5, and the accuracy of the threshold is improved.

[0130] Optionally, each time the value is adjusted, the value is reduced or maintained. By reducing the value, the situation that the threshold is too large and the sending FIFO module 301-1 is missed and falls into long-time logical interlocking can be reduced, so that the problem can be detected in time. By maintaining the value, the situation that the threshold is too small and the sending FIFO module 301-1 is detected and falls into long-time logical interlocking can be reduced, so that the situation of detecting unnecessary problems can be reduced. In summary, based on the historical detection result, the threshold is adjusted, and the detection quality and detection efficiency can be improved.

[0131] If the target count value Not_pop_cnt is greater than the target threshold Not_pop_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 falls into long-time logical interlocking; if the target count value Not_pop_cnt is less than the target threshold Not_pop_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 does not fall into long-time logical interlocking; if the target count value Not_pop_cnt is equal to the target threshold Not_pop_cnt_thred, it is determined that the target detection result represents that the sending FIFO module 301-1 falls into or does not fall into long-time logical interlocking.

[0132] It should be noted that after stopping counting the time to obtain the target count value Not_pop_cnt, on the one hand, the target detection result is determined based on the relationship between the target count value Not_pop_cnt and the target threshold Not_pop_cnt_thred. On the other hand, the target count value Not_pop_cnt can be cleared, i.e. Not_pop_cnt=0, so as to facilitate subsequent detection.

[0133] The detection processes corresponding to the candidate conditions 1 to 5 are described in detail above. In actual application, in the execution of the detection process, in addition to satisfying the candidate conditions 1 to 5, the preconditions can also be satisfied. That is, in step 201, counting the time to obtain the target count value includes: counting the time to obtain the target count value when the data buffer module satisfies the preconditions.

[0134] The precondition includes at least one of the following: the data buffer module is in a non-empty state; the data buffer module is not in a data sending state; the data buffer module sends data to the target module, and the target module is in a state of waiting to receive data.

[0135] In the present example, as shown in Figure 3 The sending FIFO module 301-1 can transmit a FIFO_Empty signal to the detection device 300 through an interface. The FIFO_Empty signal is used to represent whether the sending FIFO module 301-1 is in an empty state. When the FIFO_Empty signal is at a high level, it represents that the sending FIFO module 301-1 does not store data, and the sending FIFO module 301-1 is in an empty state. When the FIFO_Empty signal is at a low level, it represents that the sending FIFO module 301-1 stores data, and the sending FIFO module 301-1 is in a non-empty state. The first control unit 101-3 can control the FIFO_Empty signal transmitted by the sending FIFO module 301-1 to be at a high level or a low level.

[0136] Optionally, the sending FIFO module 301-1 includes at least one sending FIFO queue, and the FIFO_Empty signal includes a third sub-signal of each sending FIFO queue. The third sub-signal of any sending FIFO queue is used to represent whether the sending FIFO queue is in an empty state. When the third sub-signal is at a high level, it represents that the sending FIFO queue is in an empty state. When the third sub-signal is at a low level, it represents that the sending FIFO queue is in a non-empty state. The precondition includes that at least one sending FIFO queue is in a non-empty state.

[0137] The sending FIFO module 301-1 can also transmit a FIFO_Pop signal to the detection device 300 through an interface. The FIFO_Pop signal is used to represent whether the sending FIFO module 301-1 is in a data sending state. When the FIFO_Pop signal is at a low level, it represents that the sending FIFO module 301-1 is not in a data sending state. When the FIFO_Pop signal is at a high level, it represents that the sending FIFO module 301-1 is in a data sending state. The first control unit 101-3 can control the FIFO_Pop signal transmitted by the sending FIFO module 301-1 to be at a high level or a low level.

[0138] Optionally, the sending FIFO module 301-1 comprises at least one sending FIFO queue, and the FIFO_Pop signal comprises fourth sub-signals of the respective sending FIFO queues. The fourth sub-signal of any sending FIFO queue is used to represent whether the sending FIFO queue is in a data sending state. In this case, the fourth sub-signal is at a low level, representing that the sending FIFO queue is not in the data sending state. The fourth sub-signal is at a high level, representing that the sending FIFO queue is in the data sending state. The precondition comprises that at least one sending FIFO queue is not in the data sending state.

[0139] The sending FIFO module 301-1 can also transmit a CreditRdy signal to the detection device 300 through the interface. The CreditRdy signal is used to represent whether the receiving FIFO module 302-1 is in a state of waiting to receive data. In this case, the CreditRdy signal is at a low level, representing that the receiving FIFO module 302-1 is not in the state of waiting to receive data. The CreditRdy signal is at a high level, representing that the receiving FIFO module 302-1 is in the state of waiting to receive data. The CreditRdy signal transmitted by the sending FIFO module 301-1 can be controlled to be at a high level or a low level by the first control unit 101-3.

[0140] Optionally, the sending FIFO module 301-1 comprises at least one sending FIFO queue, the receiving FIFO module 302-1 comprises a receiving FIFO queue corresponding to each sending FIFO queue, and the CreditRdy signal comprises fifth sub-signals of the respective sending FIFO queues. The fifth sub-signal of any sending FIFO queue is used to represent whether the receiving FIFO queue corresponding to the sending FIFO queue is in a state of waiting to receive data. In this case, the fifth sub-signal is at a low level, representing that the receiving FIFO queue is not in the state of waiting to receive data. The fifth sub-signal is at a high level, representing that the receiving FIFO queue is in the state of waiting to receive data. The precondition comprises that at least one receiving FIFO queue is in the state of waiting to receive data.

[0141] It can be understood that, in addition to transmitting the signals and configuration information mentioned above to the detection device 300 through the interface, the sending FIFO module 301-1 can also transmit other signals. For example, the sending FIFO module 301-1 can also transmit a Clk signal and a rst signal to the detection device 300 through the interface. In this case, the Clk signal is a clock signal, and the rst signal is a reset signal. The rst signal is at a high level, representing that the sending FIFO module 301-1 is in a reset state. The rst signal is at a low level, representing that the sending FIFO module 301-1 is not in the reset state. The Clk signal and the rst signal transmitted by the sending FIFO module 301-1 can be controlled to be at a high level or a low level by the first control unit 101-3.

[0142] The detection device 300 can receive the FIFO_Empty signal, the FIFO_Pop signal and the CreditRdy signal in real time. If it is determined that at least one sending FIFO queue of the sending FIFO module 301-1 is in a non-empty state based on the FIFO_Empty signal, that at least one sending FIFO queue of the sending FIFO module 301-1 is not in a data sending state based on the FIFO_Pop signal, and that at least one sending FIFO queue of the receiving FIFO module 302-1 is in a state of waiting to receive data based on the CreditRdy signal, then: when the sending FIFO module 301-1 meets any one of the candidate conditions 1 to 5, the time is counted to obtain a target count value, and a target threshold is obtained. Then, according to the relationship between the target count value and the target threshold, it is determined whether the sending FIFO module 301-1 falls into a long-time logical interlocking.

[0143] In actual application, different candidate conditions correspond to different count values, and in the process of counting the time of any one candidate condition, the count values corresponding to other candidate conditions can be reset to initial values. In summary, as shown in Figure 4 The detection method of the embodiment of the application includes the following steps.

[0144] Step 401: It is determined whether the sending FIFO module 301-1 has been reset. If yes, step 402 is performed, and if not, step 401 is returned.

[0145] Step 402: It is determined whether at least one sending FIFO queue of the sending FIFO module 301-1 meets the precondition: CreditRdy==1&&Fifo_Empty==0&&Fifo_pop==0. Wherein, “&&” represents logical AND, “==” represents equal to, “0” represents low level, and “1” represents high level. Based on this, the precondition includes: the CreditRdy signal is high, that is, each receiving FIFO queue corresponding to at least one sending FIFO queue in the sending FIFO module 301-1 is in a state of waiting to receive data; the FIFO_Empty signal is low, that is, each sending FIFO queue in the sending FIFO module 301-1 is in a non-empty state; and the FIFO_pop signal is low, that is, each sending FIFO queue in the sending FIFO module 301-1 is not in a data sending state. If the precondition is met, step 404 is performed, and if the precondition is not met, step 403 is performed.

[0146] Step 403: link_cnt = 0, Fsm_cnt = 0, Np_req_ordering_cnt = 0, Not_pop_cnt = 0, Data_delay_cnt = 0. Here, link_cnt is the count value corresponding to candidate condition 1, Fsm_cnt is the count value corresponding to candidate condition 2, Np_req_ordering_cnt is the count value corresponding to candidate condition 4, Not_pop_cnt is the count value corresponding to candidate condition 5, and Data_delay_cnt is the count value corresponding to candidate condition 3. Based on this, the count values ​​corresponding to each condition are all reset to 0. Optionally, link_cnt, Fsm_cnt, Np_req_ordering_cnt, and Not_pop_cnt all include the count values ​​of each transmit FIFO queue in the transmit FIFO module 301-1. For ease of description, the following explanation uses a transmit FIFO queue as an example.

[0147] Step 404: Determine if the sending FIFO queue meets candidate condition 1: Link_active == 0. That is, candidate condition 1 is: the data transmission link between the sending FIFO queue and the corresponding receiving FIFO queue is in a non-working state. If candidate condition 1 is met, proceed to step 405; otherwise, proceed to step 406.

[0148] Step 405: increment link_cnt, set Fsm_cnt to 0, Np_req_ordering_cnt to 0, Not_pop_cnt to 0, and Data_delay_cnt to 0. This means that the count value link_cnt of the sending FIFO queue corresponding to candidate condition 1 is incremented with each counting unit, while the count values ​​corresponding to other candidate conditions are reset to 0.

[0149] Step 406: Determine if the sending FIFO queue meets candidate condition 2: FSM_active == 0. That is, candidate condition 2 is: the first state machine of the sending FIFO queue is in a non-working state. If candidate condition 2 is met, proceed to step 407; otherwise, proceed to step 408.

[0150] Step 407: link_cnt = 0, Fsm_cnt++, Np_req_ordering_cnt = 0, Not_pop_cnt = 0, Data_delay_cnt = 0. That is, the count value Fsm_cnt of the sending FIFO queue corresponding to candidate condition 2 is incremented with each counting unit, while the count values ​​corresponding to other candidate conditions are reset to 0.

[0151] Step 408, judge whether the sending FIFO queue satisfies the candidate condition 3: Data_delay_vld == 1. That is, the candidate condition 3 is that the sending FIFO queue does not store transmission data in the case of needing to send a transmission request. If the candidate condition 3 is satisfied, step 409 is executed, and if the candidate condition 3 is not satisfied, step 410 is executed.

[0152] Step 409, link_cnt = 0, Fsm_cnt = 0, Np_req_ordering_cnt = 0, Not_pop_cnt = 0, Data_delay_cnt++. That is, the count value Data_delay_cnt of the sending FIFO queue corresponding to the candidate condition 3 is accumulated with the counting unit, and the count values corresponding to other candidate conditions are reset to 0.

[0153] Step 410, judge whether the sending FIFO queue satisfies the candidate condition 4: Np_req_ordering == 0. That is, the candidate condition 4 is that the first type of request is blocked by the second type of request in the sending FIFO queue. If the candidate condition 4 is satisfied, step 412 is executed, and if the candidate condition 4 is not satisfied, step 411 is executed.

[0154] Step 411, link_cnt = 0, Fsm_cnt = 0, Np_req_ordering_cnt = 0, Not_pop_cnt++, Data_delay_cnt = 0. That is, the count value Not_pop_cnt of the sending FIFO queue corresponding to the candidate condition 5 is accumulated with the counting unit, and the count values corresponding to other candidate conditions are reset to 0.

[0155] Step 412, link_cnt = 0, Fsm_cnt = 0, Np_req_ordering_cnt++, Not_pop_cnt = 0, Data_delay_cnt = 0. That is, the count value Np_req_ordering_cnt of the sending FIFO queue corresponding to the candidate condition 4 is accumulated with the counting unit, and the count values corresponding to other candidate conditions are reset to 0.

[0156] Optionally, after it is determined that the sending FIFO module 301-1 falls into long-time logical interlocking, alarm information can also be generated, so that the relevant object can discover and solve the problem in time. Taking the candidate condition 5 as an example, if the target count value Not_pop_cnt is greater than the target threshold Not_pop_cnt_thred, it indicates that the sending FIFO module 301-1 falls into long-time logical interlocking, and in this case, the alarm information can be directly generated.

[0157] Optionally, after step 203, the method further comprises: determining a plurality of threshold intervals according to the target threshold, the plurality of threshold intervals corresponding to a plurality of levels of alarm information; determining a target interval in which the target count value is located from the plurality of threshold intervals; and generating alarm information of a level corresponding to the target interval.

[0158] In this example, different weights can be applied to the target threshold to obtain at least one threshold, each of which is greater than the target threshold. At least two threshold intervals can be determined according to the size relationship between the target threshold and each threshold. Taking candidate condition 1 as an example, two weights of 5 and 10 are applied to the target threshold Link_cnt_thred to obtain two thresholds of 5*Link_cnt_thred and 10*Link_cnt_thred. Based on the target threshold Link_cnt_thred, the two thresholds of 5*Link_cnt_thred and 10*Link_cnt_thred, three threshold intervals are determined, which are [Link_cnt_thred, 5*Link_cnt_thred), [5*Link_cnt_thred, 10*Link_cnt_thred) and [10*Link_cnt_thred, +∞) respectively.

[0159] Each threshold interval corresponds to a level of alarm information. It can be understood that the larger the average value of the threshold interval, the higher the level of the alarm information. Still taking candidate condition 1 as an example, the threshold interval [Link_cnt_thred, 5*Link_cnt_thred) corresponds to alarm information of: the state of the print data transmission link, the target count value link_cnt and the target threshold Link_cnt_thred; the threshold interval [5*Link_cnt_thred, 10*Link_cnt_thred) corresponds to alarm information of: generating a warning identifier, and simultaneously printing the state of the data transmission link, the target count value link_cnt and the target threshold Link_cnt_thred; and the threshold interval [10*Link_cnt_thred, +∞) corresponds to alarm information of: generating an error identifier, and simultaneously printing the state of the data transmission link, the target count value link_cnt and the target threshold Link_cnt_thred.

[0160] After the target count value is acquired, a target interval in which the target count value is located can be determined from a plurality of threshold intervals, and alarm information of a level corresponding to the target interval can be generated. Still taking the candidate condition 1 as an example, if the target count value link_cnt is located in the target interval [Link_cnt_thred, 5*Link_cnt_thred), the state of the data transmission link, the target count value link_cnt, and the target threshold Link_cnt_thred are printed; if the target count value link_cnt is located in the target interval [5*Link_cnt_thred, 10*Link_cnt_thred), a warning identifier is generated, and the state of the data transmission link, the target count value link_cnt, and the target threshold Link_cnt_thred are printed; and if the target count value link_cnt is located in the target interval [10*Link_cnt_thred, +∞), an error identifier is generated, and the state of the data transmission link, the target count value link_cnt, and the target threshold Link_cnt_thred are printed.

[0161] In the method, when the data cache module meets the target condition, the time is counted to obtain the target count value, so that the target count value represents the time corresponding to the target condition. The target threshold corresponding to the target condition is acquired, so that the target threshold and the target count value correspond to the same condition, so that the target threshold is a threshold that is adapted to the target count value, and has high accuracy. Based on this, the relationship between the target count value and the target threshold can be used to accurately determine whether the data cache module is trapped in long-time logical interlocking, and the false detection rate of long-time logical interlocking is reduced.

[0162] The embodiments of the present application also provide a detection device for executing the detection method mentioned above, as shown in the following Figure 5 The detection device includes:

[0163] The condition checking and counting module 501 is configured to count the time when the data cache module meets the target condition to obtain a target count value, the data cache module and the target module are associated, and the target condition represents a condition that can cause the data cache module to be trapped in logical interlocking due to the target module;

[0164] The threshold calculation module 502 is configured to acquire a target threshold corresponding to the target condition;

[0165] The timeout checking module 503 is configured to determine a target detection result according to the relationship between the target count value and the target threshold, and the target detection result represents whether the data cache module is trapped in long-time logical interlocking.

[0166] In a possible implementation, the target condition comprises that a data transmission link between the data buffering module and the target module is in a non-working state.

[0167] The threshold calculation module 502 is configured to determine the target threshold according to at least one of a first time parameter and a second time parameter, the first time parameter representing a time required for establishing the data transmission link, and the second time parameter representing a time required for disconnecting the data transmission link.

[0168] In a possible implementation, the target condition comprises that a first state machine of the data buffering module is in a non-working state, the first state machine being configured to control the data buffering module to transmit data to the target module.

[0169] The threshold calculation module 502 is configured to determine the target threshold according to a third time parameter, the third time parameter representing a time required for the first state machine to jump from the non-working state to a working state.

[0170] In a possible implementation, the data buffering module sends a transmission request and transmission data corresponding to the transmission request to the target module, and the target condition comprises that the data buffering module does not store the transmission data in a case where the transmission request needs to be sent.

[0171] The threshold calculation module 502 is configured to determine the target threshold according to a fourth time parameter, the fourth time parameter representing a maximum delay time during which the data buffering module is allowed to not store the transmission data in the case where the transmission request needs to be sent.

[0172] In a possible implementation, the data buffering module sends a first type of request and a second type of request to the target module, and the target condition comprises that the first type of request is blocked by the second type of request.

[0173] The threshold calculation module 502 is configured to determine a configured numerical value as the target threshold.

[0174] In a possible implementation, the target condition comprises at least one of the following:

[0175] The target condition comprises that a data transmission link between the data buffering module and the target module is in a working state.

[0176] The target condition comprises that a first state machine of the data buffering module is in a working state, the first state machine being configured to control the data buffering module to transmit data to the target module.

[0177] The data buffering module sends a transmission request and transmission data corresponding to the transmission request to the target module, and the target condition comprises that the data buffering module stores the transmission data in a case where the transmission request needs to be sent.

[0178] The data buffer module sends a first type of request and a second type of request to a target module, and the target condition comprises that the first type of request is not blocked by the second type of request.

[0179] The threshold calculation module 502 is configured to adjust a configured value according to a historical detection result to obtain a target threshold, and the historical detection result represents a situation in which the data buffer module is trapped in long-time logical interlocking in history.

[0180] In a possible implementation, the condition checking and counting module 501 is configured to count time when the data buffer module meets a precondition to obtain a target count value.

[0181] The precondition comprises at least one of the following:

[0182] The data buffer module is in a non-empty state.

[0183] The data buffer module is not in a data sending state.

[0184] The data buffer module sends data to a target module, and the target module is in a state of waiting to receive data.

[0185] In a possible implementation, the timeout checking module 503 is configured to:

[0186] In a case where the target count value is greater than the target threshold, it is determined that the target detection result represents that the data buffer module is trapped in long-time logical interlocking.

[0187] In a case where the target count value is less than the target threshold, it is determined that the target detection result represents that the data buffer module is not trapped in long-time logical interlocking.

[0188] In a case where the target count value is equal to the target threshold, it is determined that the target detection result represents that the data buffer module is trapped in or not trapped in long-time logical interlocking.

[0189] In a possible implementation, the apparatus further comprises an error reporting module, and the error reporting module is configured to: Figure 5 The error reporting module is not shown. In actual application, the error reporting module can be integrated with the timeout checking module 503 in the same module. Alternatively, the error reporting module is a separate module, and in this case, the error reporting module is connected with the condition checking and counting module 501 and the threshold calculation module 502. Optionally, the error reporting module is also connected with the timeout checking module 503.

[0190] The error reporting module is configured to:

[0191] determine a plurality of threshold intervals according to the target threshold, and the plurality of threshold intervals correspond to a plurality of levels of alarm information;

[0192] determine a target interval in which the target count value is located from the plurality of threshold intervals.

[0193] The alarm information corresponding to the level of the target interval is generated.

[0194] In the device, when the data buffer module meets the target condition, the time is counted to obtain a target count value, so that the target count value represents the time corresponding to the target condition. A target threshold value corresponding to the target condition is obtained, so that the target threshold value and the target count value correspond to the same condition, so that the target threshold value is a threshold value adapted to the target count value, and has higher accuracy. Based on this, according to the relationship between the target count value and the target threshold value, it can be accurately determined whether the data buffer module is in long-time logical interlocking, and the false detection rate of long-time logical interlocking is reduced.

[0195] The detection device and the detection method are based on the same inventive concept, and the technical features described when introducing the detection method are also applicable to the device embodiments. For specific details, refer to the technical features described when introducing the detection method. For the sake of brevity, they will not be described here.

[0196] Figure 6 The electronic device 600 provided by the embodiments of the present application can have great differences due to different configurations or performances, and can include one or more processors 601 and one or more memories 602, wherein the one or more memories 602 store at least one computer program, the at least one computer program is loaded and executed by the one or more processors 601 to implement the detection method provided by each method embodiment. For example, the processor 601 is a CPU. Of course, the electronic device 600 can also have a wired or wireless network interface, a keyboard, an input and output interface, and other components for realizing the functions of the device, so as to perform input and output. The electronic device 600 can also include other components for realizing the functions of the device, which will not be described here.

[0197] The electronic device can include a terminal device and a server. The terminal device can be any kind of electronic device product that can interact with a user through one or more ways such as a keyboard, a touchpad, a remote controller, voice interaction, or a handwriting device. For example, the terminal device can be a mobile phone or a computer, where the mobile phone includes but is not limited to a smart phone, a folding mobile phone, a sliding mobile phone, or a flip mobile phone, and the computer includes but is not limited to a tablet computer, a notebook computer, a desktop computer, a PPC (Pocket PC, Pocket PC), or a PC (Personal Computer, Personal Computer). In actual application, the terminal device can also include a smart speaker, a smart watch, a PDA (Personal Digital Assistant, Personal Digital Assistant), a wearable device, a smart car machine, a smart television, and the like. The server is a server or a server cluster composed of multiple servers, and the embodiments of the present application do not limit this. In addition, the functions of the terminal device and the functions of the server are not limited herein.

[0198] In the example embodiments, a computer readable storage medium is also provided, and the storage medium stores at least one computer program. The at least one computer program is loaded and executed by a processor to enable the electronic device to implement any of the above detection methods.

[0199] Optionally, the above computer readable storage medium can be a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a read-only compact disc (Compact Disc Read-Only Memory, CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0200] It should be understood that "multiple" mentioned herein refers to two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after it are in an "or" relationship.

[0201] The above only describes the example embodiments of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method of detection, characterized in that, The method comprises: counting time when the data cache module meets a target condition, to obtain a target count value, the data cache module and the target module being associated, the target condition representing a condition that can cause the data cache module to fall into logical interlocking due to the target module; obtaining a target threshold value corresponding to the target condition; determining a target detection result according to a relationship between the target count value and the target threshold value, the target detection result representing whether the data cache module falls into long-time logical interlocking.

2. The method of claim 1, wherein, The target condition comprises a data transmission link between the data cache module and the target module being in a non-working state; The target threshold value corresponding to the target condition is obtained by: determining the target threshold value according to at least one of a first time parameter and a second time parameter, the first time parameter representing a time required for establishing the data transmission link, and the second time parameter representing a time required for disconnecting the data transmission link.

3. The method of claim 1, wherein, The target condition comprises a first state machine of the data cache module being in a non-working state, the first state machine being used for controlling the data cache module to transmit data to the target module; The target threshold value corresponding to the target condition is obtained by: determining the target threshold value according to a third time parameter, the third time parameter representing a time required for the first state machine to jump from the non-working state to a working state.

4. The method of claim 1, wherein, The data cache module sends a transmission request and transmission data corresponding to the transmission request to the target module, and the target condition comprises that the data cache module does not store the transmission data in a case where the transmission request needs to be sent; The target threshold value corresponding to the target condition is obtained by: determining the target threshold value according to a fourth time parameter, the fourth time parameter representing a maximum delay time allowed for the data cache module to not store the transmission data in the case where the transmission request needs to be sent.

5. The method of claim 1, wherein, The data cache module sends a first type request and a second type request to the target module, and the target condition comprises that the first type request is blocked by the second type request; The target threshold value corresponding to the target condition is obtained by: determining a configured value as the target threshold value.

6. The method of claim 1, wherein, The target condition comprises at least one of: The target condition comprises a data transmission link between the data cache module and the target module being in a working state; The target condition comprises a first state machine of the data cache module being in a working state, the first state machine being used for controlling the data cache module to transmit data to the target module; The data cache module sends a transmission request and transmission data corresponding to the transmission request to the target module, and the target condition comprises that the data cache module stores the transmission data in a case where the transmission request needs to be sent; The data cache module sends a first type request and a second type request to the target module, and the target condition comprises that the first type request is not blocked by the second type request; The target threshold value corresponding to the target condition is obtained by: Adjust a value of a configuration according to a historical detection result, to obtain the target threshold, the historical detection result representing a case that the data buffer module is historically trapped in long-time logical interlocking.

7. The method according to any one of claims 1 to 6, characterized in that, The counting of time to obtain the target count value comprises: Counting time to obtain a target count value when the data buffer module meets a precondition; The precondition comprises at least one of the following: The data buffer module is in a non-empty state; The data buffer module is not in a data sending state; The data buffer module sends data to the target module, and the target module is in a state of waiting to receive data.

8. The method according to any one of claims 1 to 6, characterized in that, The determining of the target detection result according to the relationship between the target count value and the target threshold comprises: In the case that the target count value is greater than the target threshold, determining that the target detection result represents that the data buffer module is trapped in long-time logical interlocking; In the case that the target count value is less than the target threshold, determining that the target detection result represents that the data buffer module is not trapped in long-time logical interlocking; In the case that the target count value is equal to the target threshold, determining that the target detection result represents that the data buffer module is trapped in or not trapped in long-time logical interlocking.

9. The method according to any one of claims 1 to 6, characterized in that, The method further comprises: Determining a plurality of threshold intervals according to the target threshold, the plurality of threshold intervals corresponding to a plurality of levels of alarm information; From the plurality of threshold intervals, determining a target interval in which the target count value is located; Generating alarm information of a level corresponding to the target interval.

10. A detection device, characterized in that The device comprises: A condition checking and counting module for counting time to obtain a target count value when a data buffer module meets a target condition, the data buffer module being associated with a target module, the target condition representing a condition that can cause the data buffer module to be trapped in logical interlocking due to the target module; A threshold calculation module for obtaining a target threshold corresponding to the target condition; A timeout checking module for determining a target detection result according to the relationship between the target count value and the target threshold, the target detection result representing whether the data buffer module is trapped in long-time logical interlocking.

11. The apparatus of claim 10, wherein, The target condition comprises a data transmission link between the data buffer module and the target module being in a non-working state; The threshold calculation module is configured to determine the target threshold according to at least one of a first time parameter and a second time parameter, the first time parameter representing a time required for establishing the data transmission link, and the second time parameter representing a time required for disconnecting the data transmission link.

12. The apparatus of claim 10, wherein, The target condition comprises a first state machine of the data buffer module being in a non-working state, the first state machine being configured to control the data buffer module to transmit data to the target module; The threshold calculation module is configured to determine the target threshold according to a third time parameter, the third time parameter representing a time required for the first state machine to jump from the non-working state to a working state.

13. The apparatus of claim 10, wherein, The data cache module sends a transmission request and transmission data corresponding to the transmission request to the target module, and the target condition includes that the data cache module does not store the transmission data in a case where the transmission request needs to be sent. The threshold calculation module is configured to determine the target threshold according to a fourth time parameter, and the fourth time parameter represents a maximum delay time during which the data cache module is allowed to not store the transmission data in a case where the transmission request needs to be sent.

14. The apparatus of claim 10, wherein, The data cache module sends a first type request and a second type request to the target module, and the target condition includes that the first type request is not blocked by the second type request. The threshold calculation module is configured to determine a configured value as the target threshold.

15. The apparatus of claim 10, wherein, The target condition includes at least one of the following: The target condition includes that a data transmission link between the data cache module and the target module is in a working state. The target condition includes that a first state machine of the data cache module is in a working state, and the first state machine is configured to control the data cache module to transmit data to the target module. The data cache module sends a transmission request and transmission data corresponding to the transmission request to the target module, and the target condition includes that the data cache module stores the transmission data in a case where the transmission request needs to be sent. The data cache module sends a first type request and a second type request to the target module, and the target condition includes that the first type request is not blocked by the second type request. The threshold calculation module is configured to adjust a configured value according to a historical detection result to obtain the target threshold, and the historical detection result represents a case where the data cache module is historically trapped in long-time logical interlocking.

16. The apparatus of any one of claims 10 to 15, wherein, The condition checking and counting module is configured to count time to obtain a target count value when the data cache module meets a precondition. The precondition includes at least one of the following: The data cache module is in a non-empty state. The data cache module is not in a data sending state. The data cache module sends data to the target module, and the target module is in a state of waiting to receive data.

17. The apparatus of any one of claims 10 to 15, wherein, The timeout checking module is configured to: In a case where the target count value is greater than the target threshold, determine that the target detection result represents that the data cache module is trapped in long-time logical interlocking. In a case where the target count value is less than the target threshold, determine that the target detection result represents that the data cache module is not trapped in long-time logical interlocking. In a case where the target count value is equal to the target threshold, determine that the target detection result represents that the data cache module is trapped in or not trapped in long-time logical interlocking.

18. The apparatus of any one of claims 10 to 15, wherein, The device further includes an error reporting module, and the error reporting module is configured to: determine a plurality of threshold intervals according to the target threshold, the plurality of threshold intervals corresponding to a plurality of levels of alarm information; determine a target interval in which the target count value is located from the plurality of threshold intervals; and generate alarm information of a level corresponding to the target interval.

19. An electronic device, comprising: The electronic device comprises a processor and a memory, and the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor, so that the electronic device implements the detection method as claimed in any one of claims 1 to 9.

20. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is loaded and executed by the processor to implement the detection method as claimed in any one of claims 1 to 9.

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